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Fix a potential use of an uninitialised value in the ns32k disassembler.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
151f5de4
NC		 12020-05-28 Nick Clifton <nickc@redhat.com>
2
3 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
4 static.
5
25e1eca8
SL		 62020-05-26 Sandra Loosemore <sandra@codesourcery.com>
7
8 Fix extraction of signed constants in nios2 disassembler (again).
9
10 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
11 extractions of signed fields.
12
57b17940
SSF		 132020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
14
15 * s390-opc.txt: Relocate vector load/store instructions with
16 additional alignment parameter and change architecture level
17 constraint from z14 to z13.
18
d96bf37b
AM		 192020-05-21 Alan Modra <amodra@gmail.com>
20
21 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
22 * sparc-dis.c: Likewise.
23 * tic4x-dis.c: Likewise.
24 * xtensa-dis.c: Likewise.
25 * bpf-desc.c: Regenerate.
26 * epiphany-desc.c: Regenerate.
27 * fr30-desc.c: Regenerate.
28 * frv-desc.c: Regenerate.
29 * ip2k-desc.c: Regenerate.
30 * iq2000-desc.c: Regenerate.
31 * lm32-desc.c: Regenerate.
32 * m32c-desc.c: Regenerate.
33 * m32r-desc.c: Regenerate.
34 * mep-asm.c: Regenerate.
35 * mep-desc.c: Regenerate.
36 * mt-desc.c: Regenerate.
37 * or1k-desc.c: Regenerate.
38 * xc16x-desc.c: Regenerate.
39 * xstormy16-desc.c: Regenerate.
40
8f595e9b
NC		 412020-05-20 Nelson Chu <nelson.chu@sifive.com>
42
43 * riscv-opc.c (riscv_ext_version_table): The table used to store
44 all information about the supported spec and the corresponding ISA
45 versions. Currently, only Zicsr is supported to verify the
46 correctness of Z sub extension settings. Others will be supported
47 in the future patches.
48 (struct isa_spec_t, isa_specs): List for all supported ISA spec
49 classes and the corresponding strings.
50 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
51 spec class by giving a ISA spec string.
52 * riscv-opc.c (struct priv_spec_t): New structure.
53 (struct priv_spec_t priv_specs): List for all supported privilege spec
54 classes and the corresponding strings.
55 (riscv_get_priv_spec_class): New function. Get the corresponding
56 privilege spec class by giving a spec string.
57 (riscv_get_priv_spec_name): New function. Get the corresponding
58 privilege spec string by giving a CSR version class.
59 * riscv-dis.c: Updated since DECLARE_CSR is changed.
60 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
61 according to the chosen version. Build a hash table riscv_csr_hash to
62 store the valid CSR for the chosen pirv verison. Dump the direct
63 CSR address rather than it's name if it is invalid.
64 (parse_riscv_dis_option_without_args): New function. Parse the options
65 without arguments.
66 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
67 parse the options without arguments first, and then handle the options
68 with arguments. Add the new option -Mpriv-spec, which has argument.
69 * riscv-dis.c (print_riscv_disassembler_options): Add description
70 about the new OBJDUMP option.
71
3d205eb4
PB		 722020-05-19 Peter Bergner <bergner@linux.ibm.com>
73
74 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
75 WC values on POWER10 sync, dcbf and wait instructions.
76 (insert_pl, extract_pl): New functions.
77 (L2OPT, LS, WC): Use insert_ls and extract_ls.
78 (LS3): New , 3-bit L for sync.
79 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
80 (SC2, PL): New, 2-bit SC and PL for sync and wait.
81 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
82 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
83 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
84 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
85 <wait>: Enable PL operand on POWER10.
86 <dcbf>: Enable L3OPT operand on POWER10.
87 <sync>: Enable SC2 operand on POWER10.
88
a501eb44
SH		 892020-05-19 Stafford Horne <shorne@gmail.com>
90
91 PR 25184
92 * or1k-asm.c: Regenerate.
93 * or1k-desc.c: Regenerate.
94 * or1k-desc.h: Regenerate.
95 * or1k-dis.c: Regenerate.
96 * or1k-ibld.c: Regenerate.
97 * or1k-opc.c: Regenerate.
98 * or1k-opc.h: Regenerate.
99 * or1k-opinst.c: Regenerate.
100
3b646889
AM		 1012020-05-11 Alan Modra <amodra@gmail.com>
102
103 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
104 xsmaxcqp, xsmincqp.
105
9cc4ce88
AM		 1062020-05-11 Alan Modra <amodra@gmail.com>
107
108 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
109 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
110
5d57bc3f
AM		 1112020-05-11 Alan Modra <amodra@gmail.com>
112
113 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
114
66ef5847
AM		 1152020-05-11 Alan Modra <amodra@gmail.com>
116
117 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
118 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
119
4f3e9537
PB		 1202020-05-11 Peter Bergner <bergner@linux.ibm.com>
121
122 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
123 mnemonics.
124
ec40e91c
AM		 1252020-05-11 Alan Modra <amodra@gmail.com>
126
127 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
128 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
129 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
130 (prefix_opcodes): Add xxeval.
131
d7e97a76
AM		 1322020-05-11 Alan Modra <amodra@gmail.com>
133
134 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
135 xxgenpcvwm, xxgenpcvdm.
136
fdefed7c
AM		 1372020-05-11 Alan Modra <amodra@gmail.com>
138
139 * ppc-opc.c (MP, VXVAM_MASK): Define.
140 (VXVAPS_MASK): Use VXVA_MASK.
141 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
142 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
143 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
144 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
145
aa3c112f
AM		 1462020-05-11 Alan Modra <amodra@gmail.com>
147 Peter Bergner <bergner@linux.ibm.com>
148
149 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
150 New functions.
151 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
152 YMSK2, XA6a, XA6ap, XB6a entries.
153 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
154 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
155 (PPCVSX4): Define.
156 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
157 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
158 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
159 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
160 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
161 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
162 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
163 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
164 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
165 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
166 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
167 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
168 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
169 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
170
6edbfd3b
AM		 1712020-05-11 Alan Modra <amodra@gmail.com>
172
173 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
174 (insert_xts, extract_xts): New functions.
175 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
176 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
177 (VXRC_MASK, VXSH_MASK): Define.
178 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
179 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
180 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
181 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
182 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
183 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
184 xxblendvh, xxblendvw, xxblendvd, xxpermx.
185
c7d7aea2
AM		 1862020-05-11 Alan Modra <amodra@gmail.com>
187
188 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
189 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
190 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
191 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
192 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
193
94ba9882
AM		 1942020-05-11 Alan Modra <amodra@gmail.com>
195
196 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
197 (XTP, DQXP, DQXP_MASK): Define.
198 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
199 (prefix_opcodes): Add plxvp and pstxvp.
200
f4791f1a
AM		 2012020-05-11 Alan Modra <amodra@gmail.com>
202
203 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
204 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
205 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
206
3ff0a5ba
PB		 2072020-05-11 Peter Bergner <bergner@linux.ibm.com>
208
209 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
210
afef4fe9
PB		 2112020-05-11 Peter Bergner <bergner@linux.ibm.com>
212
213 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
214 (L1OPT): Define.
215 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
216
1224c05d
PB		 2172020-05-11 Peter Bergner <bergner@linux.ibm.com>
218
219 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
220
6bbb0c05
AM		 2212020-05-11 Alan Modra <amodra@gmail.com>
222
223 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
224
7c1f4227
AM		 2252020-05-11 Alan Modra <amodra@gmail.com>
226
227 * ppc-dis.c (ppc_opts): Add "power10" entry.
228 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
229 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
230
73199c2b
NC		 2312020-05-11 Nick Clifton <nickc@redhat.com>
232
233 * po/fr.po: Updated French translation.
234
09c1e68a
AC		 2352020-04-30 Alex Coplan <alex.coplan@arm.com>
236
237 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
238 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
239 (operand_general_constraint_met_p): validate
240 AARCH64_OPND_UNDEFINED.
241 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
242 for FLD_imm16_2.
243 * aarch64-asm-2.c: Regenerated.
244 * aarch64-dis-2.c: Regenerated.
245 * aarch64-opc-2.c: Regenerated.
246
9654d51a
NC		 2472020-04-29 Nick Clifton <nickc@redhat.com>
248
249 PR 22699
250 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
251 and SETRC insns.
252
c2e71e57
NC		 2532020-04-29 Nick Clifton <nickc@redhat.com>
254
255 * po/sv.po: Updated Swedish translation.
256
5c936ef5
NC		 2572020-04-29 Nick Clifton <nickc@redhat.com>
258
259 PR 22699
260 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
261 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
262 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
263 IMM0_8U case.
264
bb2a1453
AS		 2652020-04-21 Andreas Schwab <schwab@linux-m68k.org>
266
267 PR 25848
268 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
269 cmpi only on m68020up and cpu32.
270
c2e5c986
SD		 2712020-04-20 Sudakshina Das <sudi.das@arm.com>
272
273 * aarch64-asm.c (aarch64_ins_none): New.
274 * aarch64-asm.h (ins_none): New declaration.
275 * aarch64-dis.c (aarch64_ext_none): New.
276 * aarch64-dis.h (ext_none): New declaration.
277 * aarch64-opc.c (aarch64_print_operand): Update case for
278 AARCH64_OPND_BARRIER_PSB.
279 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
280 (AARCH64_OPERANDS): Update inserter/extracter for
281 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
282 * aarch64-asm-2.c: Regenerated.
283 * aarch64-dis-2.c: Regenerated.
284 * aarch64-opc-2.c: Regenerated.
285
8a6e1d1d
SD		 2862020-04-20 Sudakshina Das <sudi.das@arm.com>
287
288 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
289 (aarch64_feature_ras, RAS): Likewise.
290 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
291 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
292 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
293 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
294 * aarch64-asm-2.c: Regenerated.
295 * aarch64-dis-2.c: Regenerated.
296 * aarch64-opc-2.c: Regenerated.
297
e409955d
FS		 2982020-04-17 Fredrik Strupe <fredrik@strupe.net>
299
300 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
301 (print_insn_neon): Support disassembly of conditional
302 instructions.
303
c54a9b56
DF		 3042020-02-16 David Faust <david.faust@oracle.com>
305
306 * bpf-desc.c: Regenerate.
307 * bpf-desc.h: Likewise.
308 * bpf-opc.c: Regenerate.
309 * bpf-opc.h: Likewise.
310
bb651e8b
CL		 3112020-04-07 Lili Cui <lili.cui@intel.com>
312
313 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
314 (prefix_table): New instructions (see prefixes above).
315 (rm_table): Likewise
316 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
317 CPU_ANY_TSXLDTRK_FLAGS.
318 (cpu_flags): Add CpuTSXLDTRK.
319 * i386-opc.h (enum): Add CpuTSXLDTRK.
320 (i386_cpu_flags): Add cputsxldtrk.
321 * i386-opc.tbl: Add XSUSPLDTRK insns.
322 * i386-init.h: Regenerate.
323 * i386-tbl.h: Likewise.
324
4b27d27c
L		 3252020-04-02 Lili Cui <lili.cui@intel.com>
326
327 * i386-dis.c (prefix_table): New instructions serialize.
328 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
329 CPU_ANY_SERIALIZE_FLAGS.
330 (cpu_flags): Add CpuSERIALIZE.
331 * i386-opc.h (enum): Add CpuSERIALIZE.
332 (i386_cpu_flags): Add cpuserialize.
333 * i386-opc.tbl: Add SERIALIZE insns.
334 * i386-init.h: Regenerate.
335 * i386-tbl.h: Likewise.
336
832a5807
AM		 3372020-03-26 Alan Modra <amodra@gmail.com>
338
339 * disassemble.h (opcodes_assert): Declare.
340 (OPCODES_ASSERT): Define.
341 * disassemble.c: Don't include assert.h. Include opintl.h.
342 (opcodes_assert): New function.
343 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
344 (bfd_h8_disassemble): Reduce size of data array. Correctly
345 calculate maxlen. Omit insn decoding when insn length exceeds
346 maxlen. Exit from nibble loop when looking for E, before
347 accessing next data byte. Move processing of E outside loop.
348 Replace tests of maxlen in loop with assertions.
349
4c4addbe
AM		 3502020-03-26 Alan Modra <amodra@gmail.com>
351
352 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
353
a18cd0ca
AM		 3542020-03-25 Alan Modra <amodra@gmail.com>
355
356 * z80-dis.c (suffix): Init mybuf.
357
57cb32b3
AM		 3582020-03-22 Alan Modra <amodra@gmail.com>
359
360 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
361 successflly read from section.
362
beea5cc1
AM		 3632020-03-22 Alan Modra <amodra@gmail.com>
364
365 * arc-dis.c (find_format): Use ISO C string concatenation rather
366 than line continuation within a string. Don't access needs_limm
367 before testing opcode != NULL.
368
03704c77
AM		 3692020-03-22 Alan Modra <amodra@gmail.com>
370
371 * ns32k-dis.c (print_insn_arg): Update comment.
372 (print_insn_ns32k): Reduce size of index_offset array, and
373 initialize, passing -1 to print_insn_arg for args that are not
374 an index. Don't exit arg loop early. Abort on bad arg number.
375
d1023b5d
AM		 3762020-03-22 Alan Modra <amodra@gmail.com>
377
378 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
379 * s12z-opc.c: Formatting.
380 (operands_f): Return an int.
381 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
382 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
383 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
384 (exg_sex_discrim): Likewise.
385 (create_immediate_operand, create_bitfield_operand),
386 (create_register_operand_with_size, create_register_all_operand),
387 (create_register_all16_operand, create_simple_memory_operand),
388 (create_memory_operand, create_memory_auto_operand): Don't
389 segfault on malloc failure.
390 (z_ext24_decode): Return an int status, negative on fail, zero
391 on success.
392 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
393 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
394 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
395 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
396 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
397 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
398 (loop_primitive_decode, shift_decode, psh_pul_decode),
399 (bit_field_decode): Similarly.
400 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
401 to return value, update callers.
402 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
403 Don't segfault on NULL operand.
404 (decode_operation): Return OP_INVALID on first fail.
405 (decode_s12z): Check all reads, returning -1 on fail.
406
340f3ac8
AM		 4072020-03-20 Alan Modra <amodra@gmail.com>
408
409 * metag-dis.c (print_insn_metag): Don't ignore status from
410 read_memory_func.
411
fe90ae8a
AM		 4122020-03-20 Alan Modra <amodra@gmail.com>
413
414 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
415 Initialize parts of buffer not written when handling a possible
416 2-byte insn at end of section. Don't attempt decoding of such
417 an insn by the 4-byte machinery.
418
833d919c
AM		 4192020-03-20 Alan Modra <amodra@gmail.com>
420
421 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
422 partially filled buffer. Prevent lookup of 4-byte insns when
423 only VLE 2-byte insns are possible due to section size. Print
424 ".word" rather than ".long" for 2-byte leftovers.
425
327ef784
NC		 4262020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
427
428 PR 25641
429 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
430
1673df32
JB		 4312020-03-13 Jan Beulich <jbeulich@suse.com>
432
433 * i386-dis.c (X86_64_0D): Rename to ...
434 (X86_64_0E): ... this.
435
384f3689
L		 4362020-03-09 H.J. Lu <hongjiu.lu@intel.com>
437
438 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
439 * Makefile.in: Regenerated.
440
865e2027
JB		 4412020-03-09 Jan Beulich <jbeulich@suse.com>
442
443 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
444 3-operand pseudos.
445 * i386-tbl.h: Re-generate.
446
2f13234b
JB		 4472020-03-09 Jan Beulich <jbeulich@suse.com>
448
449 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
450 vprot*, vpsha*, and vpshl*.
451 * i386-tbl.h: Re-generate.
452
3fabc179
JB		 4532020-03-09 Jan Beulich <jbeulich@suse.com>
454
455 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
456 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
457 * i386-tbl.h: Re-generate.
458
3677e4c1
JB		 4592020-03-09 Jan Beulich <jbeulich@suse.com>
460
461 * i386-gen.c (set_bitfield): Ignore zero-length field names.
462 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
463 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
464 * i386-tbl.h: Re-generate.
465
4c4898e8
JB		 4662020-03-09 Jan Beulich <jbeulich@suse.com>
467
468 * i386-gen.c (struct template_arg, struct template_instance,
469 struct template_param, struct template, templates,
470 parse_template, expand_templates): New.
471 (process_i386_opcodes): Various local variables moved to
472 expand_templates. Call parse_template and expand_templates.
473 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
474 * i386-tbl.h: Re-generate.
475
bc49bfd8
JB		 4762020-03-06 Jan Beulich <jbeulich@suse.com>
477
478 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
479 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
480 register and memory source templates. Replace VexW= by VexW*
481 where applicable.
482 * i386-tbl.h: Re-generate.
483
4873e243
JB		 4842020-03-06 Jan Beulich <jbeulich@suse.com>
485
486 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
487 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
488 * i386-tbl.h: Re-generate.
489
672a349b
JB		 4902020-03-06 Jan Beulich <jbeulich@suse.com>
491
492 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
493 * i386-tbl.h: Re-generate.
494
4ed21b58
JB		 4952020-03-06 Jan Beulich <jbeulich@suse.com>
496
497 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
498 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
499 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
500 VexW0 on SSE2AVX variants.
501 (vmovq): Drop NoRex64 from XMM/XMM variants.
502 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
503 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
504 applicable use VexW0.
505 * i386-tbl.h: Re-generate.
506
643bb870
JB		 5072020-03-06 Jan Beulich <jbeulich@suse.com>
508
509 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
510 * i386-opc.h (Rex64): Delete.
511 (struct i386_opcode_modifier): Remove rex64 field.
512 * i386-opc.tbl (crc32): Drop Rex64.
513 Replace Rex64 with Size64 everywhere else.
514 * i386-tbl.h: Re-generate.
515
a23b33b3
JB		 5162020-03-06 Jan Beulich <jbeulich@suse.com>
517
518 * i386-dis.c (OP_E_memory): Exclude recording of used address
519 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
520 addressed memory operands for MPX insns.
521
a0497384
JB		 5222020-03-06 Jan Beulich <jbeulich@suse.com>
523
524 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
525 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
526 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
527 (ptwrite): Split into non-64-bit and 64-bit forms.
528 * i386-tbl.h: Re-generate.
529
b630c145
JB		 5302020-03-06 Jan Beulich <jbeulich@suse.com>
531
532 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
533 template.
534 * i386-tbl.h: Re-generate.
535
a847e322
JB		 5362020-03-04 Jan Beulich <jbeulich@suse.com>
537
538 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
539 (prefix_table): Move vmmcall here. Add vmgexit.
540 (rm_table): Replace vmmcall entry by prefix_table[] escape.
541 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
542 (cpu_flags): Add CpuSEV_ES entry.
543 * i386-opc.h (CpuSEV_ES): New.
544 (union i386_cpu_flags): Add cpusev_es field.
545 * i386-opc.tbl (vmgexit): New.
546 * i386-init.h, i386-tbl.h: Re-generate.
547
3cd7f3e3
L		 5482020-03-03 H.J. Lu <hongjiu.lu@intel.com>
549
550 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
551 with MnemonicSize.
552 * i386-opc.h (IGNORESIZE): New.
553 (DEFAULTSIZE): Likewise.
554 (IgnoreSize): Removed.
555 (DefaultSize): Likewise.
556 (MnemonicSize): New.
557 (i386_opcode_modifier): Replace ignoresize/defaultsize with
558 mnemonicsize.
559 * i386-opc.tbl (IgnoreSize): New.
560 (DefaultSize): Likewise.
561 * i386-tbl.h: Regenerated.
562
b8ba1385
SB		 5632020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
564
565 PR 25627
566 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
567 instructions.
568
10d97a0f
L		 5692020-03-03 H.J. Lu <hongjiu.lu@intel.com>
570
571 PR gas/25622
572 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
573 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
574 * i386-tbl.h: Regenerated.
575
dc1e8a47
AM		 5762020-02-26 Alan Modra <amodra@gmail.com>
577
578 * aarch64-asm.c: Indent labels correctly.
579 * aarch64-dis.c: Likewise.
580 * aarch64-gen.c: Likewise.
581 * aarch64-opc.c: Likewise.
582 * alpha-dis.c: Likewise.
583 * i386-dis.c: Likewise.
584 * nds32-asm.c: Likewise.
585 * nfp-dis.c: Likewise.
586 * visium-dis.c: Likewise.
587
265b4673
CZ		 5882020-02-25 Claudiu Zissulescu <claziss@gmail.com>
589
590 * arc-regs.h (int_vector_base): Make it available for all ARC
591 CPUs.
592
bd0cf5a6
NC		 5932020-02-20 Nelson Chu <nelson.chu@sifive.com>
594
595 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
596 changed.
597
fa164239
JW		 5982020-02-19 Nelson Chu <nelson.chu@sifive.com>
599
600 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
601 c.mv/c.li if rs1 is zero.
602
272a84b1
L		 6032020-02-17 H.J. Lu <hongjiu.lu@intel.com>
604
605 * i386-gen.c (cpu_flag_init): Replace CpuABM with
606 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
607 CPU_POPCNT_FLAGS.
608 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
609 * i386-opc.h (CpuABM): Removed.
610 (CpuPOPCNT): New.
611 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
612 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
613 popcnt. Remove CpuABM from lzcnt.
614 * i386-init.h: Regenerated.
615 * i386-tbl.h: Likewise.
616
1f730c46
JB		 6172020-02-17 Jan Beulich <jbeulich@suse.com>
618
619 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
620 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
621 VexW1 instead of open-coding them.
622 * i386-tbl.h: Re-generate.
623
c8f8eebc
JB		 6242020-02-17 Jan Beulich <jbeulich@suse.com>
625
626 * i386-opc.tbl (AddrPrefixOpReg): Define.
627 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
628 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
629 templates. Drop NoRex64.
630 * i386-tbl.h: Re-generate.
631
b9915cbc
JB		 6322020-02-17 Jan Beulich <jbeulich@suse.com>
633
634 PR gas/6518
635 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
636 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
637 into Intel syntax instance (with Unpsecified) and AT&T one
638 (without).
639 (vcvtneps2bf16): Likewise, along with folding the two so far
640 separate ones.
641 * i386-tbl.h: Re-generate.
642
ce504911
L		 6432020-02-16 H.J. Lu <hongjiu.lu@intel.com>
644
645 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
646 CPU_ANY_SSE4A_FLAGS.
647
dabec65d
AM		 6482020-02-17 Alan Modra <amodra@gmail.com>
649
650 * i386-gen.c (cpu_flag_init): Correct last change.
651
af5c13b0
L		 6522020-02-16 H.J. Lu <hongjiu.lu@intel.com>
653
654 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
655 CPU_ANY_SSE4_FLAGS.
656
6867aac0
L		 6572020-02-14 H.J. Lu <hongjiu.lu@intel.com>
658
659 * i386-opc.tbl (movsx): Remove Intel syntax comments.
660 (movzx): Likewise.
661
65fca059
JB		 6622020-02-14 Jan Beulich <jbeulich@suse.com>
663
664 PR gas/25438
665 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
666 destination for Cpu64-only variant.
667 (movzx): Fold patterns.
668 * i386-tbl.h: Re-generate.
669
7deea9aa
JB		 6702020-02-13 Jan Beulich <jbeulich@suse.com>
671
672 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
673 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
674 CPU_ANY_SSE4_FLAGS entry.
675 * i386-init.h: Re-generate.
676
6c0946d0
JB		 6772020-02-12 Jan Beulich <jbeulich@suse.com>
678
679 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
680 with Unspecified, making the present one AT&T syntax only.
681 * i386-tbl.h: Re-generate.
682
ddb56fe6
JB		 6832020-02-12 Jan Beulich <jbeulich@suse.com>
684
685 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
686 * i386-tbl.h: Re-generate.
687
5990e377
JB		 6882020-02-12 Jan Beulich <jbeulich@suse.com>
689
690 PR gas/24546
691 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
692 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
693 Amd64 and Intel64 templates.
694 (call, jmp): Likewise for far indirect variants. Dro
695 Unspecified.
696 * i386-tbl.h: Re-generate.
697
50128d0c
JB		 6982020-02-11 Jan Beulich <jbeulich@suse.com>
699
700 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
701 * i386-opc.h (ShortForm): Delete.
702 (struct i386_opcode_modifier): Remove shortform field.
703 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
704 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
705 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
706 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
707 Drop ShortForm.
708 * i386-tbl.h: Re-generate.
709
1e05b5c4
JB		 7102020-02-11 Jan Beulich <jbeulich@suse.com>
711
712 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
713 fucompi): Drop ShortForm from operand-less templates.
714 * i386-tbl.h: Re-generate.
715
2f5dd314
AM		 7162020-02-11 Alan Modra <amodra@gmail.com>
717
718 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
719 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
720 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
721 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
722 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
723
5aae9ae9
MM		 7242020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
725
726 * arm-dis.c (print_insn_cde): Define 'V' parse character.
727 (cde_opcodes): Add VCX* instructions.
728
4934a27c
MM		 7292020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
730 Matthew Malcomson <matthew.malcomson@arm.com>
731
732 * arm-dis.c (struct cdeopcode32): New.
733 (CDE_OPCODE): New macro.
734 (cde_opcodes): New disassembly table.
735 (regnames): New option to table.
736 (cde_coprocs): New global variable.
737 (print_insn_cde): New
738 (print_insn_thumb32): Use print_insn_cde.
739 (parse_arm_disassembler_options): Parse coprocN args.
740
4b5aaf5f
L		 7412020-02-10 H.J. Lu <hongjiu.lu@intel.com>
742
743 PR gas/25516
744 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
745 with ISA64.
746 * i386-opc.h (AMD64): Removed.
747 (Intel64): Likewose.
748 (AMD64): New.
749 (INTEL64): Likewise.
750 (INTEL64ONLY): Likewise.
751 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
752 * i386-opc.tbl (Amd64): New.
753 (Intel64): Likewise.
754 (Intel64Only): Likewise.
755 Replace AMD64 with Amd64. Update sysenter/sysenter with
756 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
757 * i386-tbl.h: Regenerated.
758
9fc0b501
SB		 7592020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
760
761 PR 25469
762 * z80-dis.c: Add support for GBZ80 opcodes.
763
c5d7be0c
AM		 7642020-02-04 Alan Modra <amodra@gmail.com>
765
766 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
767
44e4546f
AM		 7682020-02-03 Alan Modra <amodra@gmail.com>
769
770 * m32c-ibld.c: Regenerate.
771
b2b1453a
AM		 7722020-02-01 Alan Modra <amodra@gmail.com>
773
774 * frv-ibld.c: Regenerate.
775
4102be5c
JB		 7762020-01-31 Jan Beulich <jbeulich@suse.com>
777
778 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
779 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
780 (OP_E_memory): Replace xmm_mdq_mode case label by
781 vex_scalar_w_dq_mode one.
782 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
783
825bd36c
JB		 7842020-01-31 Jan Beulich <jbeulich@suse.com>
785
786 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
787 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
788 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
789 (intel_operand_size): Drop vex_w_dq_mode case label.
790
c3036ed0
RS		 7912020-01-31 Richard Sandiford <richard.sandiford@arm.com>
792
793 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
794 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
795
0c115f84
AM		 7962020-01-30 Alan Modra <amodra@gmail.com>
797
798 * m32c-ibld.c: Regenerate.
799
bd434cc4
JM		 8002020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
801
802 * bpf-opc.c: Regenerate.
803
aeab2b26
JB		 8042020-01-30 Jan Beulich <jbeulich@suse.com>
805
806 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
807 (dis386): Use them to replace C2/C3 table entries.
808 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
809 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
810 ones. Use Size64 instead of DefaultSize on Intel64 ones.
811 * i386-tbl.h: Re-generate.
812
62b3f548
JB		 8132020-01-30 Jan Beulich <jbeulich@suse.com>
814
815 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
816 forms.
817 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
818 DefaultSize.
819 * i386-tbl.h: Re-generate.
820
1bd8ae10
AM		 8212020-01-30 Alan Modra <amodra@gmail.com>
822
823 * tic4x-dis.c (tic4x_dp): Make unsigned.
824
bc31405e
L		 8252020-01-27 H.J. Lu <hongjiu.lu@intel.com>
826 Jan Beulich <jbeulich@suse.com>
827
828 PR binutils/25445
829 * i386-dis.c (MOVSXD_Fixup): New function.
830 (movsxd_mode): New enum.
831 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
832 (intel_operand_size): Handle movsxd_mode.
833 (OP_E_register): Likewise.
834 (OP_G): Likewise.
835 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
836 register on movsxd. Add movsxd with 16-bit destination register
837 for AMD64 and Intel64 ISAs.
838 * i386-tbl.h: Regenerated.
839
7568c93b
TC		 8402020-01-27 Tamar Christina <tamar.christina@arm.com>
841
842 PR 25403
843 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
844 * aarch64-asm-2.c: Regenerate
845 * aarch64-dis-2.c: Likewise.
846 * aarch64-opc-2.c: Likewise.
847
c006a730
JB		 8482020-01-21 Jan Beulich <jbeulich@suse.com>
849
850 * i386-opc.tbl (sysret): Drop DefaultSize.
851 * i386-tbl.h: Re-generate.
852
c906a69a
JB		 8532020-01-21 Jan Beulich <jbeulich@suse.com>
854
855 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
856 Dword.
857 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
858 * i386-tbl.h: Re-generate.
859
26916852
NC		 8602020-01-20 Nick Clifton <nickc@redhat.com>
861
862 * po/de.po: Updated German translation.
863 * po/pt_BR.po: Updated Brazilian Portuguese translation.
864 * po/uk.po: Updated Ukranian translation.
865
4d6cbb64
AM		 8662020-01-20 Alan Modra <amodra@gmail.com>
867
868 * hppa-dis.c (fput_const): Remove useless cast.
869
2bddb71a
AM		 8702020-01-20 Alan Modra <amodra@gmail.com>
871
872 * arm-dis.c (print_insn_arm): Wrap 'T' value.
873
1b1bb2c6
NC		 8742020-01-18 Nick Clifton <nickc@redhat.com>
875
876 * configure: Regenerate.
877 * po/opcodes.pot: Regenerate.
878
ae774686
NC		 8792020-01-18 Nick Clifton <nickc@redhat.com>
880
881 Binutils 2.34 branch created.
882
07f1f3aa
CB		 8832020-01-17 Christian Biesinger <cbiesinger@google.com>
884
885 * opintl.h: Fix spelling error (seperate).
886
42e04b36
L		 8872020-01-17 H.J. Lu <hongjiu.lu@intel.com>
888
889 * i386-opc.tbl: Add {vex} pseudo prefix.
890 * i386-tbl.h: Regenerated.
891
2da2eaf4
AV		 8922020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
893
894 PR 25376
895 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
896 (neon_opcodes): Likewise.
897 (select_arm_features): Make sure we enable MVE bits when selecting
898 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
899 any architecture.
900
d0849eed
JB		 9012020-01-16 Jan Beulich <jbeulich@suse.com>
902
903 * i386-opc.tbl: Drop stale comment from XOP section.
904
9cf70a44
JB		 9052020-01-16 Jan Beulich <jbeulich@suse.com>
906
907 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
908 (extractps): Add VexWIG to SSE2AVX forms.
909 * i386-tbl.h: Re-generate.
910
4814632e
JB		 9112020-01-16 Jan Beulich <jbeulich@suse.com>
912
913 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
914 Size64 from and use VexW1 on SSE2AVX forms.
915 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
916 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
917 * i386-tbl.h: Re-generate.
918
aad09917
AM		 9192020-01-15 Alan Modra <amodra@gmail.com>
920
921 * tic4x-dis.c (tic4x_version): Make unsigned long.
922 (optab, optab_special, registernames): New file scope vars.
923 (tic4x_print_register): Set up registernames rather than
924 malloc'd registertable.
925 (tic4x_disassemble): Delete optable and optable_special. Use
926 optab and optab_special instead. Throw away old optab,
927 optab_special and registernames when info->mach changes.
928
7a6bf3be
SB		 9292020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
930
931 PR 25377
932 * z80-dis.c (suffix): Use .db instruction to generate double
933 prefix.
934
ca1eaac0
AM		 9352020-01-14 Alan Modra <amodra@gmail.com>
936
937 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
938 values to unsigned before shifting.
939
1d67fe3b
TT		 9402020-01-13 Thomas Troeger <tstroege@gmx.de>
941
942 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
943 flow instructions.
944 (print_insn_thumb16, print_insn_thumb32): Likewise.
945 (print_insn): Initialize the insn info.
946 * i386-dis.c (print_insn): Initialize the insn info fields, and
947 detect jumps.
948
5e4f7e05
CZ		 9492012-01-13 Claudiu Zissulescu <claziss@gmail.com>
950
951 * arc-opc.c (C_NE): Make it required.
952
b9fe6b8a
CZ		 9532012-01-13 Claudiu Zissulescu <claziss@gmail.com>
954
955 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
956 reserved register name.
957
90dee485
AM		 9582020-01-13 Alan Modra <amodra@gmail.com>
959
960 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
961 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
962
febda64f
AM		 9632020-01-13 Alan Modra <amodra@gmail.com>
964
965 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
966 result of wasm_read_leb128 in a uint64_t and check that bits
967 are not lost when copying to other locals. Use uint32_t for
968 most locals. Use PRId64 when printing int64_t.
969
df08b588
AM		 9702020-01-13 Alan Modra <amodra@gmail.com>
971
972 * score-dis.c: Formatting.
973 * score7-dis.c: Formatting.
974
b2c759ce
AM		 9752020-01-13 Alan Modra <amodra@gmail.com>
976
977 * score-dis.c (print_insn_score48): Use unsigned variables for
978 unsigned values. Don't left shift negative values.
979 (print_insn_score32): Likewise.
980 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
981
5496abe1
AM		 9822020-01-13 Alan Modra <amodra@gmail.com>
983
984 * tic4x-dis.c (tic4x_print_register): Remove dead code.
985
202e762b
AM		 9862020-01-13 Alan Modra <amodra@gmail.com>
987
988 * fr30-ibld.c: Regenerate.
989
7ef412cf
AM		 9902020-01-13 Alan Modra <amodra@gmail.com>
991
992 * xgate-dis.c (print_insn): Don't left shift signed value.
993 (ripBits): Formatting, use 1u.
994
7f578b95
AM		 9952020-01-10 Alan Modra <amodra@gmail.com>
996
997 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
998 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
999
441af85b
AM		 10002020-01-10 Alan Modra <amodra@gmail.com>
1001
1002 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1003 and XRREG value earlier to avoid a shift with negative exponent.
1004 * m10200-dis.c (disassemble): Similarly.
1005
bce58db4
NC		 10062020-01-09 Nick Clifton <nickc@redhat.com>
1007
1008 PR 25224
1009 * z80-dis.c (ld_ii_ii): Use correct cast.
1010
40c75bc8
SB		 10112020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1012
1013 PR 25224
1014 * z80-dis.c (ld_ii_ii): Use character constant when checking
1015 opcode byte value.
1016
d835a58b
JB		 10172020-01-09 Jan Beulich <jbeulich@suse.com>
1018
1019 * i386-dis.c (SEP_Fixup): New.
1020 (SEP): Define.
1021 (dis386_twobyte): Use it for sysenter/sysexit.
1022 (enum x86_64_isa): Change amd64 enumerator to value 1.
1023 (OP_J): Compare isa64 against intel64 instead of amd64.
1024 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1025 forms.
1026 * i386-tbl.h: Re-generate.
1027
030a2e78
AM		 10282020-01-08 Alan Modra <amodra@gmail.com>
1029
1030 * z8k-dis.c: Include libiberty.h
1031 (instr_data_s): Make max_fetched unsigned.
1032 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1033 Don't exceed byte_info bounds.
1034 (output_instr): Make num_bytes unsigned.
1035 (unpack_instr): Likewise for nibl_count and loop.
1036 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1037 idx unsigned.
1038 * z8k-opc.h: Regenerate.
1039
bb82aefe
SV		 10402020-01-07 Shahab Vahedi <shahab@synopsys.com>
1041
1042 * arc-tbl.h (llock): Use 'LLOCK' as class.
1043 (llockd): Likewise.
1044 (scond): Use 'SCOND' as class.
1045 (scondd): Likewise.
1046 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1047 (scondd): Likewise.
1048
cc6aa1a6
AM		 10492020-01-06 Alan Modra <amodra@gmail.com>
1050
1051 * m32c-ibld.c: Regenerate.
1052
660e62b1
AM		 10532020-01-06 Alan Modra <amodra@gmail.com>
1054
1055 PR 25344
1056 * z80-dis.c (suffix): Don't use a local struct buffer copy.
1057 Peek at next byte to prevent recursion on repeated prefix bytes.
1058 Ensure uninitialised "mybuf" is not accessed.
1059 (print_insn_z80): Don't zero n_fetch and n_used here,..
1060 (print_insn_z80_buf): ..do it here instead.
1061
c9ae58fe
AM		 10622020-01-04 Alan Modra <amodra@gmail.com>
1063
1064 * m32r-ibld.c: Regenerate.
1065
5f57d4ec
AM		 10662020-01-04 Alan Modra <amodra@gmail.com>
1067
1068 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1069
2c5c1196
AM		 10702020-01-04 Alan Modra <amodra@gmail.com>
1071
1072 * crx-dis.c (match_opcode): Avoid shift left of signed value.
1073
2e98c6c5
AM		 10742020-01-04 Alan Modra <amodra@gmail.com>
1075
1076 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1077
567dfba2
JB		 10782020-01-03 Jan Beulich <jbeulich@suse.com>
1079
5437a02a
JB		 1080 * aarch64-tbl.h (aarch64_opcode_table): Use
1081 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1082
10832020-01-03 Jan Beulich <jbeulich@suse.com>
1084
1085 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB		 1086 forms of SUDOT and USDOT.
1087
8c45011a
JB		 10882020-01-03 Jan Beulich <jbeulich@suse.com>
1089
5437a02a 1090 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a
JB		 1091 uzip{1,2}.
1092 * opcodes/aarch64-dis-2.c: Re-generate.
1093
f4950f76
JB		 10942020-01-03 Jan Beulich <jbeulich@suse.com>
1095
5437a02a 1096 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
JB		 1097 FMMLA encoding.
1098 * opcodes/aarch64-dis-2.c: Re-generate.
1099
6655dba2
SB		 11002020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
1101
1102 * z80-dis.c: Add support for eZ80 and Z80 instructions.
1103
b14ce8bf
AM		 11042020-01-01 Alan Modra <amodra@gmail.com>
1105
1106 Update year range in copyright notice of all files.
1107
0b114740 1108For older changes see ChangeLog-2019
3499769a 1109\f
0b114740 1110Copyright (C) 2020 Free Software Foundation, Inc.
3499769a
AM		 1111
1112Copying and distribution of this file, with or without modification,
1113are permitted in any medium without royalty provided the copyright
1114notice and this notice are preserved.
1115
1116Local Variables:
1117mode: change-log
1118left-margin: 8
1119fill-column: 74
1120version-control: never
1121End:
GDB Binutils - Deliverables
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