Commit | Line | Data |
---|---|---|
1b93226d NC |
1 | 2011-07-12 Nick Clifton <nickc@redhat.com> |
2 | ||
3 | * arm-dis.c (print_insn_arm): Revert previous, undocumented, | |
4 | accidental change. | |
5 | ||
5d73b1f1 NC |
6 | 2011-07-01 Nick Clifton <nickc@redhat.com> |
7 | ||
8 | PR binutils/12329 | |
9 | * avr-dis.c (avr_operand): Fix disassembly of ELPM, LPM and SPM | |
10 | insns using post-increment addressing. | |
11 | ||
182ae480 L |
12 | 2011-06-30 H.J. Lu <hongjiu.lu@intel.com> |
13 | ||
14 | * i386-dis.c (vex_len_table): Update rorxS. | |
15 | ||
4cb0953d L |
16 | 2011-06-30 H.J. Lu <hongjiu.lu@intel.com> |
17 | ||
18 | AVX Programming Reference (June, 2011) | |
19 | * i386-dis.c (vex_len_table): Correct rorxS. | |
20 | ||
21 | * i386-opc.tbl: Correct rorx. | |
22 | * i386-tbl.h: Regenerated. | |
23 | ||
906efcbc L |
24 | 2011-06-29 H.J. Lu <hongjiu.lu@intel.com> |
25 | ||
26 | * tilegx-opc.c (find_opcode): Replace "index" with "i". | |
27 | * tilepro-opc.c (find_opcode): Likewise. | |
28 | ||
ceb94aa5 RS |
29 | 2011-06-29 Richard Sandiford <rdsandiford@googlemail.com> |
30 | ||
31 | * mips16-opc.c (jalrc, jrc): Move earlier in file. | |
32 | ||
f7002f42 L |
33 | 2011-06-21 H.J. Lu <hongjiu.lu@intel.com> |
34 | ||
35 | * i386-dis.c (prefix_table): Re-indent PREFIX_VEX_0F388C and | |
36 | PREFIX_VEX_0F388E. | |
37 | ||
56300268 AS |
38 | 2011-06-17 Andreas Schwab <schwab@redhat.com> |
39 | ||
40 | * Makefile.am (MAINTAINERCLEANFILES): Move s390-opc.tab ... | |
41 | (MOSTLYCLEANFILES): ... here. | |
42 | * Makefile.in: Regenerate. | |
43 | ||
bcf2cf9f AM |
44 | 2011-06-14 Alan Modra <amodra@gmail.com> |
45 | ||
46 | * Makefile.in: Regenerate. | |
47 | ||
aa137e4d NC |
48 | 2011-06-13 Walter Lee <walt@tilera.com> |
49 | ||
50 | * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c, | |
51 | tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c. | |
52 | * Makefile.in: Regenerate. | |
53 | * configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch. | |
54 | * configure: Regenerate. | |
55 | * disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro. | |
56 | * po/POTFILES.in: Regenerate. | |
57 | * tilegx-dis.c: New file. | |
58 | * tilegx-opc.c: New file. | |
59 | * tilepro-dis.c: New file. | |
60 | * tilepro-opc.c: New file. | |
61 | ||
6c30d220 L |
62 | 2011-06-10 H.J. Lu <hongjiu.lu@intel.com> |
63 | ||
64 | AVX Programming Reference (June, 2011) | |
65 | * i386-dis.c (XMGatherQ): New. | |
66 | * i386-dis.c (EXxmm_mb): New. | |
67 | (EXxmm_mb): Likewise. | |
68 | (EXxmm_mw): Likewise. | |
69 | (EXxmm_md): Likewise. | |
70 | (EXxmm_mq): Likewise. | |
71 | (EXxmmdw): Likewise. | |
72 | (EXxmmqd): Likewise. | |
73 | (VexGatherQ): Likewise. | |
74 | (MVexVSIBDWpX): Likewise. | |
75 | (MVexVSIBQWpX): Likewise. | |
76 | (xmm_mb_mode): Likewise. | |
77 | (xmm_mw_mode): Likewise. | |
78 | (xmm_md_mode): Likewise. | |
79 | (xmm_mq_mode): Likewise. | |
80 | (xmmdw_mode): Likewise. | |
81 | (xmmqd_mode): Likewise. | |
82 | (ymmxmm_mode): Likewise. | |
83 | (vex_vsib_d_w_dq_mode): Likewise. | |
84 | (vex_vsib_q_w_dq_mode): Likewise. | |
85 | (MOD_VEX_0F385A_PREFIX_2): Likewise. | |
86 | (MOD_VEX_0F388C_PREFIX_2): Likewise. | |
87 | (MOD_VEX_0F388E_PREFIX_2): Likewise. | |
88 | (PREFIX_0F3882): Likewise. | |
89 | (PREFIX_VEX_0F3816): Likewise. | |
90 | (PREFIX_VEX_0F3836): Likewise. | |
91 | (PREFIX_VEX_0F3845): Likewise. | |
92 | (PREFIX_VEX_0F3846): Likewise. | |
93 | (PREFIX_VEX_0F3847): Likewise. | |
94 | (PREFIX_VEX_0F3858): Likewise. | |
95 | (PREFIX_VEX_0F3859): Likewise. | |
96 | (PREFIX_VEX_0F385A): Likewise. | |
97 | (PREFIX_VEX_0F3878): Likewise. | |
98 | (PREFIX_VEX_0F3879): Likewise. | |
99 | (PREFIX_VEX_0F388C): Likewise. | |
100 | (PREFIX_VEX_0F388E): Likewise. | |
101 | (PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise. | |
102 | (PREFIX_VEX_0F38F5): Likewise. | |
103 | (PREFIX_VEX_0F38F6): Likewise. | |
104 | (PREFIX_VEX_0F3A00): Likewise. | |
105 | (PREFIX_VEX_0F3A01): Likewise. | |
106 | (PREFIX_VEX_0F3A02): Likewise. | |
107 | (PREFIX_VEX_0F3A38): Likewise. | |
108 | (PREFIX_VEX_0F3A39): Likewise. | |
109 | (PREFIX_VEX_0F3A46): Likewise. | |
110 | (PREFIX_VEX_0F3AF0): Likewise. | |
111 | (VEX_LEN_0F3816_P_2): Likewise. | |
112 | (VEX_LEN_0F3819_P_2): Likewise. | |
113 | (VEX_LEN_0F3836_P_2): Likewise. | |
114 | (VEX_LEN_0F385A_P_2_M_0): Likewise. | |
115 | (VEX_LEN_0F38F5_P_0): Likewise. | |
116 | (VEX_LEN_0F38F5_P_1): Likewise. | |
117 | (VEX_LEN_0F38F5_P_3): Likewise. | |
118 | (VEX_LEN_0F38F6_P_3): Likewise. | |
119 | (VEX_LEN_0F38F7_P_1): Likewise. | |
120 | (VEX_LEN_0F38F7_P_2): Likewise. | |
121 | (VEX_LEN_0F38F7_P_3): Likewise. | |
122 | (VEX_LEN_0F3A00_P_2): Likewise. | |
123 | (VEX_LEN_0F3A01_P_2): Likewise. | |
124 | (VEX_LEN_0F3A38_P_2): Likewise. | |
125 | (VEX_LEN_0F3A39_P_2): Likewise. | |
126 | (VEX_LEN_0F3A46_P_2): Likewise. | |
127 | (VEX_LEN_0F3AF0_P_3): Likewise. | |
128 | (VEX_W_0F3816_P_2): Likewise. | |
129 | (VEX_W_0F3818_P_2): Likewise. | |
130 | (VEX_W_0F3819_P_2): Likewise. | |
131 | (VEX_W_0F3836_P_2): Likewise. | |
132 | (VEX_W_0F3846_P_2): Likewise. | |
133 | (VEX_W_0F3858_P_2): Likewise. | |
134 | (VEX_W_0F3859_P_2): Likewise. | |
135 | (VEX_W_0F385A_P_2_M_0): Likewise. | |
136 | (VEX_W_0F3878_P_2): Likewise. | |
137 | (VEX_W_0F3879_P_2): Likewise. | |
138 | (VEX_W_0F3A00_P_2): Likewise. | |
139 | (VEX_W_0F3A01_P_2): Likewise. | |
140 | (VEX_W_0F3A02_P_2): Likewise. | |
141 | (VEX_W_0F3A38_P_2): Likewise. | |
142 | (VEX_W_0F3A39_P_2): Likewise. | |
143 | (VEX_W_0F3A46_P_2): Likewise. | |
144 | (MOD_VEX_0F3818_PREFIX_2): Removed. | |
145 | (MOD_VEX_0F3819_PREFIX_2): Likewise. | |
146 | (VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise. | |
147 | (VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise. | |
148 | (VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise. | |
149 | (VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise. | |
150 | (VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise. | |
151 | (VEX_LEN_0F3A0E_P_2): Likewise. | |
152 | (VEX_LEN_0F3A0F_P_2): Likewise. | |
153 | (VEX_LEN_0F3A42_P_2): Likewise. | |
154 | (VEX_LEN_0F3A4C_P_2): Likewise. | |
155 | (VEX_W_0F3818_P_2_M_0): Likewise. | |
156 | (VEX_W_0F3819_P_2_M_0): Likewise. | |
157 | (prefix_table): Updated. | |
158 | (three_byte_table): Likewise. | |
159 | (vex_table): Likewise. | |
160 | (vex_len_table): Likewise. | |
161 | (vex_w_table): Likewise. | |
162 | (mod_table): Likewise. | |
163 | (putop): Handle "LW". | |
164 | (intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode, | |
165 | xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode, | |
166 | vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode. | |
167 | (OP_EX): Likewise. | |
168 | (OP_E_memory): Handle vex_vsib_d_w_dq_mode and | |
169 | vex_vsib_q_w_dq_mode. | |
170 | (OP_XMM): Handle vex_vsib_q_w_dq_mode. | |
171 | (OP_VEX): Likewise. | |
172 | ||
173 | * i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS | |
174 | and CPU_ANY_AVX_FLAGS. Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS, | |
175 | CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS. | |
176 | (cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID. | |
177 | (opcode_modifiers): Add VecSIB. | |
178 | ||
179 | * i386-opc.h (CpuAVX2): New. | |
180 | (CpuBMI2): Likewise. | |
181 | (CpuLZCNT): Likewise. | |
182 | (CpuINVPCID): Likewise. | |
183 | (VecSIB128): Likewise. | |
184 | (VecSIB256): Likewise. | |
185 | (VecSIB): Likewise. | |
186 | (i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid. | |
187 | (i386_opcode_modifier): Add vecsib. | |
188 | ||
189 | * i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions. | |
190 | * i386-init.h: Regenerated. | |
191 | * i386-tbl.h: Likewise. | |
192 | ||
d535accd QN |
193 | 2011-06-03 Quentin Neill <quentin.neill@amd.com> |
194 | ||
195 | * i386-gen.c (cpu_flag_init): Add CpuF16C to CPU_BDVER2_FLAGS. | |
196 | * i386-init.h: Regenerated. | |
197 | ||
f8b960bc NC |
198 | 2011-06-03 Nick Clifton <nickc@redhat.com> |
199 | ||
200 | PR binutils/12752 | |
201 | * arm-dis.c (print_insn_coprocessor): Use bfd_vma type for | |
202 | computing address offsets. | |
203 | (print_arm_address): Likewise. | |
204 | (print_insn_arm): Likewise. | |
205 | (print_insn_thumb16): Likewise. | |
206 | (print_insn_thumb32): Likewise. | |
207 | ||
26d97720 NS |
208 | 2011-06-02 Jie Zhang <jie@codesourcery.com> |
209 | Nathan Sidwell <nathan@codesourcery.com> | |
210 | Maciej Rozycki <macro@codesourcery.com> | |
211 | ||
212 | * arm-dis.c (print_insn_coprocessor): Explicitly print #-0 | |
213 | as address offset. | |
214 | (print_arm_address): Likewise. Elide positive #0 appropriately. | |
215 | (print_insn_arm): Likewise. | |
216 | ||
f8b960bc NC |
217 | 2011-06-02 Nick Clifton <nickc@redhat.com> |
218 | ||
219 | PR gas/12752 | |
220 | * arm-dis.c (print_insn_thumb32): Do not sign extend addresses | |
221 | passed to print_address_func. | |
222 | ||
cc643b88 NC |
223 | 2011-06-02 Nick Clifton <nickc@redhat.com> |
224 | ||
225 | * arm-dis.c: Fix spelling mistakes. | |
226 | * op/opcodes.pot: Regenerate. | |
227 | ||
c8fa16ed AK |
228 | 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> |
229 | ||
230 | * s390-opc.c: Replace S390_OPERAND_REG_EVEN with | |
231 | S390_OPERAND_REG_PAIR. Fix INSTR_RRF_0UFEF instruction type. | |
232 | * s390-opc.txt: Fix cxr instruction type. | |
233 | ||
5e4b319c AK |
234 | 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> |
235 | ||
236 | * s390-opc.c: Add new instruction types marking register pair | |
237 | operands. | |
238 | * s390-opc.txt: Match instructions having register pair operands | |
239 | to the new instruction types. | |
240 | ||
fda544a2 NC |
241 | 2011-05-19 Nick Clifton <nickc@redhat.com> |
242 | ||
243 | * v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2 | |
244 | operands. | |
245 | ||
4cab4add QN |
246 | 2011-05-10 Quentin Neill <quentin.neill@amd.com> |
247 | ||
248 | * i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS. | |
249 | * i386-init.h: Regenerated. | |
250 | ||
b4e7b885 NC |
251 | 2011-04-27 Nick Clifton <nickc@redhat.com> |
252 | ||
253 | * po/da.po: Updated Danish translation. | |
254 | ||
2f7f7710 AM |
255 | 2011-04-26 Anton Blanchard <anton@samba.org> |
256 | ||
257 | * ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7. | |
258 | ||
9887672f DD |
259 | 2011-04-21 DJ Delorie <dj@redhat.com> |
260 | ||
261 | * rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs. | |
262 | * rx-decode.c: Regenerate. | |
263 | ||
3251b375 L |
264 | 2011-04-20 H.J. Lu <hongjiu.lu@intel.com> |
265 | ||
266 | * i386-init.h: Regenerated. | |
267 | ||
b13a3ca6 QN |
268 | 2011-04-19 Quentin Neill <quentin.neill@amd.com> |
269 | ||
270 | * i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits | |
271 | from bdver1 flags. | |
272 | ||
7d063384 NC |
273 | 2011-04-13 Nick Clifton <nickc@redhat.com> |
274 | ||
275 | * v850-dis.c (disassemble): Always print a closing square brace if | |
276 | an opening square brace was printed. | |
277 | ||
32a94698 NC |
278 | 2011-04-12 Nick Clifton <nickc@redhat.com> |
279 | ||
280 | PR binutils/12534 | |
281 | * arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn | |
282 | patterns. | |
283 | (print_insn_thumb32): Handle %L. | |
284 | ||
d2cd1205 JB |
285 | 2011-04-11 Julian Brown <julian@codesourcery.com> |
286 | ||
287 | * arm-dis.c (psr_name): Fix typo for BASEPRI_MAX. | |
288 | (print_insn_thumb32): Add APSR bitmask support. | |
289 | ||
1fbaefec PB |
290 | 2011-04-07 Paul Carroll<pcarroll@codesourcery.com> |
291 | ||
292 | * arm-dis.c (print_insn): init vars moved into private_data structure. | |
293 | ||
67171547 MF |
294 | 2011-03-24 Mike Frysinger <vapier@gentoo.org> |
295 | ||
296 | * bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic. | |
297 | ||
8cc66334 EW |
298 | 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com> |
299 | ||
300 | * avr-dis.c (avr_operand): Add opcode_str parameter. Check for | |
301 | post-increment to support LPM Z+ instruction. Add support for 'E' | |
302 | constraint for DES instruction. | |
303 | (print_insn_avr): Adjust calls to avr_operand. Rename variable. | |
304 | ||
34e77a92 RS |
305 | 2011-03-14 Richard Sandiford <richard.sandiford@linaro.org> |
306 | ||
307 | * arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code. | |
308 | ||
35fc36a8 RS |
309 | 2011-03-14 Richard Sandiford <richard.sandiford@linaro.org> |
310 | ||
311 | * arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC. | |
312 | Use branch types instead. | |
313 | (print_insn): Likewise. | |
314 | ||
0067d8fc MR |
315 | 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com> |
316 | ||
317 | * mips-opc.c (mips_builtin_opcodes): Correct register use | |
318 | annotation of "alnv.ps". | |
319 | ||
3eebd5eb MR |
320 | 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com> |
321 | ||
322 | * mips-opc.c (mips_builtin_opcodes): Add "pref" macro. | |
323 | ||
500cccad MF |
324 | 2011-02-22 Mike Frysinger <vapier@gentoo.org> |
325 | ||
326 | * bfin-dis.c (OUTS): Remove p NULL check and txt NUL check. | |
327 | ||
f5caf9f4 MF |
328 | 2011-02-22 Mike Frysinger <vapier@gentoo.org> |
329 | ||
330 | * bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS. | |
331 | ||
e5bc4265 MF |
332 | 2011-02-19 Mike Frysinger <vapier@gentoo.org> |
333 | ||
334 | * bfin-dis.c (saved_state): Mark static. Change a[01]x to ax[] and | |
335 | a[01]w to aw[]. Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1, | |
336 | av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts, | |
337 | exception, end_of_registers, msize, memory, bfd_mach. | |
338 | (CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG, | |
339 | LB0REG, LC1REG, LT1REG, LB1REG): Delete | |
340 | (AXREG, AWREG, LCREG, LTREG, LBREG): Define. | |
341 | (get_allreg): Change to new defines. Fallback to abort(). | |
342 | ||
602427c4 MF |
343 | 2011-02-14 Mike Frysinger <vapier@gentoo.org> |
344 | ||
345 | * bfin-dis.c: Add whitespace/parenthesis where needed. | |
346 | ||
298c1ec2 MF |
347 | 2011-02-14 Mike Frysinger <vapier@gentoo.org> |
348 | ||
349 | * bfin-dis.c (decode_LoopSetup_0): Return when reg is greater | |
350 | than 7. | |
351 | ||
822ce8ee RW |
352 | 2011-02-13 Ralf Wildenhues <Ralf.Wildenhues@gmx.de> |
353 | ||
354 | * configure: Regenerate. | |
355 | ||
13c02f06 MF |
356 | 2011-02-13 Mike Frysinger <vapier@gentoo.org> |
357 | ||
358 | * bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg. | |
359 | ||
4db66394 MF |
360 | 2011-02-13 Mike Frysinger <vapier@gentoo.org> |
361 | ||
362 | * bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1. Output | |
363 | dregs only when P is set, and dregs_lo otherwise. | |
364 | ||
36f44611 MF |
365 | 2011-02-13 Mike Frysinger <vapier@gentoo.org> |
366 | ||
367 | * bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code. | |
368 | ||
9805c0a5 MF |
369 | 2011-02-12 Mike Frysinger <vapier@gentoo.org> |
370 | ||
371 | * bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT. | |
372 | ||
43a6aa65 MF |
373 | 2011-02-12 Mike Frysinger <vapier@gentoo.org> |
374 | ||
375 | * bfin-dis.c (machine_registers): Delete REG_GP. | |
376 | (reg_names): Delete "GP". | |
377 | (decode_allregs): Change REG_GP to REG_LASTREG. | |
378 | ||
26bb3ddd MF |
379 | 2011-02-12 Mike Frysinger <vapier@gentoo.org> |
380 | ||
89c0d58c MR |
381 | * bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, |
382 | M_IH, M_IU): Delete. | |
26bb3ddd | 383 | |
69b8ea4a MF |
384 | 2011-02-11 Mike Frysinger <vapier@gentoo.org> |
385 | ||
386 | * bfin-dis.c (reg_names): Add const. | |
387 | (decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte, | |
388 | decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs, | |
389 | decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits, | |
390 | decode_counters, decode_allregs): Likewise. | |
391 | ||
42d5f9c6 MS |
392 | 2011-02-09 Michael Snyder <msnyder@vmware.com> |
393 | ||
56300268 | 394 | * i386-dis.c (OP_J): Parenthesize expression to prevent |
42d5f9c6 MS |
395 | truncated addresses. |
396 | (print_insn): Fix indentation off-by-one. | |
397 | ||
4be0c941 NC |
398 | 2011-02-01 Nick Clifton <nickc@redhat.com> |
399 | ||
400 | * po/da.po: Updated Danish translation. | |
401 | ||
6b069ee7 AM |
402 | 2011-01-21 Dave Murphy <davem@devkitpro.org> |
403 | ||
404 | * ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS. | |
405 | ||
e3949f17 L |
406 | 2011-01-18 H.J. Lu <hongjiu.lu@intel.com> |
407 | ||
408 | * i386-dis.c (sIbT): New. | |
409 | (b_T_mode): Likewise. | |
410 | (dis386): Replace sIb with sIbT on "pushT". | |
411 | (x86_64_table): Replace sIb with Ib on "aam" and "aad". | |
412 | (OP_sI): Handle b_T_mode. Properly sign-extend byte. | |
413 | ||
752573b2 JK |
414 | 2011-01-18 Jan Kratochvil <jan.kratochvil@redhat.com> |
415 | ||
416 | * i386-init.h: Regenerated. | |
417 | * i386-tbl.h: Regenerated | |
418 | ||
2a2a0f38 QN |
419 | 2011-01-17 Quentin Neill <quentin.neill@amd.com> |
420 | ||
421 | * i386-dis.c (REG_XOP_TBM_01): New. | |
422 | (REG_XOP_TBM_02): New. | |
423 | (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables. | |
424 | (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02 | |
425 | entries, and add bextr instruction. | |
426 | ||
427 | * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM. | |
428 | (cpu_flags): Add CpuTBM. | |
429 | ||
430 | * i386-opc.h (CpuTBM) New. | |
431 | (i386_cpu_flags): Add bit cputbm. | |
432 | ||
433 | * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk, | |
434 | blcs, blsfill, blsic, t1mskc, and tzmsk. | |
435 | ||
90d6ff62 DD |
436 | 2011-01-12 DJ Delorie <dj@redhat.com> |
437 | ||
438 | * rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg. | |
439 | ||
c95354ed MX |
440 | 2011-01-11 Mingjie Xing <mingjie.xing@gmail.com> |
441 | ||
442 | * mips-dis.c (print_insn_args): Adjust the value to print the real | |
443 | offset for "+c" argument. | |
444 | ||
f7465604 NC |
445 | 2011-01-10 Nick Clifton <nickc@redhat.com> |
446 | ||
447 | * po/da.po: Updated Danish translation. | |
448 | ||
639e30d2 NS |
449 | 2011-01-05 Nathan Sidwell <nathan@codesourcery.com> |
450 | ||
451 | * arm-dis.c (thumb32_opcodes): BLX must have bit zero clear. | |
452 | ||
f12dc422 L |
453 | 2011-01-04 H.J. Lu <hongjiu.lu@intel.com> |
454 | ||
455 | * i386-dis.c (REG_VEX_38F3): New. | |
456 | (PREFIX_0FBC): Likewise. | |
457 | (PREFIX_VEX_38F2): Likewise. | |
458 | (PREFIX_VEX_38F3_REG_1): Likewise. | |
459 | (PREFIX_VEX_38F3_REG_2): Likewise. | |
460 | (PREFIX_VEX_38F3_REG_3): Likewise. | |
461 | (PREFIX_VEX_38F7): Likewise. | |
462 | (VEX_LEN_38F2_P_0): Likewise. | |
463 | (VEX_LEN_38F3_R_1_P_0): Likewise. | |
464 | (VEX_LEN_38F3_R_2_P_0): Likewise. | |
465 | (VEX_LEN_38F3_R_3_P_0): Likewise. | |
466 | (VEX_LEN_38F7_P_0): Likewise. | |
467 | (dis386_twobyte): Use PREFIX_0FBC. | |
468 | (reg_table): Add REG_VEX_38F3. | |
469 | (prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2, | |
470 | PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2, | |
471 | PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7. | |
472 | (vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and | |
473 | PREFIX_VEX_38F7. | |
474 | (vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0, | |
475 | VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and | |
476 | VEX_LEN_38F7_P_0. | |
477 | ||
478 | * i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS. | |
479 | (cpu_flags): Add CpuBMI. | |
480 | ||
481 | * i386-opc.h (CpuBMI): New. | |
482 | (i386_cpu_flags): Add cpubmi. | |
483 | ||
484 | * i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt. | |
485 | * i386-init.h: Regenerated. | |
486 | * i386-tbl.h: Likewise. | |
487 | ||
cb21baef L |
488 | 2011-01-04 H.J. Lu <hongjiu.lu@intel.com> |
489 | ||
490 | * i386-dis.c (VexGdq): New. | |
491 | (OP_VEX): Handle dq_mode. | |
492 | ||
0db46eb4 L |
493 | 2011-01-01 H.J. Lu <hongjiu.lu@intel.com> |
494 | ||
495 | * i386-gen.c (process_copyright): Update copyright to 2011. | |
496 | ||
9e9e0820 | 497 | For older changes see ChangeLog-2010 |
252b5132 RH |
498 | \f |
499 | Local Variables: | |
2f6d2f85 NC |
500 | mode: change-log |
501 | left-margin: 8 | |
502 | fill-column: 74 | |
252b5132 RH |
503 | version-control: never |
504 | End: |