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Add function and function pointer tests
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
14f195c9
IT		 12014-11-17 Ilya Tocar <ilya.tocar@intel.com>
2
3 * i386-dis-evex.c (evex_table): Add vpermi2b, vpermt2b, vpermb,
4 vpmultishiftqb.
5 * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F3883, EVEX_W_0F3883_P_2.
6 * i386-gen.c (cpu_flag_init): Add CPU_AVX512VBMI_FLAGS.
7 (cpu_flags): Add CpuAVX512VBMI.
8 * i386-opc.h (enum): Add CpuAVX512VBMI.
9 (i386_cpu_flags): Add cpuavx512vbmi.
10 * i386-opc.tbl: Add vpmadd52luq, vpmultishiftqb, vpermb, vpermi2b,
11 vpermt2b.
12 * i386-init.h: Regenerated.
13 * i386-tbl.h: Likewise.
14
2cc1b5aa
IT		 152014-11-17 Ilya Tocar <ilya.tocar@intel.com>
16
17 * i386-dis-evex.c (evex_table): Add vpmadd52luq, vpmadd52huq.
18 * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F38B4,
19 PREFIX_EVEX_0F38B5.
20 * i386-gen.c (cpu_flag_init): Add CPU_AVX512IFMA_FLAGS.
21 (cpu_flags): Add CpuAVX512IFMA.
22 * i386-opc.h (enum): Add CpuAVX512IFMA.
23 (i386_cpu_flags): Add cpuavx512ifma.
24 * i386-opc.tbl: Add vpmadd52huq, vpmadd52luq.
25 * i386-init.h: Regenerated.
26 * i386-tbl.h: Likewise.
27
9d8596f0
IT		 282014-11-17 Ilya Tocar <ilya.tocar@intel.com>
29
30 * i386-dis.c (PREFIX enum): Add PREFIX_RM_0_0FAE_REG_7.
31 (prefix_table): Add pcommit.
32 * i386-gen.c (cpu_flag_init): Add CPU_PCOMMIT_FLAGS.
33 (cpu_flags): Add CpuPCOMMIT.
34 * i386-opc.h (enum): Add CpuPCOMMIT.
35 (i386_cpu_flags): Add cpupcommit.
36 * i386-opc.tbl: Add pcommit.
37 * i386-init.h: Regenerated.
38 * i386-tbl.h: Likewise.
39
c5e7287a
IT		 402014-11-17 Ilya Tocar <ilya.tocar@intel.com>
41
42 * i386-dis.c (PREFIX enum): Add PREFIX_0FAE_REG_6.
43 (prefix_table): Add clwb.
44 * i386-gen.c (cpu_flag_init): Add CPU_CLWB_FLAGS.
45 (cpu_flags): Add CpuCLWB.
46 * i386-opc.h (enum): Add CpuCLWB.
47 (i386_cpu_flags): Add cpuclwb.
48 * i386-opc.tbl: Add clwb.
49 * i386-init.h: Regenerated.
50 * i386-tbl.h: Likewise.
51
b4714c7c
SL		 522014-11-06 Sandra Loosemore <sandra@codesourcery.com>
53
54 * nios2-dis.c (nios2_find_opcode_hash): Add mach parameter.
55 (nios2_disassemble): Adjust call to nios2_find_opcode_hash.
56
ba241f2d
NC		 572014-11-03 Nick Clifton <nickc@redhat.com>
58
59 * po/fi.po: Updated Finnish translation.
60
2c629856
N		 612014-10-31 Andrew Pinski <apinski@cavium.com>
62 Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
63
64 * mips-dis.c (mips_arch_choices): Add octeon3.
65 * mips-opc.c (IOCT): Include INSN_OCTEON3.
66 (IOCT2): Likewise.
67 (IOCT3): New define.
68 (IVIRT): New define.
69 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
70 tlbinv, tlbinvf, tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp, tlti
71 IVIRT instructions.
72 Extend mtm0, mtm1, mtm2, mtp0, mtp1, mtp2 instructions to take another
73 operand for IOCT3.
74
64b588b5
NC		 752014-10-29 Nick Clifton <nickc@redhat.com>
76
77 * po/de.po: Updated German translation.
78
96ba4233
SL		 792014-10-23 Sandra Loosemore <sandra@codesourcery.com>
80
81 * nios2-opc.c (nios2_builtin_regs): Add regtype field initializers.
82 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes. Use new
83 MATCH_R1_<insn> and MASK_R1_<insn> macros in initializers. Add
84 size and format initializers. Merge 'b' arguments into 'j'.
85 (NIOS2_NUM_OPCODES): Adjust definition.
86 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
87 (nios2_opcodes): Adjust.
88 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
89 * nios2-dis.c (INSNLEN): Update comment.
90 (nios2_hash_init, nios2_hash): Delete.
91 (OPCODE_HASH_SIZE): New.
92 (nios2_r1_extract_opcode): New.
93 (nios2_disassembler_state): New.
94 (nios2_r1_disassembler_state): New.
95 (nios2_init_opcode_hash): Add state parameter. Adjust to use it.
96 (nios2_find_opcode_hash): Use state object.
97 (bad_opcode): New.
98 (nios2_print_insn_arg): Add op parameter. Use it to access
99 format. Remove 'b' case.
100 (nios2_disassemble): Remove special case for nop. Remove
101 hard-coded instruction size.
102
12e87fac
JB		 1032014-10-21 Jan Beulich <jbeulich@suse.com>
104
105 * ppc-opc.c (powerpc_opcodes): Enable msgclr and msgsnd on Power8.
106
d9490cd4
JM		 1072014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
108
109 * sparc-opc.c (sparc-opcodes): Fix several misplaced hwcap
110 entries.
0b6be415 111 Annotate several instructions with the HWCAP2_VIS3B hwcap.
d9490cd4 112
91dc4e0a
TG		 1132014-10-15 Tristan Gingold <gingold@adacore.com>
114
115 * configure: Regenerate.
116
3d68f91c
JM		 1172014-10-09 Jose E. Marchesi &lt;jose.marchesi@oracle.com&gt;
118
119 * sparc-opc.c (sparc-opcodes): Remove instructions `chkpt',
120 `commit', `random', `wr r,r,%cps', `wr r,i,%cps' and `rd %cps,r'.
121 Annotate table with HWCAP2 bits.
122 Add instructions xmontmul, xmontsqr, xmpmul.
123 (sparc-opcodes): Add the `mwait', `wr r,r,%mwait', `wr
124 r,i,%mwait' and `rd %mwait,r' instructions.
125 Add rd/wr instructions for accessing the %mcdper ancillary state
126 register.
127 (sparc-opcodes): Add sparc5/vis4.0 instructions:
128 subxc, subxccc, fpadd8, fpadds8, fpaddus8, fpaddus16, fpcmple8,
129 fpcmpgt8, fpcmpule16, fpcmpugt16, fpcmpule32, fpcmpugt32, fpmax8,
130 fpmax16, fpmax32, fpmaxu8, fpmaxu16, fpmaxu32, fpmin8, fpmin16,
131 fpmin32, fpminu8, fpminu16, fpminu32, fpsub8, fpsubs8, fpsubus8,
132 fpsubus16, and faligndatai.
133 * sparc-dis.c (v9a_asr_reg_names): Add the %mwait (%asr28)
134 ancillary state register to the table.
135 (print_insn_sparc): Handle the %mcdper ancillary state register.
136 (print_insn_sparc): Handle new operand type '}'.
137
68f34464
L		 1382014-09-22 H.J. Lu <hongjiu.lu@intel.com>
139
140 * i386-dis.c (MOD_0F20): Removed.
141 (MOD_0F21): Likewise.
142 (MOD_0F22): Likewise.
143 (MOD_0F23): Likewise.
144 (dis386_twobyte): Replace MOD_0F20, MOD_0F21, MOD_0F22 and
145 MOD_0F23 with "movZ".
146 (mod_table): Remove MOD_0F20, MOD_0F21, MOD_0F22 and MOD_0F23.
147 (OP_R): Check mod/rm byte and call OP_E_register.
148
40c7a7cb
KLC		 1492014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
150
151 * nds32-asm.c (nds32_opcodes, operand_fields, keyword_im5_i,
152 keyword_im5_m, keyword_accumulator, keyword_aridx, keyword_aridx2,
153 keyword_aridxi): Add audio ISA extension.
154 (keyword_gpr, keyword_usr, keyword_sr, keyword_cp, keyword_cpr,
155 keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm, keyword_dpref_st,
156 keyword_cctl_lv, keyword_standby_st, keyword_msync_st): Adjust scrope
157 for nds32-dis.c using.
158 (build_opcode_syntax): Remove dead code.
159 (parse_re, parse_a30b20, parse_rt21, parse_rte_start, parse_rte_end,
160 parse_rte69_start, parse_rte69_end, parse_im5_ip, parse_im5_mr,
161 parse_im6_ip, parse_im6_iq, parse_im6_mr, parse_im6_ms): Add audio ISA
162 operand parser.
163 * nds32-asm.h: Declare.
164 * nds32-dis.c: Use array nds32_opcodes to disassemble instead of
165 decoding by switch.
166
7361da2c
AB		 1672014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
168 Matthew Fortune <matthew.fortune@imgtec.com>
169
170 * mips-dis.c (mips_arch_choices): Add entries for mips32r6 and
171 mips64r6.
172 (parse_mips_dis_option): Allow MSA and virtualization support for
173 mips64r6.
174 (mips_print_arg_state): Add fields dest_regno and seen_dest.
175 (mips_seen_register): New function.
176 (print_insn_arg): Refactored code to use mips_seen_register
177 function. Add support for OP_SAME_RS_RT, OP_CHECK_PREV and
178 OP_NON_ZERO_REG. Changed OP_REPEAT_DEST_REG case to print out
179 the register rather than aborting.
180 (print_insn_args): Add length argument. Add code to correctly
181 calculate the instruction address for pc relative instructions.
182 (validate_insn_args): New static function.
183 (print_insn_mips): Prevent jalx disassembling for r6. Use
184 validate_insn_args.
185 (print_insn_micromips): Use validate_insn_args.
186 all the arguments are valid.
187 * mips-formats.h (PREV_CHECK): New define.
188 * mips-opc.c (decode_mips_operand): Add support for -a, -b, -d, -s,
189 -t, -u, -v, -w, -x, -y, -A, -B, +I, +O, +R, +:, +\, +", +;
190 (RD_pc): New define.
191 (FS): New define.
192 (I37): New define.
193 (I69): New define.
194 (mips_builtin_opcodes): Add MIPS R6 instructions. Exclude recoded
195 MIPS R6 instructions from MIPS R2 instructions.
196
4b4c407a
L		 1972014-09-10 H.J. Lu <hongjiu.lu@intel.com>
198
199 * i386-dis.c (dis386): Replace "P" with "%LP" for iret and sysret.
200 (putop): Handle "%LP".
201
df7b4545
JW		 2022014-09-03 Jiong Wang <jiong.wang@arm.com>
203
204 * aarch64-tbl.h (aarch64_opcode_table): Update encoding for mrs/msr.
205 * aarch64-dis-2.c: Update auto-generated file.
206
ee804238
JW		 2072014-09-03 Jiong Wang <jiong.wang@arm.com>
208
209 * aarch64-tbl.h (QL_R4NIL): New qualifiers.
210 (aarch64_feature_lse): New feature added.
211 (LSE): New Added.
212 (aarch64_opcode_table): New LSE instructions added. Improve
213 descriptions for ldarb/ldarh/ldar.
214 (aarch64_opcode_table): Describe PAIRREG.
215 * aarch64-opc.h (aarch64_field_kind): Add FLD_lse_sz.
216 * aarch64-opc.c (fields): Add entry for F_LSE_SZ.
217 (aarch64_print_operand): Recognize PAIRREG.
218 (operand_general_constraint_met_p): Check reg pair constraints for CASP
219 instructions.
220 * aarch64-dis.c (aarch64_ext_regno_pair): New extractor for paired reg.
221 (do_special_decoding): Recognize F_LSE_SZ.
222 * aarch64-asm.c (do_special_encoding): Recognize F_LSE_SZ.
223
5575639b
MR		 2242014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
225
226 * micromips-opc.c (decode_micromips_operand): Rename `B' to `+J'.
227 (micromips_opcodes): Use "+J" in place of "B" for "hypcall",
228 "sdbbp", "syscall" and "wait".
229
84919466
MR		 2302014-08-21 Nathan Sidwell <nathan@codesourcery.com>
231 Maciej W. Rozycki <macro@codesourcery.com>
232
233 * arm-dis.c (print_arm_address): Negate the GPR-relative offset
234 returned if the U bit is set.
235
a6c70539
MR		 2362014-08-21 Maciej W. Rozycki <macro@codesourcery.com>
237
238 * micromips-opc.c (micromips_opcodes): Remove #ifdef-ed out
239 48-bit "li" encoding.
240
9ace48f3
AA		 2412014-08-19 Andreas Arnez <arnez@linux.vnet.ibm.com>
242
243 * s390-dis.c (s390_insn_length, s390_insn_matches_opcode)
244 (s390_print_insn_with_opcode, opcode_mask_more_specific): New
245 static functions, code was moved from...
246 (print_insn_s390): ...here.
247 (s390_extract_operand): Adjust comment. Change type of first
248 parameter from 'unsigned char *' to 'const bfd_byte *'.
249 (union operand_value): New.
250 (s390_extract_operand): Change return type to union operand_value.
251 Also avoid integer overflow in sign-extension.
252 (s390_print_insn_with_opcode): Adjust to changed return value from
253 s390_extract_operand(). Change "%i" printf format to "%u" for
254 unsigned values.
255 (init_disasm): Simplify initialization of opc_index[]. This also
256 fixes an access after the last element of s390_opcodes[].
257 (print_insn_s390): Simplify the opcode search loop.
258 Check architecture mask against all searched opcodes, not just the
259 first matching one.
260 (s390_print_insn_with_opcode): Drop function pointer dereferences
261 without effect.
262 (print_insn_s390): Likewise.
263 (s390_insn_length): Simplify formula for return value.
264 (s390_print_insn_with_opcode): Avoid special handling for the
265 separator before the first operand. Use new local variable
266 'flags' in place of 'operand->flags'.
267
60ac5798
MF		 2682014-08-14 Mike Frysinger <vapier@gentoo.org>
269
270 * bfin-dis.c (struct private): Change int's to bfd_boolean's.
271 (decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
272 decode_dagMODik_0, decode_LDIMMhalf_0, decode_linkage_0):
273 Change assignment of 1 to priv->comment to TRUE.
274 (print_insn_bfin): Change legal to a bfd_boolean. Change
275 assignment of 0/1 with priv comment and parallel and legal
276 to FALSE/TRUE.
277
b3f3b4b0
MF		 2782014-08-14 Mike Frysinger <vapier@gentoo.org>
279
280 * bfin-dis.c (OUT): Define.
281 (decode_CC2stat_0): Declare new op_names array.
282 Replace multiple if statements with a single one.
283
a4e600b2
MF		 2842014-08-14 Mike Frysinger <vapier@gentoo.org>
285
286 * bfin-dis.c (struct private): Add iw0.
287 (_print_insn_bfin): Assign iw0 to priv.iw0.
288 (print_insn_bfin): Drop ifetch and use priv.iw0.
289
703ec4e8
MF		 2902014-08-13 Mike Frysinger <vapier@gentoo.org>
291
292 * bfin-dis.c (comment, parallel): Move from global scope ...
293 (struct private): ... to this new struct.
294 (decode_ProgCtrl_0, decode_CaCTRL_0, decode_PushPopReg_0,
295 decode_PushPopMultiple_0, decode_ccMV_0, decode_CCflag_0,
296 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
297 decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
298 decode_dagMODik_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
299 decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
300 decode_pseudoOChar_0, decode_pseudodbg_assert_0, _print_insn_bfin,
301 print_insn_bfin): Declare private struct. Use priv's comment and
302 parallel members.
303
ed2c4879
MF		 3042014-08-13 Mike Frysinger <vapier@gentoo.org>
305
306 * bfin-dis.c (ifetch): Do not align pc to 2 bytes.
307 (_print_insn_bfin): Add check for unaligned pc.
308
ba329817
MF		 3092014-08-13 Mike Frysinger <vapier@gentoo.org>
310
311 * bfin-dis.c (ifetch): New function.
312 (_print_insn_bfin, print_insn_bfin): Call new ifetch and return
313 -1 when it errors.
314
43885403
MF		 3152014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
316
317 * micromips-opc.c (COD): Rename throughout to...
318 (CM): New define, update to use INSN_COPROC_MOVE.
319 (LCD): Rename throughout to...
320 (LC): New define, update to use INSN_LOAD_COPROC.
321 * mips-opc.c: Likewise.
322
351cdf24
MF		 3232014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
324
325 * micromips-opc.c (COD, LCD) New macros.
326 (cfc1, ctc1): Remove FP_S attribute.
327 (dmfc1, mfc1, mfhc1): Add LCD attribute.
328 (dmtc1, mtc1, mthc1): Add COD attribute.
329 * mips-opc.c (cfc1, cftc1, ctc, cttc1): Remove FP_S attribute.
330
90a915bf
IT		 3312014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
332 Alexander Ivchenko <alexander.ivchenko@intel.com>
333 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
334 Sergey Lega <sergey.s.lega@intel.com>
335 Anna Tikhonova <anna.tikhonova@intel.com>
336 Ilya Tocar <ilya.tocar@intel.com>
337 Andrey Turetskiy <andrey.turetskiy@intel.com>
338 Ilya Verbin <ilya.verbin@intel.com>
339 Kirill Yukhin <kirill.yukhin@intel.com>
340 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
341
342 * i386-dis-evex.h: Updated.
343 * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
344 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0F3A16,
345 PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A50, PREFIX_EVEX_0F3A51,
346 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
347 PREFIX_EVEX_0F3A67.
348 (VEX_LEN enum): Add VEX_LEN_0F92_P_2, VEX_LEN_0F93_P_2,
349 VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_2_LEN_0.
350 (VEX_W enum): Add EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
351 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2, EVEX_W_0F57_P_0,
352 EVEX_W_0F57_P_2, EVEX_W_0F78_P_2, EVEX_W_0F79_P_2, EVEX_W_0F7A_P_2,
353 EVEX_W_0F7B_P_2, EVEX_W_0F3838_P_1, EVEX_W_0F3839_P_1,
354 EVEX_W_0F3A16_P_2, EVEX_W_0F3A22_P_2, EVEX_W_0F3A50_P_2,
355 EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2, EVEX_W_0F3A57_P_2,
356 EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2.
357 (prefix_table): Add entries for new instructions.
358 (vex_len_table): Ditto.
359 (vex_w_table): Ditto.
360 (OP_E_memory): Update xmmq_mode handling.
361 * i386-gen.c (cpu_flag_init): Add CPU_AVX512DQ_FLAGS.
362 (cpu_flags): Add CpuAVX512DQ.
363 * i386-init.h: Regenerared.
364 * i386-opc.h (CpuAVX512DQ): New.
365 (i386_cpu_flags): Add cpuavx512dq.
366 * i386-opc.tbl: Add AVX512DQ instructions.
367 * i386-tbl.h: Regenerate.
368
1ba585e8
IT		 3692014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
370 Alexander Ivchenko <alexander.ivchenko@intel.com>
371 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
372 Sergey Lega <sergey.s.lega@intel.com>
373 Anna Tikhonova <anna.tikhonova@intel.com>
374 Ilya Tocar <ilya.tocar@intel.com>
375 Andrey Turetskiy <andrey.turetskiy@intel.com>
376 Ilya Verbin <ilya.verbin@intel.com>
377 Kirill Yukhin <kirill.yukhin@intel.com>
378 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
379
380 * i386-dis-evex.h: Add new instructions (prefixes bellow).
381 * i386-dis.c (fetch_data): Add EdqwS, Edb, Edw, MaskBDE.
382 (enum): Add dqw_swap_mode, db_mode, dw_mode, mask_bd_mode, REG_EVEX_0F71.
383 (PREFIX enum): Add PREFIX_VEX_0F4A, PREFIX_VEX_0F99, PREFIX_VEX_0F3A31,
384 PREFIX_VEX_0F3A33, PREFIX_EVEX_0F60, PREFIX_EVEX_0F61, PREFIX_EVEX_0F63,
385 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
386 PREFIX_EVEX_0F69, PREFIX_EVEX_0F6B, PREFIX_EVEX_0F71_REG_2, PREFIX_EVEX_0F71_REG_4,
387 PREFIX_EVEX_0F71_REG_6, PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_7,
388 PREFIX_EVEX_0F74, PREFIX_EVEX_0F75, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
389 PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5, PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9,
390 PREFIX_EVEX_0FDA, PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
391 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3, PREFIX_EVEX_0FE4,
392 PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8, PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA,
393 PREFIX_EVEX_0FEC, PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
394 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8, PREFIX_EVEX_0FF9,
395 PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD, PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804,
396 PREFIX_EVEX_0F380B, PREFIX_EVEX_0F3810, PREFIX_EVEX_0F381C, PREFIX_EVEX_0F381D,
397 PREFIX_EVEX_0F3820, PREFIX_EVEX_0F3826, PREFIX_EVEX_0F382B, PREFIX_EVEX_0F3830,
398 PREFIX_EVEX_0F3838, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E, PREFIX_EVEX_0F3866,
399 PREFIX_EVEX_0F3875, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879, PREFIX_EVEX_0F387A,
400 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387D, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F3A0F,
401 PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15, PREFIX_EVEX_0F3A20, PREFIX_EVEX_0F3A3E,
402 PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A42.
403 (VEX_LEN enum): Add VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_2, VEX_LEN_0F44_P_2,
404 VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_2, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
405 VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_2,
406 VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_2, VEX_LEN_0F99_P_0,
407 VEX_LEN_0F99_P_2, VEX_LEN_0F3A31_P_2, VEX_LEN_0F3A33_P_2, VEX_W_0F41_P_2_LEN_1,
408 VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_2_LEN_1,
409 VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
410 VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, VEX_W_0F90_P_2_LEN_0,
411 VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_3_LEN_0, VEX_W_0F93_P_3_LEN_0,
412 VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, VEX_W_0F99_P_2_LEN_0,
413 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A33_P_2_LEN_0.
414 (VEX_W enum): Add EVEX_W_0F6B_P_2, EVEX_W_0F6F_P_3, EVEX_W_0F7F_P_3,
415 EVEX_W_0F3810_P_1, EVEX_W_0F3810_P_2, EVEX_W_0F3811_P_2, EVEX_W_0F3812_P_2,
416 EVEX_W_0F3820_P_1, EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2, EVEX_W_0F3828_P_1,
417 EVEX_W_0F3829_P_1, EVEX_W_0F382B_P_2, EVEX_W_0F3830_P_1, EVEX_W_0F3866_P_2,
418 EVEX_W_0F3875_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F387A_P_2,
419 EVEX_W_0F387B_P_2, EVEX_W_0F387D_P_2, EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2,
420 EVEX_W_0F3A3F_P_2, EVEX_W_0F3A42_P_2.
421 (prefix_table): Add entries for new instructions.
422 (vex_table) : Ditto.
423 (vex_len_table): Ditto.
424 (vex_w_table): Ditto.
425 (intel_operand_size): Add db_mode, dw_mode, dqw_swap_mode,
426 mask_bd_mode handling.
427 (OP_E_register): Add dqw_swap_mode, dw_mode, db_mode, mask_bd_mode
428 handling.
429 (OP_E_memory): Add dqw_mode, dw_mode, dqw_swap_mode, dqb_mode, db_mode
430 handling.
431 (OP_G): Add db_mode, dw_mode, dqw_swap_mode, mask_bd_mode handling.
432 (OP_EX): Add dqw_swap_mode handling.
433 (OP_VEX): Add mask_bd_mode handling.
434 (OP_Mask): Add mask_bd_mode handling.
435 * i386-gen.c (cpu_flag_init): Add CPU_AVX512BW_FLAGS.
436 (cpu_flags): Add CpuAVX512BW.
437 * i386-init.h: Regenerated.
438 * i386-opc.h (CpuAVX512BW): New.
439 (i386_cpu_flags): Add cpuavx512bw.
440 * i386-opc.tbl: Add AVX512BW instructions.
441 * i386-tbl.h: Regenerate.
442
99282af6
IT		 4432014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
444 Alexander Ivchenko <alexander.ivchenko@intel.com>
445 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
446 Sergey Lega <sergey.s.lega@intel.com>
447 Anna Tikhonova <anna.tikhonova@intel.com>
448 Ilya Tocar <ilya.tocar@intel.com>
449 Andrey Turetskiy <andrey.turetskiy@intel.com>
450 Ilya Verbin <ilya.verbin@intel.com>
451 Kirill Yukhin <kirill.yukhin@intel.com>
452 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
453
454 * i386-opc.tbl: Add AVX512VL and AVX512CD instructions.
455 * i386-tbl.h: Regenerate.
456
b28d1bda
IT		 4572014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
458 Alexander Ivchenko <alexander.ivchenko@intel.com>
459 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
460 Sergey Lega <sergey.s.lega@intel.com>
461 Anna Tikhonova <anna.tikhonova@intel.com>
462 Ilya Tocar <ilya.tocar@intel.com>
463 Andrey Turetskiy <andrey.turetskiy@intel.com>
464 Ilya Verbin <ilya.verbin@intel.com>
465 Kirill Yukhin <kirill.yukhin@intel.com>
466 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
467
468 * i386-dis.c (intel_operand_size): Support 128/256 length in
469 vex_vsib_q_w_dq_mode.
470 (OP_E_memory): Add ymmq_mode handling, handle new broadcast.
471 * i386-gen.c (cpu_flag_init): Add CPU_AVX512VL_FLAGS.
472 (cpu_flags): Add CpuAVX512VL.
473 * i386-init.h: Regenerated.
474 * i386-opc.h (CpuAVX512VL): New.
475 (i386_cpu_flags): Add cpuavx512vl.
476 (BROADCAST_1TO4, BROADCAST_1TO2): Define.
477 * i386-opc.tbl: Add AVX512VL instructions.
478 * i386-tbl.h: Regenerate.
479
018dc9be
SK		 4802014-07-20 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
481
482 * or1k-desc.c, * or1k-desc.h, * or1k-opc.c, * or1k-opc.h,
483 * or1k-opinst.c: Regenerate.
484
792f7758
IT		 4852014-07-08 Ilya Tocar <ilya.tocar@intel.com>
486
487 * i386-dis-evex.h (EVEX_W_0F10_P_1_M_1): Fix vmovss.
488 (EVEX_W_0F10_P_3_M_1): Fix vmovsd.
489
35eafcc7
AM		 4902014-07-04 Alan Modra <amodra@gmail.com>
491
492 * configure.ac: Rename from configure.in.
493 * Makefile.in: Regenerate.
494 * config.in: Regenerate.
495
2e98a7bd
AM		 4962014-07-04 Alan Modra <amodra@gmail.com>
497
498 * configure.in: Include bfd/version.m4.
499 (AC_INIT, AM_INIT_AUTOMAKE): Use modern form.
500 (BFD_VERSION): Delete.
501 * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Remove bfd/configure.in.
502 * configure: Regenerate.
503 * Makefile.in: Regenerate.
504
f36e8886
BS		 5052014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
506 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
507 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
508 Soundararajan <Sounderarajan.D@atmel.com>
509
510 * avr-dis.c (avr_operand): Handle constraint j for 16 bit lds/sts.
2e98a7bd
AM		 511 (print_insn_avr): Do not select opcode if insn ISA is avrtiny and
512 machine is not avrtiny.
f36e8886 513
6ddf779d
PDM		 5142014-06-26 Philippe De Muyter <phdm@macqel.be>
515
516 * or1k-desc.h (spr_field_masks): Add U suffix to the end of long
517 constants.
518
c151b1c6
AM		 5192014-06-12 Alan Modra <amodra@gmail.com>
520
521 * or1k-asm.c, * or1k-desc.c, * or1k-desc.h, * or1k-dis.c,
522 * or1k-ibld.c, * or1k-opc.c, * or1k-opc.h, * or1k-opinst.c: Regenerate.
523
d9949a36
L		 5242014-06-10 H.J. Lu <hongjiu.lu@intel.com>
525
526 * i386-dis.c (fwait_prefix): New.
527 (ckprefix): Set fwait_prefix.
528 (print_insn): Properly print prefixes before fwait.
529
a47622ac
AM		 5302014-06-07 Alan Modra <amodra@gmail.com>
531
532 * ppc-opc.c (UISIGNOPT): Define and use with cmpli.
533
270c9937
JB		 5342014-06-05 Joel Brobecker <brobecker@adacore.com>
535
536 * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add dependency on
537 bfd's development.sh.
538 * Makefile.in, configure: Regenerate.
539
9f445129
NC		 5402014-06-03 Nick Clifton <nickc@redhat.com>
541
542 * msp430-dis.c (msp430_doubleoperand): Use extension_word to
543 decide when extended addressing is being used.
544
ec9a8169
EB		 5452014-06-02 Eric Botcazou <ebotcazou@adacore.com>
546
547 * sparc-opc.c (cas): Disable for LEON.
548 (casl): Likewise.
549
cdf2a8b7
AM		 5502014-05-20 Alan Modra <amodra@gmail.com>
551
552 * m68k-dis.c: Don't include setjmp.h.
553
df18fdba
L		 5542014-05-09 H.J. Lu <hongjiu.lu@intel.com>
555
556 * i386-dis.c (ADDR16_PREFIX): Removed.
557 (ADDR32_PREFIX): Likewise.
558 (DATA16_PREFIX): Likewise.
559 (DATA32_PREFIX): Likewise.
560 (prefix_name): Updated.
561 (print_insn): Simplify data and address size prefixes processing.
562
999b995d
SK		 5632014-05-08 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
564
565 * or1k-desc.c: Regenerated.
566 * or1k-desc.h: Likewise.
567 * or1k-opc.c: Likewise.
568 * or1k-opc.h: Likewise.
569 * or1k-opinst.c: Likewise.
570
ae52f483
AB		 5712014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
572
573 * mips-opc.c (mips_builtin_opcodes): Add MIPS32r5 eretnc instruction.
574 (I34): New define.
575 (I36): New define.
576 (I66): New define.
577 (I68): New define.
578 * mips-dis.c (mips_arch_choices): Add mips32r3, mips32r5, mips64r3 and
579 mips64r5.
580 (parse_mips_dis_option): Update MSA and virtualization support to
9f445129 581 allow mips64r3 and mips64r5.
ae52f483 582
f7730599
AB		 5832014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
584
585 * mips-opc.c (G3): Remove I4.
586
285ca992
L		 5872014-05-05 H.J. Lu <hongjiu.lu@intel.com>
588
589 PR binutils/16893
590 * i386-dis.c (twobyte_has_mandatory_prefix): New variable.
591 (end_codep): Likewise.
592 (mandatory_prefix): Likewise.
593 (active_seg_prefix): Likewise.
594 (ckprefix): Set active_seg_prefix to the active segment register
595 prefix.
596 (seg_prefix): Removed.
597 (get_valid_dis386): Use the last of PREFIX_REPNZ and PREFIX_REPZ
598 for prefix index. Ignore the index if it is invalid and the
599 mandatory prefix isn't required.
600 (print_insn): Set mandatory_prefix if the PREFIX_XXX prefix is
601 mandatory. Don't set PREFIX_REPZ/PREFIX_REPNZ/PREFIX_LOCK bits
602 in used_prefixes here. Don't print unused prefixes. Check
603 active_seg_prefix for the active segment register prefix.
604 Restore the DFLAG bit in sizeflag if the data size prefix is
605 unused. Check the unused mandatory PREFIX_XXX prefixes
606 (append_seg): Only print the segment register which gets used.
607 (OP_E_memory): Check active_seg_prefix for the segment register
608 prefix.
609 (OP_OFF): Likewise.
610 (OP_OFF64): Likewise.
611 (OP_DSreg): Set active_seg_prefix to PREFIX_DS if it is unset.
612
8df14d78
L		 6132014-05-02 H.J. Lu <hongjiu.lu@intel.com>
614
615 PR binutils/16886
616 * config.in: Regenerated.
617 * configure: Likewise.
618 * configure.in: Check if sigsetjmp is available.
619 * h8500-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
620 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
621 (print_insn_h8500): Replace setjmp with OPCODES_SIGSETJMP.
622 * i386-dis.c (dis_private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
623 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
624 (print_insn): Replace setjmp with OPCODES_SIGSETJMP.
625 * ns32k-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
626 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
627 (print_insn_ns32k): Replace setjmp with OPCODES_SIGSETJMP.
628 * sysdep.h (OPCODES_SIGJMP_BUF): New macro.
629 (OPCODES_SIGSETJMP): Likewise.
630 (OPCODES_SIGLONGJMP): Likewise.
631 * vax-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
632 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
633 (print_insn_vax): Replace setjmp with OPCODES_SIGSETJMP.
634 * xtensa-dis.c (dis_private): Replace jmp_buf with
635 OPCODES_SIGJMP_BUF.
636 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
637 (print_insn_xtensa): Replace setjmp with OPCODES_SIGSETJMP.
638 * z8k-dis.c(instr_data_s): Replace jmp_buf with OPCODES_SIGJMP_BUF.
639 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
640 (print_insn_z8k): Replace setjmp with OPCODES_SIGSETJMP.
641
86a80a50
L		 6422014-05-01 H.J. Lu <hongjiu.lu@intel.com>
643
644 PR binutils/16891
645 * i386-dis.c (print_insn): Handle prefixes before fwait.
646
a9e18c6a
AM		 6472014-04-26 Alan Modra <amodra@gmail.com>
648
649 * po/POTFILES.in: Regenerate.
650
7d64c587
AB		 6512014-04-23 Andrew Bennett <andrew.bennett@imgtec.com>
652
653 * mips-dis.c (mips_arch_choices): Update mips32r2 and mips64r2
654 to allow the MIPS XPA ASE.
655 (parse_mips_dis_option): Process the -Mxpa option.
656 * mips-opc.c (XPA): New define.
657 (mips_builtin_opcodes): Add MIPS XPA instructions and move the
658 locations of the ctc0 and cfc0 instructions.
659
73589c9d
CS		 6602014-04-22 Christian Svensson <blue@cmd.nu>
661
662 * Makefile.am: Remove openrisc and or32 support. Add support for or1k.
663 * configure.in: Likewise.
664 * disassemble.c: Likewise.
665 * or1k-asm.c: New file.
666 * or1k-desc.c: New file.
667 * or1k-desc.h: New file.
668 * or1k-dis.c: New file.
669 * or1k-ibld.c: New file.
670 * or1k-opc.c: New file.
671 * or1k-opc.h: New file.
672 * or1k-opinst.c: New file.
673 * Makefile.in: Regenerate.
674 * configure: Regenerate.
675 * openrisc-asm.c: Delete.
676 * openrisc-desc.c: Delete.
677 * openrisc-desc.h: Delete.
678 * openrisc-dis.c: Delete.
679 * openrisc-ibld.c: Delete.
680 * openrisc-opc.c: Delete.
681 * openrisc-opc.h: Delete.
682 * or32-dis.c: Delete.
683 * or32-opc.c: Delete.
684
2cf200a4
IT		 6852014-04-04 Ilya Tocar <ilya.tocar@intel.com>
686
687 * i386-dis.c (rm_table): Add encls, enclu.
688 * i386-gen.c (cpu_flag_init): Add CPU_SE1_FLAGS,
689 (cpu_flags): Add CpuSE1.
690 * i386-opc.h (enum): Add CpuSE1.
691 (i386_cpu_flags): Add cpuse1.
692 * i386-opc.tbl: Add encls, enclu.
693 * i386-init.h: Regenerated.
694 * i386-tbl.h: Likewise.
695
31c981bc
AG		 6962014-04-02 Anthony Green <green@moxielogic.com>
697
698 * moxie-opc.c (moxie_form1_opc_info): Add sign-extension
699 instructions, sex.b and sex.s.
700
76dfed02
YZ		 7012014-03-26 Jiong Wang <jiong.wang@arm.com>
702
703 * aarch64-dis.c (aarch64_ext_ldst_elemlist): Check H/S undefined
704 instructions.
705
5fc35d96
IT		 7062014-03-20 Ilya Tocar <ilya.tocar@intel.com>
707
708 * i386-opc.tbl: Change memory size for vgatherpf0qps, vgatherpf1qps,
709 vscatterpf0qps, vscatterpf1qps, vgatherqps, vpgatherqd, vpscatterqd,
710 vscatterqps.
711 * i386-tbl.h: Regenerate.
712
ec92c392
JM		 7132014-03-19 Jose E. Marchesi <jose.marchesi@oracle.com>
714
715 * sparc-dis.c (v9_hpriv_reg_names): Names for %hstick_offset and
716 %hstick_enable added.
717
b8985e5c
NC		 7182014-03-19 Nick Clifton <nickc@redhat.com>
719
720 * rx-decode.opc (bwl): Allow for bogus instructions with a size
721 field of 3.
b41c812c 722 (sbwl, ubwl, SCALE): Likewise.
b8985e5c
NC		 723 * rx-decode.c: Regenerate.
724
fa47fa92
AM		 7252014-03-12 Alan Modra <amodra@gmail.com>
726
727 * Makefile.in: Regenerate.
728
4b95cf5c
AM		 7292014-03-05 Alan Modra <amodra@gmail.com>
730
731 Update copyright years.
732
cd0c81e9 7332014-03-04 Heiher <r@hev.cc>
4ba154f5
RS		 734
735 * mips-dis.c (mips_arch_choices): Usee ISA_MIPS64R2 for Loongson-3A.
736
079b5aec
RS		 7372014-03-04 Richard Sandiford <rdsandiford@googlemail.com>
738
739 * mips-opc.c (mips_builtin_opcodes): Move the udi* instructions
740 so that they come after the Loongson extensions.
741
2c80b753
AM		 7422014-03-03 Alan Modra <amodra@gmail.com>
743
744 * i386-gen.c (process_copyright): Emit copyright notice on one line.
745
b721f1fa
AM		 7462014-02-28 Alan Modra <amodra@gmail.com>
747
748 * msp430-decode.c: Regenerate.
749
f17c8bfc
YZ		 7502014-02-27 Jiong Wang <jiong.wang@arm.com>
751
752 * aarch64-tbl.h (aarch64_opcode_table): Replace IMM0 with
753 FPIMM0 for fcmeq, fcmgt, fcmge, fcmlt and fcmle.
754
a58549dd
YZ		 7552014-02-27 Yufeng Zhang <yufeng.zhang@arm.com>
756
757 * aarch64-opc.c (print_register_offset_address): Call
758 get_int_reg_name to prepare the register name.
759
d6e9dd78
IT		 7602014-02-25 Ilya Tocar <ilya.tocar@intel.com>
761
762 * i386-opc.tbl: Remove wrong variant of vcvtps2ph
763 * i386-tbl.h: Regenerate.
764
7652014-02-20 Ilya Tocar <ilya.tocar@intel.com>
dcf893b5
IT		 766
767 * i386-gen.c (cpu_flag_init): Add CPU_PREFETCHWT1_FLAGS/
768 (cpu_flags): Add CpuPREFETCHWT1.
769 * i386-init.h: Regenerate.
770 * i386-opc.h (CpuPREFETCHWT1): New.
771 (i386_cpu_flags): Add cpuprefetchwt1.
772 * i386-opc.tbl: Cahnge CPU of prefetchwt1 from CpuAVX512PF to CpuPREFETCHWT1.
773 * i386-tbl.h: Regenerate.
774
957d0955
IT		 7752014-02-20 Ilya Tocar <ilya.tocar@intel.com>
776
777 * i386-opc.tbl: Change CPU of vptestnmq, vptestnmd from CpuAVX512CD,
778 to CpuAVX512F.
779 * i386-tbl.h: Regenerate.
780
10632b79
L		 7812014-02-19 H.J. Lu <hongjiu.lu@intel.com>
782
783 * i386-gen.c (output_cpu_flags): Don't output trailing space.
784 (output_opcode_modifier): Likewise.
785 (output_operand_type): Likewise.
786 * i386-init.h: Regenerated.
787 * i386-tbl.h: Likewise.
788
963f3586
IT		 7892014-02-12 Ilya Tocar <ilya.tocar@intel.com>
790
791 * i386-dis.c (MOD enum): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4,
792 MOD_0FC7_REG_5.
793 (PREFIX enum): Add PREFIX_0FAE_REG_7.
794 (reg_table): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4 MOD_0FC7_REG_5.
795 (prefix_table): Add clflusopt.
796 (mod_table): Add xrstors, xsavec, xsaves.
797 * i386-gen.c (cpu_flag_init): Add CPU_CLFLUSHOPT_FLAGS,
798 CPU_XSAVES_FLAGS, CPU_XSAVEC_FLAGS.
799 (cpu_flags): Add CpuClflushOpt, CpuXSAVES, CpuXSAVEC.
800 * i386-init.h: Regenerate.
801 * i386-opc.tbl: Add clflushopt, xrstors, xrstors64, xsaves,
802 xsaves64, xsavec, xsavec64.
803 * i386-tbl.h: Regenerate.
804
c1c69e83
AM		 8052014-02-10 Alan Modra <amodra@gmail.com>
806
807 * po/POTFILES.in: Regenerate.
808 * po/opcodes.pot: Regenerate.
809
eaa9d1ad
MZ		 8102014-01-30 Michael Zolotukhin <michael.v.zolotukhin@gmail.com>
811 Jan Beulich <jbeulich@suse.com>
812
813 PR binutils/16490
814 * i386-dis.c (OP_E_memory): Fix shift computation for
815 vex_vsib_q_w_dq_mode.
816
e2e6193d
RM		 8172014-01-09 Bradley Nelson <bradnelson@google.com>
818 Roland McGrath <mcgrathr@google.com>
819
820 * i386-dis.c (print_insn): Do not touch all_prefixes[-1] when
821 last_rex_prefix is -1.
822
221fd5d5
L		 8232014-01-08 H.J. Lu <hongjiu.lu@intel.com>
824
825 * i386-gen.c (process_copyright): Update copyright year to 2014.
826
b0b0c9fc
MR		 8272014-01-03 Maciej W. Rozycki <macro@codesourcery.com>
828
829 * nds32-asm.c (parse_operand): Fix out-of-range integer constant.
830
5fb776a6 831For older changes see ChangeLog-2013
252b5132 832\f
5fb776a6 833Copyright (C) 2014 Free Software Foundation, Inc.
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NC		 834
835Copying and distribution of this file, with or without modification,
836are permitted in any medium without royalty provided the copyright
837notice and this notice are preserved.
838
252b5132 839Local Variables:
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NC		 840mode: change-log
841left-margin: 8
842fill-column: 74
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844End:
GDB Binutils - Deliverables
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