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arc: Change max instruction length to 64-bits
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
bdfe53e3
AB		 12016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
2
3 * arc-dis.c (struct arc_operand_iterator): Remove all fields
4 relating to long instruction processing, add new limm field.
5 (OPCODE): Rename to...
6 (OPCODE_32BIT_INSN): ...this.
7 (OPCODE_AC): Delete.
8 (skip_this_opcode): Handle different instruction lengths, update
9 macro name.
10 (special_flag_p): Update parameter type.
11 (find_format_from_table): Update for more instruction lengths.
12 (find_format_long_instructions): Delete.
13 (find_format): Update for more instruction lengths.
14 (arc_insn_length): Likewise.
15 (extract_operand_value): Update for more instruction lengths.
16 (operand_iterator_next): Remove code relating to long
17 instructions.
18 (arc_opcode_to_insn_type): New function.
19 (print_insn_arc):Update for more instructions lengths.
20 * arc-ext.c (extInstruction_t): Change argument type.
21 * arc-ext.h (extInstruction_t): Change argument type.
22 * arc-fxi.h: Change type unsigned to unsigned long long
23 extensively throughout.
24 * arc-nps400-tbl.h: Add long instructions taken from
25 arc_long_opcodes table in arc-opc.c.
26 * arc-opc.c: Update parameter types on insert/extract handlers.
27 (arc_long_opcodes): Delete.
28 (arc_num_long_opcodes): Delete.
29 (arc_opcode_len): Update for more instruction lengths.
30
90f61cce
GM		 312016-11-03 Graham Markall <graham.markall@embecosm.com>
32
33 * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
34
06fe285f
GM		 352016-11-03 Graham Markall <graham.markall@embecosm.com>
36
37 * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
38 with arc_opcode_len.
39 (find_format_long_instructions): Likewise.
40 * arc-opc.c (arc_opcode_len): New function.
41
ecf64ec6
AB		 422016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
43
44 * arc-nps400-tbl.h: Fix some instruction masks.
45
d039fef3
L		 462016-11-03 H.J. Lu <hongjiu.lu@intel.com>
47
48 * i386-dis.c (REG_82): Removed.
49 (X86_64_82_REG_0): Likewise.
50 (X86_64_82_REG_1): Likewise.
51 (X86_64_82_REG_2): Likewise.
52 (X86_64_82_REG_3): Likewise.
53 (X86_64_82_REG_4): Likewise.
54 (X86_64_82_REG_5): Likewise.
55 (X86_64_82_REG_6): Likewise.
56 (X86_64_82_REG_7): Likewise.
57 (X86_64_82): New.
58 (dis386): Use X86_64_82 instead of REG_82.
59 (reg_table): Remove REG_82.
60 (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
61 X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
62 X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
63 X86_64_82_REG_7.
64
8b89fe14
L		 652016-11-03 H.J. Lu <hongjiu.lu@intel.com>
66
67 PR binutils/20754
68 * i386-dis.c (REG_82): New.
69 (X86_64_82_REG_0): Likewise.
70 (X86_64_82_REG_1): Likewise.
71 (X86_64_82_REG_2): Likewise.
72 (X86_64_82_REG_3): Likewise.
73 (X86_64_82_REG_4): Likewise.
74 (X86_64_82_REG_5): Likewise.
75 (X86_64_82_REG_6): Likewise.
76 (X86_64_82_REG_7): Likewise.
77 (dis386): Use REG_82.
78 (reg_table): Add REG_82.
79 (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
80 X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
81 X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
82
7148c369
L		 832016-11-03 H.J. Lu <hongjiu.lu@intel.com>
84
85 * i386-dis.c (REG_82): Renamed to ...
86 (REG_83): This.
87 (dis386): Updated.
88 (reg_table): Likewise.
89
47acf0bd
IT		 902016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
91
92 * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
93 * i386-dis-evex.h (evex_table): Updated.
94 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
95 CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
96 (cpu_flags): Add CpuAVX512_4VNNIW.
97 * i386-opc.h (enum): (AVX512_4VNNIW): New.
98 (i386_cpu_flags): Add cpuavx512_4vnniw.
99 * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
100 * i386-init.h: Regenerate.
101 * i386-tbl.h: Ditto.
102
920d2ddc
IT		 1032016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
104
105 * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
106 PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
107 * i386-dis-evex.h (evex_table): Updated.
108 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
109 CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
110 (cpu_flags): Add CpuAVX512_4FMAPS.
111 (opcode_modifiers): Add ImplicitQuadGroup modifier.
112 * i386-opc.h (AVX512_4FMAP): New.
113 (i386_cpu_flags): Add cpuavx512_4fmaps.
114 (ImplicitQuadGroup): New.
115 (i386_opcode_modifier): Add implicitquadgroup.
116 * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
117 * i386-init.h: Regenerate.
118 * i386-tbl.h: Ditto.
119
e23eba97
NC		 1202016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
121 Andrew Waterman <andrew@sifive.com>
122
123 Add support for RISC-V architecture.
124 * configure.ac: Add entry for bfd_riscv_arch.
125 * configure: Regenerate.
126 * disassemble.c (disassembler): Add support for riscv.
127 (disassembler_usage): Likewise.
128 * riscv-dis.c: New file.
129 * riscv-opc.c: New file.
130
b5cefcca
L		 1312016-10-21 H.J. Lu <hongjiu.lu@intel.com>
132
133 * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
134 (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
135 (rm_table): Update the RM_0FAE_REG_7 entry.
136 * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
137 (cpu_flags): Remove CpuPCOMMIT.
138 * i386-opc.h (CpuPCOMMIT): Removed.
139 (i386_cpu_flags): Remove cpupcommit.
140 * i386-opc.tbl: Remove pcommit.
141 * i386-init.h: Regenerated.
142 * i386-tbl.h: Likewise.
143
9889cbb1
L		 1442016-10-20 H.J. Lu <hongjiu.lu@intel.com>
145
146 PR binutis/20705
147 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
148 the highest bit in VEX.vvvv for the 3-byte VEX prefix in
149 32-bit mode. Don't check vex.register_specifier in 32-bit
150 mode.
151 (OP_VEX): Check for invalid mask registers.
152
28596323
L		 1532016-10-18 H.J. Lu <hongjiu.lu@intel.com>
154
155 PR binutis/20699
156 * i386-dis.c (OP_E_memory): Check addr32flag in stead of
157 sizeflag.
158
da8d7d66
L		 1592016-10-18 H.J. Lu <hongjiu.lu@intel.com>
160
161 PR binutis/20704
162 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
163
eaf02703
MR		 1642016-10-18 Maciej W. Rozycki <macro@imgtec.com>
165
166 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
167 local variable to `index_regno'.
168
decf5bd1
CM		 1692016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
170
171 * arc-tbl.h: Removed any "inv.+" instructions from the table.
172
e5b06ef0
CZ		 1732016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
174
175 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
176 usage on ISA basis.
177
93562a34
JW		 1782016-10-11 Jiong Wang <jiong.wang@arm.com>
179
180 PR target/20666
181 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
182
362c0c4d
JW		 1832016-10-07 Jiong Wang <jiong.wang@arm.com>
184
185 PR target/20667
186 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
187 available.
188
1047201f
AM		 1892016-10-07 Alan Modra <amodra@gmail.com>
190
191 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
192
1a0670f3
AM		 1932016-10-06 Alan Modra <amodra@gmail.com>
194
195 * aarch64-opc.c: Spell fall through comments consistently.
196 * i386-dis.c: Likewise.
197 * aarch64-dis.c: Add missing fall through comments.
198 * aarch64-opc.c: Likewise.
199 * arc-dis.c: Likewise.
200 * arm-dis.c: Likewise.
201 * i386-dis.c: Likewise.
202 * m68k-dis.c: Likewise.
203 * mep-asm.c: Likewise.
204 * ns32k-dis.c: Likewise.
205 * sh-dis.c: Likewise.
206 * tic4x-dis.c: Likewise.
207 * tic6x-dis.c: Likewise.
208 * vax-dis.c: Likewise.
209
2b804145
AM		 2102016-10-06 Alan Modra <amodra@gmail.com>
211
212 * arc-ext.c (create_map): Add missing break.
213 * msp430-decode.opc (encode_as): Likewise.
214 * msp430-decode.c: Regenerate.
215
616ec358
AM		 2162016-10-06 Alan Modra <amodra@gmail.com>
217
218 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
219 * crx-dis.c (print_insn_crx): Likewise.
220
72da393d
L		 2212016-09-30 H.J. Lu <hongjiu.lu@intel.com>
222
223 PR binutils/20657
224 * i386-dis.c (putop): Don't assign alt twice.
225
744ce302
JW		 2262016-09-29 Jiong Wang <jiong.wang@arm.com>
227
228 PR target/20553
229 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
230
a5721ba2
AM		 2312016-09-29 Alan Modra <amodra@gmail.com>
232
233 * ppc-opc.c (L): Make compulsory.
234 (LOPT): New, optional form of L.
235 (HTM_R): Define as LOPT.
236 (L0, L1): Delete.
237 (L32OPT): New, optional for 32-bit L.
238 (L2OPT): New, 2-bit L for dcbf.
239 (SVC_LEC): Update.
240 (L2): Define.
241 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
242 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
243 <dcbf>: Use L2OPT.
244 <tlbiel, tlbie>: Use LOPT.
245 <wclr, wclrall>: Use L2.
246
c5da1932
VZ		 2472016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
248
249 * Makefile.in: Regenerate.
250 * configure: Likewise.
251
2b848ebd
CZ		 2522016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
253
254 * arc-ext-tbl.h (EXTINSN2OPF): Define.
255 (EXTINSN2OP): Use EXTINSN2OPF.
256 (bspeekm, bspop, modapp): New extension instructions.
257 * arc-opc.c (F_DNZ_ND): Define.
258 (F_DNZ_D): Likewise.
259 (F_SIZEB1): Changed.
260 (C_DNZ_D): Define.
261 (C_HARD): Changed.
262 * arc-tbl.h (dbnz): New instruction.
263 (prealloc): Allow it for ARC EM.
264 (xbfu): Likewise.
265
ad43e107
RS		 2662016-09-21 Richard Sandiford <richard.sandiford@arm.com>
267
268 * aarch64-opc.c (print_immediate_offset_address): Print spaces
269 after commas in addresses.
270 (aarch64_print_operand): Likewise.
271
ab3b8fcf
RS		 2722016-09-21 Richard Sandiford <richard.sandiford@arm.com>
273
274 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
275 rather than "should be" or "expected to be" in error messages.
276
bb7eff52
RS		 2772016-09-21 Richard Sandiford <richard.sandiford@arm.com>
278
279 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
280 (print_mnemonic_name): ...here.
281 (print_comment): New function.
282 (print_aarch64_insn): Call it.
283 * aarch64-opc.c (aarch64_conds): Add SVE names.
284 (aarch64_print_operand): Print alternative condition names in
285 a comment.
286
c0890d26
RS		 2872016-09-21 Richard Sandiford <richard.sandiford@arm.com>
288
289 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
290 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
291 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
292 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
293 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
294 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
295 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
296 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
297 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
298 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
299 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
300 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
301 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
302 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
303 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
304 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
305 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
306 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
307 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
308 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
309 (OP_SVE_XWU, OP_SVE_XXU): New macros.
310 (aarch64_feature_sve): New variable.
311 (SVE): New macro.
312 (_SVE_INSN): Likewise.
313 (aarch64_opcode_table): Add SVE instructions.
314 * aarch64-opc.h (extract_fields): Declare.
315 * aarch64-opc-2.c: Regenerate.
316 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
317 * aarch64-asm-2.c: Regenerate.
318 * aarch64-dis.c (extract_fields): Make global.
319 (do_misc_decoding): Handle the new SVE aarch64_ops.
320 * aarch64-dis-2.c: Regenerate.
321
116b6019
RS		 3222016-09-21 Richard Sandiford <richard.sandiford@arm.com>
323
324 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
325 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
326 aarch64_field_kinds.
327 * aarch64-opc.c (fields): Add corresponding entries.
328 * aarch64-asm.c (aarch64_get_variant): New function.
329 (aarch64_encode_variant_using_iclass): Likewise.
330 (aarch64_opcode_encode): Call it.
331 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
332 (aarch64_opcode_decode): Call it.
333
047cd301
RS		 3342016-09-21 Richard Sandiford <richard.sandiford@arm.com>
335
336 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
337 and FP register operands.
338 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
339 (FLD_SVE_Vn): New aarch64_field_kinds.
340 * aarch64-opc.c (fields): Add corresponding entries.
341 (aarch64_print_operand): Handle the new SVE core and FP register
342 operands.
343 * aarch64-opc-2.c: Regenerate.
344 * aarch64-asm-2.c: Likewise.
345 * aarch64-dis-2.c: Likewise.
346
165d4950
RS		 3472016-09-21 Richard Sandiford <richard.sandiford@arm.com>
348
349 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
350 immediate operands.
351 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
352 * aarch64-opc.c (fields): Add corresponding entry.
353 (operand_general_constraint_met_p): Handle the new SVE FP immediate
354 operands.
355 (aarch64_print_operand): Likewise.
356 * aarch64-opc-2.c: Regenerate.
357 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
358 (ins_sve_float_zero_one): New inserters.
359 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
360 (aarch64_ins_sve_float_half_two): Likewise.
361 (aarch64_ins_sve_float_zero_one): Likewise.
362 * aarch64-asm-2.c: Regenerate.
363 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
364 (ext_sve_float_zero_one): New extractors.
365 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
366 (aarch64_ext_sve_float_half_two): Likewise.
367 (aarch64_ext_sve_float_zero_one): Likewise.
368 * aarch64-dis-2.c: Regenerate.
369
e950b345
RS		 3702016-09-21 Richard Sandiford <richard.sandiford@arm.com>
371
372 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
373 integer immediate operands.
374 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
375 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
376 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
377 * aarch64-opc.c (fields): Add corresponding entries.
378 (operand_general_constraint_met_p): Handle the new SVE integer
379 immediate operands.
380 (aarch64_print_operand): Likewise.
381 (aarch64_sve_dupm_mov_immediate_p): New function.
382 * aarch64-opc-2.c: Regenerate.
383 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
384 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
385 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
386 (aarch64_ins_limm): ...here.
387 (aarch64_ins_inv_limm): New function.
388 (aarch64_ins_sve_aimm): Likewise.
389 (aarch64_ins_sve_asimm): Likewise.
390 (aarch64_ins_sve_limm_mov): Likewise.
391 (aarch64_ins_sve_shlimm): Likewise.
392 (aarch64_ins_sve_shrimm): Likewise.
393 * aarch64-asm-2.c: Regenerate.
394 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
395 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
396 * aarch64-dis.c (decode_limm): New function, split out from...
397 (aarch64_ext_limm): ...here.
398 (aarch64_ext_inv_limm): New function.
399 (decode_sve_aimm): Likewise.
400 (aarch64_ext_sve_aimm): Likewise.
401 (aarch64_ext_sve_asimm): Likewise.
402 (aarch64_ext_sve_limm_mov): Likewise.
403 (aarch64_top_bit): Likewise.
404 (aarch64_ext_sve_shlimm): Likewise.
405 (aarch64_ext_sve_shrimm): Likewise.
406 * aarch64-dis-2.c: Regenerate.
407
98907a70
RS		 4082016-09-21 Richard Sandiford <richard.sandiford@arm.com>
409
410 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
411 operands.
412 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
413 the AARCH64_MOD_MUL_VL entry.
414 (value_aligned_p): Cope with non-power-of-two alignments.
415 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
416 (print_immediate_offset_address): Likewise.
417 (aarch64_print_operand): Likewise.
418 * aarch64-opc-2.c: Regenerate.
419 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
420 (ins_sve_addr_ri_s9xvl): New inserters.
421 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
422 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
423 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
424 * aarch64-asm-2.c: Regenerate.
425 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
426 (ext_sve_addr_ri_s9xvl): New extractors.
427 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
428 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
429 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
430 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
431 * aarch64-dis-2.c: Regenerate.
432
4df068de
RS		 4332016-09-21 Richard Sandiford <richard.sandiford@arm.com>
434
435 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
436 address operands.
437 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
438 (FLD_SVE_xs_22): New aarch64_field_kinds.
439 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
440 (get_operand_specific_data): New function.
441 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
442 FLD_SVE_xs_14 and FLD_SVE_xs_22.
443 (operand_general_constraint_met_p): Handle the new SVE address
444 operands.
445 (sve_reg): New array.
446 (get_addr_sve_reg_name): New function.
447 (aarch64_print_operand): Handle the new SVE address operands.
448 * aarch64-opc-2.c: Regenerate.
449 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
450 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
451 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
452 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
453 (aarch64_ins_sve_addr_rr_lsl): Likewise.
454 (aarch64_ins_sve_addr_rz_xtw): Likewise.
455 (aarch64_ins_sve_addr_zi_u5): Likewise.
456 (aarch64_ins_sve_addr_zz): Likewise.
457 (aarch64_ins_sve_addr_zz_lsl): Likewise.
458 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
459 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
460 * aarch64-asm-2.c: Regenerate.
461 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
462 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
463 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
464 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
465 (aarch64_ext_sve_addr_ri_u6): Likewise.
466 (aarch64_ext_sve_addr_rr_lsl): Likewise.
467 (aarch64_ext_sve_addr_rz_xtw): Likewise.
468 (aarch64_ext_sve_addr_zi_u5): Likewise.
469 (aarch64_ext_sve_addr_zz): Likewise.
470 (aarch64_ext_sve_addr_zz_lsl): Likewise.
471 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
472 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
473 * aarch64-dis-2.c: Regenerate.
474
2442d846
RS		 4752016-09-21 Richard Sandiford <richard.sandiford@arm.com>
476
477 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
478 AARCH64_OPND_SVE_PATTERN_SCALED.
479 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
480 * aarch64-opc.c (fields): Add a corresponding entry.
481 (set_multiplier_out_of_range_error): New function.
482 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
483 (operand_general_constraint_met_p): Handle
484 AARCH64_OPND_SVE_PATTERN_SCALED.
485 (print_register_offset_address): Use PRIi64 to print the
486 shift amount.
487 (aarch64_print_operand): Likewise. Handle
488 AARCH64_OPND_SVE_PATTERN_SCALED.
489 * aarch64-opc-2.c: Regenerate.
490 * aarch64-asm.h (ins_sve_scale): New inserter.
491 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
492 * aarch64-asm-2.c: Regenerate.
493 * aarch64-dis.h (ext_sve_scale): New inserter.
494 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
495 * aarch64-dis-2.c: Regenerate.
496
245d2e3f
RS		 4972016-09-21 Richard Sandiford <richard.sandiford@arm.com>
498
499 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
500 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
501 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
502 (FLD_SVE_prfop): Likewise.
503 * aarch64-opc.c: Include libiberty.h.
504 (aarch64_sve_pattern_array): New variable.
505 (aarch64_sve_prfop_array): Likewise.
506 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
507 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
508 AARCH64_OPND_SVE_PRFOP.
509 * aarch64-asm-2.c: Regenerate.
510 * aarch64-dis-2.c: Likewise.
511 * aarch64-opc-2.c: Likewise.
512
d50c751e
RS		 5132016-09-21 Richard Sandiford <richard.sandiford@arm.com>
514
515 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
516 AARCH64_OPND_QLF_P_[ZM].
517 (aarch64_print_operand): Print /z and /m where appropriate.
518
f11ad6bc
RS		 5192016-09-21 Richard Sandiford <richard.sandiford@arm.com>
520
521 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
522 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
523 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
524 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
525 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
526 * aarch64-opc.c (fields): Add corresponding entries here.
527 (operand_general_constraint_met_p): Check that SVE register lists
528 have the correct length. Check the ranges of SVE index registers.
529 Check for cases where p8-p15 are used in 3-bit predicate fields.
530 (aarch64_print_operand): Handle the new SVE operands.
531 * aarch64-opc-2.c: Regenerate.
532 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
533 * aarch64-asm.c (aarch64_ins_sve_index): New function.
534 (aarch64_ins_sve_reglist): Likewise.
535 * aarch64-asm-2.c: Regenerate.
536 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
537 * aarch64-dis.c (aarch64_ext_sve_index): New function.
538 (aarch64_ext_sve_reglist): Likewise.
539 * aarch64-dis-2.c: Regenerate.
540
0c608d6b
RS		 5412016-09-21 Richard Sandiford <richard.sandiford@arm.com>
542
543 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
544 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
545 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
546 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
547 tied operands.
548
01dbfe4c
RS		 5492016-09-21 Richard Sandiford <richard.sandiford@arm.com>
550
551 * aarch64-opc.c (get_offset_int_reg_name): New function.
552 (print_immediate_offset_address): Likewise.
553 (print_register_offset_address): Take the base and offset
554 registers as parameters.
555 (aarch64_print_operand): Update caller accordingly. Use
556 print_immediate_offset_address.
557
72e9f319
RS		 5582016-09-21 Richard Sandiford <richard.sandiford@arm.com>
559
560 * aarch64-opc.c (BANK): New macro.
561 (R32, R64): Take a register number as argument
562 (int_reg): Use BANK.
563
8a7f0c1b
RS		 5642016-09-21 Richard Sandiford <richard.sandiford@arm.com>
565
566 * aarch64-opc.c (print_register_list): Add a prefix parameter.
567 (aarch64_print_operand): Update accordingly.
568
aa2aa4c6
RS		 5692016-09-21 Richard Sandiford <richard.sandiford@arm.com>
570
571 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
572 for FPIMM.
573 * aarch64-asm.h (ins_fpimm): New inserter.
574 * aarch64-asm.c (aarch64_ins_fpimm): New function.
575 * aarch64-asm-2.c: Regenerate.
576 * aarch64-dis.h (ext_fpimm): New extractor.
577 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
578 (aarch64_ext_fpimm): New function.
579 * aarch64-dis-2.c: Regenerate.
580
b5464a68
RS		 5812016-09-21 Richard Sandiford <richard.sandiford@arm.com>
582
583 * aarch64-asm.c: Include libiberty.h.
584 (insert_fields): New function.
585 (aarch64_ins_imm): Use it.
586 * aarch64-dis.c (extract_fields): New function.
587 (aarch64_ext_imm): Use it.
588
42408347
RS		 5892016-09-21 Richard Sandiford <richard.sandiford@arm.com>
590
591 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
592 with an esize parameter.
593 (operand_general_constraint_met_p): Update accordingly.
594 Fix misindented code.
595 * aarch64-asm.c (aarch64_ins_limm): Update call to
596 aarch64_logical_immediate_p.
597
4989adac
RS		 5982016-09-21 Richard Sandiford <richard.sandiford@arm.com>
599
600 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
601
bd11d5d8
RS		 6022016-09-21 Richard Sandiford <richard.sandiford@arm.com>
603
604 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
605
f807f43d
CZ		 6062016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
607
608 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
609
fd486b63
PB		 6102016-09-14 Peter Bergner <bergner@vnet.ibm.com>
611
612 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
613 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
614 xor3>: Delete mnemonics.
615 <cp_abort>: Rename mnemonic from ...
616 <cpabort>: ...to this.
617 <setb>: Change to a X form instruction.
618 <sync>: Change to 1 operand form.
619 <copy>: Delete mnemonic.
620 <copy_first>: Rename mnemonic from ...
621 <copy>: ...to this.
622 <paste, paste.>: Delete mnemonics.
623 <paste_last>: Rename mnemonic from ...
624 <paste.>: ...to this.
625
dce08442
AK		 6262016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
627
628 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
629
952c3f51
AK		 6302016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
631
632 * s390-mkopc.c (main): Support alternate arch strings.
633
8b71537b
PS		 6342016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
635
636 * s390-opc.txt: Fix kmctr instruction type.
637
5b64d091
L		 6382016-09-07 H.J. Lu <hongjiu.lu@intel.com>
639
640 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
641 * i386-init.h: Regenerated.
642
7763838e
CM		 6432016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
644
645 * opcodes/arc-dis.c (print_insn_arc): Changed.
646
1b8b6532
JM		 6472016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
648
649 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
650 camellia_fl.
651
1a336194
TP		 6522016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
653
654 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
655 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
656 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
657
6b40c462
L		 6582016-08-24 H.J. Lu <hongjiu.lu@intel.com>
659
660 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
661 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
662 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
663 PREFIX_MOD_3_0FAE_REG_4.
664 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
665 PREFIX_MOD_3_0FAE_REG_4.
666 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
667 (cpu_flags): Add CpuPTWRITE.
668 * i386-opc.h (CpuPTWRITE): New.
669 (i386_cpu_flags): Add cpuptwrite.
670 * i386-opc.tbl: Add ptwrite instruction.
671 * i386-init.h: Regenerated.
672 * i386-tbl.h: Likewise.
673
ab548d2d
AK		 6742016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
675
676 * arc-dis.h: Wrap around in extern "C".
677
344bde0a
RS		 6782016-08-23 Richard Sandiford <richard.sandiford@arm.com>
679
680 * aarch64-tbl.h (V8_2_INSN): New macro.
681 (aarch64_opcode_table): Use it.
682
5ce912d8
RS		 6832016-08-23 Richard Sandiford <richard.sandiford@arm.com>
684
685 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
686 CORE_INSN, __FP_INSN and SIMD_INSN.
687
9d30b0bd
RS		 6882016-08-23 Richard Sandiford <richard.sandiford@arm.com>
689
690 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
691 (aarch64_opcode_table): Update uses accordingly.
692
dfdaec14
AJ		 6932016-07-25 Andrew Jenner <andrew@codesourcery.com>
694 Kwok Cheung Yeung <kcy@codesourcery.com>
695
696 opcodes/
697 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
698 'e_cmplwi' to 'e_cmpli' instead.
699 (OPVUPRT, OPVUPRT_MASK): Define.
700 (powerpc_opcodes): Add E200Z4 insns.
701 (vle_opcodes): Add context save/restore insns.
702
7bd374a4
MR		 7032016-07-27 Maciej W. Rozycki <macro@imgtec.com>
704
705 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
706 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
707 "j".
708
db18dbab
GM		 7092016-07-27 Graham Markall <graham.markall@embecosm.com>
710
711 * arc-nps400-tbl.h: Change block comments to GNU format.
712 * arc-dis.c: Add new globals addrtypenames,
713 addrtypenames_max, and addtypeunknown.
714 (get_addrtype): New function.
715 (print_insn_arc): Print colons and address types when
716 required.
717 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
718 define insert and extract functions for all address types.
719 (arc_operands): Add operands for colon and all address
720 types.
721 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
722 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
723 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
724 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
725 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
726 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
727
fecd57f9
L		 7282016-07-21 H.J. Lu <hongjiu.lu@intel.com>
729
730 * configure: Regenerated.
731
37fd5ef3
CZ		 7322016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
733
734 * arc-dis.c (skipclass): New structure.
735 (decodelist): New variable.
736 (is_compatible_p): New function.
737 (new_element): Likewise.
738 (skip_class_p): Likewise.
739 (find_format_from_table): Use skip_class_p function.
740 (find_format): Decode first the extension instructions.
741 (print_insn_arc): Select either ARCEM or ARCHS based on elf
742 e_flags.
743 (parse_option): New function.
744 (parse_disassembler_options): Likewise.
745 (print_arc_disassembler_options): Likewise.
746 (print_insn_arc): Use parse_disassembler_options function. Proper
747 select ARCv2 cpu variant.
748 * disassemble.c (disassembler_usage): Add ARC disassembler
749 options.
750
92281a5b
MR		 7512016-07-13 Maciej W. Rozycki <macro@imgtec.com>
752
753 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
754 annotation from the "nal" entry and reorder it beyond "bltzal".
755
6e7ced37
JM		 7562016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
757
758 * sparc-opc.c (ldtxa): New macro.
759 (sparc_opcodes): Use the macro defined above to add entries for
760 the LDTXA instructions.
761 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
762 instruction.
763
2f831b9a 7642016-07-07 James Bowman <james.bowman@ftdichip.com>
765
766 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
767 and "jmpc".
768
c07315e0
JB		 7692016-07-01 Jan Beulich <jbeulich@suse.com>
770
771 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
772 (movzb): Adjust to cover all permitted suffixes.
773 (movzw): New.
774 * i386-tbl.h: Re-generate.
775
9243100a
JB		 7762016-07-01 Jan Beulich <jbeulich@suse.com>
777
778 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
779 (lgdt): Remove Tbyte from non-64-bit variant.
780 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
781 xsaves64, xsavec64): Remove Disp16.
782 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
783 Remove Disp32S from non-64-bit variants. Remove Disp16 from
784 64-bit variants.
785 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
786 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
787 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
788 64-bit variants.
789 * i386-tbl.h: Re-generate.
790
8325cc63
JB		 7912016-07-01 Jan Beulich <jbeulich@suse.com>
792
793 * i386-opc.tbl (xlat): Remove RepPrefixOk.
794 * i386-tbl.h: Re-generate.
795
838441e4
YQ		 7962016-06-30 Yao Qi <yao.qi@linaro.org>
797
798 * arm-dis.c (print_insn): Fix typo in comment.
799
dab26bf4
RS		 8002016-06-28 Richard Sandiford <richard.sandiford@arm.com>
801
802 * aarch64-opc.c (operand_general_constraint_met_p): Check the
803 range of ldst_elemlist operands.
804 (print_register_list): Use PRIi64 to print the index.
805 (aarch64_print_operand): Likewise.
806
5703197e
TS		 8072016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
808
809 * mcore-opc.h: Remove sentinal.
810 * mcore-dis.c (print_insn_mcore): Adjust.
811
ce440d63
GM		 8122016-06-23 Graham Markall <graham.markall@embecosm.com>
813
814 * arc-opc.c: Correct description of availability of NPS400
815 features.
816
6fd3a02d
PB		 8172016-06-22 Peter Bergner <bergner@vnet.ibm.com>
818
819 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
820 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
821 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
822 xor3>: New mnemonics.
823 <setb>: Change to a VX form instruction.
824 (insert_sh6): Add support for rldixor.
825 (extract_sh6): Likewise.
826
6b477896
TS		 8272016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
828
829 * arc-ext.h: Wrap in extern C.
830
bdd582db
GM		 8312016-06-21 Graham Markall <graham.markall@embecosm.com>
832
833 * arc-dis.c (arc_insn_length): Add comment on instruction length.
834 Use same method for determining instruction length on ARC700 and
835 NPS-400.
836 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
837 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
838 with the NPS400 subclass.
839 * arc-opc.c: Likewise.
840
96074adc
JM		 8412016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
842
843 * sparc-opc.c (rdasr): New macro.
844 (wrasr): Likewise.
845 (rdpr): Likewise.
846 (wrpr): Likewise.
847 (rdhpr): Likewise.
848 (wrhpr): Likewise.
849 (sparc_opcodes): Use the macros above to fix and expand the
850 definition of read/write instructions from/to
851 asr/privileged/hyperprivileged instructions.
852 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
853 %hva_mask_nz. Prefer softint_set and softint_clear over
854 set_softint and clear_softint.
855 (print_insn_sparc): Support %ver in Rd.
856
7a10c22f
JM		 8572016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
858
859 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
860 architecture according to the hardware capabilities they require.
861
4f26fb3a
JM		 8622016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
863
864 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
865 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
866 bfd_mach_sparc_v9{c,d,e,v,m}.
867 * sparc-opc.c (MASK_V9C): Define.
868 (MASK_V9D): Likewise.
869 (MASK_V9E): Likewise.
870 (MASK_V9V): Likewise.
871 (MASK_V9M): Likewise.
872 (v6): Add MASK_V9{C,D,E,V,M}.
873 (v6notlet): Likewise.
874 (v7): Likewise.
875 (v8): Likewise.
876 (v9): Likewise.
877 (v9andleon): Likewise.
878 (v9a): Likewise.
879 (v9b): Likewise.
880 (v9c): Define.
881 (v9d): Likewise.
882 (v9e): Likewise.
883 (v9v): Likewise.
884 (v9m): Likewise.
885 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
886
3ee6e4fb
NC		 8872016-06-15 Nick Clifton <nickc@redhat.com>
888
889 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
890 constants to match expected behaviour.
891 (nds32_parse_opcode): Likewise. Also for whitespace.
892
02f3be19
AB		 8932016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
894
895 * arc-opc.c (extract_rhv1): Extract value from insn.
896
6f9f37ed 8972016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM		 898
899 * arc-nps400-tbl.h: Add ldbit instruction.
900 * arc-opc.c: Add flag classes required for ldbit.
901
6f9f37ed 9022016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM		 903
904 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
905 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
906 support the above instructions.
907
6f9f37ed 9082016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM		 909
910 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
911 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
912 csma, cbba, zncv, and hofs.
913 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
914 support the above instructions.
915
9162016-06-06 Graham Markall <graham.markall@embecosm.com>
917
918 * arc-nps400-tbl.h: Add andab and orab instructions.
919
9202016-06-06 Graham Markall <graham.markall@embecosm.com>
921
922 * arc-nps400-tbl.h: Add addl-like instructions.
923
9242016-06-06 Graham Markall <graham.markall@embecosm.com>
925
926 * arc-nps400-tbl.h: Add mxb and imxb instructions.
927
9282016-06-06 Graham Markall <graham.markall@embecosm.com>
929
930 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
931 instructions.
932
b2cc3f6f
AK		 9332016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
934
935 * s390-dis.c (option_use_insn_len_bits_p): New file scope
936 variable.
937 (init_disasm): Handle new command line option "insnlength".
938 (print_s390_disassembler_options): Mention new option in help
939 output.
940 (print_insn_s390): Use the encoded insn length when dumping
941 unknown instructions.
942
1857fe72
DC		 9432016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
944
945 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
946 to the address and set as symbol address for LDS/ STS immediate operands.
947
14b57c7c
AM		 9482016-06-07 Alan Modra <amodra@gmail.com>
949
950 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
951 cpu for "vle" to e500.
952 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
953 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
954 (PPCNONE): Delete, substitute throughout.
955 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
956 except for major opcode 4 and 31.
957 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
958
4d1464f2
MW		 9592016-06-07 Matthew Wahab <matthew.wahab@arm.com>
960
961 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
962 ARM_EXT_RAS in relevant entries.
963
026122a6
PB		 9642016-06-03 Peter Bergner <bergner@vnet.ibm.com>
965
966 PR binutils/20196
967 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
968 opcodes for E6500.
969
07f5af7d
L		 9702016-06-03 H.J. Lu <hongjiu.lu@intel.com>
971
972 PR binutis/18386
973 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
974 (indir_v_mode): New.
975 Add comments for '&'.
976 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
977 (putop): Handle '&'.
978 (intel_operand_size): Handle indir_v_mode.
979 (OP_E_register): Likewise.
980 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
981 64-bit indirect call/jmp for AMD64.
982 * i386-tbl.h: Regenerated
983
4eb6f892
AB		 9842016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
985
986 * arc-dis.c (struct arc_operand_iterator): New structure.
987 (find_format_from_table): All the old content from find_format,
988 with some minor adjustments, and parameter renaming.
989 (find_format_long_instructions): New function.
990 (find_format): Rewritten.
991 (arc_insn_length): Add LSB parameter.
992 (extract_operand_value): New function.
993 (operand_iterator_next): New function.
994 (print_insn_arc): Use new functions to find opcode, and iterator
995 over operands.
996 * arc-opc.c (insert_nps_3bit_dst_short): New function.
997 (extract_nps_3bit_dst_short): New function.
998 (insert_nps_3bit_src2_short): New function.
999 (extract_nps_3bit_src2_short): New function.
1000 (insert_nps_bitop1_size): New function.
1001 (extract_nps_bitop1_size): New function.
1002 (insert_nps_bitop2_size): New function.
1003 (extract_nps_bitop2_size): New function.
1004 (insert_nps_bitop_mod4_msb): New function.
1005 (extract_nps_bitop_mod4_msb): New function.
1006 (insert_nps_bitop_mod4_lsb): New function.
1007 (extract_nps_bitop_mod4_lsb): New function.
1008 (insert_nps_bitop_dst_pos3_pos4): New function.
1009 (extract_nps_bitop_dst_pos3_pos4): New function.
1010 (insert_nps_bitop_ins_ext): New function.
1011 (extract_nps_bitop_ins_ext): New function.
1012 (arc_operands): Add new operands.
1013 (arc_long_opcodes): New global array.
1014 (arc_num_long_opcodes): New global.
1015 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1016
1fe0971e
TS		 10172016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1018
1019 * nds32-asm.h: Add extern "C".
1020 * sh-opc.h: Likewise.
1021
315f180f
GM		 10222016-06-01 Graham Markall <graham.markall@embecosm.com>
1023
1024 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1025 0,b,limm to the rflt instruction.
1026
a2b5fccc
TS		 10272016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1028
1029 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1030 constant.
1031
0cbd0046
L		 10322016-05-29 H.J. Lu <hongjiu.lu@intel.com>
1033
1034 PR gas/20145
1035 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1036 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1037 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1038 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1039 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1040 * i386-init.h: Regenerated.
1041
1848e567
L		 10422016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1043
1044 PR gas/20145
1045 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
1046 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
1047 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1048 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1049 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
1050 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1051 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1052 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
1053 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1054 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1055 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
1056 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
1057 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
1058 CpuRegMask for AVX512.
1059 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1060 and CpuRegMask.
1061 (set_bitfield_from_cpu_flag_init): New function.
1062 (set_bitfield): Remove const on f. Call
1063 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1064 * i386-opc.h (CpuRegMMX): New.
1065 (CpuRegXMM): Likewise.
1066 (CpuRegYMM): Likewise.
1067 (CpuRegZMM): Likewise.
1068 (CpuRegMask): Likewise.
1069 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1070 and cpuregmask.
1071 * i386-init.h: Regenerated.
1072 * i386-tbl.h: Likewise.
1073
e92bae62
L		 10742016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1075
1076 PR gas/20154
1077 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1078 (opcode_modifiers): Add AMD64 and Intel64.
1079 (main): Properly verify CpuMax.
1080 * i386-opc.h (CpuAMD64): Removed.
1081 (CpuIntel64): Likewise.
1082 (CpuMax): Set to CpuNo64.
1083 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1084 (AMD64): New.
1085 (Intel64): Likewise.
1086 (i386_opcode_modifier): Add amd64 and intel64.
1087 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1088 on call and jmp.
1089 * i386-init.h: Regenerated.
1090 * i386-tbl.h: Likewise.
1091
e89c5eaa
L		 10922016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1093
1094 PR gas/20154
1095 * i386-gen.c (main): Fail if CpuMax is incorrect.
1096 * i386-opc.h (CpuMax): Set to CpuIntel64.
1097 * i386-tbl.h: Regenerated.
1098
77d66e7b
NC		 10992016-05-27 Nick Clifton <nickc@redhat.com>
1100
1101 PR target/20150
1102 * msp430-dis.c (msp430dis_read_two_bytes): New function.
1103 (msp430dis_opcode_unsigned): New function.
1104 (msp430dis_opcode_signed): New function.
1105 (msp430_singleoperand): Use the new opcode reading functions.
1106 Only disassenmble bytes if they were successfully read.
1107 (msp430_doubleoperand): Likewise.
1108 (msp430_branchinstr): Likewise.
1109 (msp430x_callx_instr): Likewise.
1110 (print_insn_msp430): Check that it is safe to read bytes before
1111 attempting disassembly. Use the new opcode reading functions.
1112
19dfcc89
PB		 11132016-05-26 Peter Bergner <bergner@vnet.ibm.com>
1114
1115 * ppc-opc.c (CY): New define. Document it.
1116 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1117
f3ad7637
L		 11182016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1119
1120 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1121 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1122 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
1123 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1124 CPU_ANY_AVX_FLAGS.
1125 * i386-init.h: Regenerated.
1126
f1360d58
L		 11272016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1128
1129 PR gas/20141
1130 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1131 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1132 * i386-init.h: Regenerated.
1133
293f5f65
L		 11342016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1135
1136 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1137 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
1138 * i386-init.h: Regenerated.
1139
d9eca1df
CZ		 11402016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1141
1142 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1143 information.
1144 (print_insn_arc): Set insn_type information.
1145 * arc-opc.c (C_CC): Add F_CLASS_COND.
1146 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1147 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1148 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1149 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1150 (brne, brne_s, jeq_s, jne_s): Likewise.
1151
87789e08
CZ		 11522016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1153
1154 * arc-tbl.h (neg): New instruction variant.
1155
c810e0b8
CZ		 11562016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
1157
1158 * arc-dis.c (find_format, find_format, get_auxreg)
1159 (print_insn_arc): Changed.
1160 * arc-ext.h (INSERT_XOP): Likewise.
1161
3d207518
TS		 11622016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1163
1164 * tic54x-dis.c (sprint_mmr): Adjust.
1165 * tic54x-opc.c: Likewise.
1166
514e58b7
AM		 11672016-05-19 Alan Modra <amodra@gmail.com>
1168
1169 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1170
e43de63c
AM		 11712016-05-19 Alan Modra <amodra@gmail.com>
1172
1173 * ppc-opc.c: Formatting.
1174 (NSISIGNOPT): Define.
1175 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1176
1401d2fe
MR		 11772016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1178
1179 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1180 replacing references to `micromips_ase' throughout.
1181 (_print_insn_mips): Don't use file-level microMIPS annotation to
1182 determine the disassembly mode with the symbol table.
1183
1178da44
PB		 11842016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1185
1186 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1187
8f4f9071
MF		 11882016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1189
1190 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1191 mips64r6.
1192 * mips-opc.c (D34): New macro.
1193 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1194
8bc52696
AF		 11952016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1196
1197 * i386-dis.c (prefix_table): Add RDPID instruction.
1198 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1199 (cpu_flags): Add RDPID bitfield.
1200 * i386-opc.h (enum): Add RDPID element.
1201 (i386_cpu_flags): Add RDPID field.
1202 * i386-opc.tbl: Add RDPID instruction.
1203 * i386-init.h: Regenerate.
1204 * i386-tbl.h: Regenerate.
1205
39d911fc
TP		 12062016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1207
1208 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1209 branch type of a symbol.
1210 (print_insn): Likewise.
1211
16a1fa25
TP		 12122016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1213
1214 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1215 Mainline Security Extensions instructions.
1216 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1217 Extensions instructions.
1218 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1219 instructions.
1220 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1221 special registers.
1222
d751b79e
JM		 12232016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1224
1225 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1226
945e0f82
CZ		 12272016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1228
1229 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1230 (arcExtMap_genOpcode): Likewise.
1231 * arc-opc.c (arg_32bit_rc): Define new variable.
1232 (arg_32bit_u6): Likewise.
1233 (arg_32bit_limm): Likewise.
1234
20f55f38
SN		 12352016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1236
1237 * aarch64-gen.c (VERIFIER): Define.
1238 * aarch64-opc.c (VERIFIER): Define.
1239 (verify_ldpsw): Use static linkage.
1240 * aarch64-opc.h (verify_ldpsw): Remove.
1241 * aarch64-tbl.h: Use VERIFIER for verifiers.
1242
4bd13cde
NC		 12432016-04-28 Nick Clifton <nickc@redhat.com>
1244
1245 PR target/19722
1246 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1247 * aarch64-opc.c (verify_ldpsw): New function.
1248 * aarch64-opc.h (verify_ldpsw): New prototype.
1249 * aarch64-tbl.h: Add initialiser for verifier field.
1250 (LDPSW): Set verifier to verify_ldpsw.
1251
c0f92bf9
L		 12522016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1253
1254 PR binutils/19983
1255 PR binutils/19984
1256 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1257 smaller than address size.
1258
e6c7cdec
TS		 12592016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1260
1261 * alpha-dis.c: Regenerate.
1262 * crx-dis.c: Likewise.
1263 * disassemble.c: Likewise.
1264 * epiphany-opc.c: Likewise.
1265 * fr30-opc.c: Likewise.
1266 * frv-opc.c: Likewise.
1267 * ip2k-opc.c: Likewise.
1268 * iq2000-opc.c: Likewise.
1269 * lm32-opc.c: Likewise.
1270 * lm32-opinst.c: Likewise.
1271 * m32c-opc.c: Likewise.
1272 * m32r-opc.c: Likewise.
1273 * m32r-opinst.c: Likewise.
1274 * mep-opc.c: Likewise.
1275 * mt-opc.c: Likewise.
1276 * or1k-opc.c: Likewise.
1277 * or1k-opinst.c: Likewise.
1278 * tic80-opc.c: Likewise.
1279 * xc16x-opc.c: Likewise.
1280 * xstormy16-opc.c: Likewise.
1281
537aefaf
AB		 12822016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1283
1284 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1285 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1286 calcsd, and calcxd instructions.
1287 * arc-opc.c (insert_nps_bitop_size): Delete.
1288 (extract_nps_bitop_size): Delete.
1289 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1290 (extract_nps_qcmp_m3): Define.
1291 (extract_nps_qcmp_m2): Define.
1292 (extract_nps_qcmp_m1): Define.
1293 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1294 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1295 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1296 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1297 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1298 NPS_QCMP_M3.
1299
c8f785f2
AB		 13002016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1301
1302 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1303
6fd8e7c2
L		 13042016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1305
1306 * Makefile.in: Regenerated with automake 1.11.6.
1307 * aclocal.m4: Likewise.
1308
4b0c052e
AB		 13092016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1310
1311 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1312 instructions.
1313 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1314 (extract_nps_cmem_uimm16): New function.
1315 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1316
cb040366
AB		 13172016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1318
1319 * arc-dis.c (arc_insn_length): New function.
1320 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1321 (find_format): Change insnLen parameter to unsigned.
1322
accc0180
NC		 13232016-04-13 Nick Clifton <nickc@redhat.com>
1324
1325 PR target/19937
1326 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1327 the LD.B and LD.BU instructions.
1328
f36e33da
CZ		 13292016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1330
1331 * arc-dis.c (find_format): Check for extension flags.
1332 (print_flags): New function.
1333 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1334 .extAuxRegister.
1335 * arc-ext.c (arcExtMap_coreRegName): Use
1336 LAST_EXTENSION_CORE_REGISTER.
1337 (arcExtMap_coreReadWrite): Likewise.
1338 (dump_ARC_extmap): Update printing.
1339 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1340 (arc_aux_regs): Add cpu field.
1341 * arc-regs.h: Add cpu field, lower case name aux registers.
1342
1c2e355e
CZ		 13432016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1344
1345 * arc-tbl.h: Add rtsc, sleep with no arguments.
1346
b99747ae
CZ		 13472016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1348
1349 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1350 Initialize.
1351 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1352 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1353 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1354 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1355 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1356 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1357 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1358 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1359 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1360 (arc_opcode arc_opcodes): Null terminate the array.
1361 (arc_num_opcodes): Remove.
1362 * arc-ext.h (INSERT_XOP): Define.
1363 (extInstruction_t): Likewise.
1364 (arcExtMap_instName): Delete.
1365 (arcExtMap_insn): New function.
1366 (arcExtMap_genOpcode): Likewise.
1367 * arc-ext.c (ExtInstruction): Remove.
1368 (create_map): Zero initialize instruction fields.
1369 (arcExtMap_instName): Remove.
1370 (arcExtMap_insn): New function.
1371 (dump_ARC_extmap): More info while debuging.
1372 (arcExtMap_genOpcode): New function.
1373 * arc-dis.c (find_format): New function.
1374 (print_insn_arc): Use find_format.
1375 (arc_get_disassembler): Enable dump_ARC_extmap only when
1376 debugging.
1377
92708cec
MR		 13782016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1379
1380 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1381 instruction bits out.
1382
a42a4f84
AB		 13832016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1384
1385 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1386 * arc-opc.c (arc_flag_operands): Add new flags.
1387 (arc_flag_classes): Add new classes.
1388
1328504b
AB		 13892016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1390
1391 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1392
820f03ff
AB		 13932016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1394
1395 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1396 encode1, rflt, crc16, and crc32 instructions.
1397 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1398 (arc_flag_classes): Add C_NPS_R.
1399 (insert_nps_bitop_size_2b): New function.
1400 (extract_nps_bitop_size_2b): Likewise.
1401 (insert_nps_bitop_uimm8): Likewise.
1402 (extract_nps_bitop_uimm8): Likewise.
1403 (arc_operands): Add new operand entries.
1404
8ddf6b2a
CZ		 14052016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1406
b99747ae
CZ		 1407 * arc-regs.h: Add a new subclass field. Add double assist
1408 accumulator register values.
1409 * arc-tbl.h: Use DPA subclass to mark the double assist
1410 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1411 * arc-opc.c (RSP): Define instead of SP.
1412 (arc_aux_regs): Add the subclass field.
8ddf6b2a 1413
589a7d88
JW		 14142016-04-05 Jiong Wang <jiong.wang@arm.com>
1415
1416 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1417
0a191de9 14182016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 1419
1420 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1421 NPS_R_SRC1.
1422
0a106562
AB		 14232016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1424
1425 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1426 issues. No functional changes.
1427
bd05ac5f
CZ		 14282016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1429
b99747ae
CZ		 1430 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1431 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1432 (RTT): Remove duplicate.
1433 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1434 (PCT_CONFIG*): Remove.
1435 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 1436
9885948f
CZ		 14372016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1438
b99747ae 1439 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 1440
f2dd8838
CZ		 14412016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1442
b99747ae
CZ		 1443 * arc-tbl.h (invld07): Remove.
1444 * arc-ext-tbl.h: New file.
1445 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1446 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 1447
0d2f91fe
JK		 14482016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1449
1450 Fix -Wstack-usage warnings.
1451 * aarch64-dis.c (print_operands): Substitute size.
1452 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1453
a6b71f42
JM		 14542016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1455
1456 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1457 to get a proper diagnostic when an invalid ASR register is used.
1458
9780e045
NC		 14592016-03-22 Nick Clifton <nickc@redhat.com>
1460
1461 * configure: Regenerate.
1462
e23e8ebe
AB		 14632016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1464
1465 * arc-nps400-tbl.h: New file.
1466 * arc-opc.c: Add top level comment.
1467 (insert_nps_3bit_dst): New function.
1468 (extract_nps_3bit_dst): New function.
1469 (insert_nps_3bit_src2): New function.
1470 (extract_nps_3bit_src2): New function.
1471 (insert_nps_bitop_size): New function.
1472 (extract_nps_bitop_size): New function.
1473 (arc_flag_operands): Add nps400 entries.
1474 (arc_flag_classes): Add nps400 entries.
1475 (arc_operands): Add nps400 entries.
1476 (arc_opcodes): Add nps400 include.
1477
1ae8ab47
AB		 14782016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1479
1480 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1481 the new class enum values.
1482
8699fc3e
AB		 14832016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1484
1485 * arc-dis.c (print_insn_arc): Handle nps400.
1486
24740d83
AB		 14872016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1488
1489 * arc-opc.c (BASE): Delete.
1490
8678914f
NC		 14912016-03-18 Nick Clifton <nickc@redhat.com>
1492
1493 PR target/19721
1494 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1495 of MOV insn that aliases an ORR insn.
1496
cc933301
JW		 14972016-03-16 Jiong Wang <jiong.wang@arm.com>
1498
1499 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1500
f86f5863
TS		 15012016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1502
1503 * mcore-opc.h: Add const qualifiers.
1504 * microblaze-opc.h (struct op_code_struct): Likewise.
1505 * sh-opc.h: Likewise.
1506 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1507 (tic4x_print_op): Likewise.
1508
62de1c63
AM		 15092016-03-02 Alan Modra <amodra@gmail.com>
1510
d11698cd 1511 * or1k-desc.h: Regenerate.
62de1c63 1512 * fr30-ibld.c: Regenerate.
c697cf0b 1513 * rl78-decode.c: Regenerate.
62de1c63 1514
020efce5
NC		 15152016-03-01 Nick Clifton <nickc@redhat.com>
1516
1517 PR target/19747
1518 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1519
b0c11777
RL		 15202016-02-24 Renlin Li <renlin.li@arm.com>
1521
1522 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1523 (print_insn_coprocessor): Support fp16 instructions.
1524
3e309328
RL		 15252016-02-24 Renlin Li <renlin.li@arm.com>
1526
1527 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1528 vminnm, vrint(mpna).
1529
8afc7bea
RL		 15302016-02-24 Renlin Li <renlin.li@arm.com>
1531
1532 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1533 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1534
4fd7268a
L		 15352016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1536
1537 * i386-dis.c (print_insn): Parenthesize expression to prevent
1538 truncated addresses.
1539 (OP_J): Likewise.
1540
4670103e
CZ		 15412016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1542 Janek van Oirschot <jvanoirs@synopsys.com>
1543
b99747ae
CZ		 1544 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1545 variable.
4670103e 1546
c1d9289f
NC		 15472016-02-04 Nick Clifton <nickc@redhat.com>
1548
1549 PR target/19561
1550 * msp430-dis.c (print_insn_msp430): Add a special case for
1551 decoding an RRC instruction with the ZC bit set in the extension
1552 word.
1553
a143b004
AB		 15542016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1555
1556 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1557 * epiphany-ibld.c: Regenerate.
1558 * fr30-ibld.c: Regenerate.
1559 * frv-ibld.c: Regenerate.
1560 * ip2k-ibld.c: Regenerate.
1561 * iq2000-ibld.c: Regenerate.
1562 * lm32-ibld.c: Regenerate.
1563 * m32c-ibld.c: Regenerate.
1564 * m32r-ibld.c: Regenerate.
1565 * mep-ibld.c: Regenerate.
1566 * mt-ibld.c: Regenerate.
1567 * or1k-ibld.c: Regenerate.
1568 * xc16x-ibld.c: Regenerate.
1569 * xstormy16-ibld.c: Regenerate.
1570
b89807c6
AB		 15712016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1572
1573 * epiphany-dis.c: Regenerated from latest cpu files.
1574
d8c823c8
MM		 15752016-02-01 Michael McConville <mmcco@mykolab.com>
1576
1577 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1578 test bit.
1579
5bc5ae88
RL		 15802016-01-25 Renlin Li <renlin.li@arm.com>
1581
1582 * arm-dis.c (mapping_symbol_for_insn): New function.
1583 (find_ifthen_state): Call mapping_symbol_for_insn().
1584
0bff6e2d
MW		 15852016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1586
1587 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1588 of MSR UAO immediate operand.
1589
100b4f2e
MR		 15902016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1591
1592 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1593 instruction support.
1594
5c14705f
AM		 15952016-01-17 Alan Modra <amodra@gmail.com>
1596
1597 * configure: Regenerate.
1598
4d82fe66
NC		 15992016-01-14 Nick Clifton <nickc@redhat.com>
1600
1601 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1602 instructions that can support stack pointer operations.
1603 * rl78-decode.c: Regenerate.
1604 * rl78-dis.c: Fix display of stack pointer in MOVW based
1605 instructions.
1606
651657fa
MW		 16072016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1608
1609 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1610 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1611 erxtatus_el1 and erxaddr_el1.
1612
105bde57
MW		 16132016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1614
1615 * arm-dis.c (arm_opcodes): Add "esb".
1616 (thumb_opcodes): Likewise.
1617
afa8d405
PB		 16182016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1619
1620 * ppc-opc.c <xscmpnedp>: Delete.
1621 <xvcmpnedp>: Likewise.
1622 <xvcmpnedp.>: Likewise.
1623 <xvcmpnesp>: Likewise.
1624 <xvcmpnesp.>: Likewise.
1625
83c3256e
AS		 16262016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1627
1628 PR gas/13050
1629 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1630 addition to ISA_A.
1631
6f2750fe
AM		 16322016-01-01 Alan Modra <amodra@gmail.com>
1633
1634 Update year range in copyright notice of all files.
1635
3499769a
AM		 1636For older changes see ChangeLog-2015
1637\f
1638Copyright (C) 2016 Free Software Foundation, Inc.
1639
1640Copying and distribution of this file, with or without modification,
1641are permitted in any medium without royalty provided the copyright
1642notice and this notice are preserved.
1643
1644Local Variables:
1645mode: change-log
1646left-margin: 8
1647fill-column: 74
1648version-control: never
1649End:
GDB Binutils - Deliverables
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