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Use gdb_bfd_sections in get_stap_base_address
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
6e25f888
DF		 12020-09-18 David Faust <david.faust@oracle.com>
2
3 * bpf-desc.c: Regenerate.
4 * bpf-desc.h: Likewise.
5 * bpf-opc.c: Likewise.
6 * bpf-opc.h: Likewise.
7
c568ac5f
AB		 82020-09-16 Andrew Burgess <andrew.burgess@embecosm.com>
9
10 * csky-dis.c (csky_get_disassembler): Don't return NULL when there
11 is no BFD.
12
c1229f84
AM		 132020-09-16 Alan Modra <amodra@gmail.com>
14
15 * ppc-dis.c (ppc_symbol_is_valid): Adjust elf_symbol_from invocation.
16
7ad57880
NC		 172020-09-10 Nick Clifton <nickc@redhat.com>
18
19 * ppc-dis.c (ppc_symbol_is_valid): New function. Returns false
20 for hidden, local, no-type symbols.
21 (disassemble_init_powerpc): Point the symbol_is_valid field in the
22 info structure at the new function.
23
79c8d443
CQ		 242020-09-10 Cooper Qu <cooper.qu@linux.alibaba.com>
25
26 * csky-opc.h (csky_v2_opcodes): Add L2Cache instructions.
27 * testsuite/gas/csky/cskyv2_ck860.d : Adjust to icache.iva
28 opcode fixing.
29
0332f662
NC		 302020-09-10 Nick Clifton <nickc@redhat.com>
31
32 * csky-dis.c (csky_output_operand): Coerce the immediate values to
33 long before printing.
34
23bef3fe
AM		 352020-09-10 Alan Modra <amodra@gmail.com>
36
37 * csky-dis.c (csky_output_operand): Don't sprintf str to itself.
38
6a1ed910
CQ		 392020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
40
41 * csky-opc.h (csky_v2_opcodes): Change mvtc and mulsw's
42 ISA flag.
43
1feede9b
CQ		 442020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
45
46 * csky-dis.c (csky_output_operand): Add handlers for
47 OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
48 OPRND_TYPE_DFLOAT_FMOVI. Refine OPRND_TYPE_FREGLIST_DASH
49 to support FPUV3 instructions.
50 * csky-opc.h (enum operand_type): New enum OPRND_TYPE_IMM9b,
51 OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
52 OPRND_TYPE_DFLOAT_FMOVI.
53 (OPRND_MASK_4_5, OPRND_MASK_6, OPRND_MASK_6_7, OPRND_MASK_6_8,
54 OPRND_MASK_7, OPRND_MASK_7_8, OPRND_MASK_17_24,
55 OPRND_MASK_20, OPRND_MASK_20_21, OPRND_MASK_20_22,
56 OPRND_MASK_20_23, OPRND_MASK_20_24, OPRND_MASK_20_25,
57 OPRND_MASK_0_3or5_8, OPRND_MASK_0_3or6_7, OPRND_MASK_0_3or25,
58 OPRND_MASK_0_4or21_24, OPRND_MASK_5or20_21,
59 OPRND_MASK_5or20_22, OPRND_MASK_5or20_23, OPRND_MASK_5or20_24,
60 OPRND_MASK_5or20_25, OPRND_MASK_8_9or21_25,
61 OPRND_MASK_8_9or16_25, OPRND_MASK_4_6or20, OPRND_MASK_5_7or20,
62 OPRND_MASK_4_5or20or25, OPRND_MASK_4_6or20or25,
63 OPRND_MASK_4_7or20or25, OPRND_MASK_6_9or17_24,
64 OPRND_MASK_6_7or20, OPRND_MASK_6or20, OPRND_MASK_7or20,
65 OPRND_MASK_5or8_9or16_25, OPRND_MASK_5or8_9or20_25): Define.
66 (csky_v2_opcodes): Add FPUV3 instructions.
67
38cf07a6
AC		 682020-09-08 Alex Coplan <alex.coplan@arm.com>
69
70 * aarch64-dis.c (print_operands): Pass CPU features to
71 aarch64_print_operand().
72 * aarch64-opc.c (aarch64_print_operand): Use CPU features to determine
73 preferred disassembly of system registers.
74 (SR_RNG): Refactor to use new SR_FEAT2 macro.
75 (SR_FEAT2): New.
76 (SR_V8_1_A): New.
77 (SR_V8_4_A): New.
78 (SR_V8_A): New.
79 (SR_V8_R): New.
80 (SR_EXPAND_ELx): New.
81 (SR_EXPAND_EL12): New.
82 (aarch64_sys_regs): Specify which registers are only on
83 A-profile, add R-profile system registers.
84 (ENC_BARLAR): New.
85 (PRBARn_ELx): New.
86 (PRLARn_ELx): New.
87 (aarch64_sys_ins_reg_supported_p): Reject EL3 registers for
88 Armv8-R AArch64.
89
03fb3142
AC		 902020-09-08 Alex Coplan <alex.coplan@arm.com>
91
92 * aarch64-tbl.h (aarch64_feature_v8_r): New.
93 (ARMV8_R): New.
94 (V8_R_INSN): New.
95 (aarch64_opcode_table): Add dfb.
96 * aarch64-opc-2.c: Regenerate.
97 * aarch64-asm-2.c: Regenerate.
98 * aarch64-dis-2.c: Regenerate.
99
95830c98
AC		 1002020-09-08 Alex Coplan <alex.coplan@arm.com>
101
102 * aarch64-dis.c (arch_variant): New.
103 (determine_disassembling_preference): Disassemble according to
104 arch variant.
105 (select_aarch64_variant): New.
106 (print_insn_aarch64): Set feature set.
107
7c80dd4c
AM		 1082020-09-02 Alan Modra <amodra@gmail.com>
109
110 * v850-opc.c (insert_i5div1, insert_i5div2, insert_i5div3),
111 (insert_d5_4, insert_d8_6, insert_d8_7, insert_v8, insert_d9),
112 (insert_u16_loop, insert_d16_15, insert_d16_16, insert_d17_16),
113 (insert_d22, insert_d23, insert_d23_align1, insert_i9, insert_u9),
114 (insert_spe, insert_r4, insert_POS, insert_WIDTH, insert_SELID),
115 (insert_VECTOR8, insert_VECTOR5, insert_CACHEOP, insert_PREFOP),
116 (nsert_IMM10U, insert_SRSEL1, insert_SRSEL2): Use unsigned long
117 for value parameter and update code to suit.
118 (extract_d9, extract_d16_15, extract_d16_16, extract_d17_16),
119 (extract_d22, extract_d23, extract_i9): Use unsigned long variables.
120
b4b39349
AM		 1212020-09-02 Alan Modra <amodra@gmail.com>
122
123 * i386-dis.c (OP_E_memory): Don't cast to signed type when
124 negating.
125 (get32, get32s): Use unsigned types in shift expressions.
126
caf4537a
AM		 1272020-09-02 Alan Modra <amodra@gmail.com>
128
129 * csky-dis.c (print_insn_csky): Use unsigned type for "given".
130
3c5097ea
AM		 1312020-09-02 Alan Modra <amodra@gmail.com>
132
133 * crx-dis.c: Whitespace.
134 (print_arg): Use unsigned type for longdisp and mask variables,
135 and for left shift constant.
136
ae3e98b4
AM		 1372020-09-02 Alan Modra <amodra@gmail.com>
138
139 * cgen-ibld.in (insert_normal, extract_normal): Use 1UL in left shift.
140 * bpf-ibld.c: Regenerate.
141 * epiphany-ibld.c: Regenerate.
142 * fr30-ibld.c: Regenerate.
143 * frv-ibld.c: Regenerate.
144 * ip2k-ibld.c: Regenerate.
145 * iq2000-ibld.c: Regenerate.
146 * lm32-ibld.c: Regenerate.
147 * m32c-ibld.c: Regenerate.
148 * m32r-ibld.c: Regenerate.
149 * mep-ibld.c: Regenerate.
150 * mt-ibld.c: Regenerate.
151 * or1k-ibld.c: Regenerate.
152 * xc16x-ibld.c: Regenerate.
153 * xstormy16-ibld.c: Regenerate.
154
427202d9
AM		 1552020-09-02 Alan Modra <amodra@gmail.com>
156
157 * bfin-dis.c (MASKBITS): Use SIGNBIT.
158
4211a340
CQ		 1592020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
160
161 * csky-opc.h (csky_v2_opcodes): Move divul and divsl
162 to CSKYV2_ISA_3E3R3 instruction set.
163
8119cc38
CQ		 1642020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
165
166 * csky-opc.h (csky_v2_opcodes): Fix Encode of mulsws.
167
8dbe96f0
AM		 1682020-09-01 Alan Modra <amodra@gmail.com>
169
170 * mep-ibld.c: Regenerate.
171
e2e82b11
CQ		 1722020-08-31 Cooper Qu <cooper.qu@linux.alibaba.com>
173
174 * csky-dis.c (csky_output_operand): Assign dis_info.value for
175 OPRND_TYPE_VREG.
176
2781f857
AM		 1772020-08-30 Alan Modra <amodra@gmail.com>
178
179 * cr16-dis.c: Formatting.
180 (parameter): Delete struct typedef. Use dwordU instead
181 throughout file.
182 (make_argument <arg_idxr>): Simplify detection of cbitb, sbitb
183 and tbitb.
184 (make_argument <arg_cr>): Extract 20-bit field not 16-bit.
185
0c0577f6
AM		 1862020-08-29 Alan Modra <amodra@gmail.com>
187
188 PR 26446
189 * csky-opc.h (MAX_OPRND_NUM): Define to 5.
190 (union csky_operand): Use MAX_OPRND_NUM to size oprnds array.
191
a1e60a1b
AM		 1922020-08-28 Alan Modra <amodra@gmail.com>
193
194 PR 26449
195 PR 26450
196 * cgen-ibld.in (insert_1): Use 1UL in forming mask.
197 (extract_normal): Likewise.
198 (insert_normal): Likewise, and move past zero length test.
199 (put_insn_int_value): Handle mask for zero length, use 1UL.
200 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
201 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
202 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
203 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
204
0861f561
CQ		 2052020-08-28 Cooper Qu <cooper.qu@linux.alibaba.com>
206
207 * csky-dis.c (CSKY_DEFAULT_ISA): Define.
208 (csky_dis_info): Add member isa.
209 (csky_find_inst_info): Skip instructions that do not belong to
210 current CPU.
211 (csky_get_disassembler): Get infomation from attribute section.
212 (print_insn_csky): Set defualt ISA flag.
213 * csky.h (CSKY_ISA_VDSP_2): Rename from CSKY_ISA_VDSP_V2.
214 * csky-opc.h (struct csky_opcode): Change isa_flag16 and
215 isa_flag32'type to unsigned 64 bits.
216
31b3f3e6
JM		 2172020-08-26 Jose E. Marchesi <jemarch@gnu.org>
218
219 * disassemble.c (enum epbf_isa_attr): Add ISA_XBPFBE, ISA_EBPFMAX.
220
4449c81a
DF		 2212020-08-26 David Faust <david.faust@oracle.com>
222
223 * bpf-desc.c: Regenerate.
224 * bpf-desc.h: Likewise.
225 * bpf-opc.c: Likewise.
226 * bpf-opc.h: Likewise.
227 * disassemble.c (disassemble_init_for_target): Set bits for xBPF
228 ISA when appropriate.
229
8640c87d
AM		 2302020-08-25 Alan Modra <amodra@gmail.com>
231
232 PR 26504
233 * vax-dis.c (parse_disassembler_options): Always add at least one
234 to entry_addr_total_slots.
235
531c73a3
CQ		 2362020-08-24 Cooper Qu <cooper.qu@linux.alibaba.com>
237
238 * csky-dis.c (csky_find_inst_info): Skip CK860's instructions
239 in other CPUs to speed up disassembling.
240 * csky-opc.h (csky_v2_opcodes): Add CK860's instructions,
241 Change plsli.u16 to plsli.16, change sync's operand format.
242
d04aee0f
CQ		 2432020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
244
245 * csky-opc.h (csky_v2_opcodes): Add instruction bnezad.
246
ccf61261
NC		 2472020-08-21 Nick Clifton <nickc@redhat.com>
248
249 * aarch64-dis.c (get_sym_code_type): Return FALSE for non-ELF
250 symbols.
251
d285ba8d
CQ		 2522020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
253
254 * csky-opc.h (csky_v2_opcodes): Add two operands form for bloop.
255
18a8a00e
AM		 2562020-08-19 Alan Modra <amodra@gmail.com>
257
258 * ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq,
259 vcmpuq and xvtlsbb.
260
587a4371
PB		 2612020-08-18 Peter Bergner <bergner@linux.ibm.com>
262
263 * ppc-opc.c (powerpc_opcodes) <xvcvbf16sp>: Rename from this...
264 <xvcvbf16spn>: ...to this.
265
2e49fd1e
AC		 2662020-08-12 Alex Coplan <alex.coplan@arm.com>
267
268 * aarch64-opc.c (aarch64_sys_regs): Add MPAM registers.
269
79ddc884
NC		 2702020-08-12 Nick Clifton <nickc@redhat.com>
271
272 * po/sr.po: Updated Serbian translation.
273
08770ec2
AM		 2742020-08-11 Alan Modra <amodra@gmail.com>
275
276 * ppc-opc.c (powerpc_opcodes): Move cctpl, cctpm and cctph.
277
f7cb161e
PW		 2782020-08-10 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
279
280 * aarch64-opc.c (aarch64_print_operand):
281 (aarch64_sys_reg_deprecated_p): Functions paramaters changed.
282 (aarch64_sys_reg_supported_p): Function removed.
283 (aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
284 (aarch64_sys_ins_reg_supported_p): Merged aarch64_sys_reg_supported_p
285 into this function.
286
3eb65174
AM		 2872020-08-10 Alan Modra <amodra@gmail.com>
288
289 * ppc-opc.c (powerpc_opcodes): Add many mtspr and mfspr extended
290 instructions.
291
8b2742a1
AM		 2922020-08-10 Alan Modra <amodra@gmail.com>
293
294 * ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru.
295 Enable icbt for power5, miso for power8.
296
5fbec329
AM		 2972020-08-10 Alan Modra <amodra@gmail.com>
298
299 * ppc-opc.c (powerpc_opcodes): Prioritise mtfprd and mtvrd over
300 mtvsrd, and similarly for mfvsrd.
301
563a3225
CG		 3022020-08-04 Christian Groessler <chris@groessler.org>
303 Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com>
304
305 * z8kgen.c (opt): Fix "sout imm16,rs" and "soutb imm16,rbs"
306 opcodes (special "out" to absolute address).
307 * z8k-opc.h: Regenerate.
308
41eb8e88
L		 3092020-07-30 H.J. Lu <hongjiu.lu@intel.com>
310
311 PR gas/26305
312 * i386-opc.h (Prefix_Disp8): New.
313 (Prefix_Disp16): Likewise.
314 (Prefix_Disp32): Likewise.
315 (Prefix_Load): Likewise.
316 (Prefix_Store): Likewise.
317 (Prefix_VEX): Likewise.
318 (Prefix_VEX3): Likewise.
319 (Prefix_EVEX): Likewise.
320 (Prefix_REX): Likewise.
321 (Prefix_NoOptimize): Likewise.
322 * i386-opc.tbl: Use Prefix_XXX on pseudo prefixes. Add {disp16}.
323 * i386-tbl.h: Regenerated.
324
98116973
AA		 3252020-07-29 Andreas Arnez <arnez@linux.ibm.com>
326
327 * s390-mkopc.c (insertExpandedMnemonic): Handle unreachable
328 default case with abort() instead of printing an error message and
329 continuing, to avoid a maybe-uninitialized warning.
330
2dddfa20
NC		 3312020-07-24 Nick Clifton <nickc@redhat.com>
332
333 * po/de.po: Updated German translation.
334
bf4ba07c
JB		 3352020-07-21 Jan Beulich <jbeulich@suse.com>
336
337 * i386-dis.c (OP_E_memory): Revert previous change.
338
04c662e2
L		 3392020-07-15 H.J. Lu <hongjiu.lu@intel.com>
340
341 PR gas/26237
342 * i386-dis.c (OP_E_memory): Don't display eiz with no scale
343 without base nor index registers.
344
f0e8d0ba
JB		 3452020-07-15 Jan Beulich <jbeulich@suse.com>
346
347 * i386-dis.c (putop): Move 'V' and 'W' handling.
348
c3f5525f
JB		 3492020-07-15 Jan Beulich <jbeulich@suse.com>
350
351 * i386-dis.c (dis386): Adjust 'V' description. Use P-based
352 construct for push/pop of register.
353 (putop): Honor cond when handling 'P'. Drop handling of plain
354 'V'.
355
36938cab
JB		 3562020-07-15 Jan Beulich <jbeulich@suse.com>
357
358 * i386-dis.c (dis386): Adjust 'P', 'T', 'U', and '@'
359 description. Drop '&' description. Use P for push of immediate,
360 pushf/popf, enter, and leave. Use %LP for lret/retf.
361 (dis386_twobyte): Use P for push/pop of fs/gs.
362 (reg_table): Use P for push/pop. Use @ for near call/jmp.
363 (x86_64_table): Use P for far call/jmp.
364 (putop): Drop handling of 'U' and '&'. Move and adjust handling
365 of '@'. Adjust handling of 'P' and 'T'. Drop case_P and case_Q
366 labels.
367 (OP_J): Drop marking of REX_W as used for v_mode (ISA-dependent)
368 and dqw_mode (unconditional).
369
8e58ef80
L		 3702020-07-14 H.J. Lu <hongjiu.lu@intel.com>
371
372 PR gas/26237
373 * i386-dis.c (OP_E_memory): Without base nor index registers,
374 32-bit displacement to 64 bits.
375
570b0ed6
CZ		 3762020-07-14 Claudiu Zissulescu <claziss@gmail.com>
377
378 * arc-dis.c (print_insn_arc): Detect and emit a warning when a
379 faulty double register pair is detected.
380
bfbd9438
JB		 3812020-07-14 Jan Beulich <jbeulich@suse.com>
382
383 * i386-dis.c (OP_D): Print dr<N> instead of db<N> in Intel mode.
384
78467458
JB		 3852020-07-14 Jan Beulich <jbeulich@suse.com>
386
387 * i386-dis.c (OP_R, Rm): Delete.
388 (MOD_0F24, MOD_0F26): Rename to ...
389 (X86_64_0F24, X86_64_0F26): ... respectively.
390 (dis386): Update 'L' and 'Z' comments.
391 (dis386_twobyte): Replace Rm by Em. Change opcode 0F24 and 0F26
392 table references.
393 (mod_table): Move opcode 0F24 and 0F26 entries ...
394 (x86_64_table): ... here.
395 (putop): Drop handling of 'L'. Set modrm.mod to 3 for 'Z'. Move
396 'Z' case block.
397
464d2b65
JB		 3982020-07-14 Jan Beulich <jbeulich@suse.com>
399
400 * i386-dis.c (Rd, Rdq, MaskR): Delete.
401 (MOD_EVEX_0F3828_P_1, MOD_EVEX_0F382A_P_1_W_1,
402 MOD_EVEX_0F3838_P_1, MOD_EVEX_0F383A_P_1_W_0,
403 MOD_EVEX_0F387A_W_0, MOD_EVEX_0F387B_W_0,
404 MOD_EVEX_0F387C): New enumerators.
405 (reg_table): Use Edq for rdssp.
406 (prefix_table): Use Edq for incssp.
407 (mod_table): Use Rm for move to/from %tr. Use MaskE for kand*,
408 kandn*, knot*, kor*, kxnor*, kxor*, kadd*, kunpck*, kortest*,
409 ktest*, and kshift*. Use Edq / MaskE for kmov*.
410 * i386-dis-evex.h: Reference mod_table[] for opcode 0F387C.
411 * i386-dis-evex-mod.h: New entries for opcodes 0F3828, 0F382A,
412 0F3838, 0F383A, 0F387A, 0F387B, and 0F387C.
413 * i386-dis-evex-prefix.h: Reference mod_table[] for opcodes
414 0F3828_P_1 and 0F3838_P_1.
415 * i386-dis-evex-w.h: Reference mod_table[] for opcodes
416 0F382A_P_1, 0F383A_P_1, 0F387A, and 0F387B.
417
035e7389
JB		 4182020-07-14 Jan Beulich <jbeulich@suse.com>
419
420 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_3,
421 PREFIX_0FAE_REG_5_MOD_0, PREFIX_0FC3_MOD_0, PREFIX_0F38C8,
422 PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC,
423 PREFIX_0F38CD, PREFIX_0F38F9, PREFIX_0F3ACC, PREFIX_VEX_0F77,
424 PREFIX_VEX_0F38F2, PREFIX_VEX_0F38F3_REG_1,
425 PREFIX_VEX_0F38F3_REG_2, PREFIX_VEX_0F38F3_REG_3): Delete.
426 (MOD_0F38F9_PREFIX_0, VEX_LEN_0F77_P_0, VEX_LEN_0F38F2_P_0,
427 VEX_LEN_0F38F3_R_1_P_0, VEX_LEN_0F38F3_R_2_P_0,
428 VEX_LEN_0F38F3_R_3_P_0): Rename to ...
429 (MOD_0F38F9, VEX_LEN_0F77, VEX_LEN_0F38F2, VEX_LEN_0F38F3_R_1,
430 VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3): ... these respectively.
431 (reg_table, prefix_table, three_byte_table, vex_table,
432 vex_len_table, mod_table, rm_table): Replace / remove respective
433 entries.
434 (intel_operand_size, OP_E_register, OP_G): Avoid undue setting
435 of PREFIX_DATA in used_prefixes.
436
bb5b3501
JB		 4372020-07-14 Jan Beulich <jbeulich@suse.com>
438
439 * i386-dis.c (MOD_VEX_0F3A30_L_0_W_0, MOD_VEX_0F3A30_L_0_W_1,
440 MOD_VEX_0F3A31_L_0_W_0, MOD_VEX_0F3A31_L_0_W_1,
441 MOD_VEX_0F3A32_L_0_W_0, MOD_VEX_0F3A32_L_0_W_1,
442 MOD_VEX_0F3A33_L_0_W_0, MOD_VEX_0F3A33_L_0_W_1): Replace by ...
443 (MOD_VEX_0F3A30_L_0, MOD_VEX_0F3A31_L_0,
444 MOD_VEX_0F3A32_L_0, MOD_VEX_0F3A33_L_0): ... these.
445 (VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
446 VEX_W_0F3A33_L_0): Delete.
447 (dis386): Adjust "BW" description.
448 (vex_len_table): Refer to mod_table[] for opcodes 0F3A30,
449 0F3A31, 0F3A32, and 0F3A33.
450 (vex_w_table): Delete opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
451 entries.
452 (mod_table): Replace opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
453 entries.
454
7531c613
JB		 4552020-07-14 Jan Beulich <jbeulich@suse.com>
456
457 * i386-dis.c (PREFIX_0F6C, PREFIX_0F6D, PREFIX_0F73_REG_3,
458 PREFIX_0F73_REG_7, PREFIX_0F3810, PREFIX_0F3814, PREFIX_0F3815,
459 PREFIX_0F3817, PREFIX_0F3820, PREFIX_0F3821, PREFIX_0F3822,
460 PREFIX_0F3823, PREFIX_0F3824, PREFIX_0F3825, PREFIX_0F3828,
461 PREFIX_0F3829, PREFIX_0F382A, PREFIX_0F382B, PREFIX_0F3830,
462 PREFIX_0F3831, PREFIX_0F3832, PREFIX_0F3833, PREFIX_0F3834,
463 PREFIX_0F3835, PREFIX_0F3837, PREFIX_0F3838, PREFIX_0F3839,
464 PREFIX_0F383A, PREFIX_0F383B, PREFIX_0F383C, PREFIX_0F383D,
465 PREFIX_0F383E, PREFIX_0F383F, PREFIX_0F3840, PREFIX_0F3841,
466 PREFIX_0F3880, PREFIX_0F3881, PREFIX_0F3882, PREFIX_0F38CF,
467 PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, PREFIX_0F38DE,
468 PREFIX_0F38DF, PREFIX_0F38F5, PREFIX_0F3A08, PREFIX_0F3A09,
469 PREFIX_0F3A0A, PREFIX_0F3A0B, PREFIX_0F3A0C, PREFIX_0F3A0D,
470 PREFIX_0F3A0E, PREFIX_0F3A14, PREFIX_0F3A15, PREFIX_0F3A16,
471 PREFIX_0F3A17, PREFIX_0F3A20, PREFIX_0F3A21, PREFIX_0F3A22,
472 PREFIX_0F3A40, PREFIX_0F3A41, PREFIX_0F3A42, PREFIX_0F3A44,
473 PREFIX_0F3A60, PREFIX_0F3A61, PREFIX_0F3A62, PREFIX_0F3A63,
474 PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F60,
475 PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63,
476 PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66,
477 PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69,
478 PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C,
479 PREFIX_VEX_0F6D, PREFIX_VEX_0F6E, PREFIX_VEX_0F71_REG_2,
480 PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6,
481 PREFIX_VEX_0F72_REG_2, PREFIX_VEX_0F72_REG_4,
482 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
483 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
484 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74,
485 PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0FC4,
486 PREFIX_VEX_0FC5, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
487 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
488 PREFIX_VEX_0FD6, PREFIX_VEX_0FD7, PREFIX_VEX_0FD8,
489 PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDB,
490 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
491 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
492 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
493 PREFIX_VEX_0FE5, PREFIX_VEX_0FE7, PREFIX_VEX_0FE8,
494 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
495 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
496 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1, PREFIX_VEX_0FF2,
497 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
498 PREFIX_VEX_0FF6, PREFIX_VEX_0FF7, PREFIX_VEX_0FF8,
499 PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB,
500 PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE,
501 PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802,
502 PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805,
503 PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808,
504 PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B,
505 PREFIX_VEX_0F380C, PREFIX_VEX_0F380D, PREFIX_VEX_0F380E,
506 PREFIX_VEX_0F380F, PREFIX_VEX_0F3813, PREFIX_VEX_0F3816,
507 PREFIX_VEX_0F3817, PREFIX_VEX_0F3818, PREFIX_VEX_0F3819,
508 PREFIX_VEX_0F381A, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D,
509 PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821,
510 PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824,
511 PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829,
512 PREFIX_VEX_0F382A, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C,
513 PREFIX_VEX_0F382D, PREFIX_VEX_0F382E, PREFIX_VEX_0F382F,
514 PREFIX_VEX_0F3830, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
515 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
516 PREFIX_VEX_0F3836, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838,
517 PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B,
518 PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E,
519 PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3841,
520 PREFIX_VEX_0F3845, PREFIX_VEX_0F3846, PREFIX_VEX_0F3847,
521 PREFIX_VEX_0F3858, PREFIX_VEX_0F3859, PREFIX_VEX_0F385A,
522 PREFIX_VEX_0F3878, PREFIX_VEX_0F3879, PREFIX_VEX_0F388C,
523 PREFIX_VEX_0F388E, PREFIX_VEX_0F3890, PREFIX_VEX_0F3891,
524 PREFIX_VEX_0F3892, PREFIX_VEX_0F3893, PREFIX_VEX_0F3896,
525 PREFIX_VEX_0F3897, PREFIX_VEX_0F3898, PREFIX_VEX_0F3899,
526 PREFIX_VEX_0F389A, PREFIX_VEX_0F389B, PREFIX_VEX_0F389C,
527 PREFIX_VEX_0F389D, PREFIX_VEX_0F389E, PREFIX_VEX_0F389F,
528 PREFIX_VEX_0F38A6, PREFIX_VEX_0F38A7, PREFIX_VEX_0F38A8,
529 PREFIX_VEX_0F38A9, PREFIX_VEX_0F38AA, PREFIX_VEX_0F38AB,
530 PREFIX_VEX_0F38AC, PREFIX_VEX_0F38AD, PREFIX_VEX_0F38AE,
531 PREFIX_VEX_0F38AF, PREFIX_VEX_0F38B6, PREFIX_VEX_0F38B7,
532 PREFIX_VEX_0F38B8, PREFIX_VEX_0F38B9, PREFIX_VEX_0F38BA,
533 PREFIX_VEX_0F38BB, PREFIX_VEX_0F38BC, PREFIX_VEX_0F38BD,
534 PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, PREFIX_VEX_0F38CF,
535 PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD,
536 PREFIX_VEX_0F38DE, PREFIX_VEX_0F38DF, PREFIX_VEX_0F3A00,
537 PREFIX_VEX_0F3A01, PREFIX_VEX_0F3A02, PREFIX_VEX_0F3A04,
538 PREFIX_VEX_0F3A05, PREFIX_VEX_0F3A06, PREFIX_VEX_0F3A08,
539 PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B,
540 PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E,
541 PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A14, PREFIX_VEX_0F3A15,
542 PREFIX_VEX_0F3A16, PREFIX_VEX_0F3A17, PREFIX_VEX_0F3A18,
543 PREFIX_VEX_0F3A19, PREFIX_VEX_0F3A1D, PREFIX_VEX_0F3A20,
544 PREFIX_VEX_0F3A21, PREFIX_VEX_0F3A22, PREFIX_VEX_0F3A30,
545 PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3A33,
546 PREFIX_VEX_0F3A38, PREFIX_VEX_0F3A39, PREFIX_VEX_0F3A40,
547 PREFIX_VEX_0F3A41, PREFIX_VEX_0F3A42, PREFIX_VEX_0F3A44,
548 PREFIX_VEX_0F3A46, PREFIX_VEX_0F3A48, PREFIX_VEX_0F3A49,
549 PREFIX_VEX_0F3A4A, PREFIX_VEX_0F3A4B, PREFIX_VEX_0F3A4C,
550 PREFIX_VEX_0F3A5C, PREFIX_VEX_0F3A5D, PREFIX_VEX_0F3A5E,
551 PREFIX_VEX_0F3A5F, PREFIX_VEX_0F3A60, PREFIX_VEX_0F3A61,
552 PREFIX_VEX_0F3A62, PREFIX_VEX_0F3A63, PREFIX_VEX_0F3A68,
553 PREFIX_VEX_0F3A69, PREFIX_VEX_0F3A6A, PREFIX_VEX_0F3A6B,
554 PREFIX_VEX_0F3A6C, PREFIX_VEX_0F3A6D, PREFIX_VEX_0F3A6E,
555 PREFIX_VEX_0F3A6F, PREFIX_VEX_0F3A78, PREFIX_VEX_0F3A79,
556 PREFIX_VEX_0F3A7A, PREFIX_VEX_0F3A7B, PREFIX_VEX_0F3A7C,
557 PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F,
558 PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF,
559 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F66,
560 PREFIX_EVEX_0F6E, PREFIX_EVEX_0F71_REG_2,
561 PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6,
562 PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
563 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
564 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
565 PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_6,
566 PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75,
567 PREFIX_EVEX_0F76, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
568 PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF,
569 PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB,
570 PREFIX_EVEX_0FEF, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3816,
571 PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B,
572 PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F382C,
573 PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
574 PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F,
575 PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843,
576 PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846,
577 PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D,
578 PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3850,
579 PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855,
580 PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B,
581 PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864,
582 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3870,
583 PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875,
584 PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387A,
585 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387D,
586 PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3883,
587 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
588 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F388F,
589 PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892,
590 PREFIX_EVEX_0F3893, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1,
591 PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38B4,
592 PREFIX_EVEX_0F38B5, PREFIX_EVEX_0F38C4,
593 PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2,
594 PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6,
595 PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2,
596 PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6,
597 PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB,
598 PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00,
599 PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A05,
600 PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A,
601 PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15,
602 PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18,
603 PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B,
604 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A20,
605 PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A23,
606 PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27,
607 PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A,
608 PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F,
609 PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A50,
610 PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55,
611 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
612 PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
613 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73): Delete.
614 (MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2,
615 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
616 MOD_VEX_0F381A_PREFIX_2, MOD_VEX_0F382A_PREFIX_2,
617 MOD_VEX_0F382C_PREFIX_2, MOD_VEX_0F382D_PREFIX_2,
618 MOD_VEX_0F382E_PREFIX_2, MOD_VEX_0F382F_PREFIX_2,
619 MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2,
620 MOD_VEX_0F388E_PREFIX_2, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
621 MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
622 MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
623 MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
624 MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F381A_P_2_W_0,
625 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
626 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
627 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0,
628 MOD_EVEX_0F385B_P_2_W_1, VEX_LEN_0F6E_P_2,
629 VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2,
630 VEX_LEN_0FF7_P_2, VEX_LEN_0F3816_P_2, VEX_LEN_0F3819_P_2,
631 VEX_LEN_0F381A_P_2_M_0, VEX_LEN_0F3836_P_2,
632 VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0,
633 VEX_LEN_0F38DB_P_2, VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2,
634 VEX_LEN_0F3A06_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2,
635 VEX_LEN_0F3A16_P_2, VEX_LEN_0F3A17_P_2, VEX_LEN_0F3A18_P_2,
636 VEX_LEN_0F3A19_P_2, VEX_LEN_0F3A20_P_2, VEX_LEN_0F3A21_P_2,
637 VEX_LEN_0F3A22_P_2, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A31_P_2,
638 VEX_LEN_0F3A32_P_2, VEX_LEN_0F3A33_P_2, VEX_LEN_0F3A38_P_2,
639 VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, VEX_LEN_0F3A46_P_2,
640 VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, VEX_LEN_0F3A62_P_2,
641 VEX_LEN_0F3A63_P_2, VEX_LEN_0F3ADF_P_2, EVEX_LEN_0F6E_P_2,
642 EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2, EVEX_LEN_0FD6_P_2,
643 EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3819_P_2_W_0,
644 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0_M_0,
645 EVEX_LEN_0F381A_P_2_W_1_M_0, EVEX_LEN_0F381B_P_2_W_0_M_0,
646 EVEX_LEN_0F381B_P_2_W_1_M_0, EVEX_LEN_0F3836_P_2,
647 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
648 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0,
649 EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2,
650 EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2,
651 EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1,
652 EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1,
653 EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1,
654 EVEX_LEN_0F38C7_R_6_P_2_W_0, EVEX_LEN_0F38C7_R_6_P_2_W_1,
655 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1,
656 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
657 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A18_P_2_W_0,
658 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
659 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
660 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
661 EVEX_LEN_0F3A1B_P_2_W_1, EVEX_LEN_0F3A20_P_2,
662 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2,
663 EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1,
664 EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1,
665 EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1,
666 EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1,
667 EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1,
668 EVEX_LEN_0F3A43_P_2_W_0, EVEX_LEN_0F3A43_P_2_W_1
669 VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2,
670 VEX_W_0F380F_P_2, VEX_W_0F3813_P_2, VEX_W_0F3816_P_2,
671 VEX_W_0F3818_P_2, VEX_W_0F3819_P_2,
672 VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F382C_P_2_M_0,
673 VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0,
674 VEX_W_0F382F_P_2_M_0, VEX_W_0F3836_P_2,
675 VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2,
676 VEX_W_0F385A_P_2_M_0_L_0, VEX_W_0F3878_P_2,
677 VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, VEX_W_0F3A00_P_2,
678 VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2,
679 VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2_L_0,
680 VEX_W_0F3A18_P_2_L_0, VEX_W_0F3A19_P_2_L_0,
681 VEX_W_0F3A1D_P_2, VEX_W_0F3A30_P_2_LEN_0,
682 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0,
683 VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2_L_0,
684 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0,
685 VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2,
686 VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F66_P_2,
687 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2,
688 EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2,
689 EVEX_W_0F76_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE7_P_2,
690 EVEX_W_0F380D_P_2, EVEX_W_0F3819_P_2,
691 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2,
692 EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
693 EVEX_W_0F3837_P_2, EVEX_W_0F3859_P_2,
694 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2,
695 EVEX_W_0F3870_P_2, EVEX_W_0F387A_P_2,
696 EVEX_W_0F387B_P_2, EVEX_W_0F3883_P_2,
697 EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2,
698 EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
699 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2,
700 EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2,
701 EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
702 EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
703 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2,
704 EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2,
705 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
706 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A21_P_2,
707 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2,
708 EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
709 EVEX_W_0F3A3B_P_2, EVEX_W_0F3A42_P_2,
710 EVEX_W_0F3A43_P_2, EVEX_W_0F3A70_P_2,
711 EVEX_W_0F3A72_P_2): Rename to ...
712 (MOD_0F382A, MOD_0F38F5, MOD_VEX_0FD7, MOD_VEX_0FE7,
713 MOD_VEX_0F381A, MOD_VEX_0F382A, MOD_VEX_0F382C, MOD_VEX_0F382D,
714 MOD_VEX_0F382E, MOD_VEX_0F382F, MOD_VEX_0F385A, MOD_VEX_0F388C,
715 MOD_VEX_0F388E, MOD_VEX_0F3A30_L_0_W_0,
716 MOD_VEX_0F3A30_L_0_W_1, MOD_VEX_0F3A31_L_0_W_0,
717 MOD_VEX_0F3A31_L_0_W_1, MOD_VEX_0F3A32_L_0_W_0,
718 MOD_VEX_0F3A32_L_0_W_1, MOD_VEX_0F3A33_L_0_W_0,
719 MOD_VEX_0F3A33_L_0_W_1, MOD_EVEX_0F381A_W_0,
720 MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, MOD_EVEX_0F381B_W_1,
721 MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, MOD_EVEX_0F385B_W_0,
722 MOD_EVEX_0F385B_W_1, VEX_LEN_0F6E, VEX_LEN_0FC4, VEX_LEN_0FC5,
723 VEX_LEN_0FD6, VEX_LEN_0FF7, VEX_LEN_0F3816, VEX_LEN_0F3819,
724 VEX_LEN_0F381A_M_0, VEX_LEN_0F3836, VEX_LEN_0F3841,
725 VEX_LEN_0F385A_M_0, VEX_LEN_0F38DB, VEX_LEN_0F3A00,
726 VEX_LEN_0F3A01, VEX_LEN_0F3A06, VEX_LEN_0F3A14, VEX_LEN_0F3A15,
727 VEX_LEN_0F3A16, VEX_LEN_0F3A17, VEX_LEN_0F3A18, VEX_LEN_0F3A19,
728 VEX_LEN_0F3A20, VEX_LEN_0F3A21, VEX_LEN_0F3A22, VEX_LEN_0F3A30,
729 VEX_LEN_0F3A31, VEX_LEN_0F3A32, VEX_LEN_0F3A33, VEX_LEN_0F3A38,
730 VEX_LEN_0F3A39, VEX_LEN_0F3A41, VEX_LEN_0F3A46, VEX_LEN_0F3A60,
731 VEX_LEN_0F3A61, VEX_LEN_0F3A62, VEX_LEN_0F3A63, VEX_LEN_0F3ADF,
732 EVEX_LEN_0F6E, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
733 EVEX_LEN_0F3816, EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
734 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
735 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
736 EVEX_LEN_0F3836, EVEX_LEN_0F385A_W_0_M_0,
737 EVEX_LEN_0F385A_W_1_M_0, EVEX_LEN_0F385B_W_0_M_0,
738 EVEX_LEN_0F385B_W_1_M_0, EVEX_LEN_0F38C6_R_1_M_0,
739 EVEX_LEN_0F38C6_R_2_M_0, EVEX_LEN_0F38C6_R_5_M_0,
740 EVEX_LEN_0F38C6_R_6_M_0, EVEX_LEN_0F38C7_R_1_M_0_W_0,
741 EVEX_LEN_0F38C7_R_1_M_0_W_1, EVEX_LEN_0F38C7_R_2_M_0_W_0,
742 EVEX_LEN_0F38C7_R_2_M_0_W_1, EVEX_LEN_0F38C7_R_5_M_0_W_0,
743 EVEX_LEN_0F38C7_R_5_M_0_W_1, EVEX_LEN_0F38C7_R_6_M_0_W_0,
744 EVEX_LEN_0F38C7_R_6_M_0_W_1, EVEX_LEN_0F3A00_W_1,
745 EVEX_LEN_0F3A01_W_1, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
746 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A18_W_0,
747 EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
748 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0,
749 EVEX_LEN_0F3A1A_W_1, EVEX_LEN_0F3A1B_W_0,
750 EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A20, EVEX_LEN_0F3A21_W_0,
751 EVEX_LEN_0F3A22, EVEX_LEN_0F3A23_W_0, EVEX_LEN_0F3A23_W_1,
752 EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
753 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1,
754 EVEX_LEN_0F3A3A_W_0, EVEX_LEN_0F3A3A_W_1,
755 EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
756 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1
757 VEX_W_0F380C, VEX_W_0F380D, VEX_W_0F380E, VEX_W_0F380F,
758 VEX_W_0F3813, VEX_W_0F3816_L_1, VEX_W_0F3818,
759 VEX_W_0F3819_L_1, VEX_W_0F381A_M_0_L_1, VEX_W_0F382C_M_0,
760 VEX_W_0F382D_M_0, VEX_W_0F382E_M_0, VEX_W_0F382F_M_0,
761 VEX_W_0F3836, VEX_W_0F3846, VEX_W_0F3858, VEX_W_0F3859,
762 VEX_W_0F385A_M_0_L_0, VEX_W_0F3878, VEX_W_0F3879,
763 VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1,
764 VEX_W_0F3A02, VEX_W_0F3A04, VEX_W_0F3A05, VEX_W_0F3A06_L_1,
765 VEX_W_0F3A18_L_1, VEX_W_0F3A19_L_1, VEX_W_0F3A1D,
766 VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
767 VEX_W_0F3A33_L_0, VEX_W_0F3A38_L_1, VEX_W_0F3A39_L_1,
768 VEX_W_0F3A46_L_1, VEX_W_0F3A4A, VEX_W_0F3A4B, VEX_W_0F3A4C,
769 VEX_W_0F3ACE, VEX_W_0F3ACF, EVEX_W_0F66, EVEX_W_0F72_R_2,
770 EVEX_W_0F72_R_6, EVEX_W_0F73_R_2, EVEX_W_0F73_R_6,
771 EVEX_W_0F76, EVEX_W_0FD6_L_0, EVEX_W_0FE7, EVEX_W_0F380D,
772 EVEX_W_0F3819, EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F381E,
773 EVEX_W_0F381F, EVEX_W_0F3837, EVEX_W_0F3859, EVEX_W_0F385A,
774 EVEX_W_0F385B, EVEX_W_0F3870, EVEX_W_0F387A, EVEX_W_0F387B,
775 EVEX_W_0F3883, EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1,
776 EVEX_W_0F38A3, EVEX_W_0F38C7_R_1_M_0,
777 EVEX_W_0F38C7_R_2_M_0, EVEX_W_0F38C7_R_5_M_0,
778 EVEX_W_0F38C7_R_6_M_0, EVEX_W_0F3A00, EVEX_W_0F3A01,
779 EVEX_W_0F3A05, EVEX_W_0F3A08, EVEX_W_0F3A09, EVEX_W_0F3A0A,
780 EVEX_W_0F3A0B, EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A,
781 EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
782 EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
783 EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
784 respectively.
785 (dis386_twobyte, three_byte_table, vex_table, vex_len_table,
786 vex_w_table, mod_table): Replace / remove respective entries.
787 (print_insn): Move up dp->prefix_requirement handling. Handle
788 PREFIX_DATA.
789 * i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-mod.h,
790 i386-dis-evex-prefix.h, i386-dis-evex-reg.h, i386-dis-evex-w.h:
791 Replace / remove respective entries.
792
17d3c7ec
JB		 7932020-07-14 Jan Beulich <jbeulich@suse.com>
794
795 * i386-dis.c (PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
796 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F): Delete.
797 (prefix_table): Add EXxEVexS operand to vcvttss2si, vcvttsd2si,
798 vcvtss2si, vcvtsd2si, vucomiss, and vucomisd table entries.
799 Retain X macro and PREFIX_OPCODE use from tjhe EVEX table for
800 the latter two.
801 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
802 0F2C, 0F2D, 0F2E, and 0F2F.
803 * i386-dis-evex-prefix.h: Delete opcode 0F2C, 0F2D, 0F2E, and
804 0F2F table entries.
805
41f5efc6
JB		 8062020-07-14 Jan Beulich <jbeulich@suse.com>
807
808 * i386-dis.c (OP_VexR, VexScalarR): New.
809 (OP_EX_Vex, OP_XMM_Vex, EXdVexScalarS, EXqVexScalarS,
810 XMVexScalar, d_scalar_swap_mode, q_scalar_swap_mode,
811 need_vex_reg): Delete.
812 (prefix_table): Replace VexScalar by VexScalarR and
813 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
814 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
815 (vex_len_table): Replace EXqVexScalarS by EXqS.
816 (get_valid_dis386): Don't set need_vex_reg.
817 (print_insn): Don't initialize need_vex_reg.
818 (intel_operand_size, OP_E_memory): Drop d_scalar_swap_mode and
819 q_scalar_swap_mode cases.
820 (OP_EX): Don't check for d_scalar_swap_mode and
821 q_scalar_swap_mode.
822 (OP_VEX): Done check need_vex_reg.
823 * i386-dis-evex-w.h: Replace VexScalar by VexScalarR and
824 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
825 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
826
89e65d17
JB		 8272020-07-14 Jan Beulich <jbeulich@suse.com>
828
829 * i386-dis.c (Vex128, Vex256, vex128_mode, vex256_mode): Delete.
830 (VEX_W_0F381A_P_2_M_0, VEX_W_0F385A_P_2_M_0, VEX_W_0F3A06_P_2,
831 VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, VEX_W_0F3A38_P_2,
832 VEX_W_0F3A39_P_2, VEX_W_0F3A46_P_2): Rename to ...
833 (VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F385A_P_2_M_0_L_0,
834 VEX_W_0F3A06_P_2_L_0, VEX_W_0F3A18_P_2_L_0,
835 VEX_W_0F3A19_P_2_L_0, VEX_W_0F3A38_P_2_L_0,
836 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0): ... respectively.
837 (vex_table): Replace Vex128 by Vex.
838 (vex_len_table): Likewise. Adjust referenced enum names.
839 (vex_w_table): Replace Vex128 and Vex256 by Vex. Adjust
840 referenced enum names.
841 (OP_VEX): Drop vex128_mode and vex256_mode cases.
842 * i386-dis-evex-len.h (evex_len_table): Replace Vex128 by Vex.
843
492a76aa
JB		 8442020-07-14 Jan Beulich <jbeulich@suse.com>
845
846 * i386-dis.c (dis386): "LW" description now applies to "DQ".
847 (putop): Handle "DQ". Don't handle "LW" anymore.
848 (prefix_table, mod_table): Replace %LW by %DQ.
849 * i386-dis-evex-len.h, i386-dis-evex-prefix.h: Likewise.
850
059edf8b
JB		 8512020-07-14 Jan Beulich <jbeulich@suse.com>
852
853 * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
854 dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
855 d_scalar_swap_mode case handling. Move shift adjsutment into
856 the case its applicable to.
857
4726e9a4
JB		 8582020-07-14 Jan Beulich <jbeulich@suse.com>
859
860 * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
861 (EXbScalar, EXwScalar): Fold to ...
862 (EXbwUnit): ... this.
863 (b_scalar_mode, w_scalar_mode): Fold to ...
864 (bw_unit_mode): ... this.
865 (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
866 w_scalar_mode handling by bw_unit_mode one.
867 * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
868 ...
869 * i386-dis-evex-prefix.h: ... here.
870
b24d668c
JB		 8712020-07-14 Jan Beulich <jbeulich@suse.com>
872
873 * i386-dis.c (PCMPESTR_Fixup): Delete.
874 (dis386): Adjust "LQ" description.
875 (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
876 cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
877 PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
878 vpcmpestrm, and vpcmpestri.
879 (putop): Honor "cond" when handling LQ.
880 * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
881 vcvtsi2ss and vcvtusi2ss.
882 * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
883 vcvtsi2sd and vcvtusi2sd.
884
c4de7606
JB		 8852020-07-14 Jan Beulich <jbeulich@suse.com>
886
887 * i386-dis.c (VCMP_Fixup, VCMP): Delete.
888 (simd_cmp_op): Add const.
889 (vex_cmp_op): Move up and drop initial 8 entries. Add const.
890 (CMP_Fixup): Handle VEX case.
891 (prefix_table): Replace VCMP by CMP.
892 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
893
9ab00b61
JB		 8942020-07-14 Jan Beulich <jbeulich@suse.com>
895
896 * i386-dis.c (MOVBE_Fixup): Delete.
897 (Mv): Define.
898 (prefix_table): Use Mv for movbe entries.
899
2875b28a
JB		 9002020-07-14 Jan Beulich <jbeulich@suse.com>
901
902 * i386-dis.c (CRC32_Fixup): Delete.
903 (prefix_table): Use Eb/Ev for crc32 entries.
904
e184e611
JB		 9052020-07-14 Jan Beulich <jbeulich@suse.com>
906
907 * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
908 Conditionalize invocations of "USED_REX (0)".
909
e8b5d5f9
JB		 9102020-07-14 Jan Beulich <jbeulich@suse.com>
911
912 * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
913 CH, DH, BH, AX, DX): Delete.
914 (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
915 eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
916 dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
917
260cd341
LC		 9182020-07-10 Lili Cui <lili.cui@intel.com>
919
920 * i386-dis.c (TMM): New.
921 (EXtmm): Likewise.
922 (VexTmm): Likewise.
923 (MVexSIBMEM): Likewise.
924 (tmm_mode): Likewise.
925 (vex_sibmem_mode): Likewise.
926 (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
927 (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
928 (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
929 (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
930 (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
931 (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
932 (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
933 (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
934 (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
935 (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
936 (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
937 (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
938 (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
939 (PREFIX_VEX_0F3849_X86_64): Likewise.
940 (PREFIX_VEX_0F384B_X86_64): Likewise.
941 (PREFIX_VEX_0F385C_X86_64): Likewise.
942 (PREFIX_VEX_0F385E_X86_64): Likewise.
943 (X86_64_VEX_0F3849): Likewise.
944 (X86_64_VEX_0F384B): Likewise.
945 (X86_64_VEX_0F385C): Likewise.
946 (X86_64_VEX_0F385E): Likewise.
947 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
948 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
949 (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
950 (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
951 (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
952 (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
953 (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
954 (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
955 (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
956 (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
957 (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
958 (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
959 (VEX_W_0F3849_X86_64_P_0): Likewise.
960 (VEX_W_0F3849_X86_64_P_2): Likewise.
961 (VEX_W_0F3849_X86_64_P_3): Likewise.
962 (VEX_W_0F384B_X86_64_P_1): Likewise.
963 (VEX_W_0F384B_X86_64_P_2): Likewise.
964 (VEX_W_0F384B_X86_64_P_3): Likewise.
965 (VEX_W_0F385C_X86_64_P_1): Likewise.
966 (VEX_W_0F385E_X86_64_P_0): Likewise.
967 (VEX_W_0F385E_X86_64_P_1): Likewise.
968 (VEX_W_0F385E_X86_64_P_2): Likewise.
969 (VEX_W_0F385E_X86_64_P_3): Likewise.
970 (names_tmm): Likewise.
971 (att_names_tmm): Likewise.
972 (intel_operand_size): Handle void_mode.
973 (OP_XMM): Handle tmm_mode.
974 (OP_EX): Likewise.
975 (OP_VEX): Likewise.
976 * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
977 CpuAMX_BF16 and CpuAMX_TILE.
978 (operand_type_shorthands): Add RegTMM.
979 (operand_type_init): Likewise.
980 (operand_types): Add Tmmword.
981 (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
982 (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
983 * i386-opc.h (CpuAMX_INT8): New.
984 (CpuAMX_BF16): Likewise.
985 (CpuAMX_TILE): Likewise.
986 (SIBMEM): Likewise.
987 (Tmmword): Likewise.
988 (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
989 (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
990 (i386_operand_type): Add tmmword.
991 * i386-opc.tbl: Add AMX instructions.
992 * i386-reg.tbl: Add AMX registers.
993 * i386-init.h: Regenerated.
994 * i386-tbl.h: Likewise.
995
467bbef0
JB		 9962020-07-08 Jan Beulich <jbeulich@suse.com>
997
998 * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
999 (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
1000 Rename to ...
1001 (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
1002 REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
1003 respectively.
1004 (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
1005 VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
1006 VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
1007 VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
1008 VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
1009 VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
1010 VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
1011 VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
1012 VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
1013 VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
1014 VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
1015 VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
1016 VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
1017 VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
1018 VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
1019 VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
1020 VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
1021 VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
1022 VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
1023 VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
1024 VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
1025 VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
1026 VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
1027 VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
1028 VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
1029 VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
1030 VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
1031 VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
1032 VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
1033 VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
1034 VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
1035 VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
1036 VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
1037 VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
1038 VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
1039 VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
1040 (reg_table): Re-order XOP entries. Adjust their operands.
1041 (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
1042 08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
1043 08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
1044 09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
1045 09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
1046 09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
1047 entries by references ...
1048 (vex_len_table): ... to resepctive new entries here. For several
1049 new and existing entries reference ...
1050 (vex_w_table): ... new entries here.
1051 (mod_table): New MOD_VEX_0FXOP_09_12 entry.
1052
6384fd9e
JB		 10532020-07-08 Jan Beulich <jbeulich@suse.com>
1054
1055 * i386-dis.c (XMVexScalarI4): Define.
1056 (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
1057 VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
1058 VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
1059 (vex_len_table): Move scalar FMA4 entries ...
1060 (prefix_table): ... here.
1061 (OP_REG_VexI4): Handle scalar_mode.
1062 * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
1063 * i386-tbl.h: Re-generate.
1064
e6123d0c
JB		 10652020-07-08 Jan Beulich <jbeulich@suse.com>
1066
1067 * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
1068 Vex_2src_2): Delete.
1069 (OP_VexW, VexW): New.
1070 (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
1071 for shifts and rotates by register.
1072
93abb146
JB		 10732020-07-08 Jan Beulich <jbeulich@suse.com>
1074
1075 * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
1076 VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
1077 OP_EX_VexReg): Delete.
1078 (OP_VexI4, VexI4): New.
1079 (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
1080 (prefix_table): ... here.
1081 (print_insn): Drop setting of vex_w_done.
1082
b13b1bc0
JB		 10832020-07-08 Jan Beulich <jbeulich@suse.com>
1084
1085 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
1086 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
1087 (xop_table): Replace operands of 4-operand insns.
1088 (OP_REG_VexI4): Move VEX.W based operand swaping here.
1089
f337259f
CZ		 10902020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
1091
1092 * arc-opc.c (insert_rbd): New function.
1093 (RBD): Define.
1094 (RBDdup): Likewise.
1095 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
1096 instructions.
1097
931452b6
JB		 10982020-07-07 Jan Beulich <jbeulich@suse.com>
1099
1100 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
1101 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
1102 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
1103 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
1104 Delete.
1105 (putop): Handle "BW".
1106 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
1107 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
1108 and 0F3A3F ...
1109 * i386-dis-evex-prefix.h: ... here.
1110
b5b098c2
JB		 11112020-07-06 Jan Beulich <jbeulich@suse.com>
1112
1113 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
1114 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
1115 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
1116 VEX_W_0FXOP_09_83): New enumerators.
1117 (xop_table): Reference the above.
1118 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
1119 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
1120 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
1121 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
1122
21a3faeb
JB		 11232020-07-06 Jan Beulich <jbeulich@suse.com>
1124
1125 * i386-dis.c (EVEX_W_0F3838_P_1,
1126 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
1127 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
1128 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
1129 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
1130 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
1131 (putop): Centralize management of last[]. Delete SAVE_LAST.
1132 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
1133 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
1134 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
1135 * i386-dis-evex-prefix.h: here.
1136
bc152a17
JB		 11372020-07-06 Jan Beulich <jbeulich@suse.com>
1138
1139 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
1140 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
1141 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
1142 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
1143 enumerators.
1144 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
1145 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
1146 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
1147 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
1148 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
1149 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
1150 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
1151 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
1152 these, respectively.
1153 * i386-dis-evex-len.h: Adjust comments.
1154 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
1155 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
1156 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
1157 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
1158 MOD_EVEX_0F385B_P_2_W_1 table entries.
1159 * i386-dis-evex-w.h: Reference mod_table[] for
1160 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
1161 EVEX_W_0F385B_P_2.
1162
c82a99a0
JB		 11632020-07-06 Jan Beulich <jbeulich@suse.com>
1164
1165 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
1166 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
1167 EXymm.
1168 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
1169 Likewise. Mark 256-bit entries invalid.
1170
fedfb81e
JB		 11712020-07-06 Jan Beulich <jbeulich@suse.com>
1172
1173 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1174 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1175 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1176 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1177 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1178 PREFIX_EVEX_0F382B): Delete.
1179 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
1180 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
1181 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
1182 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
1183 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
1184 to ...
1185 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
1186 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
1187 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
1188 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
1189 respectively.
1190 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
1191 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
1192 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1193 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1194 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1195 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1196 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1197 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1198 PREFIX_EVEX_0F382B): Remove table entries.
1199 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
1200 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
1201 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1202
3a57774c
JB		 12032020-07-06 Jan Beulich <jbeulich@suse.com>
1204
1205 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
1206 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
1207 enumerators.
1208 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
1209 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
1210 EVEX_LEN_0F3A01_P_2_W_1 table entries.
1211 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1212 entries.
1213
e74d9fa9
JB		 12142020-07-06 Jan Beulich <jbeulich@suse.com>
1215
1216 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
1217 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
1218 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1219 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
1220 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
1221 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
1222 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1223 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
1224 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1225 entries.
1226
6431c801
JB		 12272020-07-06 Jan Beulich <jbeulich@suse.com>
1228
1229 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
1230 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
1231 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
1232 respectively.
1233 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
1234 entries.
1235 * i386-dis-evex.h (evex_table): Reference VEX table entry for
1236 opcode 0F3A1D.
1237 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
1238 entry.
1239 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
1240
6df22cf6
JB		 12412020-07-06 Jan Beulich <jbeulich@suse.com>
1242
1243 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1244 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1245 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1246 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1247 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1248 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1249 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1250 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1251 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1252 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1253 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1254 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1255 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1256 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1257 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1258 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1259 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1260 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1261 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1262 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1263 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1264 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1265 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1266 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1267 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1268 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1269 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
1270 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
1271 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
1272 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
1273 (prefix_table): Add EXxEVexR to FMA table entries.
1274 (OP_Rounding): Move abort() invocation.
1275 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1276 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
1277 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
1278 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
1279 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
1280 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
1281 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
1282 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
1283 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
1284 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
1285 0F3ACE, 0F3ACF.
1286 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1287 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1288 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1289 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1290 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1291 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1292 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1293 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1294 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1295 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1296 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1297 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1298 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1299 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1300 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1301 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1302 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1303 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1304 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1305 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1306 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1307 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1308 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1309 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1310 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1311 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1312 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
1313 Delete table entries.
1314 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
1315 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
1316 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
1317 Likewise.
1318
39e0f456
JB		 13192020-07-06 Jan Beulich <jbeulich@suse.com>
1320
1321 * i386-dis.c (EXqScalarS): Delete.
1322 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
1323 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
1324
5b872f7d
JB		 13252020-07-06 Jan Beulich <jbeulich@suse.com>
1326
1327 * i386-dis.c (safe-ctype.h): Include.
1328 (EXdScalar, EXqScalar): Delete.
1329 (d_scalar_mode, q_scalar_mode): Delete.
1330 (prefix_table, vex_len_table): Use EXxmm_md in place of
1331 EXdScalar and EXxmm_mq in place of EXqScalar.
1332 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
1333 d_scalar_mode and q_scalar_mode.
1334 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
1335 (vmovsd): Use EXxmm_mq.
1336
ddc73fa9
NC		 13372020-07-06 Yuri Chornoivan <yurchor@ukr.net>
1338
1339 PR 26204
1340 * arc-dis.c: Fix spelling mistake.
1341 * po/opcodes.pot: Regenerate.
1342
17550be7
NC		 13432020-07-06 Nick Clifton <nickc@redhat.com>
1344
1345 * po/pt_BR.po: Updated Brazilian Portugugese translation.
1346 * po/uk.po: Updated Ukranian translation.
1347
b19d852d
NC		 13482020-07-04 Nick Clifton <nickc@redhat.com>
1349
1350 * configure: Regenerate.
1351 * po/opcodes.pot: Regenerate.
1352
b115b9fd
NC		 13532020-07-04 Nick Clifton <nickc@redhat.com>
1354
1355 Binutils 2.35 branch created.
1356
c2ecccb3
L		 13572020-07-02 H.J. Lu <hongjiu.lu@intel.com>
1358
1359 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
1360 * i386-opc.h (VexSwapSources): New.
1361 (i386_opcode_modifier): Add vexswapsources.
1362 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
1363 with two source operands swapped.
1364 * i386-tbl.h: Regenerated.
1365
08ccfccf
NC		 13662020-06-30 Nelson Chu <nelson.chu@sifive.com>
1367
1368 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
1369 unprivileged CSR can also be initialized.
1370
279edac5
AM		 13712020-06-29 Alan Modra <amodra@gmail.com>
1372
1373 * arm-dis.c: Use C style comments.
1374 * cr16-opc.c: Likewise.
1375 * ft32-dis.c: Likewise.
1376 * moxie-opc.c: Likewise.
1377 * tic54x-dis.c: Likewise.
1378 * s12z-opc.c: Remove useless comment.
1379 * xgate-dis.c: Likewise.
1380
e978ad62
L		 13812020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1382
1383 * i386-opc.tbl: Add a blank line.
1384
63112cd6
L		 13852020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1386
1387 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
1388 (VecSIB128): Renamed to ...
1389 (VECSIB128): This.
1390 (VecSIB256): Renamed to ...
1391 (VECSIB256): This.
1392 (VecSIB512): Renamed to ...
1393 (VECSIB512): This.
1394 (VecSIB): Renamed to ...
1395 (SIB): This.
1396 (i386_opcode_modifier): Replace vecsib with sib.
79b32e73 1397 * i386-opc.tbl (VecSIB128): New.
63112cd6
L		 1398 (VecSIB256): Likewise.
1399 (VecSIB512): Likewise.
79b32e73 1400 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
63112cd6
L		 1401 and VecSIB512, respectively.
1402
d1c36125
JB		 14032020-06-26 Jan Beulich <jbeulich@suse.com>
1404
1405 * i386-dis.c: Adjust description of I macro.
1406 (x86_64_table): Drop use of I.
1407 (float_mem): Replace use of I.
1408 (putop): Remove handling of I. Adjust setting/clearing of "alt".
1409
2a1bb84c
JB		 14102020-06-26 Jan Beulich <jbeulich@suse.com>
1411
1412 * i386-dis.c: (print_insn): Avoid straight assignment to
1413 priv.orig_sizeflag when processing -M sub-options.
1414
8f570d62
JB		 14152020-06-25 Jan Beulich <jbeulich@suse.com>
1416
1417 * i386-dis.c: Adjust description of J macro.
1418 (dis386, x86_64_table, mod_table): Replace J.
1419 (putop): Remove handling of J.
1420
464dc4af
JB		 14212020-06-25 Jan Beulich <jbeulich@suse.com>
1422
1423 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
1424
589958d6
JB		 14252020-06-25 Jan Beulich <jbeulich@suse.com>
1426
1427 * i386-dis.c: Adjust description of "LQ" macro.
1428 (dis386_twobyte): Use LQ for sysret.
1429 (putop): Adjust handling of LQ.
1430
39ff0b81
NC		 14312020-06-22 Nelson Chu <nelson.chu@sifive.com>
1432
1433 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
1434 * riscv-dis.c: Include elfxx-riscv.h.
1435
d27c357a
JB		 14362020-06-18 H.J. Lu <hongjiu.lu@intel.com>
1437
1438 * i386-dis.c (prefix_table): Revert the last vmgexit change.
1439
6fde587f
CL		 14402020-06-17 Lili Cui <lili.cui@intel.com>
1441
1442 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
1443
efe30057
L		 14442020-06-14 H.J. Lu <hongjiu.lu@intel.com>
1445
1446 PR gas/26115
1447 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
1448 * i386-opc.tbl: Likewise.
1449 * i386-tbl.h: Regenerated.
1450
d8af286f
NC		 14512020-06-12 Nelson Chu <nelson.chu@sifive.com>
1452
1453 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
1454
14962256
AC		 14552020-06-11 Alex Coplan <alex.coplan@arm.com>
1456
1457 * aarch64-opc.c (SYSREG): New macro for describing system registers.
1458 (SR_CORE): Likewise.
1459 (SR_FEAT): Likewise.
1460 (SR_RNG): Likewise.
1461 (SR_V8_1): Likewise.
1462 (SR_V8_2): Likewise.
1463 (SR_V8_3): Likewise.
1464 (SR_V8_4): Likewise.
1465 (SR_PAN): Likewise.
1466 (SR_RAS): Likewise.
1467 (SR_SSBS): Likewise.
1468 (SR_SVE): Likewise.
1469 (SR_ID_PFR2): Likewise.
1470 (SR_PROFILE): Likewise.
1471 (SR_MEMTAG): Likewise.
1472 (SR_SCXTNUM): Likewise.
1473 (aarch64_sys_regs): Refactor to store feature information in the table.
1474 (aarch64_sys_reg_supported_p): Collapse logic for system registers
1475 that now describe their own features.
1476 (aarch64_pstatefield_supported_p): Likewise.
1477
f9630fa6
L		 14782020-06-09 H.J. Lu <hongjiu.lu@intel.com>
1479
1480 * i386-dis.c (prefix_table): Fix a typo in comments.
1481
73239888
JB		 14822020-06-09 Jan Beulich <jbeulich@suse.com>
1483
1484 * i386-dis.c (rex_ignored): Delete.
1485 (ckprefix): Drop rex_ignored initialization.
1486 (get_valid_dis386): Drop setting of rex_ignored.
1487 (print_insn): Drop checking of rex_ignored. Don't record data
1488 size prefix as used with VEX-and-alike encodings.
1489
18897deb
JB		 14902020-06-09 Jan Beulich <jbeulich@suse.com>
1491
1492 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
1493 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
1494 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
1495 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
1496 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
1497 VEX_0F12, and VEX_0F16.
1498 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
1499 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
1500 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
1501 from movlps and movhlps. New MOD_0F12_PREFIX_2,
1502 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
1503 MOD_VEX_0F16_PREFIX_2 entries.
1504
97e6786a
JB		 15052020-06-09 Jan Beulich <jbeulich@suse.com>
1506
1507 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
1508 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
1509 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1510 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
1511 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
1512 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
1513 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
1514 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
1515 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
1516 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
1517 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
1518 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
1519 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
1520 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
1521 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
1522 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
1523 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
1524 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
1525 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
1526 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
1527 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
1528 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
1529 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
1530 EVEX_W_0FC6_P_2): Delete.
1531 (print_insn): Add EVEX.W vs embedded prefix consistency check
1532 to prefix validation.
1533 * i386-dis-evex.h (evex_table): Don't further descend for
1534 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
1535 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
1536 and 0F2B.
1537 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
1538 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
1539 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
1540 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
1541 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
1542 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1543 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
1544 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
1545 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
1546 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
1547 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
1548 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
1549 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
1550 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
1551 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
1552 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
1553 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
1554 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
1555 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
1556 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
1557 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
1558 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
1559 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
1560 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
1561 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
1562 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
1563 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
1564
bf926894
JB		 15652020-06-09 Jan Beulich <jbeulich@suse.com>
1566
1567 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
1568 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
1569 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
1570 vmovmskpX.
1571 (print_insn): Drop pointless check against bad_opcode. Split
1572 prefix validation into legacy and VEX-and-alike parts.
1573 (putop): Re-work 'X' macro handling.
1574
a5aaedb9
JB		 15752020-06-09 Jan Beulich <jbeulich@suse.com>
1576
1577 * i386-dis.c (MOD_0F51): Rename to ...
1578 (MOD_0F50): ... this.
1579
26417f19
AC		 15802020-06-08 Alex Coplan <alex.coplan@arm.com>
1581
1582 * arm-dis.c (arm_opcodes): Add dfb.
1583 (thumb32_opcodes): Add dfb.
1584
8a6fb3f9
JB		 15852020-06-08 Jan Beulich <jbeulich@suse.com>
1586
1587 * i386-opc.h (reg_entry): Const-qualify reg_name field.
1588
1424c35d
AM		 15892020-06-06 Alan Modra <amodra@gmail.com>
1590
1591 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
1592
d3d1cc7b
AM		 15932020-06-05 Alan Modra <amodra@gmail.com>
1594
1595 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
1596 size is large enough.
1597
d8740be1
JM		 15982020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
1599
1600 * disassemble.c (disassemble_init_for_target): Set endian_code for
1601 bpf targets.
1602 * bpf-desc.c: Regenerate.
1603 * bpf-opc.c: Likewise.
1604 * bpf-dis.c: Likewise.
1605
e9bffec9
JM		 16062020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
1607
1608 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
1609 (cgen_put_insn_value): Likewise.
1610 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
1611 * cgen-dis.in (print_insn): Likewise.
1612 * cgen-ibld.in (insert_1): Likewise.
1613 (insert_1): Likewise.
1614 (insert_insn_normal): Likewise.
1615 (extract_1): Likewise.
1616 * bpf-dis.c: Regenerate.
1617 * bpf-ibld.c: Likewise.
1618 * bpf-ibld.c: Likewise.
1619 * cgen-dis.in: Likewise.
1620 * cgen-ibld.in: Likewise.
1621 * cgen-opc.c: Likewise.
1622 * epiphany-dis.c: Likewise.
1623 * epiphany-ibld.c: Likewise.
1624 * fr30-dis.c: Likewise.
1625 * fr30-ibld.c: Likewise.
1626 * frv-dis.c: Likewise.
1627 * frv-ibld.c: Likewise.
1628 * ip2k-dis.c: Likewise.
1629 * ip2k-ibld.c: Likewise.
1630 * iq2000-dis.c: Likewise.
1631 * iq2000-ibld.c: Likewise.
1632 * lm32-dis.c: Likewise.
1633 * lm32-ibld.c: Likewise.
1634 * m32c-dis.c: Likewise.
1635 * m32c-ibld.c: Likewise.
1636 * m32r-dis.c: Likewise.
1637 * m32r-ibld.c: Likewise.
1638 * mep-dis.c: Likewise.
1639 * mep-ibld.c: Likewise.
1640 * mt-dis.c: Likewise.
1641 * mt-ibld.c: Likewise.
1642 * or1k-dis.c: Likewise.
1643 * or1k-ibld.c: Likewise.
1644 * xc16x-dis.c: Likewise.
1645 * xc16x-ibld.c: Likewise.
1646 * xstormy16-dis.c: Likewise.
1647 * xstormy16-ibld.c: Likewise.
1648
b3db6d07
JM		 16492020-06-04 Jose E. Marchesi <jemarch@gnu.org>
1650
1651 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
1652 (print_insn_): Handle instruction endian.
1653 * bpf-dis.c: Regenerate.
1654 * bpf-desc.c: Regenerate.
1655 * epiphany-dis.c: Likewise.
1656 * epiphany-desc.c: Likewise.
1657 * fr30-dis.c: Likewise.
1658 * fr30-desc.c: Likewise.
1659 * frv-dis.c: Likewise.
1660 * frv-desc.c: Likewise.
1661 * ip2k-dis.c: Likewise.
1662 * ip2k-desc.c: Likewise.
1663 * iq2000-dis.c: Likewise.
1664 * iq2000-desc.c: Likewise.
1665 * lm32-dis.c: Likewise.
1666 * lm32-desc.c: Likewise.
1667 * m32c-dis.c: Likewise.
1668 * m32c-desc.c: Likewise.
1669 * m32r-dis.c: Likewise.
1670 * m32r-desc.c: Likewise.
1671 * mep-dis.c: Likewise.
1672 * mep-desc.c: Likewise.
1673 * mt-dis.c: Likewise.
1674 * mt-desc.c: Likewise.
1675 * or1k-dis.c: Likewise.
1676 * or1k-desc.c: Likewise.
1677 * xc16x-dis.c: Likewise.
1678 * xc16x-desc.c: Likewise.
1679 * xstormy16-dis.c: Likewise.
1680 * xstormy16-desc.c: Likewise.
1681
4ee4189f
NC		 16822020-06-03 Nick Clifton <nickc@redhat.com>
1683
1684 * po/sr.po: Updated Serbian translation.
1685
44730156
NC		 16862020-06-03 Nelson Chu <nelson.chu@sifive.com>
1687
1688 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
1689 (riscv_get_priv_spec_class): Likewise.
1690
3c3d0376
AM		 16912020-06-01 Alan Modra <amodra@gmail.com>
1692
1693 * bpf-desc.c: Regenerate.
1694
78c1c354
JM		 16952020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
1696 David Faust <david.faust@oracle.com>
1697
1698 * bpf-desc.c: Regenerate.
1699 * bpf-opc.h: Likewise.
1700 * bpf-opc.c: Likewise.
1701 * bpf-dis.c: Likewise.
1702
efcf5fb5
AM		 17032020-05-28 Alan Modra <amodra@gmail.com>
1704
1705 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
1706 values.
1707
ab382d64
AM		 17082020-05-28 Alan Modra <amodra@gmail.com>
1709
1710 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
1711 immediates.
1712 (print_insn_ns32k): Revert last change.
1713
151f5de4
NC		 17142020-05-28 Nick Clifton <nickc@redhat.com>
1715
1716 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
1717 static.
1718
25e1eca8
SL		 17192020-05-26 Sandra Loosemore <sandra@codesourcery.com>
1720
1721 Fix extraction of signed constants in nios2 disassembler (again).
1722
1723 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
1724 extractions of signed fields.
1725
57b17940
SSF		 17262020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
1727
1728 * s390-opc.txt: Relocate vector load/store instructions with
1729 additional alignment parameter and change architecture level
1730 constraint from z14 to z13.
1731
d96bf37b
AM		 17322020-05-21 Alan Modra <amodra@gmail.com>
1733
1734 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
1735 * sparc-dis.c: Likewise.
1736 * tic4x-dis.c: Likewise.
1737 * xtensa-dis.c: Likewise.
1738 * bpf-desc.c: Regenerate.
1739 * epiphany-desc.c: Regenerate.
1740 * fr30-desc.c: Regenerate.
1741 * frv-desc.c: Regenerate.
1742 * ip2k-desc.c: Regenerate.
1743 * iq2000-desc.c: Regenerate.
1744 * lm32-desc.c: Regenerate.
1745 * m32c-desc.c: Regenerate.
1746 * m32r-desc.c: Regenerate.
1747 * mep-asm.c: Regenerate.
1748 * mep-desc.c: Regenerate.
1749 * mt-desc.c: Regenerate.
1750 * or1k-desc.c: Regenerate.
1751 * xc16x-desc.c: Regenerate.
1752 * xstormy16-desc.c: Regenerate.
1753
8f595e9b
NC		 17542020-05-20 Nelson Chu <nelson.chu@sifive.com>
1755
1756 * riscv-opc.c (riscv_ext_version_table): The table used to store
1757 all information about the supported spec and the corresponding ISA
1758 versions. Currently, only Zicsr is supported to verify the
1759 correctness of Z sub extension settings. Others will be supported
1760 in the future patches.
1761 (struct isa_spec_t, isa_specs): List for all supported ISA spec
1762 classes and the corresponding strings.
1763 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
1764 spec class by giving a ISA spec string.
1765 * riscv-opc.c (struct priv_spec_t): New structure.
1766 (struct priv_spec_t priv_specs): List for all supported privilege spec
1767 classes and the corresponding strings.
1768 (riscv_get_priv_spec_class): New function. Get the corresponding
1769 privilege spec class by giving a spec string.
1770 (riscv_get_priv_spec_name): New function. Get the corresponding
1771 privilege spec string by giving a CSR version class.
1772 * riscv-dis.c: Updated since DECLARE_CSR is changed.
1773 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
1774 according to the chosen version. Build a hash table riscv_csr_hash to
1775 store the valid CSR for the chosen pirv verison. Dump the direct
1776 CSR address rather than it's name if it is invalid.
1777 (parse_riscv_dis_option_without_args): New function. Parse the options
1778 without arguments.
1779 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
1780 parse the options without arguments first, and then handle the options
1781 with arguments. Add the new option -Mpriv-spec, which has argument.
1782 * riscv-dis.c (print_riscv_disassembler_options): Add description
1783 about the new OBJDUMP option.
1784
3d205eb4
PB		 17852020-05-19 Peter Bergner <bergner@linux.ibm.com>
1786
1787 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
1788 WC values on POWER10 sync, dcbf and wait instructions.
1789 (insert_pl, extract_pl): New functions.
1790 (L2OPT, LS, WC): Use insert_ls and extract_ls.
1791 (LS3): New , 3-bit L for sync.
1792 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
1793 (SC2, PL): New, 2-bit SC and PL for sync and wait.
1794 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
1795 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
1796 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
1797 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
1798 <wait>: Enable PL operand on POWER10.
1799 <dcbf>: Enable L3OPT operand on POWER10.
1800 <sync>: Enable SC2 operand on POWER10.
1801
a501eb44
SH		 18022020-05-19 Stafford Horne <shorne@gmail.com>
1803
1804 PR 25184
1805 * or1k-asm.c: Regenerate.
1806 * or1k-desc.c: Regenerate.
1807 * or1k-desc.h: Regenerate.
1808 * or1k-dis.c: Regenerate.
1809 * or1k-ibld.c: Regenerate.
1810 * or1k-opc.c: Regenerate.
1811 * or1k-opc.h: Regenerate.
1812 * or1k-opinst.c: Regenerate.
1813
3b646889
AM		 18142020-05-11 Alan Modra <amodra@gmail.com>
1815
1816 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
1817 xsmaxcqp, xsmincqp.
1818
9cc4ce88
AM		 18192020-05-11 Alan Modra <amodra@gmail.com>
1820
1821 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
1822 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
1823
5d57bc3f
AM		 18242020-05-11 Alan Modra <amodra@gmail.com>
1825
1826 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
1827
66ef5847
AM		 18282020-05-11 Alan Modra <amodra@gmail.com>
1829
1830 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
1831 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
1832
4f3e9537
PB		 18332020-05-11 Peter Bergner <bergner@linux.ibm.com>
1834
1835 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
1836 mnemonics.
1837
ec40e91c
AM		 18382020-05-11 Alan Modra <amodra@gmail.com>
1839
1840 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
1841 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
1842 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
1843 (prefix_opcodes): Add xxeval.
1844
d7e97a76
AM		 18452020-05-11 Alan Modra <amodra@gmail.com>
1846
1847 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
1848 xxgenpcvwm, xxgenpcvdm.
1849
fdefed7c
AM		 18502020-05-11 Alan Modra <amodra@gmail.com>
1851
1852 * ppc-opc.c (MP, VXVAM_MASK): Define.
1853 (VXVAPS_MASK): Use VXVA_MASK.
1854 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
1855 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
1856 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
1857 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
1858
aa3c112f
AM		 18592020-05-11 Alan Modra <amodra@gmail.com>
1860 Peter Bergner <bergner@linux.ibm.com>
1861
1862 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
1863 New functions.
1864 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
1865 YMSK2, XA6a, XA6ap, XB6a entries.
1866 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
1867 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
1868 (PPCVSX4): Define.
1869 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
1870 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
1871 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
1872 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
1873 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
1874 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
1875 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
1876 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
1877 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
1878 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
1879 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
1880 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
1881 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
1882 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
1883
6edbfd3b
AM		 18842020-05-11 Alan Modra <amodra@gmail.com>
1885
1886 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
1887 (insert_xts, extract_xts): New functions.
1888 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
1889 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
1890 (VXRC_MASK, VXSH_MASK): Define.
1891 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
1892 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
1893 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
1894 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
1895 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
1896 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
1897 xxblendvh, xxblendvw, xxblendvd, xxpermx.
1898
c7d7aea2
AM		 18992020-05-11 Alan Modra <amodra@gmail.com>
1900
1901 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
1902 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
1903 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
1904 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
1905 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
1906
94ba9882
AM		 19072020-05-11 Alan Modra <amodra@gmail.com>
1908
1909 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
1910 (XTP, DQXP, DQXP_MASK): Define.
1911 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
1912 (prefix_opcodes): Add plxvp and pstxvp.
1913
f4791f1a
AM		 19142020-05-11 Alan Modra <amodra@gmail.com>
1915
1916 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
1917 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
1918 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
1919
3ff0a5ba
PB		 19202020-05-11 Peter Bergner <bergner@linux.ibm.com>
1921
1922 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
1923
afef4fe9
PB		 19242020-05-11 Peter Bergner <bergner@linux.ibm.com>
1925
1926 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
1927 (L1OPT): Define.
1928 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
1929
1224c05d
PB		 19302020-05-11 Peter Bergner <bergner@linux.ibm.com>
1931
1932 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
1933
6bbb0c05
AM		 19342020-05-11 Alan Modra <amodra@gmail.com>
1935
1936 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
1937
7c1f4227
AM		 19382020-05-11 Alan Modra <amodra@gmail.com>
1939
1940 * ppc-dis.c (ppc_opts): Add "power10" entry.
1941 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
1942 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
1943
73199c2b
NC		 19442020-05-11 Nick Clifton <nickc@redhat.com>
1945
1946 * po/fr.po: Updated French translation.
1947
09c1e68a
AC		 19482020-04-30 Alex Coplan <alex.coplan@arm.com>
1949
1950 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
1951 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
1952 (operand_general_constraint_met_p): validate
1953 AARCH64_OPND_UNDEFINED.
1954 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
1955 for FLD_imm16_2.
1956 * aarch64-asm-2.c: Regenerated.
1957 * aarch64-dis-2.c: Regenerated.
1958 * aarch64-opc-2.c: Regenerated.
1959
9654d51a
NC		 19602020-04-29 Nick Clifton <nickc@redhat.com>
1961
1962 PR 22699
1963 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
1964 and SETRC insns.
1965
c2e71e57
NC		 19662020-04-29 Nick Clifton <nickc@redhat.com>
1967
1968 * po/sv.po: Updated Swedish translation.
1969
5c936ef5
NC		 19702020-04-29 Nick Clifton <nickc@redhat.com>
1971
1972 PR 22699
1973 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
1974 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
1975 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
1976 IMM0_8U case.
1977
bb2a1453
AS		 19782020-04-21 Andreas Schwab <schwab@linux-m68k.org>
1979
1980 PR 25848
1981 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
1982 cmpi only on m68020up and cpu32.
1983
c2e5c986
SD		 19842020-04-20 Sudakshina Das <sudi.das@arm.com>
1985
1986 * aarch64-asm.c (aarch64_ins_none): New.
1987 * aarch64-asm.h (ins_none): New declaration.
1988 * aarch64-dis.c (aarch64_ext_none): New.
1989 * aarch64-dis.h (ext_none): New declaration.
1990 * aarch64-opc.c (aarch64_print_operand): Update case for
1991 AARCH64_OPND_BARRIER_PSB.
1992 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
1993 (AARCH64_OPERANDS): Update inserter/extracter for
1994 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
1995 * aarch64-asm-2.c: Regenerated.
1996 * aarch64-dis-2.c: Regenerated.
1997 * aarch64-opc-2.c: Regenerated.
1998
8a6e1d1d
SD		 19992020-04-20 Sudakshina Das <sudi.das@arm.com>
2000
2001 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
2002 (aarch64_feature_ras, RAS): Likewise.
2003 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
2004 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
2005 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
2006 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
2007 * aarch64-asm-2.c: Regenerated.
2008 * aarch64-dis-2.c: Regenerated.
2009 * aarch64-opc-2.c: Regenerated.
2010
e409955d
FS		 20112020-04-17 Fredrik Strupe <fredrik@strupe.net>
2012
2013 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
2014 (print_insn_neon): Support disassembly of conditional
2015 instructions.
2016
c54a9b56
DF		 20172020-02-16 David Faust <david.faust@oracle.com>
2018
2019 * bpf-desc.c: Regenerate.
2020 * bpf-desc.h: Likewise.
2021 * bpf-opc.c: Regenerate.
2022 * bpf-opc.h: Likewise.
2023
bb651e8b
CL		 20242020-04-07 Lili Cui <lili.cui@intel.com>
2025
2026 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
2027 (prefix_table): New instructions (see prefixes above).
2028 (rm_table): Likewise
2029 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
2030 CPU_ANY_TSXLDTRK_FLAGS.
2031 (cpu_flags): Add CpuTSXLDTRK.
2032 * i386-opc.h (enum): Add CpuTSXLDTRK.
2033 (i386_cpu_flags): Add cputsxldtrk.
2034 * i386-opc.tbl: Add XSUSPLDTRK insns.
2035 * i386-init.h: Regenerate.
2036 * i386-tbl.h: Likewise.
2037
4b27d27c
L		 20382020-04-02 Lili Cui <lili.cui@intel.com>
2039
2040 * i386-dis.c (prefix_table): New instructions serialize.
2041 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
2042 CPU_ANY_SERIALIZE_FLAGS.
2043 (cpu_flags): Add CpuSERIALIZE.
2044 * i386-opc.h (enum): Add CpuSERIALIZE.
2045 (i386_cpu_flags): Add cpuserialize.
2046 * i386-opc.tbl: Add SERIALIZE insns.
2047 * i386-init.h: Regenerate.
2048 * i386-tbl.h: Likewise.
2049
832a5807
AM		 20502020-03-26 Alan Modra <amodra@gmail.com>
2051
2052 * disassemble.h (opcodes_assert): Declare.
2053 (OPCODES_ASSERT): Define.
2054 * disassemble.c: Don't include assert.h. Include opintl.h.
2055 (opcodes_assert): New function.
2056 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
2057 (bfd_h8_disassemble): Reduce size of data array. Correctly
2058 calculate maxlen. Omit insn decoding when insn length exceeds
2059 maxlen. Exit from nibble loop when looking for E, before
2060 accessing next data byte. Move processing of E outside loop.
2061 Replace tests of maxlen in loop with assertions.
2062
4c4addbe
AM		 20632020-03-26 Alan Modra <amodra@gmail.com>
2064
2065 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
2066
a18cd0ca
AM		 20672020-03-25 Alan Modra <amodra@gmail.com>
2068
2069 * z80-dis.c (suffix): Init mybuf.
2070
57cb32b3
AM		 20712020-03-22 Alan Modra <amodra@gmail.com>
2072
2073 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
2074 successflly read from section.
2075
beea5cc1
AM		 20762020-03-22 Alan Modra <amodra@gmail.com>
2077
2078 * arc-dis.c (find_format): Use ISO C string concatenation rather
2079 than line continuation within a string. Don't access needs_limm
2080 before testing opcode != NULL.
2081
03704c77
AM		 20822020-03-22 Alan Modra <amodra@gmail.com>
2083
2084 * ns32k-dis.c (print_insn_arg): Update comment.
2085 (print_insn_ns32k): Reduce size of index_offset array, and
2086 initialize, passing -1 to print_insn_arg for args that are not
2087 an index. Don't exit arg loop early. Abort on bad arg number.
2088
d1023b5d
AM		 20892020-03-22 Alan Modra <amodra@gmail.com>
2090
2091 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
2092 * s12z-opc.c: Formatting.
2093 (operands_f): Return an int.
2094 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
2095 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
2096 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
2097 (exg_sex_discrim): Likewise.
2098 (create_immediate_operand, create_bitfield_operand),
2099 (create_register_operand_with_size, create_register_all_operand),
2100 (create_register_all16_operand, create_simple_memory_operand),
2101 (create_memory_operand, create_memory_auto_operand): Don't
2102 segfault on malloc failure.
2103 (z_ext24_decode): Return an int status, negative on fail, zero
2104 on success.
2105 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
2106 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
2107 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
2108 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
2109 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
2110 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
2111 (loop_primitive_decode, shift_decode, psh_pul_decode),
2112 (bit_field_decode): Similarly.
2113 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
2114 to return value, update callers.
2115 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
2116 Don't segfault on NULL operand.
2117 (decode_operation): Return OP_INVALID on first fail.
2118 (decode_s12z): Check all reads, returning -1 on fail.
2119
340f3ac8
AM		 21202020-03-20 Alan Modra <amodra@gmail.com>
2121
2122 * metag-dis.c (print_insn_metag): Don't ignore status from
2123 read_memory_func.
2124
fe90ae8a
AM		 21252020-03-20 Alan Modra <amodra@gmail.com>
2126
2127 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
2128 Initialize parts of buffer not written when handling a possible
2129 2-byte insn at end of section. Don't attempt decoding of such
2130 an insn by the 4-byte machinery.
2131
833d919c
AM		 21322020-03-20 Alan Modra <amodra@gmail.com>
2133
2134 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
2135 partially filled buffer. Prevent lookup of 4-byte insns when
2136 only VLE 2-byte insns are possible due to section size. Print
2137 ".word" rather than ".long" for 2-byte leftovers.
2138
327ef784
NC		 21392020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
2140
2141 PR 25641
2142 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
2143
1673df32
JB		 21442020-03-13 Jan Beulich <jbeulich@suse.com>
2145
2146 * i386-dis.c (X86_64_0D): Rename to ...
2147 (X86_64_0E): ... this.
2148
384f3689
L		 21492020-03-09 H.J. Lu <hongjiu.lu@intel.com>
2150
2151 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
2152 * Makefile.in: Regenerated.
2153
865e2027
JB		 21542020-03-09 Jan Beulich <jbeulich@suse.com>
2155
2156 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
2157 3-operand pseudos.
2158 * i386-tbl.h: Re-generate.
2159
2f13234b
JB		 21602020-03-09 Jan Beulich <jbeulich@suse.com>
2161
2162 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
2163 vprot*, vpsha*, and vpshl*.
2164 * i386-tbl.h: Re-generate.
2165
3fabc179
JB		 21662020-03-09 Jan Beulich <jbeulich@suse.com>
2167
2168 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
2169 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
2170 * i386-tbl.h: Re-generate.
2171
3677e4c1
JB		 21722020-03-09 Jan Beulich <jbeulich@suse.com>
2173
2174 * i386-gen.c (set_bitfield): Ignore zero-length field names.
2175 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
2176 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
2177 * i386-tbl.h: Re-generate.
2178
4c4898e8
JB		 21792020-03-09 Jan Beulich <jbeulich@suse.com>
2180
2181 * i386-gen.c (struct template_arg, struct template_instance,
2182 struct template_param, struct template, templates,
2183 parse_template, expand_templates): New.
2184 (process_i386_opcodes): Various local variables moved to
2185 expand_templates. Call parse_template and expand_templates.
2186 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
2187 * i386-tbl.h: Re-generate.
2188
bc49bfd8
JB		 21892020-03-06 Jan Beulich <jbeulich@suse.com>
2190
2191 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
2192 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
2193 register and memory source templates. Replace VexW= by VexW*
2194 where applicable.
2195 * i386-tbl.h: Re-generate.
2196
4873e243
JB		 21972020-03-06 Jan Beulich <jbeulich@suse.com>
2198
2199 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
2200 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
2201 * i386-tbl.h: Re-generate.
2202
672a349b
JB		 22032020-03-06 Jan Beulich <jbeulich@suse.com>
2204
2205 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
2206 * i386-tbl.h: Re-generate.
2207
4ed21b58
JB		 22082020-03-06 Jan Beulich <jbeulich@suse.com>
2209
2210 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
2211 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
2212 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
2213 VexW0 on SSE2AVX variants.
2214 (vmovq): Drop NoRex64 from XMM/XMM variants.
2215 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
2216 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
2217 applicable use VexW0.
2218 * i386-tbl.h: Re-generate.
2219
643bb870
JB		 22202020-03-06 Jan Beulich <jbeulich@suse.com>
2221
2222 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
2223 * i386-opc.h (Rex64): Delete.
2224 (struct i386_opcode_modifier): Remove rex64 field.
2225 * i386-opc.tbl (crc32): Drop Rex64.
2226 Replace Rex64 with Size64 everywhere else.
2227 * i386-tbl.h: Re-generate.
2228
a23b33b3
JB		 22292020-03-06 Jan Beulich <jbeulich@suse.com>
2230
2231 * i386-dis.c (OP_E_memory): Exclude recording of used address
2232 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
2233 addressed memory operands for MPX insns.
2234
a0497384
JB		 22352020-03-06 Jan Beulich <jbeulich@suse.com>
2236
2237 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
2238 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
2239 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
2240 (ptwrite): Split into non-64-bit and 64-bit forms.
2241 * i386-tbl.h: Re-generate.
2242
b630c145
JB		 22432020-03-06 Jan Beulich <jbeulich@suse.com>
2244
2245 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
2246 template.
2247 * i386-tbl.h: Re-generate.
2248
a847e322
JB		 22492020-03-04 Jan Beulich <jbeulich@suse.com>
2250
2251 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
2252 (prefix_table): Move vmmcall here. Add vmgexit.
2253 (rm_table): Replace vmmcall entry by prefix_table[] escape.
2254 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
2255 (cpu_flags): Add CpuSEV_ES entry.
2256 * i386-opc.h (CpuSEV_ES): New.
2257 (union i386_cpu_flags): Add cpusev_es field.
2258 * i386-opc.tbl (vmgexit): New.
2259 * i386-init.h, i386-tbl.h: Re-generate.
2260
3cd7f3e3
L		 22612020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2262
2263 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
2264 with MnemonicSize.
2265 * i386-opc.h (IGNORESIZE): New.
2266 (DEFAULTSIZE): Likewise.
2267 (IgnoreSize): Removed.
2268 (DefaultSize): Likewise.
2269 (MnemonicSize): New.
2270 (i386_opcode_modifier): Replace ignoresize/defaultsize with
2271 mnemonicsize.
2272 * i386-opc.tbl (IgnoreSize): New.
2273 (DefaultSize): Likewise.
2274 * i386-tbl.h: Regenerated.
2275
b8ba1385
SB		 22762020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2277
2278 PR 25627
2279 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
2280 instructions.
2281
10d97a0f
L		 22822020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2283
2284 PR gas/25622
2285 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
2286 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
2287 * i386-tbl.h: Regenerated.
2288
dc1e8a47
AM		 22892020-02-26 Alan Modra <amodra@gmail.com>
2290
2291 * aarch64-asm.c: Indent labels correctly.
2292 * aarch64-dis.c: Likewise.
2293 * aarch64-gen.c: Likewise.
2294 * aarch64-opc.c: Likewise.
2295 * alpha-dis.c: Likewise.
2296 * i386-dis.c: Likewise.
2297 * nds32-asm.c: Likewise.
2298 * nfp-dis.c: Likewise.
2299 * visium-dis.c: Likewise.
2300
265b4673
CZ		 23012020-02-25 Claudiu Zissulescu <claziss@gmail.com>
2302
2303 * arc-regs.h (int_vector_base): Make it available for all ARC
2304 CPUs.
2305
bd0cf5a6
NC		 23062020-02-20 Nelson Chu <nelson.chu@sifive.com>
2307
2308 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
2309 changed.
2310
fa164239
JW		 23112020-02-19 Nelson Chu <nelson.chu@sifive.com>
2312
2313 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
2314 c.mv/c.li if rs1 is zero.
2315
272a84b1
L		 23162020-02-17 H.J. Lu <hongjiu.lu@intel.com>
2317
2318 * i386-gen.c (cpu_flag_init): Replace CpuABM with
2319 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
2320 CPU_POPCNT_FLAGS.
2321 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
2322 * i386-opc.h (CpuABM): Removed.
2323 (CpuPOPCNT): New.
2324 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
2325 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
2326 popcnt. Remove CpuABM from lzcnt.
2327 * i386-init.h: Regenerated.
2328 * i386-tbl.h: Likewise.
2329
1f730c46
JB		 23302020-02-17 Jan Beulich <jbeulich@suse.com>
2331
2332 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
2333 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
2334 VexW1 instead of open-coding them.
2335 * i386-tbl.h: Re-generate.
2336
c8f8eebc
JB		 23372020-02-17 Jan Beulich <jbeulich@suse.com>
2338
2339 * i386-opc.tbl (AddrPrefixOpReg): Define.
2340 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
2341 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
2342 templates. Drop NoRex64.
2343 * i386-tbl.h: Re-generate.
2344
b9915cbc
JB		 23452020-02-17 Jan Beulich <jbeulich@suse.com>
2346
2347 PR gas/6518
2348 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
2349 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
2350 into Intel syntax instance (with Unpsecified) and AT&T one
2351 (without).
2352 (vcvtneps2bf16): Likewise, along with folding the two so far
2353 separate ones.
2354 * i386-tbl.h: Re-generate.
2355
ce504911
L		 23562020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2357
2358 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
2359 CPU_ANY_SSE4A_FLAGS.
2360
dabec65d
AM		 23612020-02-17 Alan Modra <amodra@gmail.com>
2362
2363 * i386-gen.c (cpu_flag_init): Correct last change.
2364
af5c13b0
L		 23652020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2366
2367 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
2368 CPU_ANY_SSE4_FLAGS.
2369
6867aac0
L		 23702020-02-14 H.J. Lu <hongjiu.lu@intel.com>
2371
2372 * i386-opc.tbl (movsx): Remove Intel syntax comments.
2373 (movzx): Likewise.
2374
65fca059
JB		 23752020-02-14 Jan Beulich <jbeulich@suse.com>
2376
2377 PR gas/25438
2378 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
2379 destination for Cpu64-only variant.
2380 (movzx): Fold patterns.
2381 * i386-tbl.h: Re-generate.
2382
7deea9aa
JB		 23832020-02-13 Jan Beulich <jbeulich@suse.com>
2384
2385 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
2386 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
2387 CPU_ANY_SSE4_FLAGS entry.
2388 * i386-init.h: Re-generate.
2389
6c0946d0
JB		 23902020-02-12 Jan Beulich <jbeulich@suse.com>
2391
2392 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
2393 with Unspecified, making the present one AT&T syntax only.
2394 * i386-tbl.h: Re-generate.
2395
ddb56fe6
JB		 23962020-02-12 Jan Beulich <jbeulich@suse.com>
2397
2398 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
2399 * i386-tbl.h: Re-generate.
2400
5990e377
JB		 24012020-02-12 Jan Beulich <jbeulich@suse.com>
2402
2403 PR gas/24546
2404 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
2405 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
2406 Amd64 and Intel64 templates.
2407 (call, jmp): Likewise for far indirect variants. Dro
2408 Unspecified.
2409 * i386-tbl.h: Re-generate.
2410
50128d0c
JB		 24112020-02-11 Jan Beulich <jbeulich@suse.com>
2412
2413 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
2414 * i386-opc.h (ShortForm): Delete.
2415 (struct i386_opcode_modifier): Remove shortform field.
2416 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
2417 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
2418 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
2419 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
2420 Drop ShortForm.
2421 * i386-tbl.h: Re-generate.
2422
1e05b5c4
JB		 24232020-02-11 Jan Beulich <jbeulich@suse.com>
2424
2425 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
2426 fucompi): Drop ShortForm from operand-less templates.
2427 * i386-tbl.h: Re-generate.
2428
2f5dd314
AM		 24292020-02-11 Alan Modra <amodra@gmail.com>
2430
2431 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
2432 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
2433 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
2434 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
2435 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2436
5aae9ae9
MM		 24372020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
2438
2439 * arm-dis.c (print_insn_cde): Define 'V' parse character.
2440 (cde_opcodes): Add VCX* instructions.
2441
4934a27c
MM		 24422020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
2443 Matthew Malcomson <matthew.malcomson@arm.com>
2444
2445 * arm-dis.c (struct cdeopcode32): New.
2446 (CDE_OPCODE): New macro.
2447 (cde_opcodes): New disassembly table.
2448 (regnames): New option to table.
2449 (cde_coprocs): New global variable.
2450 (print_insn_cde): New
2451 (print_insn_thumb32): Use print_insn_cde.
2452 (parse_arm_disassembler_options): Parse coprocN args.
2453
4b5aaf5f
L		 24542020-02-10 H.J. Lu <hongjiu.lu@intel.com>
2455
2456 PR gas/25516
2457 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
2458 with ISA64.
2459 * i386-opc.h (AMD64): Removed.
2460 (Intel64): Likewose.
2461 (AMD64): New.
2462 (INTEL64): Likewise.
2463 (INTEL64ONLY): Likewise.
2464 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
2465 * i386-opc.tbl (Amd64): New.
2466 (Intel64): Likewise.
2467 (Intel64Only): Likewise.
2468 Replace AMD64 with Amd64. Update sysenter/sysenter with
2469 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
2470 * i386-tbl.h: Regenerated.
2471
9fc0b501
SB		 24722020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
2473
2474 PR 25469
2475 * z80-dis.c: Add support for GBZ80 opcodes.
2476
c5d7be0c
AM		 24772020-02-04 Alan Modra <amodra@gmail.com>
2478
2479 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2480
44e4546f
AM		 24812020-02-03 Alan Modra <amodra@gmail.com>
2482
2483 * m32c-ibld.c: Regenerate.
2484
b2b1453a
AM		 24852020-02-01 Alan Modra <amodra@gmail.com>
2486
2487 * frv-ibld.c: Regenerate.
2488
4102be5c
JB		 24892020-01-31 Jan Beulich <jbeulich@suse.com>
2490
2491 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
2492 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
2493 (OP_E_memory): Replace xmm_mdq_mode case label by
2494 vex_scalar_w_dq_mode one.
2495 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
2496
825bd36c
JB		 24972020-01-31 Jan Beulich <jbeulich@suse.com>
2498
2499 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
2500 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
2501 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
2502 (intel_operand_size): Drop vex_w_dq_mode case label.
2503
c3036ed0
RS		 25042020-01-31 Richard Sandiford <richard.sandiford@arm.com>
2505
2506 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
2507 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
2508
0c115f84
AM		 25092020-01-30 Alan Modra <amodra@gmail.com>
2510
2511 * m32c-ibld.c: Regenerate.
2512
bd434cc4
JM		 25132020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
2514
2515 * bpf-opc.c: Regenerate.
2516
aeab2b26
JB		 25172020-01-30 Jan Beulich <jbeulich@suse.com>
2518
2519 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
2520 (dis386): Use them to replace C2/C3 table entries.
2521 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
2522 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
2523 ones. Use Size64 instead of DefaultSize on Intel64 ones.
2524 * i386-tbl.h: Re-generate.
2525
62b3f548
JB		 25262020-01-30 Jan Beulich <jbeulich@suse.com>
2527
2528 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
2529 forms.
2530 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
2531 DefaultSize.
2532 * i386-tbl.h: Re-generate.
2533
1bd8ae10
AM		 25342020-01-30 Alan Modra <amodra@gmail.com>
2535
2536 * tic4x-dis.c (tic4x_dp): Make unsigned.
2537
bc31405e
L		 25382020-01-27 H.J. Lu <hongjiu.lu@intel.com>
2539 Jan Beulich <jbeulich@suse.com>
2540
2541 PR binutils/25445
2542 * i386-dis.c (MOVSXD_Fixup): New function.
2543 (movsxd_mode): New enum.
2544 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
2545 (intel_operand_size): Handle movsxd_mode.
2546 (OP_E_register): Likewise.
2547 (OP_G): Likewise.
2548 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
2549 register on movsxd. Add movsxd with 16-bit destination register
2550 for AMD64 and Intel64 ISAs.
2551 * i386-tbl.h: Regenerated.
2552
7568c93b
TC		 25532020-01-27 Tamar Christina <tamar.christina@arm.com>
2554
2555 PR 25403
2556 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
2557 * aarch64-asm-2.c: Regenerate
2558 * aarch64-dis-2.c: Likewise.
2559 * aarch64-opc-2.c: Likewise.
2560
c006a730
JB		 25612020-01-21 Jan Beulich <jbeulich@suse.com>
2562
2563 * i386-opc.tbl (sysret): Drop DefaultSize.
2564 * i386-tbl.h: Re-generate.
2565
c906a69a
JB		 25662020-01-21 Jan Beulich <jbeulich@suse.com>
2567
2568 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
2569 Dword.
2570 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
2571 * i386-tbl.h: Re-generate.
2572
26916852
NC		 25732020-01-20 Nick Clifton <nickc@redhat.com>
2574
2575 * po/de.po: Updated German translation.
2576 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2577 * po/uk.po: Updated Ukranian translation.
2578
4d6cbb64
AM		 25792020-01-20 Alan Modra <amodra@gmail.com>
2580
2581 * hppa-dis.c (fput_const): Remove useless cast.
2582
2bddb71a
AM		 25832020-01-20 Alan Modra <amodra@gmail.com>
2584
2585 * arm-dis.c (print_insn_arm): Wrap 'T' value.
2586
1b1bb2c6
NC		 25872020-01-18 Nick Clifton <nickc@redhat.com>
2588
2589 * configure: Regenerate.
2590 * po/opcodes.pot: Regenerate.
2591
ae774686
NC		 25922020-01-18 Nick Clifton <nickc@redhat.com>
2593
2594 Binutils 2.34 branch created.
2595
07f1f3aa
CB		 25962020-01-17 Christian Biesinger <cbiesinger@google.com>
2597
2598 * opintl.h: Fix spelling error (seperate).
2599
42e04b36
L		 26002020-01-17 H.J. Lu <hongjiu.lu@intel.com>
2601
2602 * i386-opc.tbl: Add {vex} pseudo prefix.
2603 * i386-tbl.h: Regenerated.
2604
2da2eaf4
AV		 26052020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
2606
2607 PR 25376
2608 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
2609 (neon_opcodes): Likewise.
2610 (select_arm_features): Make sure we enable MVE bits when selecting
2611 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
2612 any architecture.
2613
d0849eed
JB		 26142020-01-16 Jan Beulich <jbeulich@suse.com>
2615
2616 * i386-opc.tbl: Drop stale comment from XOP section.
2617
9cf70a44
JB		 26182020-01-16 Jan Beulich <jbeulich@suse.com>
2619
2620 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
2621 (extractps): Add VexWIG to SSE2AVX forms.
2622 * i386-tbl.h: Re-generate.
2623
4814632e
JB		 26242020-01-16 Jan Beulich <jbeulich@suse.com>
2625
2626 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
2627 Size64 from and use VexW1 on SSE2AVX forms.
2628 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
2629 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
2630 * i386-tbl.h: Re-generate.
2631
aad09917
AM		 26322020-01-15 Alan Modra <amodra@gmail.com>
2633
2634 * tic4x-dis.c (tic4x_version): Make unsigned long.
2635 (optab, optab_special, registernames): New file scope vars.
2636 (tic4x_print_register): Set up registernames rather than
2637 malloc'd registertable.
2638 (tic4x_disassemble): Delete optable and optable_special. Use
2639 optab and optab_special instead. Throw away old optab,
2640 optab_special and registernames when info->mach changes.
2641
7a6bf3be
SB		 26422020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
2643
2644 PR 25377
2645 * z80-dis.c (suffix): Use .db instruction to generate double
2646 prefix.
2647
ca1eaac0
AM		 26482020-01-14 Alan Modra <amodra@gmail.com>
2649
2650 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
2651 values to unsigned before shifting.
2652
1d67fe3b
TT		 26532020-01-13 Thomas Troeger <tstroege@gmx.de>
2654
2655 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
2656 flow instructions.
2657 (print_insn_thumb16, print_insn_thumb32): Likewise.
2658 (print_insn): Initialize the insn info.
2659 * i386-dis.c (print_insn): Initialize the insn info fields, and
2660 detect jumps.
2661
5e4f7e05
CZ		 26622012-01-13 Claudiu Zissulescu <claziss@gmail.com>
2663
2664 * arc-opc.c (C_NE): Make it required.
2665
b9fe6b8a
CZ		 26662012-01-13 Claudiu Zissulescu <claziss@gmail.com>
2667
2668 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
2669 reserved register name.
2670
90dee485
AM		 26712020-01-13 Alan Modra <amodra@gmail.com>
2672
2673 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
2674 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
2675
febda64f
AM		 26762020-01-13 Alan Modra <amodra@gmail.com>
2677
2678 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
2679 result of wasm_read_leb128 in a uint64_t and check that bits
2680 are not lost when copying to other locals. Use uint32_t for
2681 most locals. Use PRId64 when printing int64_t.
2682
df08b588
AM		 26832020-01-13 Alan Modra <amodra@gmail.com>
2684
2685 * score-dis.c: Formatting.
2686 * score7-dis.c: Formatting.
2687
b2c759ce
AM		 26882020-01-13 Alan Modra <amodra@gmail.com>
2689
2690 * score-dis.c (print_insn_score48): Use unsigned variables for
2691 unsigned values. Don't left shift negative values.
2692 (print_insn_score32): Likewise.
2693 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
2694
5496abe1
AM		 26952020-01-13 Alan Modra <amodra@gmail.com>
2696
2697 * tic4x-dis.c (tic4x_print_register): Remove dead code.
2698
202e762b
AM		 26992020-01-13 Alan Modra <amodra@gmail.com>
2700
2701 * fr30-ibld.c: Regenerate.
2702
7ef412cf
AM		 27032020-01-13 Alan Modra <amodra@gmail.com>
2704
2705 * xgate-dis.c (print_insn): Don't left shift signed value.
2706 (ripBits): Formatting, use 1u.
2707
7f578b95
AM		 27082020-01-10 Alan Modra <amodra@gmail.com>
2709
2710 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
2711 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
2712
441af85b
AM		 27132020-01-10 Alan Modra <amodra@gmail.com>
2714
2715 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
2716 and XRREG value earlier to avoid a shift with negative exponent.
2717 * m10200-dis.c (disassemble): Similarly.
2718
bce58db4
NC		 27192020-01-09 Nick Clifton <nickc@redhat.com>
2720
2721 PR 25224
2722 * z80-dis.c (ld_ii_ii): Use correct cast.
2723
40c75bc8
SB		 27242020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2725
2726 PR 25224
2727 * z80-dis.c (ld_ii_ii): Use character constant when checking
2728 opcode byte value.
2729
d835a58b
JB		 27302020-01-09 Jan Beulich <jbeulich@suse.com>
2731
2732 * i386-dis.c (SEP_Fixup): New.
2733 (SEP): Define.
2734 (dis386_twobyte): Use it for sysenter/sysexit.
2735 (enum x86_64_isa): Change amd64 enumerator to value 1.
2736 (OP_J): Compare isa64 against intel64 instead of amd64.
2737 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
2738 forms.
2739 * i386-tbl.h: Re-generate.
2740
030a2e78
AM		 27412020-01-08 Alan Modra <amodra@gmail.com>
2742
2743 * z8k-dis.c: Include libiberty.h
2744 (instr_data_s): Make max_fetched unsigned.
2745 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
2746 Don't exceed byte_info bounds.
2747 (output_instr): Make num_bytes unsigned.
2748 (unpack_instr): Likewise for nibl_count and loop.
2749 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
2750 idx unsigned.
2751 * z8k-opc.h: Regenerate.
2752
bb82aefe
SV		 27532020-01-07 Shahab Vahedi <shahab@synopsys.com>
2754
2755 * arc-tbl.h (llock): Use 'LLOCK' as class.
2756 (llockd): Likewise.
2757 (scond): Use 'SCOND' as class.
2758 (scondd): Likewise.
2759 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
2760 (scondd): Likewise.
2761
cc6aa1a6
AM		 27622020-01-06 Alan Modra <amodra@gmail.com>
2763
2764 * m32c-ibld.c: Regenerate.
2765
660e62b1
AM		 27662020-01-06 Alan Modra <amodra@gmail.com>
2767
2768 PR 25344
2769 * z80-dis.c (suffix): Don't use a local struct buffer copy.
2770 Peek at next byte to prevent recursion on repeated prefix bytes.
2771 Ensure uninitialised "mybuf" is not accessed.
2772 (print_insn_z80): Don't zero n_fetch and n_used here,..
2773 (print_insn_z80_buf): ..do it here instead.
2774
c9ae58fe
AM		 27752020-01-04 Alan Modra <amodra@gmail.com>
2776
2777 * m32r-ibld.c: Regenerate.
2778
5f57d4ec
AM		 27792020-01-04 Alan Modra <amodra@gmail.com>
2780
2781 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
2782
2c5c1196
AM		 27832020-01-04 Alan Modra <amodra@gmail.com>
2784
2785 * crx-dis.c (match_opcode): Avoid shift left of signed value.
2786
2e98c6c5
AM		 27872020-01-04 Alan Modra <amodra@gmail.com>
2788
2789 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
2790
567dfba2
JB		 27912020-01-03 Jan Beulich <jbeulich@suse.com>
2792
5437a02a
JB		 2793 * aarch64-tbl.h (aarch64_opcode_table): Use
2794 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
2795
27962020-01-03 Jan Beulich <jbeulich@suse.com>
2797
2798 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB		 2799 forms of SUDOT and USDOT.
2800
8c45011a
JB		 28012020-01-03 Jan Beulich <jbeulich@suse.com>
2802
5437a02a 2803 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a
JB		 2804 uzip{1,2}.
2805 * opcodes/aarch64-dis-2.c: Re-generate.
2806
f4950f76
JB		 28072020-01-03 Jan Beulich <jbeulich@suse.com>
2808
5437a02a 2809 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
JB		 2810 FMMLA encoding.
2811 * opcodes/aarch64-dis-2.c: Re-generate.
2812
6655dba2
SB		 28132020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
2814
2815 * z80-dis.c: Add support for eZ80 and Z80 instructions.
2816
b14ce8bf
AM		 28172020-01-01 Alan Modra <amodra@gmail.com>
2818
2819 Update year range in copyright notice of all files.
2820
0b114740 2821For older changes see ChangeLog-2019
3499769a 2822\f
0b114740 2823Copyright (C) 2020 Free Software Foundation, Inc.
3499769a
AM		 2824
2825Copying and distribution of this file, with or without modification,
2826are permitted in any medium without royalty provided the copyright
2827notice and this notice are preserved.
2828
2829Local Variables:
2830mode: change-log
2831left-margin: 8
2832fill-column: 74
2833version-control: never
2834End:
GDB Binutils - Deliverables
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