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[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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943d398f
AM		 12012-12-13 Alan Modra <amodra@gmail.com>
2
3 PR binutils/14950
4 * ppc-opc.c (insert_sci8, extract_sci8): Rewrite.
5 (insert_sci8n, extract_sci8n): Likewise.
6
02a79b89
JR		 72012-11-30 Oleg Raikhman <oleg@adapteva.com>
8 Joern Rennecke <joern.rennecke@embecosm.com>
9
10 * epiphany-desc.c, epiphany-desc.h, epiphany-opc.c: Regenerate.
11
cdaaa29d
RM		 122012-11-29 Roland McGrath <mcgrathr@google.com>
13
14 * s390-mkopc.c (file_header): Add const.
15
94dda8b7
ME		 162012-11-29 David Holsgrove <david.holsgrove@xilinx.com>
17
18 * microblaze-opc.h: Rename INST_TYPE_RD_R1_SPECIAL to
19 INST_TYPE_R1_R2_SPECIAL
20 * microblaze-dis.c (print_insn_microblaze): Same.
21
776fc418
AM		 222012-11-23 Alan Modra <amodra@gmail.com>
23
24 * ppc-dis.c (ppc_parse_cpu): Add "sticky" param. Track bits
25 set from ppc_opts.sticky in it. Delete "retain_mask".
26 (powerpc_init_dialect): Choose default dialect from info->mach
27 before parsing -M options. Handle more bfd_mach_ppc variants.
28 Update common default to power7.
29
abe9f67d
ME		 302012-11-21 David Holsgrove <david.holsgrove@xilinx.com>
31
32 * microblaze-opc.h (op_code_struct): Add swapb, swaph Increase MAX_OPCODES.
33 * microblaze-opcm.h (microblaze_instr): Likewise
34
0db4b326
ME		 352012-11-21 Edgar E. Iglesias <edgar.iglesias@gmail.com>
36
37 * microblaze-opcm.h: Add REG_SLR_MASK, REG_SHR_MASK, REG_SHR and REG_SLR
38 * microblaze-dis.c (get_field_special): Handle REG_SLR_MASK and REG_SHR_MASK
39
9b30cccc
L		 402012-11-20 Kirill Yukhin <kirill.yukhin@intel.com>
41 H.J. Lu <hongjiu.lu@intel.com>
42
43 PR gas/14859
44 * i386-opc.tbl: Fix opcode for 64-bit jecxz.
45 * i386-tbl.h: Regenerated.
46
0b7fe784
AK		 472012-11-20 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
48
49 * s390-opc.txt: Fix srstu and strag opcodes.
50
d3da7741
ME		 512012-11-14 David Holsgrove <david.holsgrove@xilinx.com>
52
53 * microblaze-opc.h: Define new instruction type INST_TYPE_IMM5,
54 update OPCODE_MASK_H13S, add OPCODE_MASK_HN, define MIN_IMM5 / MAX_IMM5,
55 and increase MAX_OPCODES.
56 (op_code_struct): add mbar and sleep
57 * microblaze-opcm.h (microblaze_instr): add mbar
58 Define IMM_MBAR and IMM5_MBAR_MASK
59 * microblaze-dis.c: Add get_field_imm5_mbar
60 (print_insn_microblaze): Add support for INST_TYPE_IMM5 and INST_TYPE_NONE
61
ed8ec0ec
ME		 622012-11-14 Edgar E. Iglesias <edgar.iglesias@gmail.com>
63
64 * microblaze-opc.h: Increase MAX_OPCODES (op_code_struct): add clz insn
65 * microblaze-opcm.h (microblaze_instr): add clz
66
e692c217
ME		 672012-11-14 Edgar E. Iglesias <edgar.iglesias@gmail.com>
68
cdaaa29d 69 * microblaze-opc.h: Increase MAX_OPCODES (op_code_struct): add lbur,
e692c217
ME		 70 lhur, lwr, sbr, shr, swr
71 * microblaze-opcm.h (microblaze_instr): add lbur, lhur, lwr, sbr, shr,
72 swr
73
de863c74
NC		 742012-11-09 Nick Clifton <nickc@redhat.com>
75
76 * configure.in: Add bfd_v850_rh850_arch.
77 * configure: Regenerate.
78 * disassemble.c (disassembler): Likewise.
79
5bb3703f
L		 802012-11-09 H.J. Lu <hongjiu.lu@intel.com>
81
82 * aarch64-opc.h (gen_mask): Remove trailing redundant `;'.
83 * ia64-gen.c (fetch_insn_class): Likewise.
84
6febeb74
AM		 852012-11-08 Alan Modra <amodra@gmail.com>
86
87 * po/POTFILES.in: Regenerate.
88
d17dce55
AM		 892012-11-05 Alan Modra <amodra@gmail.com>
90
91 * configure.in: Apply 2012-09-10 change to config.in here.
92
aac129d7
AK		 932012-10-26 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
94
95 * s390-mkopc.c: Accept empty lines in s390-opc.txt.
d17dce55
AM		 96 * s390-opc.c: Add M_20OPT field. New instruction formats RRF_RURR2
97 and RRF_RMRR.
aac129d7
AK		 98 * s390-opc.txt: Add new instructions. New instruction type for lptea.
99
747a4ac1
CG		 1002012-10-26 Christian Groessler <chris@groessler.org>
101
102 * z8kgen.c (struct op): Fix encoding for translate opcodes (trdb,
103 trdrb, trib, trirb, trtdb, trtdrb, trtib, trtirb). Remove
104 non-existing opcode trtrb.
105 * z8k-opc.h: Regenerate.
106
62082a42
AM		 1072012-10-26 Alan Modra <amodra@gmail.com>
108
109 * ppc-opc (powerpc_opcodes): "lfdp" and "stfdp" use DS offset.
110
6c067bbb
RM		 1112012-10-24 Roland McGrath <mcgrathr@google.com>
112
113 * i386-dis.c (ckprefix): When bailing out for fwait with prefixes,
114 set rex_used to rex.
115
ab4437c3
PB		 1162012-10-22 Peter Bergner <bergner@vnet.ibm.com>
117
118 * ppc-opc.c (powerpc_opcodes) <vcfpsxws>: Fix opcode spelling.
119
9a176a4a
TT		 1202012-10-18 Tom Tromey <tromey@redhat.com>
121
122 * tic54x-dis.c (print_instruction): Don't use K&R style.
123 (print_parallel_instruction, sprint_dual_address)
124 (sprint_indirect_address, sprint_direct_address, sprint_mmr)
125 (sprint_cc2, sprint_condition): Likewise.
126
4ad3b7ef
KT		 1272012-10-18 Kai Tietz <ktietz@redhat.com>
128
129 * aarch64-asm.c (aarch64_ins_ldst_reglist): Initialize
130 value with a default.
131 (do_special_encoding): Likewise.
132 (aarch64_ins_ldst_elemlist): Pre-initialize QSsize, and opcodeh2
133 variables with default.
134 * arc-dis.c (write_comments_): Don't use strncat due
135 size of state->commentBuffer pointer isn't predictable.
136
b7a54b55
YZ		 1372012-10-15 Yufeng Zhang <yufeng.zhang@arm.com>
138
139 * aarch64-opc.c (aarch64_sys_regs): Add rmr_el1, rmr_el2 and
140 rmr_el3; remove daifset and daifclr.
141
9b61754a
YZ		 1422012-10-15 Yufeng Zhang <yufeng.zhang@arm.com>
143
144 * aarch64-opc.c (operand_general_constraint_met_p): Change to check
145 the alignment of addr.offset.imm instead of that of shifter.amount for
146 operand type AARCH64_OPND_ADDR_UIMM12.
147
f8ece37f
RE		 1482012-10-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
149
150 * arm-dis.c: Use preferred form of vrint instruction variants
151 for disassembly.
152
5e5c50d3
NE		 1532012-10-09 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
154
155 * i386-gen.c (cpu_flag_init): Add CPU_BDVER3_FLAGS.
156 * i386-init.h: Regenerated.
157
c7a5aa9c
PB		 1582012-10-05 Peter Bergner <bergner@vnet.ibm.com>
159
160 * ppc-dis.c (ppc_opts) <altivec>: Use PPC_OPCODE_ALTIVEC2;
161 * ppc-opc.c (VBA): New define.
162 (powerpc_opcodes) <vcuxwfp, vcsxwfp, vcfpuxws, vcfpsxsw, vmr, vnot,
163 mfppr, mfppr32, mtppr, mtppr32>: New extended mnemonics.
164
04ee5257
NC		 1652012-10-04 Nick Clifton <nickc@redhat.com>
166
167 * v850-dis.c (disassemble): Place square parentheses around second
168 register operand of clr1, not1, set1 and tst1 instructions.
169
cfc72779
AK		 1702012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
171
172 * s390-mkopc.c: Support new option zEC12.
173 * s390-opc.c: Add new instruction formats.
174 * s390-opc.txt: Add new instructions for zEC12.
175
1415a2a7
AG		 1762012-09-27 Anthony Green <green@moxielogic.com>
177
178 * moxie-dis.c (print_insn_moxie): Print 'bad' instructions.
179 * moxie-opc.c: All 'bad' instructions have the itype MOXIE_BAD.
180
160a30bb
L		 1812012-09-25 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
182
04ee5257
NC		 183 * i386-gen.c (cpu_flag_init): Add missing Cpu flags in
184 CPU_BDVER1_FLAGS, CPU_BDVER2_FLAGS, CPU_BTVER1_FLAGS
160a30bb
L		 185 and CPU_BTVER2_FLAGS.
186 * i386-init.h: Regenerated.
187
60aa667e
L		 1882012-09-20 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
189
190 * i386-gen.c (cpu_flag_init): Add CpuCX16 to CPU_NOCONA_FLAGS,
191 CPU_CORE_FLAGS, CPU_CORE2_FLAGS, CPU_COREI7_FLAGS,
192 CPU_BDVER1_FLAGS, CPU_BDVER2_FLAGS, CPU_BTVER1_FLAGS,
193 CPU_BTVER2_FLAGS. Add CPU_CX16_FLAGS.
194 (cpu_flags): Add CpuCX16.
195 * i386-opc.h (CpuCX16): New.
196 (i386_cpu_flags): Add cpucx16.
197 * i386-opc.tbl: Replace CpuSSE3 with CpuCX16 for cmpxchg16b.
198 * i386-tbl.h: Regenerate.
199 * i386-init.h: Likewise.
200
4b8c8c02
RE		 2012012-09-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
202
60aa667e 203 * arm-dis.c: Changed ldra and strl-form mnemonics
4b8c8c02
RE		 204 to lda and stl-form.
205
83ea18d0
MR		 2062012-09-18 Chao-ying Fu <fu@mips.com>
207
208 * micromips-opc.c (micromips_opcodes): Correct the encoding of
209 the "swxc1" instruction.
210
062f38fa
RE		 2112012-09-17 Yufeng Zhang <yufeng.zhang@arm.com>
212
213 * aarch64-asm.c (aarch64_ins_imm_half): Remove ATTRIBUTE_UNUSED from
214 the parameter 'inst'.
215 (aarch64_ins_addr_simm): Add ATTRIBUTE_UNUSED to the parameter 'inst'.
216 (convert_mov_to_movewide): Change to assert (0) when
217 aarch64_wide_constant_p returns FALSE.
218
b132a67d
DE		 2192012-09-14 David Edelsohn <dje.gcc@gmail.com>
220
221 * configure: Regenerate.
222
1f9b75dd
AG		 2232012-09-14 Anthony Green <green@moxielogic.com>
224
225 * moxie-dis.c (print_insn_moxie): Branch targets are relative to
226 the address after the branch instruction.
227
e202fa84
AG		 2282012-09-13 Anthony Green <green@moxielogic.com>
229
230 * moxie-dis.c (print_insn_moxie): Handle bi-endian encodings.
231
00716ab1
AM		 2322012-09-10 Matthias Klose <doko@ubuntu.com>
233
234 * config.in: Disable sanity check for kfreebsd.
235
6d2920c8
L		 2362012-09-10 H.J. Lu <hongjiu.lu@intel.com>
237
238 * configure: Regenerated.
239
b3e14eda
L		 2402012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
241
242 * ia64-asmtab.h (completer_index): Extend bitfield to full uint.
243 * ia64-gen.c: Promote completer index type to longlong.
244 (irf_operand): Add new register recognition.
245 (in_iclass_mov_x): Add an entry for the new mov_* instruction type.
246 (lookup_specifier): Add new resource recognition.
247 (insert_bit_table_ent): Relax abort condition according to the
248 changed completer index type.
249 (print_dis_table): Fix printf format for completer index.
250 * ia64-ic.tbl: Add a new instruction class.
251 * ia64-opc-i.c (ia64_opcodes_i): Define new I-instructions.
252 * ia64-opc-m.c (ia64_opcodes_m): Define new M-instructions.
253 * ia64-opc.h: Define short names for new operand types.
254 * ia64-raw.tbl: Add new RAW resource for DAHR register.
255 * ia64-waw.tbl: Add new WAW resource for DAHR register.
256 * ia64-asmtab.c: Regenerate.
257
382c72e9
PB		 2582012-08-29 Peter Bergner <bergner@vnet.ibm.com>
259
260 * ppc-opc.c (VXASHB_MASK): New define.
261 (powerpc_opcodes) <vsldoi>: Use VXASHB_MASK.
262
fb048c26
PB		 2632012-08-28 Peter Bergner <bergner@vnet.ibm.com>
264
265 * ppc-opc.c (UIMM4, UIMM3, UIMM2, VXVA_MASK, VXVB_MASK, VXVAVB_MASK,
266 VXVDVA_MASK, VXUIMM4_MASK, VXUIMM3_MASK, VXUIMM2_MASK): New defines.
267 (powerpc_opcodes) <vexptefp, vlogefp, vrefp, vrfim, vrfin, vrfip,
268 vrfiz, vrsqrtefp, vupkhpx, vupkhsb, vupkhsh, vupklpx, vupklsb,
269 vupklsh>: Use VXVA_MASK.
270 <vspltisb, vspltish, vspltisw>: Use VXVB_MASK.
271 <mfvscr>: Use VXVAVB_MASK.
272 <mtvscr>: Use VXVDVA_MASK.
273 <vspltb>: Use VXUIMM4_MASK.
274 <vsplth>: Use VXUIMM3_MASK.
275 <vspltw>: Use VXUIMM2_MASK.
276
3c9017d2
MGD		 2772012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
278
279 * arm-dis.c (neon_opcodes): Add 2 operand sha instructions.
280
48adcd8e
MGD		 2812012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
282
283 * arm-dis.c (neon_opcodes): Add SHA 3-operand instructions.
284
4f51b4bd
MGD		 2852012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
286
287 * arm-dis.c (neon_opcodes): Handle VMULL.P64.
288
91ff7894
MGD		 2892012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
290
291 * arm-dis.c (neon_opcodes): Add support for AES instructions.
292
c70a8987
MGD		 2932012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
294
295 * arm-dis.c (coprocessor_opcodes): Add support for HP/DP
296 conversions.
297
30bdf752
MGD		 2982012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
299
300 * arm-dis.c (coprocessor_opcodes): Add VRINT.
301 (neon_opcodes): Likewise.
302
7e8e6784
MGD		 3032012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
304
305 * arm-dis.c (coprocessor_opcodes): Add support for new VCVT
306 variants.
307 (neon_opcodes): Likewise.
308
73924fbc
MGD		 3092012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
310
311 * arm-dis.c (coprocessor_opcodes): Add VMAXNM/VMINNM.
312 (neon_opcodes): Likewise.
313
33399f07
MGD		 3142012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
315
316 * arm-dis.c (coprocessor_opcodes): Add VSEL.
317 (print_insn_coprocessor): Add new %<>c bitfield format
318 specifier.
319
9eb6c0f1
MGD		 3202012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
321
322 * arm-dis.c (arm_opcodes): Add LDRA/STRL instructions.
323 (thumb32_opcodes): Likewise.
324 (print_arm_insn): Add support for %<>T formatter.
325
8884b720
MGD		 3262012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
327
328 * arm-dis.c (arm_opcodes): Add HLT.
329 (thumb_opcodes): Likewise.
330
b79f7053
MGD		 3312012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
332
333 * arm-dis.c (thumb32_opcodes): Add DCPS instruction.
334
53c4b28b
MGD		 3352012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
336
337 * arm-dis.c (arm_opcodes): Add SEVL.
338 (thumb_opcodes): Likewise.
339 (thumb32_opcodes): Likewise.
340
e797f7e0
MGD		 3412012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
342
343 * arm-dis.c (data_barrier_option): New function.
344 (print_insn_arm): Use data_barrier_option.
345 (print_insn_thumb32): Use data_barrier_option.
346
e2efe87d
MGD		 3472012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com
348
349 * arm-dis.c (COND_UNCOND): New constant.
350 (print_insn_coprocessor): Add support for %u format specifier.
351 (print_insn_neon): Likewise.
352
2c63854f
DM		 3532012-08-21 David S. Miller <davem@davemloft.net>
354
355 * sparc-opc.c (4-argument crypto instructions): Fix encoding using
356 F3F4 macro.
357
e67ed0e8
AM		 3582012-08-20 Edmar Wienskoski <edmar@freescale.com>
359
360 * ppc-opc.c (powerpc_opcodes): Changed opcode for vabsdub,
361 vabsduh, vabsduw, mviwsplt.
362
7b458c12
L		 3632012-08-17 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
364
365 * i386-gen.c (cpu_flag_init): Add CPU_BTVER1_FLAGS and
366 CPU_BTVER2_FLAGS.
367
e67ed0e8 368 * i386-opc.h: Update CpuPRFCHW comment.
7b458c12
L		 369
370 * i386-opc.tbl: Enable prefetch instruction for CpuPRFCHW.
371 * i386-init.h: Regenerated.
372 * i386-tbl.h: Likewise.
373
eb80cb87
NC		 3742012-08-17 Nick Clifton <nickc@redhat.com>
375
376 * po/uk.po: New Ukranian translation.
377 * configure.in (ALL_LINGUAS): Add uk.
378 * configure: Regenerate.
379
8baf7b78
PB		 3802012-08-16 Peter Bergner <bergner@vnet.ibm.com>
381
382 * ppc-opc.c (powerpc_opcodes) <"lswx">: Use RAX for the second and
383 RBX for the third operand.
384 <"lswi">: Use RAX for second and NBI for the third operand.
385
3d557b4c
DD		 3862012-08-15 DJ Delorie <dj@redhat.com>
387
388 * rl78-decode.opc (rl78_decode_opcode): Merge %e and %[01]
389 operands, so that data addresses can be corrected when not
390 ES-overridden.
391 * rl78-decode.c: Regenerate.
392 * rl78-dis.c (print_insn_rl78): Make order of modifiers
393 irrelevent. When the 'e' specifier is used on an operand and no
394 ES prefix is provided, adjust address to make it absolute.
395
588925d0
PB		 3962012-08-15 Peter Bergner <bergner@vnet.ibm.com>
397
398 * ppc-opc.c <RSQ, RTQ>: Use PPC_OPERAND_GPR.
399
9f6a6cc0
PB		 4002012-08-15 Peter Bergner <bergner@vnet.ibm.com>
401
402 * ppc-opc.c <xnop, yield, mdoio, mdoom>: New extended mnemonics.
403
fc8c4fd1
MR		 4042012-08-14 Maciej W. Rozycki <macro@codesourcery.com>
405
406 * mips-dis.c (print_insn_args): Add GET_OP and GET_OP_S local
407 macros, use local variables for info struct member accesses,
408 update the type of the variable used to hold the instruction
409 word.
410 (print_insn_mips, print_mips16_insn_arg): Likewise.
411 (print_insn_mips16): Add GET_OP and GET_OP_S local macros, use
412 local variables for info struct member accesses.
413 (print_insn_micromips): Add GET_OP_S local macro.
414 (_print_insn_mips): Update the type of the variable used to hold
415 the instruction word.
416
a06ea964 4172012-08-13 Ian Bolton <ian.bolton@arm.com>
e67ed0e8
AM		 418 Laurent Desnogues <laurent.desnogues@arm.com>
419 Jim MacArthur <jim.macarthur@arm.com>
420 Marcus Shawcroft <marcus.shawcroft@arm.com>
421 Nigel Stephens <nigel.stephens@arm.com>
422 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
423 Richard Earnshaw <rearnsha@arm.com>
424 Sofiane Naci <sofiane.naci@arm.com>
425 Tejas Belagod <tejas.belagod@arm.com>
426 Yufeng Zhang <yufeng.zhang@arm.com>
a06ea964
NC		 427
428 * Makefile.am: Add AArch64.
429 * Makefile.in: Regenerate.
430 * aarch64-asm.c: New file.
431 * aarch64-asm.h: New file.
432 * aarch64-dis.c: New file.
433 * aarch64-dis.h: New file.
434 * aarch64-gen.c: New file.
435 * aarch64-opc.c: New file.
436 * aarch64-opc.h: New file.
437 * aarch64-tbl.h: New file.
438 * configure.in: Add AArch64.
439 * configure: Regenerate.
440 * disassemble.c: Add AArch64.
441 * aarch64-asm-2.c: New file (automatically generated).
442 * aarch64-dis-2.c: New file (automatically generated).
443 * aarch64-opc-2.c: New file (automatically generated).
444 * po/POTFILES.in: Regenerate.
445
35d0a169
MR		 4462012-08-13 Maciej W. Rozycki <macro@codesourcery.com>
447
448 * micromips-opc.c (micromips_opcodes): Update comment.
449 * mips-opc.c (mips_builtin_opcodes): Likewise. Mark coprocessor
450 instructions for IOCT as appropriate.
451 * mips-dis.c (print_insn_mips): Replace OPCODE_IS_MEMBER with
452 opcode_is_member.
453 * configure.in: Substitute NO_WMISSING_FIELD_INITIALIZERS with
454 the result of a check for the -Wno-missing-field-initializers
455 GCC option.
456 * Makefile.am (NO_WMISSING_FIELD_INITIALIZERS): New variable.
457 (mips-opc.lo): Pass $(NO_WMISSING_FIELD_INITIALIZERS) to
458 compilation.
459 (mips16-opc.lo): Likewise.
460 (micromips-opc.lo): Likewise.
461 * aclocal.m4: Regenerate.
462 * configure: Regenerate.
463 * Makefile.in: Regenerate.
464
5c5acbbd
L		 4652012-08-11 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
466
467 PR gas/14423
468 * i386-gen.c (cpu_flag_init): Add CpuFMA in CPU_BDVER2_FLAGS.
469 * i386-init.h: Regenerated.
470
3c892704
NC		 4712012-08-09 Nick Clifton <nickc@redhat.com>
472
473 * po/vi.po: Updated Vietnamese translation.
474
d7189fa5
RM		 4752012-08-07 Roland McGrath <mcgrathr@google.com>
476
477 * i386-dis.c (reg_table): Fill out REG_0F0D table with
478 AMD-reserved cases as "prefetch".
479 (MOD_0F18_REG_4, MOD_0F18_REG_5): New enum constants.
480 (MOD_0F18_REG_6, MOD_0F18_REG_7): Likewise.
481 (reg_table): Use those under REG_0F18.
482 (mod_table): Add those cases as "nop/reserved".
483
4c692bc7
JB		 4842012-08-07 Jan Beulich <jbeulich@suse.com>
485
486 * i386-opc.tbl: Remove "FIXME" comments from SVME instructions.
487
de882298
RM		 4882012-08-06 Roland McGrath <mcgrathr@google.com>
489
490 * i386-dis.c (print_insn): Print spaces between multiple excess
491 prefixes. Return actual number of excess prefixes consumed,
492 not always one.
493
494 * i386-dis.c (OP_REG): Ignore REX_B for segment register cases.
495
7bb15c6f
RM		 4962012-08-06 Roland McGrath <mcgrathr@google.com>
497 Victor Khimenko <khim@google.com>
498 H.J. Lu <hongjiu.lu@intel.com>
499
500 * i386-dis.c (OP_sI): In b_T_mode and v_mode, REX_W trumps DFLAG.
501 (putop): For 'T', 'U', and 'V', treat REX_W like DFLAG.
502 (intel_operand_size): For stack_v_mode, treat REX_W like DFLAG.
503 (OP_E_register): Likewise.
504 (OP_REG): For low 8 whole registers, treat REX_W like DFLAG.
505
3843081d
JBG		 5062012-08-02 Jan-Benedict Glaw <jbglaw@lug-owl.de>
507
508 * configure.in: Formatting.
509 * configure: Regenerate.
510
48891606
AM		 5112012-08-01 Alan Modra <amodra@gmail.com>
512
513 * h8300-dis.c: Fix printf arg warnings.
514 * i960-dis.c: Likewise.
515 * mips-dis.c: Likewise.
516 * pdp11-dis.c: Likewise.
517 * sh-dis.c: Likewise.
518 * v850-dis.c: Likewise.
519 * configure.in: Formatting.
520 * configure: Regenerate.
521 * rl78-decode.c: Regenerate.
522 * po/POTFILES.in: Regenerate.
523
03f66e8a 5242012-07-31 Chao-Ying Fu <fu@mips.com>
e67ed0e8
AM		 525 Catherine Moore <clm@codesourcery.com>
526 Maciej W. Rozycki <macro@codesourcery.com>
03f66e8a
MR		 527
528 * micromips-opc.c (WR_a, RD_a, MOD_a): New macros.
529 (DSP_VOLA): Likewise.
530 (D32, D33): Likewise.
531 (micromips_opcodes): Add DSP ASE instructions.
48891606 532 * mips-dis.c (print_insn_micromips) <'2', '3'>: New cases.
03f66e8a
MR		 533 <'4', '5', '6', '7', '8', '0', '^', '@'>: Likewise.
534
94948e64
JB		 5352012-07-31 Jan Beulich <jbeulich@suse.com>
536
537 * i386-opc.tbl (vmovntdqa): Move up into 256-bit integer AVX2
538 instruction group. Mark as requiring AVX2.
539 * i386-tbl.h: Re-generate.
540
a6dc81d2
NC		 5412012-07-30 Nick Clifton <nickc@redhat.com>
542
543 * po/opcodes.pot: Updated template.
544 * po/es.po: Updated Spanish translation.
545 * po/fi.po: Updated Finnish translation.
546
c4dd807e
MF		 5472012-07-27 Mike Frysinger <vapier@gentoo.org>
548
549 * configure.in (BFD_VERSION): Run bfd/configure --version and
550 parse the output of that.
551 * configure: Regenerate.
552
03edbe3b
JL		 5532012-07-25 James Lemke <jwlemke@codesourcery.com>
554
555 * ppc-opc.c (powerpc_opcodes): Add/remove PPCVLE for some 32-bit insns.
556
63d08c68
NC		 5572012-07-24 Stephan McCamant <smcc@cs.berkeley.edu>
558 Dr David Alan Gilbert <dave@treblig.org>
d908c8af
NC		 559
560 PR binutils/13135
561 * arm-dis.c: Add necessary casts for printing integer values.
562 Use %s when printing string values.
563 * hppa-dis.c: Likewise.
564 * m68k-dis.c: Likewise.
565 * microblaze-dis.c: Likewise.
566 * mips-dis.c: Likewise.
567 * sparc-dis.c: Likewise.
568
ff688e1f
L		 5692012-07-19 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
570
571 PR binutils/14355
572 * i386-dis.c (VEX_LEN_0FXOP_08_CC): New.
573 (VEX_LEN_0FXOP_08_CD): Likewise.
574 (VEX_LEN_0FXOP_08_CE): Likewise.
575 (VEX_LEN_0FXOP_08_CF): Likewise.
576 (VEX_LEN_0FXOP_08_EC): Likewise.
577 (VEX_LEN_0FXOP_08_ED): Likewise.
578 (VEX_LEN_0FXOP_08_EE): Likewise.
579 (VEX_LEN_0FXOP_08_EF): Likewise.
580 (xop_table): Fix entries for vpcomb, vpcomw, vpcomd, vpcomq,
581 vpcomub, vpcomuw, vpcomud, vpcomuq.
582 (vex_len_table): Add entries for VEX_LEN_0FXOP_08_CC,
583 VEX_LEN_0FXOP_08_CD, VEX_LEN_0FXOP_08_CE, VEX_LEN_0FXOP_08_CF,
584 VEX_LEN_0FXOP_08_EC, VEX_LEN_0FXOP_08_ED, VEX_LEN_0FXOP_08_EE,
585 VEX_LEN_0FXOP_08_EF.
586
e2e1fcde
L		 5872012-07-16 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
588
589 * i386-dis.c (PREFIX_0F38F6): New.
590 (prefix_table): Add adcx, adox instructions.
591 (three_byte_table): Use PREFIX_0F38F6.
592 (mod_table): Add rdseed instruction.
593 * i386-gen.c (cpu_flag_init): Add CpuADX, CpuRDSEED, CpuPRFCHW.
594 (cpu_flags): Likewise.
595 * i386-opc.h: Add CpuADX, CpuRDSEED, CpuPRFCHW.
596 (i386_cpu_flags): Add fields cpurdseed, cpuadx, cpuprfchw.
597 * i386-opc.tbl: Add instrcutions adcx, adox, rdseed. Extend
598 prefetchw.
599 * i386-tbl.h: Regenerate.
600 * i386-init.h: Likewise.
601
8b99bf0b
TS		 6022012-07-05 Thomas Schwinge <thomas@codesourcery.com>
603
f4263ca2 604 * mips-dis.c: Remove gratuitous newline.
8b99bf0b 605
416cf80a
SK		 6062012-07-05 Sean Keys <skeys@ipdatasys.com>
607
608 * xgate-dis.c: Removed an IF statement that will
e67ed0e8
AM		 609 always be false due to overlapping operand masks.
610 * xgate-opc.c: Corrected 'com' opcode entry and
611 fixed spacing.
416cf80a 612
9fa0f14a
RM		 6132012-07-02 Roland McGrath <mcgrathr@google.com>
614
615 * i386-opc.tbl: Add RepPrefixOk to nop.
616 * i386-tbl.h: Regenerate.
617
4c6a93d3
NC		 6182012-06-28 Nick Clifton <nickc@redhat.com>
619
620 * po/vi.po: Updated Vietnamese translation.
621
29c048b6
RM		 6222012-06-22 Roland McGrath <mcgrathr@google.com>
623
fe13e45b
RM		 624 * i386-opc.tbl: Add RepPrefixOk to ret.
625 * i386-tbl.h: Regenerate.
626
29c048b6
RM		 627 * i386-opc.h (RepPrefixOk): New enum constant.
628 (i386_opcode_modifier): New bitfield 'repprefixok'.
629 * i386-gen.c (opcode_modifiers): Add RepPrefixOk.
630 * i386-opc.tbl: Add RepPrefixOk to bsf, bsr, and to all
631 instructions that have IsString.
632 * i386-tbl.h: Regenerate.
633
c7a8dbf9
AS		 6342012-06-11 Andreas Schwab <schwab@linux-m68k.org>
635
636 * ppc-opc.c (lvsl, lvebx, isellt, icbt, ldepx, lwepx, lvsr, lvehx)
637 (iselgt, lvewx, iseleq, isel, dcbst, dcbstep, dcbfl, dcbf, lbepx)
638 (lvx, dcbfep, dcbtstls, stvebx, dcbtstlse, stdepx, stwepx, dcbtls)
639 (stvehx, dcbtlse, stvewx, stbepx, icblc, stvx, dcbtstt, dcbtst)
640 (dcbtst, dcbtstep, dcbtt, dcbt, dcbt, lhepx, eciwx, dcbtep)
641 (dcread, lxvdsx, lvxl, dcblc, sthepx, ecowx, dcbi, dcread, icbtls)
642 (stvxl, lxsdx, lfdepx, stxsdx, stfdepx, dcba, dcbal, lxvw4x)
643 (tlbivax, lfdpx, lxvd2x, tlbsrx., stxvw4x, tlbsx, tlbsx., stfdpx)
644 (stfqx, stxvd2x, icbi, icbiep, icread, dcbzep): Change RA to RA0.
645
94caa966
AM		 6462012-05-19 Alan Modra <amodra@gmail.com>
647
648 * ppc-dis.c: Don't include elf32-ppc.h, do include elf/ppc.h.
649 (get_powerpc_dialect): Detect VLE sections from ELF sh_flags.
650
5eb3690e
AM		 6512012-05-18 Alan Modra <amodra@gmail.com>
652
71fe7bab
AM		 653 * ia64-opc.c: Remove #include "ansidecl.h".
654 * z8kgen.c: Include sysdep.h first.
655
5eb3690e
AM		 656 * arc-dis.c: Include sysdep.h first, remove some redundant includes.
657 * bfin-dis.c: Likewise.
658 * i860-dis.c: Likewise.
659 * ia64-dis.c: Likewise.
660 * ia64-gen.c: Likewise.
661 * m68hc11-dis.c: Likewise.
662 * mmix-dis.c: Likewise.
663 * msp430-dis.c: Likewise.
664 * or32-dis.c: Likewise.
665 * rl78-dis.c: Likewise.
666 * rx-dis.c: Likewise.
667 * tic4x-dis.c: Likewise.
668 * tilegx-opc.c: Likewise.
669 * tilepro-opc.c: Likewise.
670 * rx-decode.c: Regenerate.
671
a4ebc835
AM		 6722012-05-17 James Lemke <jwlemke@codesourcery.com>
673
674 * ppc-opc.c (powerpc_macros): Add entries for e_extlwi to e_clrlslwi.
675
98c76446
AM		 6762012-05-17 James Lemke <jwlemke@codesourcery.com>
677
678 * ppc-opc.c (extract_sprg): Use ALLOW8_SPRG to include VLE.
679
df7b86aa
NC		 6802012-05-17 Daniel Richard G. <skunk@iskunk.org>
681 Nick Clifton <nickc@redhat.com>
682
683 PR 14072
684 * configure.in: Add check that sysdep.h has been included before
685 any system header files.
686 * configure: Regenerate.
687 * config.in: Regenerate.
688 * sysdep.h: Generate an error if included before config.h.
689 * alpha-opc.c: Include sysdep.h before any other header file.
690 * alpha-dis.c: Likewise.
691 * avr-dis.c: Likewise.
692 * cgen-opc.c: Likewise.
693 * cr16-dis.c: Likewise.
694 * cris-dis.c: Likewise.
695 * crx-dis.c: Likewise.
696 * d10v-dis.c: Likewise.
697 * d10v-opc.c: Likewise.
698 * d30v-dis.c: Likewise.
699 * d30v-opc.c: Likewise.
700 * h8500-dis.c: Likewise.
701 * i370-dis.c: Likewise.
702 * i370-opc.c: Likewise.
703 * m10200-dis.c: Likewise.
704 * m10300-dis.c: Likewise.
705 * micromips-opc.c: Likewise.
706 * mips-opc.c: Likewise.
707 * mips61-opc.c: Likewise.
708 * moxie-dis.c: Likewise.
709 * or32-opc.c: Likewise.
710 * pj-dis.c: Likewise.
711 * ppc-dis.c: Likewise.
712 * ppc-opc.c: Likewise.
713 * s390-dis.c: Likewise.
714 * sh-dis.c: Likewise.
715 * sh64-dis.c: Likewise.
716 * sparc-dis.c: Likewise.
717 * sparc-opc.c: Likewise.
718 * spu-dis.c: Likewise.
719 * tic30-dis.c: Likewise.
720 * tic54x-dis.c: Likewise.
721 * tic80-dis.c: Likewise.
722 * tic80-opc.c: Likewise.
723 * tilegx-dis.c: Likewise.
724 * tilepro-dis.c: Likewise.
725 * v850-dis.c: Likewise.
726 * v850-opc.c: Likewise.
727 * vax-dis.c: Likewise.
728 * w65-dis.c: Likewise.
729 * xgate-dis.c: Likewise.
730 * xtensa-dis.c: Likewise.
731 * rl78-decode.opc: Likewise.
732 * rl78-decode.c: Regenerate.
733 * rx-decode.opc: Likewise.
734 * rx-decode.c: Regenerate.
735
e1dad58d
AM		 7362012-05-17 Alan Modra <amodra@gmail.com>
737
738 * ppc_dis.c: Don't include elf/ppc.h.
739
101af531
NC		 7402012-05-16 Meador Inge <meadori@codesourcery.com>
741
742 * arm-dis.c (arm_opcodes): Don't disassemble STMFD/LDMIA sp!, {reg}
743 to PUSH/POP {reg}.
744
6927f982
NC		 7452012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
746 Stephane Carrez <stcarrez@nerim.fr>
747
748 * configure.in: Add S12X and XGATE co-processor support to m68hc11
749 target.
750 * disassemble.c: Likewise.
751 * configure: Regenerate.
752 * m68hc11-dis.c: Make objdump output more consistent, use hex
753 instead of decimal and use 0x prefix for hex.
754 * m68hc11-opc.c: Add S12X and XGATE opcodes.
755
b9c361e0
JL		 7562012-05-14 James Lemke <jwlemke@codesourcery.com>
757
758 * ppc-dis.c (get_powerpc_dialect): Use is_ppc_vle.
759 (PPC_OPCD_SEGS, VLE_OPCD_SEGS): New defines.
760 (vle_opcd_indices): New array.
761 (lookup_vle): New function.
762 (disassemble_init_powerpc): Revise for second (VLE) opcode table.
763 (print_insn_powerpc): Likewise.
764 * ppc-opc.c: Likewise.
765
7662012-05-14 Catherine Moore <clm@codesourcery.com>
767 Maciej W. Rozycki <macro@codesourcery.com>
768 Rhonda Wittels <rhonda@codesourcery.com>
769 Nathan Froyd <froydnj@codesourcery.com>
770
771 * ppc-opc.c (insert_arx, extract_arx): New functions.
772 (insert_ary, extract_ary): New functions.
773 (insert_li20, extract_li20): New functions.
774 (insert_rx, extract_rx): New functions.
775 (insert_ry, extract_ry): New functions.
776 (insert_sci8, extract_sci8): New functions.
777 (insert_sci8n, extract_sci8n): New functions.
778 (insert_sd4h, extract_sd4h): New functions.
779 (insert_sd4w, extract_sd4w): New functions.
780 (insert_vlesi, extract_vlesi): New functions.
781 (insert_vlensi, extract_vlensi): New functions.
782 (insert_vleui, extract_vleui): New functions.
783 (insert_vleil, extract_vleil): New functions.
784 (BI_MASK, BB_MASK, BT): Use PPC_OPERAND_CR_BIT.
785 (BI16, BI32, BO32, B8): New.
786 (B15, B24, CRD32, CRS): New.
787 (CRD, OBF, BFA, CR, CRFS): Use PPC_OPERAND_CR_REG.
788 (DB, IMM20, RD, Rx, ARX, RY, RZ): New.
789 (ARY, SCLSCI8, SCLSCI8N, SE_SD, SE_SDH): New.
790 (SH6_MASK): Use PPC_OPSHIFT_INV.
791 (SI8, UI5, OIMM5, UI7, BO16): New.
792 (VLESIMM, VLENSIMM, VLEUIMM, VLEUIMML): New.
793 (XT6, XA6, XB6, XB6S, XC6): Use PPC_OPSHIFT_INV.
794 (ALLOW8_SPRG): New.
795 (insert_sprg, extract_sprg): Check ALLOW8_SPRG.
796 (OPVUP, OPVUP_MASK OPVUP): New
797 (BD8, BD8_MASK, BD8IO, BD8IO_MASK): New.
798 (EBD8IO, EBD8IO1_MASK, EBD8IO2_MASK, EBD8IO3_MASK): New.
799 (BD15, BD15_MASK, EBD15, EBD15_MASK, EBD15BI, EBD15BI_MASK): New.
800 (BD24,BD24_MASK, C_LK, C_LK_MASK, C, C_MASK): New.
801 (IA16, IA16_MASK, I16A, I16A_MASK, I16L, I16L_MASK): New.
802 (IM7, IM7_MASK, LI20, LI20_MASK, SCI8, SCI8_MASK): New.
803 (SCI8BF, SCI8BF_MASK, SD4, SD4_MASK): New.
804 (SE_IM5, SE_IM5_MASK): New.
805 (SE_R, SE_R_MASK, SE_RR, SE_RR_MASK): New.
806 (EX, EX_MASK, BO16F, BO16T, BO32F, BO32T): New.
807 (BO32DNZ, BO32DZ): New.
808 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW): Include PPC_OPCODE_VLE.
809 (PPCVLE): New.
810 (powerpc_opcodes): Add new VLE instructions. Update existing
811 instruction to include PPCVLE if supported.
812 * ppc-dis.c (ppc_opts): Add vle entry.
813 (get_powerpc_dialect): New function.
814 (powerpc_init_dialect): VLE support.
815 (print_insn_big_powerpc): Call get_powerpc_dialect.
816 (print_insn_little_powerpc): Likewise.
817 (operand_value_powerpc): Handle negative shift counts.
818 (print_insn_powerpc): Handle 2-byte instruction lengths.
819
208a4923
NC		 8202012-05-11 Daniel Richard G. <skunk@iskunk.org>
821
822 PR binutils/14028
823 * configure.in: Invoke ACX_HEADER_STRING.
824 * configure: Regenerate.
825 * config.in: Regenerate.
826 * sysdep.h: If STRINGS_WITH_STRING is defined then include both
827 string.h and strings.h.
828
6750a3a7
NC		 8292012-05-11 Nick Clifton <nickc@redhat.com>
830
831 PR binutils/14006
832 * arm-dis.c (print_insn): Fix detection of instruction mode in
833 files containing multiple executable sections.
834
f6c1a2d5
NC		 8352012-05-03 Sean Keys <skeys@ipdatasys.com>
836
837 * Makefile.in, configure: regenerate
838 * disassemble.c (disassembler): Recognize ARCH_XGATE.
839 * xgate-dis.c (read_memory, print_insn, print_insn_xgate):
840 New functions.
841 * configure.in: Recognize xgate.
842 * xgate-dis.c, xgate-opc.c: New files for support of xgate
843 * Makefile.am (CFILES, ALL_MACHINES): New files for disassembly
844 and opcode generation for xgate.
845
78e98aab
DD		 8462012-04-30 DJ Delorie <dj@redhat.com>
847
848 * rx-decode.opc (MOV): Do not sign-extend immediates which are
849 already the maximum bit size.
850 * rx-decode.c: Regenerate.
851
ec668d69
DM		 8522012-04-27 David S. Miller <davem@davemloft.net>
853
2e52845b
DM		 854 * sparc-dis.c (v9a_asr_reg_names): Add 'cfr'.
855 * sparc-opc.c (sparc_opcodes): Add rd/wr cases for %cfr.
856
58004e23
DM		 857 * sparc-opc.c (sparc_opcodes): Add 'wr X, %pause' and 'pause'.
858 * sparc-dis.c (v9a_asr_reg_names): Add 'pause'.
859
698544e1
DM		 860 * sparc-opc.c (CBCOND): New define.
861 (CBCOND_XCC): Likewise.
862 (cbcond): New helper macro.
863 (sparc_opcodes): Add compare-and-branch instructions.
864
6cda1326
DM		 865 * sparc-dis.c (print_insn_sparc): Handle ')'.
866 * sparc-opc.c (sparc_opcodes): Add crypto instructions.
867
ec668d69
DM		 868 * sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
869 into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
870
2615994e
DM		 8712012-04-12 David S. Miller <davem@davemloft.net>
872
873 * sparc-dis.c (X_DISP10): Define.
874 (print_insn_sparc): Handle '='.
875
5de10af0
MF		 8762012-04-01 Mike Frysinger <vapier@gentoo.org>
877
878 * bfin-dis.c (fmtconst): Replace decimal handling with a single
879 sprintf call and the '*' field width.
880
55a36193
MK		 8812012-03-23 Maxim Kuvyrkov <maxim@codesourcery.com>
882
883 * mips-dis.c (mips_arch_choices): Add entry for Broadcom XLP.
884
d6688282
AM		 8852012-03-16 Alan Modra <amodra@gmail.com>
886
887 * ppc-dis.c (PPC_OPC_SEGS, PPC_OP_TO_SEG): Delete.
888 (powerpc_opcd_indices): Bump array size.
889 (disassemble_init_powerpc): Set powerpc_opcd_indices entries
890 corresponding to unused opcodes to following entry.
891 (lookup_powerpc): New function, extracted and optimised from..
892 (print_insn_powerpc): ..here.
893
b240011a
AM		 8942012-03-15 Alan Modra <amodra@gmail.com>
895 James Lemke <jwlemke@codesourcery.com>
896
897 * disassemble.c (disassemble_init_for_target): Handle ppc init.
898 * ppc-dis.c (private): New var.
899 (powerpc_init_dialect): Don't return calloc failure, instead use
900 private.
901 (PPC_OPCD_SEGS, PPC_OP_TO_SEG): Define.
902 (powerpc_opcd_indices): New array.
903 (disassemble_init_powerpc): New function.
904 (print_insn_big_powerpc): Don't init dialect here.
905 (print_insn_little_powerpc): Likewise.
906 (print_insn_powerpc): Start search using powerpc_opcd_indices.
907
aea77599
AM		 9082012-03-10 Edmar Wienskoski <edmar@freescale.com>
909
910 * ppc-dis.c (ppc_opts): Add entries for "e5500" and "e6500".
911 * ppc-opc.c (insert_ls, TMR, ESYNC, XSYNCLE_MASK): New.
912 (PPCVEC2, PPCTMR, E6500): New short names.
913 (powerpc_opcodes): Add vabsdub, vabsduh, vabsduw, dni, mvidsplt,
914 mviwsplt, icblq., mftmr, mttmr, dcblq., miso, lvexbx, lvexhx,
915 lvexwx, stvexbx, stvexhx, stvexwx, lvepx, lvepxl, stvepx, stvepxl,
916 lvtrx, lvtrxl, lvtlx, lvtlxl, stvfrx, stvfrxl, stvflx, stvflxl,
917 lvswx, lvswxl, stvswx, stvswxl, lvsm mnemonics. Accept LS, ESYNC
918 optional operands on sync instruction for E6500 target.
919
5333187a
AK		 9202012-03-08 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
921
922 * s390-opc.txt: Set instruction type of pku to SS_L2RDRD.
923
a597d2d3
AM		 9242012-02-27 Alan Modra <amodra@gmail.com>
925
926 * mt-dis.c: Regenerate.
927
3f26eb3a
AM		 9282012-02-27 Alan Modra <amodra@gmail.com>
929
930 * v850-opc.c (extract_v8): Rearrange to make it obvious this
931 is the inverse of corresponding insert function.
932 (extract_d22, extract_u9, extract_r4): Likewise.
933 (extract_d9): Correct sign extension.
934 (extract_d16_15): Don't assume "long" is 32 bits, and don't
935 rely on implementation defined behaviour for shift right of
936 signed types.
937 (extract_d16_16, extract_d17_16, extract_i9): Likewise.
938 (extract_d23): Likewise, and correct mask.
939
1f42f8b3
AM		 9402012-02-27 Alan Modra <amodra@gmail.com>
941
942 * crx-dis.c (print_arg): Mask constant to 32 bits.
943 * crx-opc.c (cst4_map): Use int array.
944
cdb06235
AM		 9452012-02-27 Alan Modra <amodra@gmail.com>
946
947 * arc-dis.c (BITS): Don't use shifts to mask off bits.
948 (FIELDD): Sign extend with xor,sub.
949
6f7be959
WL		 9502012-02-25 Walter Lee <walt@tilera.com>
951
952 * tilegx-opc.c: Handle TILEGX_OPC_LD4S_TLS and TILEGX_OPC_LD_TLS.
953 * tilepro-opc.c: Handle TILEPRO_OPC_LW_TLS and
954 TILEPRO_OPC_LW_TLS_SN.
955
82c2def5
L		 9562012-02-21 H.J. Lu <hongjiu.lu@intel.com>
957
958 * i386-opc.h (HLEPrefixNone): New.
959 (HLEPrefixLock): Likewise.
960 (HLEPrefixAny): Likewise.
961 (HLEPrefixRelease): Likewise.
962
42164a71
L		 9632012-02-08 H.J. Lu <hongjiu.lu@intel.com>
964
965 * i386-dis.c (HLE_Fixup1): New.
966 (HLE_Fixup2): Likewise.
967 (HLE_Fixup3): Likewise.
968 (Ebh1): Likewise.
969 (Evh1): Likewise.
970 (Ebh2): Likewise.
971 (Evh2): Likewise.
972 (Ebh3): Likewise.
973 (Evh3): Likewise.
974 (MOD_C6_REG_7): Likewise.
975 (MOD_C7_REG_7): Likewise.
976 (RM_C6_REG_7): Likewise.
977 (RM_C7_REG_7): Likewise.
978 (XACQUIRE_PREFIX): Likewise.
979 (XRELEASE_PREFIX): Likewise.
980 (dis386): Use Ebh1/Evh1 on add, adc, and, btc, btr, bts,
981 cmpxchg, dec, inc, neg, not, or, sbb, sub, xor and xadd. Use
982 Ebh2/Evh2 on xchg. Use Ebh3/Evh3 on mov.
983 (reg_table): Use Ebh1/Evh1 on add, adc, and, dec, inc, neg,
984 not, or, sbb, sub and xor. Use Ebh3/Evh3 on mov. Use
985 MOD_C6_REG_7 and MOD_C7_REG_7.
986 (mod_table): Add MOD_C6_REG_7 and MOD_C7_REG_7.
987 (rm_table): Add RM_C6_REG_7 and RM_C7_REG_7. Add xend and
988 xtest.
989 (prefix_name): Handle XACQUIRE_PREFIX and XRELEASE_PREFIX.
990 (CMPXCHG8B_Fixup): Handle HLE prefix on cmpxchg8b.
991
992 * i386-gen.c (cpu_flag_init): Add CPU_HLE_FLAGS and
993 CPU_RTM_FLAGS.
994 (cpu_flags): Add CpuHLE and CpuRTM.
995 (opcode_modifiers): Add HLEPrefixOk.
996
997 * i386-opc.h (CpuHLE): New.
998 (CpuRTM): Likewise.
999 (HLEPrefixOk): Likewise.
1000 (i386_cpu_flags): Add cpuhle and cpurtm.
1001 (i386_opcode_modifier): Add hleprefixok.
1002
1003 * i386-opc.tbl: Add HLEPrefixOk=3 to mov. Add HLEPrefixOk to
1004 add, adc, and, btc, btr, bts, cmpxchg, dec, inc, neg, not, or,
1005 sbb, sub, xor and xadd. Add HLEPrefixOk=2 to xchg with memory
1006 operand. Add xacquire, xrelease, xabort, xbegin, xend and
1007 xtest.
1008 * i386-init.h: Regenerated.
1009 * i386-tbl.h: Likewise.
1010
21abe33a
DD		 10112012-01-24 DJ Delorie <dj@redhat.com>
1012
1013 * rl78-decode.opc (rl78_decode_opcode): Add NOT1.
1014 * rl78-decode.c: Regenerate.
1015
e20cc039
AM		 10162012-01-17 James Murray <jsm@jsm-net.demon.co.uk>
1017
1018 PR binutils/10173
1019 * cr16-dis.c (print_arg): Test symtab_size not num_symbols.
1020
e143d25c
AS		 10212012-01-17 Andreas Schwab <schwab@linux-m68k.org>
1022
1023 * m68k-opc.c (m68k_opcodes): Fix entries for pmove with BADx/BACx
1024 register and move them after pmove with PSR/PCSR register.
1025
8729a6f6
L		 10262012-01-13 H.J. Lu <hongjiu.lu@intel.com>
1027
1028 * i386-dis.c (mod_table): Add vmfunc.
1029
1030 * i386-gen.c (cpu_flag_init): Add CPU_VMFUNC_FLAGS.
1031 (cpu_flags): CpuVMFUNC.
1032
1033 * i386-opc.h (CpuVMFUNC): New.
1034 (i386_cpu_flags): Add cpuvmfunc.
1035
1036 * i386-opc.tbl: Add vmfunc.
1037 * i386-init.h: Regenerated.
1038 * i386-tbl.h: Likewise.
5011093d 1039
23e1d329 1040For older changes see ChangeLog-2011
252b5132 1041\f
752937aa
NC		 1042Copyright (C) 2012 Free Software Foundation, Inc.
1043
1044Copying and distribution of this file, with or without modification,
1045are permitted in any medium without royalty provided the copyright
1046notice and this notice are preserved.
1047
252b5132 1048Local Variables:
2f6d2f85
NC		 1049mode: change-log
1050left-margin: 8
1051fill-column: 74
252b5132
RH		 1052version-control: never
1053End:
GDB Binutils - Deliverables
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