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[AArch64][SVE 31/32] Add SVE instructions
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
c0890d26
RS		 12016-09-21 Richard Sandiford <richard.sandiford@arm.com>
2
3 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
4 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
5 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
6 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
7 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
8 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
9 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
10 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
11 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
12 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
13 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
14 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
15 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
16 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
17 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
18 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
19 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
20 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
21 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
22 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
23 (OP_SVE_XWU, OP_SVE_XXU): New macros.
24 (aarch64_feature_sve): New variable.
25 (SVE): New macro.
26 (_SVE_INSN): Likewise.
27 (aarch64_opcode_table): Add SVE instructions.
28 * aarch64-opc.h (extract_fields): Declare.
29 * aarch64-opc-2.c: Regenerate.
30 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
31 * aarch64-asm-2.c: Regenerate.
32 * aarch64-dis.c (extract_fields): Make global.
33 (do_misc_decoding): Handle the new SVE aarch64_ops.
34 * aarch64-dis-2.c: Regenerate.
35
116b6019
RS		 362016-09-21 Richard Sandiford <richard.sandiford@arm.com>
37
38 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
39 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
40 aarch64_field_kinds.
41 * aarch64-opc.c (fields): Add corresponding entries.
42 * aarch64-asm.c (aarch64_get_variant): New function.
43 (aarch64_encode_variant_using_iclass): Likewise.
44 (aarch64_opcode_encode): Call it.
45 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
46 (aarch64_opcode_decode): Call it.
47
047cd301
RS		 482016-09-21 Richard Sandiford <richard.sandiford@arm.com>
49
50 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
51 and FP register operands.
52 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
53 (FLD_SVE_Vn): New aarch64_field_kinds.
54 * aarch64-opc.c (fields): Add corresponding entries.
55 (aarch64_print_operand): Handle the new SVE core and FP register
56 operands.
57 * aarch64-opc-2.c: Regenerate.
58 * aarch64-asm-2.c: Likewise.
59 * aarch64-dis-2.c: Likewise.
60
165d4950
RS		 612016-09-21 Richard Sandiford <richard.sandiford@arm.com>
62
63 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
64 immediate operands.
65 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
66 * aarch64-opc.c (fields): Add corresponding entry.
67 (operand_general_constraint_met_p): Handle the new SVE FP immediate
68 operands.
69 (aarch64_print_operand): Likewise.
70 * aarch64-opc-2.c: Regenerate.
71 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
72 (ins_sve_float_zero_one): New inserters.
73 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
74 (aarch64_ins_sve_float_half_two): Likewise.
75 (aarch64_ins_sve_float_zero_one): Likewise.
76 * aarch64-asm-2.c: Regenerate.
77 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
78 (ext_sve_float_zero_one): New extractors.
79 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
80 (aarch64_ext_sve_float_half_two): Likewise.
81 (aarch64_ext_sve_float_zero_one): Likewise.
82 * aarch64-dis-2.c: Regenerate.
83
e950b345
RS		 842016-09-21 Richard Sandiford <richard.sandiford@arm.com>
85
86 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
87 integer immediate operands.
88 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
89 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
90 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
91 * aarch64-opc.c (fields): Add corresponding entries.
92 (operand_general_constraint_met_p): Handle the new SVE integer
93 immediate operands.
94 (aarch64_print_operand): Likewise.
95 (aarch64_sve_dupm_mov_immediate_p): New function.
96 * aarch64-opc-2.c: Regenerate.
97 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
98 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
99 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
100 (aarch64_ins_limm): ...here.
101 (aarch64_ins_inv_limm): New function.
102 (aarch64_ins_sve_aimm): Likewise.
103 (aarch64_ins_sve_asimm): Likewise.
104 (aarch64_ins_sve_limm_mov): Likewise.
105 (aarch64_ins_sve_shlimm): Likewise.
106 (aarch64_ins_sve_shrimm): Likewise.
107 * aarch64-asm-2.c: Regenerate.
108 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
109 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
110 * aarch64-dis.c (decode_limm): New function, split out from...
111 (aarch64_ext_limm): ...here.
112 (aarch64_ext_inv_limm): New function.
113 (decode_sve_aimm): Likewise.
114 (aarch64_ext_sve_aimm): Likewise.
115 (aarch64_ext_sve_asimm): Likewise.
116 (aarch64_ext_sve_limm_mov): Likewise.
117 (aarch64_top_bit): Likewise.
118 (aarch64_ext_sve_shlimm): Likewise.
119 (aarch64_ext_sve_shrimm): Likewise.
120 * aarch64-dis-2.c: Regenerate.
121
98907a70
RS		 1222016-09-21 Richard Sandiford <richard.sandiford@arm.com>
123
124 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
125 operands.
126 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
127 the AARCH64_MOD_MUL_VL entry.
128 (value_aligned_p): Cope with non-power-of-two alignments.
129 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
130 (print_immediate_offset_address): Likewise.
131 (aarch64_print_operand): Likewise.
132 * aarch64-opc-2.c: Regenerate.
133 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
134 (ins_sve_addr_ri_s9xvl): New inserters.
135 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
136 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
137 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
138 * aarch64-asm-2.c: Regenerate.
139 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
140 (ext_sve_addr_ri_s9xvl): New extractors.
141 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
142 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
143 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
144 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
145 * aarch64-dis-2.c: Regenerate.
146
4df068de
RS		 1472016-09-21 Richard Sandiford <richard.sandiford@arm.com>
148
149 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
150 address operands.
151 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
152 (FLD_SVE_xs_22): New aarch64_field_kinds.
153 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
154 (get_operand_specific_data): New function.
155 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
156 FLD_SVE_xs_14 and FLD_SVE_xs_22.
157 (operand_general_constraint_met_p): Handle the new SVE address
158 operands.
159 (sve_reg): New array.
160 (get_addr_sve_reg_name): New function.
161 (aarch64_print_operand): Handle the new SVE address operands.
162 * aarch64-opc-2.c: Regenerate.
163 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
164 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
165 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
166 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
167 (aarch64_ins_sve_addr_rr_lsl): Likewise.
168 (aarch64_ins_sve_addr_rz_xtw): Likewise.
169 (aarch64_ins_sve_addr_zi_u5): Likewise.
170 (aarch64_ins_sve_addr_zz): Likewise.
171 (aarch64_ins_sve_addr_zz_lsl): Likewise.
172 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
173 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
174 * aarch64-asm-2.c: Regenerate.
175 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
176 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
177 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
178 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
179 (aarch64_ext_sve_addr_ri_u6): Likewise.
180 (aarch64_ext_sve_addr_rr_lsl): Likewise.
181 (aarch64_ext_sve_addr_rz_xtw): Likewise.
182 (aarch64_ext_sve_addr_zi_u5): Likewise.
183 (aarch64_ext_sve_addr_zz): Likewise.
184 (aarch64_ext_sve_addr_zz_lsl): Likewise.
185 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
186 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
187 * aarch64-dis-2.c: Regenerate.
188
2442d846
RS		 1892016-09-21 Richard Sandiford <richard.sandiford@arm.com>
190
191 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
192 AARCH64_OPND_SVE_PATTERN_SCALED.
193 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
194 * aarch64-opc.c (fields): Add a corresponding entry.
195 (set_multiplier_out_of_range_error): New function.
196 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
197 (operand_general_constraint_met_p): Handle
198 AARCH64_OPND_SVE_PATTERN_SCALED.
199 (print_register_offset_address): Use PRIi64 to print the
200 shift amount.
201 (aarch64_print_operand): Likewise. Handle
202 AARCH64_OPND_SVE_PATTERN_SCALED.
203 * aarch64-opc-2.c: Regenerate.
204 * aarch64-asm.h (ins_sve_scale): New inserter.
205 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
206 * aarch64-asm-2.c: Regenerate.
207 * aarch64-dis.h (ext_sve_scale): New inserter.
208 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
209 * aarch64-dis-2.c: Regenerate.
210
245d2e3f
RS		 2112016-09-21 Richard Sandiford <richard.sandiford@arm.com>
212
213 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
214 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
215 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
216 (FLD_SVE_prfop): Likewise.
217 * aarch64-opc.c: Include libiberty.h.
218 (aarch64_sve_pattern_array): New variable.
219 (aarch64_sve_prfop_array): Likewise.
220 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
221 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
222 AARCH64_OPND_SVE_PRFOP.
223 * aarch64-asm-2.c: Regenerate.
224 * aarch64-dis-2.c: Likewise.
225 * aarch64-opc-2.c: Likewise.
226
d50c751e
RS		 2272016-09-21 Richard Sandiford <richard.sandiford@arm.com>
228
229 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
230 AARCH64_OPND_QLF_P_[ZM].
231 (aarch64_print_operand): Print /z and /m where appropriate.
232
f11ad6bc
RS		 2332016-09-21 Richard Sandiford <richard.sandiford@arm.com>
234
235 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
236 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
237 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
238 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
239 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
240 * aarch64-opc.c (fields): Add corresponding entries here.
241 (operand_general_constraint_met_p): Check that SVE register lists
242 have the correct length. Check the ranges of SVE index registers.
243 Check for cases where p8-p15 are used in 3-bit predicate fields.
244 (aarch64_print_operand): Handle the new SVE operands.
245 * aarch64-opc-2.c: Regenerate.
246 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
247 * aarch64-asm.c (aarch64_ins_sve_index): New function.
248 (aarch64_ins_sve_reglist): Likewise.
249 * aarch64-asm-2.c: Regenerate.
250 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
251 * aarch64-dis.c (aarch64_ext_sve_index): New function.
252 (aarch64_ext_sve_reglist): Likewise.
253 * aarch64-dis-2.c: Regenerate.
254
0c608d6b
RS		 2552016-09-21 Richard Sandiford <richard.sandiford@arm.com>
256
257 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
258 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
259 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
260 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
261 tied operands.
262
01dbfe4c
RS		 2632016-09-21 Richard Sandiford <richard.sandiford@arm.com>
264
265 * aarch64-opc.c (get_offset_int_reg_name): New function.
266 (print_immediate_offset_address): Likewise.
267 (print_register_offset_address): Take the base and offset
268 registers as parameters.
269 (aarch64_print_operand): Update caller accordingly. Use
270 print_immediate_offset_address.
271
72e9f319
RS		 2722016-09-21 Richard Sandiford <richard.sandiford@arm.com>
273
274 * aarch64-opc.c (BANK): New macro.
275 (R32, R64): Take a register number as argument
276 (int_reg): Use BANK.
277
8a7f0c1b
RS		 2782016-09-21 Richard Sandiford <richard.sandiford@arm.com>
279
280 * aarch64-opc.c (print_register_list): Add a prefix parameter.
281 (aarch64_print_operand): Update accordingly.
282
aa2aa4c6
RS		 2832016-09-21 Richard Sandiford <richard.sandiford@arm.com>
284
285 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
286 for FPIMM.
287 * aarch64-asm.h (ins_fpimm): New inserter.
288 * aarch64-asm.c (aarch64_ins_fpimm): New function.
289 * aarch64-asm-2.c: Regenerate.
290 * aarch64-dis.h (ext_fpimm): New extractor.
291 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
292 (aarch64_ext_fpimm): New function.
293 * aarch64-dis-2.c: Regenerate.
294
b5464a68
RS		 2952016-09-21 Richard Sandiford <richard.sandiford@arm.com>
296
297 * aarch64-asm.c: Include libiberty.h.
298 (insert_fields): New function.
299 (aarch64_ins_imm): Use it.
300 * aarch64-dis.c (extract_fields): New function.
301 (aarch64_ext_imm): Use it.
302
42408347
RS		 3032016-09-21 Richard Sandiford <richard.sandiford@arm.com>
304
305 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
306 with an esize parameter.
307 (operand_general_constraint_met_p): Update accordingly.
308 Fix misindented code.
309 * aarch64-asm.c (aarch64_ins_limm): Update call to
310 aarch64_logical_immediate_p.
311
4989adac
RS		 3122016-09-21 Richard Sandiford <richard.sandiford@arm.com>
313
314 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
315
bd11d5d8
RS		 3162016-09-21 Richard Sandiford <richard.sandiford@arm.com>
317
318 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
319
f807f43d
CZ		 3202016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
321
322 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
323
fd486b63
PB		 3242016-09-14 Peter Bergner <bergner@vnet.ibm.com>
325
326 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
327 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
328 xor3>: Delete mnemonics.
329 <cp_abort>: Rename mnemonic from ...
330 <cpabort>: ...to this.
331 <setb>: Change to a X form instruction.
332 <sync>: Change to 1 operand form.
333 <copy>: Delete mnemonic.
334 <copy_first>: Rename mnemonic from ...
335 <copy>: ...to this.
336 <paste, paste.>: Delete mnemonics.
337 <paste_last>: Rename mnemonic from ...
338 <paste.>: ...to this.
339
dce08442
AK		 3402016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
341
342 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
343
952c3f51
AK		 3442016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
345
346 * s390-mkopc.c (main): Support alternate arch strings.
347
8b71537b
PS		 3482016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
349
350 * s390-opc.txt: Fix kmctr instruction type.
351
5b64d091
L		 3522016-09-07 H.J. Lu <hongjiu.lu@intel.com>
353
354 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
355 * i386-init.h: Regenerated.
356
7763838e
CM		 3572016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
358
359 * opcodes/arc-dis.c (print_insn_arc): Changed.
360
1b8b6532
JM		 3612016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
362
363 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
364 camellia_fl.
365
1a336194
TP		 3662016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
367
368 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
369 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
370 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
371
6b40c462
L		 3722016-08-24 H.J. Lu <hongjiu.lu@intel.com>
373
374 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
375 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
376 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
377 PREFIX_MOD_3_0FAE_REG_4.
378 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
379 PREFIX_MOD_3_0FAE_REG_4.
380 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
381 (cpu_flags): Add CpuPTWRITE.
382 * i386-opc.h (CpuPTWRITE): New.
383 (i386_cpu_flags): Add cpuptwrite.
384 * i386-opc.tbl: Add ptwrite instruction.
385 * i386-init.h: Regenerated.
386 * i386-tbl.h: Likewise.
387
ab548d2d
AK		 3882016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
389
390 * arc-dis.h: Wrap around in extern "C".
391
344bde0a
RS		 3922016-08-23 Richard Sandiford <richard.sandiford@arm.com>
393
394 * aarch64-tbl.h (V8_2_INSN): New macro.
395 (aarch64_opcode_table): Use it.
396
5ce912d8
RS		 3972016-08-23 Richard Sandiford <richard.sandiford@arm.com>
398
399 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
400 CORE_INSN, __FP_INSN and SIMD_INSN.
401
9d30b0bd
RS		 4022016-08-23 Richard Sandiford <richard.sandiford@arm.com>
403
404 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
405 (aarch64_opcode_table): Update uses accordingly.
406
dfdaec14
AJ		 4072016-07-25 Andrew Jenner <andrew@codesourcery.com>
408 Kwok Cheung Yeung <kcy@codesourcery.com>
409
410 opcodes/
411 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
412 'e_cmplwi' to 'e_cmpli' instead.
413 (OPVUPRT, OPVUPRT_MASK): Define.
414 (powerpc_opcodes): Add E200Z4 insns.
415 (vle_opcodes): Add context save/restore insns.
416
7bd374a4
MR		 4172016-07-27 Maciej W. Rozycki <macro@imgtec.com>
418
419 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
420 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
421 "j".
422
db18dbab
GM		 4232016-07-27 Graham Markall <graham.markall@embecosm.com>
424
425 * arc-nps400-tbl.h: Change block comments to GNU format.
426 * arc-dis.c: Add new globals addrtypenames,
427 addrtypenames_max, and addtypeunknown.
428 (get_addrtype): New function.
429 (print_insn_arc): Print colons and address types when
430 required.
431 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
432 define insert and extract functions for all address types.
433 (arc_operands): Add operands for colon and all address
434 types.
435 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
436 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
437 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
438 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
439 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
440 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
441
fecd57f9
L		 4422016-07-21 H.J. Lu <hongjiu.lu@intel.com>
443
444 * configure: Regenerated.
445
37fd5ef3
CZ		 4462016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
447
448 * arc-dis.c (skipclass): New structure.
449 (decodelist): New variable.
450 (is_compatible_p): New function.
451 (new_element): Likewise.
452 (skip_class_p): Likewise.
453 (find_format_from_table): Use skip_class_p function.
454 (find_format): Decode first the extension instructions.
455 (print_insn_arc): Select either ARCEM or ARCHS based on elf
456 e_flags.
457 (parse_option): New function.
458 (parse_disassembler_options): Likewise.
459 (print_arc_disassembler_options): Likewise.
460 (print_insn_arc): Use parse_disassembler_options function. Proper
461 select ARCv2 cpu variant.
462 * disassemble.c (disassembler_usage): Add ARC disassembler
463 options.
464
92281a5b
MR		 4652016-07-13 Maciej W. Rozycki <macro@imgtec.com>
466
467 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
468 annotation from the "nal" entry and reorder it beyond "bltzal".
469
6e7ced37
JM		 4702016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
471
472 * sparc-opc.c (ldtxa): New macro.
473 (sparc_opcodes): Use the macro defined above to add entries for
474 the LDTXA instructions.
475 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
476 instruction.
477
2f831b9a 4782016-07-07 James Bowman <james.bowman@ftdichip.com>
479
480 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
481 and "jmpc".
482
c07315e0
JB		 4832016-07-01 Jan Beulich <jbeulich@suse.com>
484
485 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
486 (movzb): Adjust to cover all permitted suffixes.
487 (movzw): New.
488 * i386-tbl.h: Re-generate.
489
9243100a
JB		 4902016-07-01 Jan Beulich <jbeulich@suse.com>
491
492 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
493 (lgdt): Remove Tbyte from non-64-bit variant.
494 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
495 xsaves64, xsavec64): Remove Disp16.
496 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
497 Remove Disp32S from non-64-bit variants. Remove Disp16 from
498 64-bit variants.
499 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
500 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
501 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
502 64-bit variants.
503 * i386-tbl.h: Re-generate.
504
8325cc63
JB		 5052016-07-01 Jan Beulich <jbeulich@suse.com>
506
507 * i386-opc.tbl (xlat): Remove RepPrefixOk.
508 * i386-tbl.h: Re-generate.
509
838441e4
YQ		 5102016-06-30 Yao Qi <yao.qi@linaro.org>
511
512 * arm-dis.c (print_insn): Fix typo in comment.
513
dab26bf4
RS		 5142016-06-28 Richard Sandiford <richard.sandiford@arm.com>
515
516 * aarch64-opc.c (operand_general_constraint_met_p): Check the
517 range of ldst_elemlist operands.
518 (print_register_list): Use PRIi64 to print the index.
519 (aarch64_print_operand): Likewise.
520
5703197e
TS		 5212016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
522
523 * mcore-opc.h: Remove sentinal.
524 * mcore-dis.c (print_insn_mcore): Adjust.
525
ce440d63
GM		 5262016-06-23 Graham Markall <graham.markall@embecosm.com>
527
528 * arc-opc.c: Correct description of availability of NPS400
529 features.
530
6fd3a02d
PB		 5312016-06-22 Peter Bergner <bergner@vnet.ibm.com>
532
533 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
534 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
535 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
536 xor3>: New mnemonics.
537 <setb>: Change to a VX form instruction.
538 (insert_sh6): Add support for rldixor.
539 (extract_sh6): Likewise.
540
6b477896
TS		 5412016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
542
543 * arc-ext.h: Wrap in extern C.
544
bdd582db
GM		 5452016-06-21 Graham Markall <graham.markall@embecosm.com>
546
547 * arc-dis.c (arc_insn_length): Add comment on instruction length.
548 Use same method for determining instruction length on ARC700 and
549 NPS-400.
550 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
551 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
552 with the NPS400 subclass.
553 * arc-opc.c: Likewise.
554
96074adc
JM		 5552016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
556
557 * sparc-opc.c (rdasr): New macro.
558 (wrasr): Likewise.
559 (rdpr): Likewise.
560 (wrpr): Likewise.
561 (rdhpr): Likewise.
562 (wrhpr): Likewise.
563 (sparc_opcodes): Use the macros above to fix and expand the
564 definition of read/write instructions from/to
565 asr/privileged/hyperprivileged instructions.
566 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
567 %hva_mask_nz. Prefer softint_set and softint_clear over
568 set_softint and clear_softint.
569 (print_insn_sparc): Support %ver in Rd.
570
7a10c22f
JM		 5712016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
572
573 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
574 architecture according to the hardware capabilities they require.
575
4f26fb3a
JM		 5762016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
577
578 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
579 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
580 bfd_mach_sparc_v9{c,d,e,v,m}.
581 * sparc-opc.c (MASK_V9C): Define.
582 (MASK_V9D): Likewise.
583 (MASK_V9E): Likewise.
584 (MASK_V9V): Likewise.
585 (MASK_V9M): Likewise.
586 (v6): Add MASK_V9{C,D,E,V,M}.
587 (v6notlet): Likewise.
588 (v7): Likewise.
589 (v8): Likewise.
590 (v9): Likewise.
591 (v9andleon): Likewise.
592 (v9a): Likewise.
593 (v9b): Likewise.
594 (v9c): Define.
595 (v9d): Likewise.
596 (v9e): Likewise.
597 (v9v): Likewise.
598 (v9m): Likewise.
599 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
600
3ee6e4fb
NC		 6012016-06-15 Nick Clifton <nickc@redhat.com>
602
603 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
604 constants to match expected behaviour.
605 (nds32_parse_opcode): Likewise. Also for whitespace.
606
02f3be19
AB		 6072016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
608
609 * arc-opc.c (extract_rhv1): Extract value from insn.
610
6f9f37ed 6112016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM		 612
613 * arc-nps400-tbl.h: Add ldbit instruction.
614 * arc-opc.c: Add flag classes required for ldbit.
615
6f9f37ed 6162016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM		 617
618 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
619 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
620 support the above instructions.
621
6f9f37ed 6222016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM		 623
624 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
625 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
626 csma, cbba, zncv, and hofs.
627 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
628 support the above instructions.
629
6302016-06-06 Graham Markall <graham.markall@embecosm.com>
631
632 * arc-nps400-tbl.h: Add andab and orab instructions.
633
6342016-06-06 Graham Markall <graham.markall@embecosm.com>
635
636 * arc-nps400-tbl.h: Add addl-like instructions.
637
6382016-06-06 Graham Markall <graham.markall@embecosm.com>
639
640 * arc-nps400-tbl.h: Add mxb and imxb instructions.
641
6422016-06-06 Graham Markall <graham.markall@embecosm.com>
643
644 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
645 instructions.
646
b2cc3f6f
AK		 6472016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
648
649 * s390-dis.c (option_use_insn_len_bits_p): New file scope
650 variable.
651 (init_disasm): Handle new command line option "insnlength".
652 (print_s390_disassembler_options): Mention new option in help
653 output.
654 (print_insn_s390): Use the encoded insn length when dumping
655 unknown instructions.
656
1857fe72
DC		 6572016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
658
659 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
660 to the address and set as symbol address for LDS/ STS immediate operands.
661
14b57c7c
AM		 6622016-06-07 Alan Modra <amodra@gmail.com>
663
664 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
665 cpu for "vle" to e500.
666 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
667 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
668 (PPCNONE): Delete, substitute throughout.
669 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
670 except for major opcode 4 and 31.
671 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
672
4d1464f2
MW		 6732016-06-07 Matthew Wahab <matthew.wahab@arm.com>
674
675 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
676 ARM_EXT_RAS in relevant entries.
677
026122a6
PB		 6782016-06-03 Peter Bergner <bergner@vnet.ibm.com>
679
680 PR binutils/20196
681 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
682 opcodes for E6500.
683
07f5af7d
L		 6842016-06-03 H.J. Lu <hongjiu.lu@intel.com>
685
686 PR binutis/18386
687 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
688 (indir_v_mode): New.
689 Add comments for '&'.
690 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
691 (putop): Handle '&'.
692 (intel_operand_size): Handle indir_v_mode.
693 (OP_E_register): Likewise.
694 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
695 64-bit indirect call/jmp for AMD64.
696 * i386-tbl.h: Regenerated
697
4eb6f892
AB		 6982016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
699
700 * arc-dis.c (struct arc_operand_iterator): New structure.
701 (find_format_from_table): All the old content from find_format,
702 with some minor adjustments, and parameter renaming.
703 (find_format_long_instructions): New function.
704 (find_format): Rewritten.
705 (arc_insn_length): Add LSB parameter.
706 (extract_operand_value): New function.
707 (operand_iterator_next): New function.
708 (print_insn_arc): Use new functions to find opcode, and iterator
709 over operands.
710 * arc-opc.c (insert_nps_3bit_dst_short): New function.
711 (extract_nps_3bit_dst_short): New function.
712 (insert_nps_3bit_src2_short): New function.
713 (extract_nps_3bit_src2_short): New function.
714 (insert_nps_bitop1_size): New function.
715 (extract_nps_bitop1_size): New function.
716 (insert_nps_bitop2_size): New function.
717 (extract_nps_bitop2_size): New function.
718 (insert_nps_bitop_mod4_msb): New function.
719 (extract_nps_bitop_mod4_msb): New function.
720 (insert_nps_bitop_mod4_lsb): New function.
721 (extract_nps_bitop_mod4_lsb): New function.
722 (insert_nps_bitop_dst_pos3_pos4): New function.
723 (extract_nps_bitop_dst_pos3_pos4): New function.
724 (insert_nps_bitop_ins_ext): New function.
725 (extract_nps_bitop_ins_ext): New function.
726 (arc_operands): Add new operands.
727 (arc_long_opcodes): New global array.
728 (arc_num_long_opcodes): New global.
729 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
730
1fe0971e
TS		 7312016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
732
733 * nds32-asm.h: Add extern "C".
734 * sh-opc.h: Likewise.
735
315f180f
GM		 7362016-06-01 Graham Markall <graham.markall@embecosm.com>
737
738 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
739 0,b,limm to the rflt instruction.
740
a2b5fccc
TS		 7412016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
742
743 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
744 constant.
745
0cbd0046
L		 7462016-05-29 H.J. Lu <hongjiu.lu@intel.com>
747
748 PR gas/20145
749 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
750 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
751 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
752 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
753 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
754 * i386-init.h: Regenerated.
755
1848e567
L		 7562016-05-27 H.J. Lu <hongjiu.lu@intel.com>
757
758 PR gas/20145
759 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
760 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
761 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
762 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
763 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
764 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
765 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
766 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
767 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
768 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
769 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
770 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
771 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
772 CpuRegMask for AVX512.
773 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
774 and CpuRegMask.
775 (set_bitfield_from_cpu_flag_init): New function.
776 (set_bitfield): Remove const on f. Call
777 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
778 * i386-opc.h (CpuRegMMX): New.
779 (CpuRegXMM): Likewise.
780 (CpuRegYMM): Likewise.
781 (CpuRegZMM): Likewise.
782 (CpuRegMask): Likewise.
783 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
784 and cpuregmask.
785 * i386-init.h: Regenerated.
786 * i386-tbl.h: Likewise.
787
e92bae62
L		 7882016-05-27 H.J. Lu <hongjiu.lu@intel.com>
789
790 PR gas/20154
791 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
792 (opcode_modifiers): Add AMD64 and Intel64.
793 (main): Properly verify CpuMax.
794 * i386-opc.h (CpuAMD64): Removed.
795 (CpuIntel64): Likewise.
796 (CpuMax): Set to CpuNo64.
797 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
798 (AMD64): New.
799 (Intel64): Likewise.
800 (i386_opcode_modifier): Add amd64 and intel64.
801 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
802 on call and jmp.
803 * i386-init.h: Regenerated.
804 * i386-tbl.h: Likewise.
805
e89c5eaa
L		 8062016-05-27 H.J. Lu <hongjiu.lu@intel.com>
807
808 PR gas/20154
809 * i386-gen.c (main): Fail if CpuMax is incorrect.
810 * i386-opc.h (CpuMax): Set to CpuIntel64.
811 * i386-tbl.h: Regenerated.
812
77d66e7b
NC		 8132016-05-27 Nick Clifton <nickc@redhat.com>
814
815 PR target/20150
816 * msp430-dis.c (msp430dis_read_two_bytes): New function.
817 (msp430dis_opcode_unsigned): New function.
818 (msp430dis_opcode_signed): New function.
819 (msp430_singleoperand): Use the new opcode reading functions.
820 Only disassenmble bytes if they were successfully read.
821 (msp430_doubleoperand): Likewise.
822 (msp430_branchinstr): Likewise.
823 (msp430x_callx_instr): Likewise.
824 (print_insn_msp430): Check that it is safe to read bytes before
825 attempting disassembly. Use the new opcode reading functions.
826
19dfcc89
PB		 8272016-05-26 Peter Bergner <bergner@vnet.ibm.com>
828
829 * ppc-opc.c (CY): New define. Document it.
830 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
831
f3ad7637
L		 8322016-05-25 H.J. Lu <hongjiu.lu@intel.com>
833
834 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
835 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
836 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
837 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
838 CPU_ANY_AVX_FLAGS.
839 * i386-init.h: Regenerated.
840
f1360d58
L		 8412016-05-25 H.J. Lu <hongjiu.lu@intel.com>
842
843 PR gas/20141
844 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
845 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
846 * i386-init.h: Regenerated.
847
293f5f65
L		 8482016-05-25 H.J. Lu <hongjiu.lu@intel.com>
849
850 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
851 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
852 * i386-init.h: Regenerated.
853
d9eca1df
CZ		 8542016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
855
856 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
857 information.
858 (print_insn_arc): Set insn_type information.
859 * arc-opc.c (C_CC): Add F_CLASS_COND.
860 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
861 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
862 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
863 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
864 (brne, brne_s, jeq_s, jne_s): Likewise.
865
87789e08
CZ		 8662016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
867
868 * arc-tbl.h (neg): New instruction variant.
869
c810e0b8
CZ		 8702016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
871
872 * arc-dis.c (find_format, find_format, get_auxreg)
873 (print_insn_arc): Changed.
874 * arc-ext.h (INSERT_XOP): Likewise.
875
3d207518
TS		 8762016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
877
878 * tic54x-dis.c (sprint_mmr): Adjust.
879 * tic54x-opc.c: Likewise.
880
514e58b7
AM		 8812016-05-19 Alan Modra <amodra@gmail.com>
882
883 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
884
e43de63c
AM		 8852016-05-19 Alan Modra <amodra@gmail.com>
886
887 * ppc-opc.c: Formatting.
888 (NSISIGNOPT): Define.
889 (powerpc_opcodes <subis>): Use NSISIGNOPT.
890
1401d2fe
MR		 8912016-05-18 Maciej W. Rozycki <macro@imgtec.com>
892
893 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
894 replacing references to `micromips_ase' throughout.
895 (_print_insn_mips): Don't use file-level microMIPS annotation to
896 determine the disassembly mode with the symbol table.
897
1178da44
PB		 8982016-05-13 Peter Bergner <bergner@vnet.ibm.com>
899
900 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
901
8f4f9071
MF		 9022016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
903
904 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
905 mips64r6.
906 * mips-opc.c (D34): New macro.
907 (mips_builtin_opcodes): Define bposge32c for DSPr3.
908
8bc52696
AF		 9092016-05-10 Alexander Fomin <alexander.fomin@intel.com>
910
911 * i386-dis.c (prefix_table): Add RDPID instruction.
912 * i386-gen.c (cpu_flag_init): Add RDPID flag.
913 (cpu_flags): Add RDPID bitfield.
914 * i386-opc.h (enum): Add RDPID element.
915 (i386_cpu_flags): Add RDPID field.
916 * i386-opc.tbl: Add RDPID instruction.
917 * i386-init.h: Regenerate.
918 * i386-tbl.h: Regenerate.
919
39d911fc
TP		 9202016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
921
922 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
923 branch type of a symbol.
924 (print_insn): Likewise.
925
16a1fa25
TP		 9262016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
927
928 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
929 Mainline Security Extensions instructions.
930 (thumb_opcodes): Add entries for narrow ARMv8-M Security
931 Extensions instructions.
932 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
933 instructions.
934 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
935 special registers.
936
d751b79e
JM		 9372016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
938
939 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
940
945e0f82
CZ		 9412016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
942
943 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
944 (arcExtMap_genOpcode): Likewise.
945 * arc-opc.c (arg_32bit_rc): Define new variable.
946 (arg_32bit_u6): Likewise.
947 (arg_32bit_limm): Likewise.
948
20f55f38
SN		 9492016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
950
951 * aarch64-gen.c (VERIFIER): Define.
952 * aarch64-opc.c (VERIFIER): Define.
953 (verify_ldpsw): Use static linkage.
954 * aarch64-opc.h (verify_ldpsw): Remove.
955 * aarch64-tbl.h: Use VERIFIER for verifiers.
956
4bd13cde
NC		 9572016-04-28 Nick Clifton <nickc@redhat.com>
958
959 PR target/19722
960 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
961 * aarch64-opc.c (verify_ldpsw): New function.
962 * aarch64-opc.h (verify_ldpsw): New prototype.
963 * aarch64-tbl.h: Add initialiser for verifier field.
964 (LDPSW): Set verifier to verify_ldpsw.
965
c0f92bf9
L		 9662016-04-23 H.J. Lu <hongjiu.lu@intel.com>
967
968 PR binutils/19983
969 PR binutils/19984
970 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
971 smaller than address size.
972
e6c7cdec
TS		 9732016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
974
975 * alpha-dis.c: Regenerate.
976 * crx-dis.c: Likewise.
977 * disassemble.c: Likewise.
978 * epiphany-opc.c: Likewise.
979 * fr30-opc.c: Likewise.
980 * frv-opc.c: Likewise.
981 * ip2k-opc.c: Likewise.
982 * iq2000-opc.c: Likewise.
983 * lm32-opc.c: Likewise.
984 * lm32-opinst.c: Likewise.
985 * m32c-opc.c: Likewise.
986 * m32r-opc.c: Likewise.
987 * m32r-opinst.c: Likewise.
988 * mep-opc.c: Likewise.
989 * mt-opc.c: Likewise.
990 * or1k-opc.c: Likewise.
991 * or1k-opinst.c: Likewise.
992 * tic80-opc.c: Likewise.
993 * xc16x-opc.c: Likewise.
994 * xstormy16-opc.c: Likewise.
995
537aefaf
AB		 9962016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
997
998 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
999 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1000 calcsd, and calcxd instructions.
1001 * arc-opc.c (insert_nps_bitop_size): Delete.
1002 (extract_nps_bitop_size): Delete.
1003 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1004 (extract_nps_qcmp_m3): Define.
1005 (extract_nps_qcmp_m2): Define.
1006 (extract_nps_qcmp_m1): Define.
1007 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1008 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1009 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1010 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1011 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1012 NPS_QCMP_M3.
1013
c8f785f2
AB		 10142016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1015
1016 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1017
6fd8e7c2
L		 10182016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1019
1020 * Makefile.in: Regenerated with automake 1.11.6.
1021 * aclocal.m4: Likewise.
1022
4b0c052e
AB		 10232016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1024
1025 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1026 instructions.
1027 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1028 (extract_nps_cmem_uimm16): New function.
1029 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1030
cb040366
AB		 10312016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1032
1033 * arc-dis.c (arc_insn_length): New function.
1034 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1035 (find_format): Change insnLen parameter to unsigned.
1036
accc0180
NC		 10372016-04-13 Nick Clifton <nickc@redhat.com>
1038
1039 PR target/19937
1040 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1041 the LD.B and LD.BU instructions.
1042
f36e33da
CZ		 10432016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1044
1045 * arc-dis.c (find_format): Check for extension flags.
1046 (print_flags): New function.
1047 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1048 .extAuxRegister.
1049 * arc-ext.c (arcExtMap_coreRegName): Use
1050 LAST_EXTENSION_CORE_REGISTER.
1051 (arcExtMap_coreReadWrite): Likewise.
1052 (dump_ARC_extmap): Update printing.
1053 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1054 (arc_aux_regs): Add cpu field.
1055 * arc-regs.h: Add cpu field, lower case name aux registers.
1056
1c2e355e
CZ		 10572016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1058
1059 * arc-tbl.h: Add rtsc, sleep with no arguments.
1060
b99747ae
CZ		 10612016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1062
1063 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1064 Initialize.
1065 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1066 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1067 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1068 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1069 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1070 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1071 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1072 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1073 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1074 (arc_opcode arc_opcodes): Null terminate the array.
1075 (arc_num_opcodes): Remove.
1076 * arc-ext.h (INSERT_XOP): Define.
1077 (extInstruction_t): Likewise.
1078 (arcExtMap_instName): Delete.
1079 (arcExtMap_insn): New function.
1080 (arcExtMap_genOpcode): Likewise.
1081 * arc-ext.c (ExtInstruction): Remove.
1082 (create_map): Zero initialize instruction fields.
1083 (arcExtMap_instName): Remove.
1084 (arcExtMap_insn): New function.
1085 (dump_ARC_extmap): More info while debuging.
1086 (arcExtMap_genOpcode): New function.
1087 * arc-dis.c (find_format): New function.
1088 (print_insn_arc): Use find_format.
1089 (arc_get_disassembler): Enable dump_ARC_extmap only when
1090 debugging.
1091
92708cec
MR		 10922016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1093
1094 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1095 instruction bits out.
1096
a42a4f84
AB		 10972016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1098
1099 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1100 * arc-opc.c (arc_flag_operands): Add new flags.
1101 (arc_flag_classes): Add new classes.
1102
1328504b
AB		 11032016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1104
1105 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1106
820f03ff
AB		 11072016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1108
1109 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1110 encode1, rflt, crc16, and crc32 instructions.
1111 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1112 (arc_flag_classes): Add C_NPS_R.
1113 (insert_nps_bitop_size_2b): New function.
1114 (extract_nps_bitop_size_2b): Likewise.
1115 (insert_nps_bitop_uimm8): Likewise.
1116 (extract_nps_bitop_uimm8): Likewise.
1117 (arc_operands): Add new operand entries.
1118
8ddf6b2a
CZ		 11192016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1120
b99747ae
CZ		 1121 * arc-regs.h: Add a new subclass field. Add double assist
1122 accumulator register values.
1123 * arc-tbl.h: Use DPA subclass to mark the double assist
1124 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1125 * arc-opc.c (RSP): Define instead of SP.
1126 (arc_aux_regs): Add the subclass field.
8ddf6b2a 1127
589a7d88
JW		 11282016-04-05 Jiong Wang <jiong.wang@arm.com>
1129
1130 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1131
0a191de9 11322016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 1133
1134 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1135 NPS_R_SRC1.
1136
0a106562
AB		 11372016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1138
1139 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1140 issues. No functional changes.
1141
bd05ac5f
CZ		 11422016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1143
b99747ae
CZ		 1144 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1145 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1146 (RTT): Remove duplicate.
1147 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1148 (PCT_CONFIG*): Remove.
1149 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 1150
9885948f
CZ		 11512016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1152
b99747ae 1153 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 1154
f2dd8838
CZ		 11552016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1156
b99747ae
CZ		 1157 * arc-tbl.h (invld07): Remove.
1158 * arc-ext-tbl.h: New file.
1159 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1160 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 1161
0d2f91fe
JK		 11622016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1163
1164 Fix -Wstack-usage warnings.
1165 * aarch64-dis.c (print_operands): Substitute size.
1166 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1167
a6b71f42
JM		 11682016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1169
1170 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1171 to get a proper diagnostic when an invalid ASR register is used.
1172
9780e045
NC		 11732016-03-22 Nick Clifton <nickc@redhat.com>
1174
1175 * configure: Regenerate.
1176
e23e8ebe
AB		 11772016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1178
1179 * arc-nps400-tbl.h: New file.
1180 * arc-opc.c: Add top level comment.
1181 (insert_nps_3bit_dst): New function.
1182 (extract_nps_3bit_dst): New function.
1183 (insert_nps_3bit_src2): New function.
1184 (extract_nps_3bit_src2): New function.
1185 (insert_nps_bitop_size): New function.
1186 (extract_nps_bitop_size): New function.
1187 (arc_flag_operands): Add nps400 entries.
1188 (arc_flag_classes): Add nps400 entries.
1189 (arc_operands): Add nps400 entries.
1190 (arc_opcodes): Add nps400 include.
1191
1ae8ab47
AB		 11922016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1193
1194 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1195 the new class enum values.
1196
8699fc3e
AB		 11972016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1198
1199 * arc-dis.c (print_insn_arc): Handle nps400.
1200
24740d83
AB		 12012016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1202
1203 * arc-opc.c (BASE): Delete.
1204
8678914f
NC		 12052016-03-18 Nick Clifton <nickc@redhat.com>
1206
1207 PR target/19721
1208 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1209 of MOV insn that aliases an ORR insn.
1210
cc933301
JW		 12112016-03-16 Jiong Wang <jiong.wang@arm.com>
1212
1213 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1214
f86f5863
TS		 12152016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1216
1217 * mcore-opc.h: Add const qualifiers.
1218 * microblaze-opc.h (struct op_code_struct): Likewise.
1219 * sh-opc.h: Likewise.
1220 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1221 (tic4x_print_op): Likewise.
1222
62de1c63
AM		 12232016-03-02 Alan Modra <amodra@gmail.com>
1224
d11698cd 1225 * or1k-desc.h: Regenerate.
62de1c63 1226 * fr30-ibld.c: Regenerate.
c697cf0b 1227 * rl78-decode.c: Regenerate.
62de1c63 1228
020efce5
NC		 12292016-03-01 Nick Clifton <nickc@redhat.com>
1230
1231 PR target/19747
1232 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1233
b0c11777
RL		 12342016-02-24 Renlin Li <renlin.li@arm.com>
1235
1236 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1237 (print_insn_coprocessor): Support fp16 instructions.
1238
3e309328
RL		 12392016-02-24 Renlin Li <renlin.li@arm.com>
1240
1241 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1242 vminnm, vrint(mpna).
1243
8afc7bea
RL		 12442016-02-24 Renlin Li <renlin.li@arm.com>
1245
1246 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1247 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1248
4fd7268a
L		 12492016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1250
1251 * i386-dis.c (print_insn): Parenthesize expression to prevent
1252 truncated addresses.
1253 (OP_J): Likewise.
1254
4670103e
CZ		 12552016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1256 Janek van Oirschot <jvanoirs@synopsys.com>
1257
b99747ae
CZ		 1258 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1259 variable.
4670103e 1260
c1d9289f
NC		 12612016-02-04 Nick Clifton <nickc@redhat.com>
1262
1263 PR target/19561
1264 * msp430-dis.c (print_insn_msp430): Add a special case for
1265 decoding an RRC instruction with the ZC bit set in the extension
1266 word.
1267
a143b004
AB		 12682016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1269
1270 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1271 * epiphany-ibld.c: Regenerate.
1272 * fr30-ibld.c: Regenerate.
1273 * frv-ibld.c: Regenerate.
1274 * ip2k-ibld.c: Regenerate.
1275 * iq2000-ibld.c: Regenerate.
1276 * lm32-ibld.c: Regenerate.
1277 * m32c-ibld.c: Regenerate.
1278 * m32r-ibld.c: Regenerate.
1279 * mep-ibld.c: Regenerate.
1280 * mt-ibld.c: Regenerate.
1281 * or1k-ibld.c: Regenerate.
1282 * xc16x-ibld.c: Regenerate.
1283 * xstormy16-ibld.c: Regenerate.
1284
b89807c6
AB		 12852016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1286
1287 * epiphany-dis.c: Regenerated from latest cpu files.
1288
d8c823c8
MM		 12892016-02-01 Michael McConville <mmcco@mykolab.com>
1290
1291 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1292 test bit.
1293
5bc5ae88
RL		 12942016-01-25 Renlin Li <renlin.li@arm.com>
1295
1296 * arm-dis.c (mapping_symbol_for_insn): New function.
1297 (find_ifthen_state): Call mapping_symbol_for_insn().
1298
0bff6e2d
MW		 12992016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1300
1301 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1302 of MSR UAO immediate operand.
1303
100b4f2e
MR		 13042016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1305
1306 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1307 instruction support.
1308
5c14705f
AM		 13092016-01-17 Alan Modra <amodra@gmail.com>
1310
1311 * configure: Regenerate.
1312
4d82fe66
NC		 13132016-01-14 Nick Clifton <nickc@redhat.com>
1314
1315 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1316 instructions that can support stack pointer operations.
1317 * rl78-decode.c: Regenerate.
1318 * rl78-dis.c: Fix display of stack pointer in MOVW based
1319 instructions.
1320
651657fa
MW		 13212016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1322
1323 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1324 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1325 erxtatus_el1 and erxaddr_el1.
1326
105bde57
MW		 13272016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1328
1329 * arm-dis.c (arm_opcodes): Add "esb".
1330 (thumb_opcodes): Likewise.
1331
afa8d405
PB		 13322016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1333
1334 * ppc-opc.c <xscmpnedp>: Delete.
1335 <xvcmpnedp>: Likewise.
1336 <xvcmpnedp.>: Likewise.
1337 <xvcmpnesp>: Likewise.
1338 <xvcmpnesp.>: Likewise.
1339
83c3256e
AS		 13402016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1341
1342 PR gas/13050
1343 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1344 addition to ISA_A.
1345
6f2750fe
AM		 13462016-01-01 Alan Modra <amodra@gmail.com>
1347
1348 Update year range in copyright notice of all files.
1349
3499769a
AM		 1350For older changes see ChangeLog-2015
1351\f
1352Copyright (C) 2016 Free Software Foundation, Inc.
1353
1354Copying and distribution of this file, with or without modification,
1355are permitted in any medium without royalty provided the copyright
1356notice and this notice are preserved.
1357
1358Local Variables:
1359mode: change-log
1360left-margin: 8
1361fill-column: 74
1362version-control: never
1363End:
GDB Binutils - Deliverables
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