[deliverable/binutils-gdb.git] / opcodes / ChangeLog

2013-02-15  Markos Chandras  <markos.chandras@imgtec.com>

	* metag-dis.c: Initialize outf->bytes_per_chunk to 4
	which also makes the disassembler output be in little
	endian like it should be.

2013-02-14  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
	fields to NULL.
	(aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.

2013-02-13  Maciej W. Rozycki  <macro@codesourcery.com>

	* mips-dis.c (is_compressed_mode_p): Only match symbols from the
	section disassembled.

2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* arm-dis.c: Update strht pattern.

2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>

	* mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
	single-float.  Disable ll, lld, sc and scd for EE.  Disable the
	trunc.w.s macro for EE.

2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
            Andrew Jenner <andrew@codesourcery.com>

	Based on patches from Altera Corporation.

	* Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
	nios2-opc.c.
	* Makefile.in: Regenerated.
	* configure.in: Add case for bfd_nios2_arch.
	* configure: Regenerated.
	* disassemble.c (ARCH_nios2): Define.
	(disassembler): Add case for bfd_arch_nios2.
	* nios2-dis.c: New file.
	* nios2-opc.c: New file.

2013-02-04  Alan Modra  <amodra@gmail.com>

	* po/POTFILES.in: Regenerate.
	* rl78-decode.c: Regenerate.
	* rx-decode.c: Regenerate.

2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
	ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
	* aarch64-asm.c (convert_xtl_to_shll): New function.
	(convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	calling convert_xtl_to_shll.
	* aarch64-dis.c (convert_shll_to_xtl): New function.
	(convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	calling convert_shll_to_xtl.
	* aarch64-gen.c: Update copyright year.
	* aarch64-asm-2.c: Re-generate.
	* aarch64-dis-2.c: Re-generate.
	* aarch64-opc-2.c: Re-generate.

2013-01-24  Nick Clifton  <nickc@redhat.com>

	* v850-dis.c: Add support for e3v5 architecture.
	* v850-opc.c: Likewise.

2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
	* aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
	* aarch64-opc.c (operand_general_constraint_met_p): For
	AARCH64_MOD_LSL, move the range check on the shift amount before the
	alignment check; change to call set_sft_amount_out_of_range_error
	instead of set_imm_out_of_range_error.
	* aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
	(aarch64_opcode_table): Remove the OP enumerator from the asimdimm
	8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
	SIMD_IMM_SFT.

2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2013-01-15  Nick Clifton  <nickc@redhat.com>

	* v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
	values.
	* v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.

2013-01-14  Will Newton <will.newton@imgtec.com>

	* metag-dis.c (REG_WIDTH): Increase to 64.

2013-01-10  Peter Bergner <bergner@vnet.ibm.com>

	* ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
	* ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
	XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
	(SH6): Update.
	<"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
	"tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
	"treclaim.", "tsr.">: Add POWER8 HTM opcodes.
	<"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.

2013-01-10  Will Newton <will.newton@imgtec.com>

	* Makefile.am: Add Meta.
	* configure.in: Add Meta.
	* disassemble.c: Add Meta support.
	* metag-dis.c: New file.
	* Makefile.in: Regenerate.
	* configure: Regenerate.

2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>

	* cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
	(match_opcode): Rename to cr16_match_opcode.

2013-01-04  Juergen Urban <JuergenUrban@gmx.de>

	* mips-dis.c: Add names for CP0 registers of r5900.
	* mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
	instructions sq and lq.
	Add support for MIPS r5900 CPU.
	Add support for 128 bit MMI (Multimedia Instructions).
	Add support for EE instructions (Emotion Engine).
	Disable unsupported floating point instructions (64 bit and
	undefined compare operations).
	Enable instructions of MIPS ISA IV which are supported by r5900.
	Disable 64 bit co processor instructions.
	Disable 64 bit multiplication and division instructions.
	Disable instructions for co-processor 2 and 3, because these are
	not supported (preparation for later VU0 support (Vector Unit)).
	Disable cvt.w.s because this behaves like trunc.w.s and the
	correct execution can't be ensured on r5900.
	Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
	will confuse less developers and compilers.

2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-opc.c (aarch64_print_operand): Change to print
	AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
	in comment.
	* aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
	from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
	OP_MOV_IMM_WIDE.

2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
	PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.

2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (process_copyright): Update copyright year to 2013.

2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>

	* cr16-dis.c (match_opcode,make_instruction): Remove static
	declaration.
	(dwordU,wordU): Moved typedefs to opcode/cr16.h
	(cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.

For older changes see ChangeLog-2012
\f
Copyright (C) 2013 Free Software Foundation, Inc.

Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.

Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
Commit	Line	Data
9d1df426 NC	1	2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
	2
	3	* metag-dis.c: Initialize outf->bytes_per_chunk to 4
	4	which also makes the disassembler output be in little
	5	endian like it should be.
	6
a1ccaec9 YZ	7	2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
	8
	9	* aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
	10	fields to NULL.
	11	(aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
	12
ef068ef4	13	2013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
5417f71e MR	14
	15	* mips-dis.c (is_compressed_mode_p): Only match symbols from the
	16	section disassembled.
	17
6fe6ded9 RE	18	2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
	19
	20	* arm-dis.c: Update strht pattern.
	21
0aa27725 RS	22	2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
	23
	24	* mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
	25	single-float. Disable ll, lld, sc and scd for EE. Disable the
	26	trunc.w.s macro for EE.
	27
36591ba1 SL	28	2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
	29	Andrew Jenner <andrew@codesourcery.com>
	30
	31	Based on patches from Altera Corporation.
	32
	33	* Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
	34	nios2-opc.c.
	35	* Makefile.in: Regenerated.
	36	* configure.in: Add case for bfd_nios2_arch.
	37	* configure: Regenerated.
	38	* disassemble.c (ARCH_nios2): Define.
	39	(disassembler): Add case for bfd_arch_nios2.
	40	* nios2-dis.c: New file.
	41	* nios2-opc.c: New file.
	42
545093a4 AM	43	2013-02-04 Alan Modra <amodra@gmail.com>
	44
	45	* po/POTFILES.in: Regenerate.
	46	* rl78-decode.c: Regenerate.
	47	* rx-decode.c: Regenerate.
	48
e30181a5 YZ	49	2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
	50
	51	* aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
	52	ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
	53	* aarch64-asm.c (convert_xtl_to_shll): New function.
	54	(convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	55	calling convert_xtl_to_shll.
	56	* aarch64-dis.c (convert_shll_to_xtl): New function.
	57	(convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	58	calling convert_shll_to_xtl.
	59	* aarch64-gen.c: Update copyright year.
	60	* aarch64-asm-2.c: Re-generate.
	61	* aarch64-dis-2.c: Re-generate.
	62	* aarch64-opc-2.c: Re-generate.
	63
78c8d46c NC	64	2013-01-24 Nick Clifton <nickc@redhat.com>
	65
	66	* v850-dis.c: Add support for e3v5 architecture.
	67	* v850-opc.c: Likewise.
	68
f5555712 YZ	69	2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
	70
	71	* aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
	72	* aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
	73	* aarch64-opc.c (operand_general_constraint_met_p): For
78c8d46c	74	AARCH64_MOD_LSL, move the range check on the shift amount before the
f5555712 YZ	75	alignment check; change to call set_sft_amount_out_of_range_error
	76	instead of set_imm_out_of_range_error.
	77	* aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
	78	(aarch64_opcode_table): Remove the OP enumerator from the asimdimm
	79	8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
	80	SIMD_IMM_SFT.
	81
2f81ff92 L	82	2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
	83
	84	* i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
	85
	86	* i386-init.h: Regenerated.
	87	* i386-tbl.h: Likewise.
	88
dd42f060 NC	89	2013-01-15 Nick Clifton <nickc@redhat.com>
	90
	91	* v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
	92	values.
	93	* v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
	94
a4533ed8 NC	95	2013-01-14 Will Newton <will.newton@imgtec.com>
	96
	97	* metag-dis.c (REG_WIDTH): Increase to 64.
	98
5817ffd1 PB	99	2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
	100
	101	* ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
	102	* ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
	103	XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
	104	(SH6): Update.
	105	<"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
	106	"tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
	107	"treclaim.", "tsr.">: Add POWER8 HTM opcodes.
	108	<"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
	109
a3c62988 NC	110	2013-01-10 Will Newton <will.newton@imgtec.com>
	111
	112	* Makefile.am: Add Meta.
	113	* configure.in: Add Meta.
	114	* disassemble.c: Add Meta support.
	115	* metag-dis.c: New file.
	116	* Makefile.in: Regenerate.
	117	* configure: Regenerate.
	118
73335eae NC	119	2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
	120
	121	* cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
	122	(match_opcode): Rename to cr16_match_opcode.
	123
e407c74b NC	124	2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
	125
	126	* mips-dis.c: Add names for CP0 registers of r5900.
	127	* mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
	128	instructions sq and lq.
	129	Add support for MIPS r5900 CPU.
	130	Add support for 128 bit MMI (Multimedia Instructions).
	131	Add support for EE instructions (Emotion Engine).
	132	Disable unsupported floating point instructions (64 bit and
	133	undefined compare operations).
	134	Enable instructions of MIPS ISA IV which are supported by r5900.
	135	Disable 64 bit co processor instructions.
	136	Disable 64 bit multiplication and division instructions.
	137	Disable instructions for co-processor 2 and 3, because these are
	138	not supported (preparation for later VU0 support (Vector Unit)).
	139	Disable cvt.w.s because this behaves like trunc.w.s and the
	140	correct execution can't be ensured on r5900.
	141	Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
	142	will confuse less developers and compilers.
	143
a32c3ff8 NC	144	2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
a32c3ff8 NC	145
fb098a1e YZ	146	* aarch64-opc.c (aarch64_print_operand): Change to print
	147	AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
	148	in comment.
	149	* aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
	150	from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
	151	OP_MOV_IMM_WIDE.
	152
	153	2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
	154
	155	* aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
	156	PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
a32c3ff8	157
62658407 L	158	2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
	159
	160	* i386-gen.c (process_copyright): Update copyright year to 2013.
	161
bab4becb	162	2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
5bf135a7	163
bab4becb NC	164	* cr16-dis.c (match_opcode,make_instruction): Remove static
	165	declaration.
	166	(dwordU,wordU): Moved typedefs to opcode/cr16.h
	167	(cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
5bf135a7	168
bab4becb	169	For older changes see ChangeLog-2012
252b5132	170	\f
bab4becb	171	Copyright (C) 2013 Free Software Foundation, Inc.
752937aa NC	172
	173	Copying and distribution of this file, with or without modification,
	174	are permitted in any medium without royalty provided the copyright
	175	notice and this notice are preserved.
	176
252b5132	177	Local Variables:
2f6d2f85 NC	178	mode: change-log
	179	left-margin: 8
	180	fill-column: 74
252b5132 RH	181	version-control: never
252b5132 RH	182	End: