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PR gdb/21574: Mention $SHELL and startup-with-shell on "help run"
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
e64519d1
NC		 12017-06-14 Nick Clifton <nickc@redhat.com>
2
3 PR binutils/21576
4 * score7-dis.c (score_opcodes): Add sentinel.
5
6394c606
YQ		 62017-06-14 Yao Qi <yao.qi@linaro.org>
7
8 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
9 * arm-dis.c: Likewise.
10 * ia64-dis.c: Likewise.
11 * mips-dis.c: Likewise.
12 * spu-dis.c: Likewise.
13 * disassemble.h (print_insn_aarch64): New declaration, moved from
14 include/dis-asm.h.
15 (print_insn_big_arm, print_insn_big_mips): Likewise.
16 (print_insn_i386, print_insn_ia64): Likewise.
17 (print_insn_little_arm, print_insn_little_mips): Likewise.
18
db5fa770
NC		 192017-06-14 Nick Clifton <nickc@redhat.com>
20
21 PR binutils/21587
22 * rx-decode.opc: Include libiberty.h
23 (GET_SCALE): New macro - validates access to SCALE array.
24 (GET_PSCALE): New macro - validates access to PSCALE array.
25 (DIs, SIs, S2Is, rx_disp): Use new macros.
26 * rx-decode.c: Regenerate.
27
05c966f3
AV		 282017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
29
30 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
31
10045478
AK		 322017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
33
34 * arc-dis.c (enforced_isa_mask): Declare.
35 (cpu_types): Likewise.
36 (parse_cpu_option): New function.
37 (parse_disassembler_options): Use it.
38 (print_insn_arc): Use enforced_isa_mask.
39 (print_arc_disassembler_options): Document new options.
40
88c1242d
YQ		 412017-05-24 Yao Qi <yao.qi@linaro.org>
42
43 * alpha-dis.c: Include disassemble.h, don't include
44 dis-asm.h.
45 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
46 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
47 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
48 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
49 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
50 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
51 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
52 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
53 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
54 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
55 * moxie-dis.c, msp430-dis.c, mt-dis.c:
56 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
57 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
58 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
59 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
60 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
61 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
62 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
63 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
64 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
65 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
66 * z80-dis.c, z8k-dis.c: Likewise.
67 * disassemble.h: New file.
68
ab20fa4a
YQ		 692017-05-24 Yao Qi <yao.qi@linaro.org>
70
71 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
72 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
73
003ca0fd
YQ		 742017-05-24 Yao Qi <yao.qi@linaro.org>
75
76 * disassemble.c (disassembler): Add arguments a, big and mach.
77 Use them.
78
04ef582a
L		 792017-05-22 H.J. Lu <hongjiu.lu@intel.com>
80
81 * i386-dis.c (NOTRACK_Fixup): New.
82 (NOTRACK): Likewise.
83 (NOTRACK_PREFIX): Likewise.
84 (last_active_prefix): Likewise.
85 (reg_table): Use NOTRACK on indirect call and jmp.
86 (ckprefix): Set last_active_prefix.
87 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
88 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
89 * i386-opc.h (NoTrackPrefixOk): New.
90 (i386_opcode_modifier): Add notrackprefixok.
91 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
92 Add notrack.
93 * i386-tbl.h: Regenerated.
94
64517994
JM		 952017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
96
97 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
98 (X_IMM2): Define.
99 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
100 bfd_mach_sparc_v9m8.
101 (print_insn_sparc): Handle new operand types.
102 * sparc-opc.c (MASK_M8): Define.
103 (v6): Add MASK_M8.
104 (v6notlet): Likewise.
105 (v7): Likewise.
106 (v8): Likewise.
107 (v9): Likewise.
108 (v9a): Likewise.
109 (v9b): Likewise.
110 (v9c): Likewise.
111 (v9d): Likewise.
112 (v9e): Likewise.
113 (v9v): Likewise.
114 (v9m): Likewise.
115 (v9andleon): Likewise.
116 (m8): Define.
117 (HWS_VM8): Define.
118 (HWS2_VM8): Likewise.
119 (sparc_opcode_archs): Add entry for "m8".
120 (sparc_opcodes): Add OSA2017 and M8 instructions
121 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
122 fpx{ll,ra,rl}64x,
123 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
124 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
125 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
126 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
127 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
128 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
129 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
130 ASI_CORE_SELECT_COMMIT_NHT.
131
535b785f
AM		 1322017-05-18 Alan Modra <amodra@gmail.com>
133
134 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
135 * aarch64-dis.c: Likewise.
136 * aarch64-gen.c: Likewise.
137 * aarch64-opc.c: Likewise.
138
25499ac7
MR		 1392017-05-15 Maciej W. Rozycki <macro@imgtec.com>
140 Matthew Fortune <matthew.fortune@imgtec.com>
141
142 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
143 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
144 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
145 (print_insn_arg) <OP_REG28>: Add handler.
146 (validate_insn_args) <OP_REG28>: Handle.
147 (print_mips16_insn_arg): Handle MIPS16 instructions that require
148 32-bit encoding and 9-bit immediates.
149 (print_insn_mips16): Handle MIPS16 instructions that require
150 32-bit encoding and MFC0/MTC0 operand decoding.
151 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
152 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
153 (RD_C0, WR_C0, E2, E2MT): New macros.
154 (mips16_opcodes): Add entries for MIPS16e2 instructions:
155 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
156 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
157 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
158 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
159 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
160 instructions, "swl", "swr", "sync" and its "sync_acquire",
161 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
162 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
163 regular/extended entries for original MIPS16 ISA revision
164 instructions whose extended forms are subdecoded in the MIPS16e2
165 ISA revision: "li", "sll" and "srl".
166
fdfb4752
MR		 1672017-05-15 Maciej W. Rozycki <macro@imgtec.com>
168
169 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
170 reference in CP0 move operand decoding.
171
a4f89915
MR		 1722017-05-12 Maciej W. Rozycki <macro@imgtec.com>
173
174 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
175 type to hexadecimal.
176 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
177
99e2d67a
MR		 1782017-05-11 Maciej W. Rozycki <macro@imgtec.com>
179
180 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
181 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
182 "sync_rmb" and "sync_wmb" as aliases.
183 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
184 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
185
53a346d8
CZ		 1862017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
187
188 * arc-dis.c (parse_option): Update quarkse_em option..
189 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
190 QUARKSE1.
191 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
192
f91d48de
KC		 1932017-05-03 Kito Cheng <kito.cheng@gmail.com>
194
195 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
196
43e379d7
MC		 1972017-05-01 Michael Clark <michaeljclark@mac.com>
198
199 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
200 register.
201
a4ddc54e
MR		 2022017-05-02 Maciej W. Rozycki <macro@imgtec.com>
203
204 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
205 and branches and not synthetic data instructions.
206
fe50e98c
BE		 2072017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
208
209 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
210
126124cc
CZ		 2112017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
212
213 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
214 * arc-opc.c (insert_r13el): New function.
215 (R13_EL): Define.
216 * arc-tbl.h: Add new enter/leave variants.
217
be6a24d8
CZ		 2182017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
219
220 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
221
0348fd79
MR		 2222017-04-25 Maciej W. Rozycki <macro@imgtec.com>
223
224 * mips-dis.c (print_mips_disassembler_options): Add
225 `no-aliases'.
226
6e3d1f07
MR		 2272017-04-25 Maciej W. Rozycki <macro@imgtec.com>
228
229 * mips16-opc.c (AL): New macro.
230 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
231 of "ld" and "lw" as aliases.
232
957f6b39
TC		 2332017-04-24 Tamar Christina <tamar.christina@arm.com>
234
235 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
236 arguments.
237
a8cc8a54
AM		 2382017-04-22 Alexander Fedotov <alfedotov@gmail.com>
239 Alan Modra <amodra@gmail.com>
240
241 * ppc-opc.c (ELEV): Define.
242 (vle_opcodes): Add se_rfgi and e_sc.
243 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
244 for E200Z4.
245
3ab87b68
JM		 2462017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
247
248 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
249
792f174f
NC		 2502017-04-21 Nick Clifton <nickc@redhat.com>
251
252 PR binutils/21380
253 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
254 LD3R and LD4R.
255
42742084
AM		 2562017-04-13 Alan Modra <amodra@gmail.com>
257
258 * epiphany-desc.c: Regenerate.
259 * fr30-desc.c: Regenerate.
260 * frv-desc.c: Regenerate.
261 * ip2k-desc.c: Regenerate.
262 * iq2000-desc.c: Regenerate.
263 * lm32-desc.c: Regenerate.
264 * m32c-desc.c: Regenerate.
265 * m32r-desc.c: Regenerate.
266 * mep-desc.c: Regenerate.
267 * mt-desc.c: Regenerate.
268 * or1k-desc.c: Regenerate.
269 * xc16x-desc.c: Regenerate.
270 * xstormy16-desc.c: Regenerate.
271
9a85b496
AM		 2722017-04-11 Alan Modra <amodra@gmail.com>
273
ef85eab0 274 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
c03dc33b
AM		 275 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
276 PPC_OPCODE_TMR for e6500.
9a85b496
AM		 277 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
278 (PPCVEC3): Define as PPC_OPCODE_POWER9.
9570835e
AM		 279 (PPCVSX2): Define as PPC_OPCODE_POWER8.
280 (PPCVSX3): Define as PPC_OPCODE_POWER9.
ef85eab0 281 (PPCHTM): Define as PPC_OPCODE_POWER8.
c03dc33b 282 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
9a85b496 283
62adc510
AM		 2842017-04-10 Alan Modra <amodra@gmail.com>
285
286 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
287 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
288 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
289 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
290
aa808707
PC		 2912017-04-09 Pip Cet <pipcet@gmail.com>
292
293 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
294 appropriate floating-point precision directly.
295
ac8f0f72
AM		 2962017-04-07 Alan Modra <amodra@gmail.com>
297
298 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
299 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
300 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
301 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
302 vector instructions with E6500 not PPCVEC2.
303
62ecb94c
PC		 3042017-04-06 Pip Cet <pipcet@gmail.com>
305
306 * Makefile.am: Add wasm32-dis.c.
307 * configure.ac: Add wasm32-dis.c to wasm32 target.
308 * disassemble.c: Add wasm32 disassembler code.
309 * wasm32-dis.c: New file.
310 * Makefile.in: Regenerate.
311 * configure: Regenerate.
312 * po/POTFILES.in: Regenerate.
313 * po/opcodes.pot: Regenerate.
314
f995bbe8
PA		 3152017-04-05 Pedro Alves <palves@redhat.com>
316
317 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
318 * arm-dis.c (parse_arm_disassembler_options): Constify.
319 * ppc-dis.c (powerpc_init_dialect): Constify local.
320 * vax-dis.c (parse_disassembler_options): Constify.
321
b5292032
PD		 3222017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
323
324 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
325 RISCV_GP_SYMBOL.
326
f96bd6c2
PC		 3272017-03-30 Pip Cet <pipcet@gmail.com>
328
329 * configure.ac: Add (empty) bfd_wasm32_arch target.
330 * configure: Regenerate
331 * po/opcodes.pot: Regenerate.
332
f7c514a3
JM		 3332017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
334
335 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
336 OSA2015.
337 * opcodes/sparc-opc.c (asi_table): New ASIs.
338
52be03fd
AM		 3392017-03-29 Alan Modra <amodra@gmail.com>
340
341 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
342 "raw" option.
343 (lookup_powerpc): Don't special case -1 dialect. Handle
344 PPC_OPCODE_RAW.
345 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
346 lookup_powerpc call, pass it on second.
347
9b753937
AM		 3482017-03-27 Alan Modra <amodra@gmail.com>
349
350 PR 21303
351 * ppc-dis.c (struct ppc_mopt): Comment.
352 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
353
c0c31e91
RZ		 3542017-03-27 Rinat Zelig <rinat@mellanox.com>
355
356 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
357 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
358 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
359 (insert_nps_misc_imm_offset): New function.
360 (extract_nps_misc imm_offset): New function.
361 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
362 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
363
2253c8f0
AK		 3642017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
365
366 * s390-mkopc.c (main): Remove vx2 check.
367 * s390-opc.txt: Remove vx2 instruction flags.
368
645d3342
RZ		 3692017-03-21 Rinat Zelig <rinat@mellanox.com>
370
371 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
372 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
373 (insert_nps_imm_offset): New function.
374 (extract_nps_imm_offset): New function.
375 (insert_nps_imm_entry): New function.
376 (extract_nps_imm_entry): New function.
377
4b94dd2d
AM		 3782017-03-17 Alan Modra <amodra@gmail.com>
379
380 PR 21248
381 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
382 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
383 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
384
b416fe87
KC		 3852017-03-14 Kito Cheng <kito.cheng@gmail.com>
386
387 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
388 <c.andi>: Likewise.
389 <c.addiw> Likewise.
390
03b039a5
KC		 3912017-03-14 Kito Cheng <kito.cheng@gmail.com>
392
393 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
394
2c232b83
AW		 3952017-03-13 Andrew Waterman <andrew@sifive.com>
396
397 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
398 <srl> Likewise.
399 <srai> Likewise.
400 <sra> Likewise.
401
86fa6981
L		 4022017-03-09 H.J. Lu <hongjiu.lu@intel.com>
403
404 * i386-gen.c (opcode_modifiers): Replace S with Load.
405 * i386-opc.h (S): Removed.
406 (Load): New.
407 (i386_opcode_modifier): Replace s with load.
408 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
409 and {evex}. Replace S with Load.
410 * i386-tbl.h: Regenerated.
411
c1fe188b
L		 4122017-03-09 H.J. Lu <hongjiu.lu@intel.com>
413
414 * i386-opc.tbl: Use CpuCET on rdsspq.
415 * i386-tbl.h: Regenerated.
416
4b8b687e
PB		 4172017-03-08 Peter Bergner <bergner@vnet.ibm.com>
418
419 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
420 <vsx>: Do not use PPC_OPCODE_VSX3;
421
1437d063
PB		 4222017-03-08 Peter Bergner <bergner@vnet.ibm.com>
423
424 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
425
603555e5
L		 4262017-03-06 H.J. Lu <hongjiu.lu@intel.com>
427
428 * i386-dis.c (REG_0F1E_MOD_3): New enum.
429 (MOD_0F1E_PREFIX_1): Likewise.
430 (MOD_0F38F5_PREFIX_2): Likewise.
431 (MOD_0F38F6_PREFIX_0): Likewise.
432 (RM_0F1E_MOD_3_REG_7): Likewise.
433 (PREFIX_MOD_0_0F01_REG_5): Likewise.
434 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
435 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
436 (PREFIX_0F1E): Likewise.
437 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
438 (PREFIX_0F38F5): Likewise.
439 (dis386_twobyte): Use PREFIX_0F1E.
440 (reg_table): Add REG_0F1E_MOD_3.
441 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
442 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
443 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
444 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
445 (three_byte_table): Use PREFIX_0F38F5.
446 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
447 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
448 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
449 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
450 PREFIX_MOD_3_0F01_REG_5_RM_2.
451 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
452 (cpu_flags): Add CpuCET.
453 * i386-opc.h (CpuCET): New enum.
454 (CpuUnused): Commented out.
455 (i386_cpu_flags): Add cpucet.
456 * i386-opc.tbl: Add Intel CET instructions.
457 * i386-init.h: Regenerated.
458 * i386-tbl.h: Likewise.
459
73f07bff
AM		 4602017-03-06 Alan Modra <amodra@gmail.com>
461
462 PR 21124
463 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
464 (extract_raq, extract_ras, extract_rbx): New functions.
465 (powerpc_operands): Use opposite corresponding insert function.
466 (Q_MASK): Define.
467 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
468 register restriction.
469
65b48a81
PB		 4702017-02-28 Peter Bergner <bergner@vnet.ibm.com>
471
472 * disassemble.c Include "safe-ctype.h".
473 (disassemble_init_for_target): Handle s390 init.
474 (remove_whitespace_and_extra_commas): New function.
475 (disassembler_options_cmp): Likewise.
476 * arm-dis.c: Include "libiberty.h".
477 (NUM_ELEM): Delete.
478 (regnames): Use long disassembler style names.
479 Add force-thumb and no-force-thumb options.
480 (NUM_ARM_REGNAMES): Rename from this...
481 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
482 (get_arm_regname_num_options): Delete.
483 (set_arm_regname_option): Likewise.
484 (get_arm_regnames): Likewise.
485 (parse_disassembler_options): Likewise.
486 (parse_arm_disassembler_option): Rename from this...
487 (parse_arm_disassembler_options): ...to this. Make static.
488 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
489 (print_insn): Use parse_arm_disassembler_options.
490 (disassembler_options_arm): New function.
491 (print_arm_disassembler_options): Handle updated regnames.
492 * ppc-dis.c: Include "libiberty.h".
493 (ppc_opts): Add "32" and "64" entries.
494 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
495 (powerpc_init_dialect): Add break to switch statement.
496 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
497 (disassembler_options_powerpc): New function.
498 (print_ppc_disassembler_options): Use ARRAY_SIZE.
499 Remove printing of "32" and "64".
500 * s390-dis.c: Include "libiberty.h".
501 (init_flag): Remove unneeded variable.
502 (struct s390_options_t): New structure type.
503 (options): New structure.
504 (init_disasm): Rename from this...
505 (disassemble_init_s390): ...to this. Add initializations for
506 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
507 (print_insn_s390): Delete call to init_disasm.
508 (disassembler_options_s390): New function.
509 (print_s390_disassembler_options): Print using information from
510 struct 'options'.
511 * po/opcodes.pot: Regenerate.
512
15c7c1d8
JB		 5132017-02-28 Jan Beulich <jbeulich@suse.com>
514
515 * i386-dis.c (PCMPESTR_Fixup): New.
516 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
517 (prefix_table): Use PCMPESTR_Fixup.
518 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
519 PCMPESTR_Fixup.
520 (vex_w_table): Delete VPCMPESTR{I,M} entries.
521 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
522 Split 64-bit and non-64-bit variants.
523 * opcodes/i386-tbl.h: Re-generate.
524
582e12bf
RS		 5252017-02-24 Richard Sandiford <richard.sandiford@arm.com>
526
527 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
528 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
529 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
530 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
531 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
532 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
533 (OP_SVE_V_HSD): New macros.
534 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
535 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
536 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
537 (aarch64_opcode_table): Add new SVE instructions.
538 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
539 for rotation operands. Add new SVE operands.
540 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
541 (ins_sve_quad_index): Likewise.
542 (ins_imm_rotate): Split into...
543 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
544 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
545 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
546 functions.
547 (aarch64_ins_sve_addr_ri_s4): New function.
548 (aarch64_ins_sve_quad_index): Likewise.
549 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
550 * aarch64-asm-2.c: Regenerate.
551 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
552 (ext_sve_quad_index): Likewise.
553 (ext_imm_rotate): Split into...
554 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
555 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
556 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
557 functions.
558 (aarch64_ext_sve_addr_ri_s4): New function.
559 (aarch64_ext_sve_quad_index): Likewise.
560 (aarch64_ext_sve_index): Allow quad indices.
561 (do_misc_decoding): Likewise.
562 * aarch64-dis-2.c: Regenerate.
563 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
564 aarch64_field_kinds.
565 (OPD_F_OD_MASK): Widen by one bit.
566 (OPD_F_NO_ZR): Bump accordingly.
567 (get_operand_field_width): New function.
568 * aarch64-opc.c (fields): Add new SVE fields.
569 (operand_general_constraint_met_p): Handle new SVE operands.
570 (aarch64_print_operand): Likewise.
571 * aarch64-opc-2.c: Regenerate.
572
f482d304
RS		 5732017-02-24 Richard Sandiford <richard.sandiford@arm.com>
574
575 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
576 (aarch64_feature_compnum): ...this.
577 (SIMD_V8_3): Replace with...
578 (COMPNUM): ...this.
579 (CNUM_INSN): New macro.
580 (aarch64_opcode_table): Use it for the complex number instructions.
581
7db2c588
JB		 5822017-02-24 Jan Beulich <jbeulich@suse.com>
583
584 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
585
1e9d41d4
SL		 5862017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
587
588 Add support for associating SPARC ASIs with an architecture level.
589 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
590 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
591 decoding of SPARC ASIs.
592
53c4d625
JB		 5932017-02-23 Jan Beulich <jbeulich@suse.com>
594
595 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
596 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
597
11648de5
JB		 5982017-02-21 Jan Beulich <jbeulich@suse.com>
599
600 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
601 1 (instead of to itself). Correct typo.
602
f98d33be
AW		 6032017-02-14 Andrew Waterman <andrew@sifive.com>
604
605 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
606 pseudoinstructions.
607
773fb663
RS		 6082017-02-15 Richard Sandiford <richard.sandiford@arm.com>
609
610 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
611 (aarch64_sys_reg_supported_p): Handle them.
612
cc07cda6
CZ		 6132017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
614
615 * arc-opc.c (UIMM6_20R): Define.
616 (SIMM12_20): Use above.
617 (SIMM12_20R): Define.
618 (SIMM3_5_S): Use above.
619 (UIMM7_A32_11R_S): Define.
620 (UIMM7_9_S): Use above.
621 (UIMM3_13R_S): Define.
622 (SIMM11_A32_7_S): Use above.
623 (SIMM9_8R): Define.
624 (UIMM10_A32_8_S): Use above.
625 (UIMM8_8R_S): Define.
626 (W6): Use above.
627 (arc_relax_opcodes): Use all above defines.
628
66a5a740
VG		 6292017-02-15 Vineet Gupta <vgupta@synopsys.com>
630
631 * arc-regs.h: Distinguish some of the registers different on
632 ARC700 and HS38 cpus.
633
7e0de605
AM		 6342017-02-14 Alan Modra <amodra@gmail.com>
635
636 PR 21118
637 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
638 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
639
54064fdb
AM		 6402017-02-11 Stafford Horne <shorne@gmail.com>
641 Alan Modra <amodra@gmail.com>
642
643 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
644 Use insn_bytes_value and insn_int_value directly instead. Don't
645 free allocated memory until function exit.
646
dce75bf9
NP		 6472017-02-10 Nicholas Piggin <npiggin@gmail.com>
648
649 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
650
1b7e3d2f
NC		 6512017-02-03 Nick Clifton <nickc@redhat.com>
652
653 PR 21096
654 * aarch64-opc.c (print_register_list): Ensure that the register
655 list index will fir into the tb buffer.
656 (print_register_offset_address): Likewise.
657 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
658
8ec5cf65
AD		 6592017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
660
661 PR 21056
662 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
663 instructions when the previous fetch packet ends with a 32-bit
664 instruction.
665
a1aa5e81
DD		 6662017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
667
668 * pru-opc.c: Remove vague reference to a future GDB port.
669
add3afb2
NC		 6702017-01-20 Nick Clifton <nickc@redhat.com>
671
672 * po/ga.po: Updated Irish translation.
673
c13a63b0
SN		 6742017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
675
676 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
677
9608051a
YQ		 6782017-01-13 Yao Qi <yao.qi@linaro.org>
679
680 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
681 if FETCH_DATA returns 0.
682 (m68k_scan_mask): Likewise.
683 (print_insn_m68k): Update code to handle -1 return value.
684
f622ea96
YQ		 6852017-01-13 Yao Qi <yao.qi@linaro.org>
686
687 * m68k-dis.c (enum print_insn_arg_error): New.
688 (NEXTBYTE): Replace -3 with
689 PRINT_INSN_ARG_MEMORY_ERROR.
690 (NEXTULONG): Likewise.
691 (NEXTSINGLE): Likewise.
692 (NEXTDOUBLE): Likewise.
693 (NEXTDOUBLE): Likewise.
694 (NEXTPACKED): Likewise.
695 (FETCH_ARG): Likewise.
696 (FETCH_DATA): Update comments.
697 (print_insn_arg): Update comments. Replace magic numbers with
698 enum.
699 (match_insn_m68k): Likewise.
700
620214f7
IT		 7012017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
702
703 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
704 * i386-dis-evex.h (evex_table): Updated.
705 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
706 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
707 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
708 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
709 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
710 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
711 * i386-init.h: Regenerate.
712 * i386-tbl.h: Ditto.
713
d95014a2
YQ		 7142017-01-12 Yao Qi <yao.qi@linaro.org>
715
716 * msp430-dis.c (msp430_singleoperand): Return -1 if
717 msp430dis_opcode_signed returns false.
718 (msp430_doubleoperand): Likewise.
719 (msp430_branchinstr): Return -1 if
720 msp430dis_opcode_unsigned returns false.
721 (msp430x_calla_instr): Likewise.
722 (print_insn_msp430): Likewise.
723
0ae60c3e
NC		 7242017-01-05 Nick Clifton <nickc@redhat.com>
725
726 PR 20946
727 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
728 could not be matched.
729 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
730 NULL.
731
d74d4880
SN		 7322017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
733
734 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
735 (aarch64_opcode_table): Use RCPC_INSN.
736
cc917fd9
KC		 7372017-01-03 Kito Cheng <kito.cheng@gmail.com>
738
739 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
740 extension.
741 * riscv-opcodes/all-opcodes: Likewise.
742
b52d3cfc
DP		 7432017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
744
745 * riscv-dis.c (print_insn_args): Add fall through comment.
746
f90c58d5
NC		 7472017-01-03 Nick Clifton <nickc@redhat.com>
748
749 * po/sr.po: New Serbian translation.
750 * configure.ac (ALL_LINGUAS): Add sr.
751 * configure: Regenerate.
752
f47b0d4a
AM		 7532017-01-02 Alan Modra <amodra@gmail.com>
754
755 * epiphany-desc.h: Regenerate.
756 * epiphany-opc.h: Regenerate.
757 * fr30-desc.h: Regenerate.
758 * fr30-opc.h: Regenerate.
759 * frv-desc.h: Regenerate.
760 * frv-opc.h: Regenerate.
761 * ip2k-desc.h: Regenerate.
762 * ip2k-opc.h: Regenerate.
763 * iq2000-desc.h: Regenerate.
764 * iq2000-opc.h: Regenerate.
765 * lm32-desc.h: Regenerate.
766 * lm32-opc.h: Regenerate.
767 * m32c-desc.h: Regenerate.
768 * m32c-opc.h: Regenerate.
769 * m32r-desc.h: Regenerate.
770 * m32r-opc.h: Regenerate.
771 * mep-desc.h: Regenerate.
772 * mep-opc.h: Regenerate.
773 * mt-desc.h: Regenerate.
774 * mt-opc.h: Regenerate.
775 * or1k-desc.h: Regenerate.
776 * or1k-opc.h: Regenerate.
777 * xc16x-desc.h: Regenerate.
778 * xc16x-opc.h: Regenerate.
779 * xstormy16-desc.h: Regenerate.
780 * xstormy16-opc.h: Regenerate.
781
2571583a
AM		 7822017-01-02 Alan Modra <amodra@gmail.com>
783
784 Update year range in copyright notice of all files.
785
5c1ad6b5 786For older changes see ChangeLog-2016
3499769a 787\f
5c1ad6b5 788Copyright (C) 2017 Free Software Foundation, Inc.
3499769a
AM		 789
790Copying and distribution of this file, with or without modification,
791are permitted in any medium without royalty provided the copyright
792notice and this notice are preserved.
793
794Local Variables:
795mode: change-log
796left-margin: 8
797fill-column: 74
798version-control: never
799End:
GDB Binutils - Deliverables
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