[deliverable/binutils-gdb.git] / opcodes / ChangeLog

2013-04-24  Sandra Loosemore  <sandra@codesourcery.com>

	* nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
	to "eccinj".

2013-04-17  Wei-chen Wang  <cole945@gmail.com>

	PR binutils/15369
	* cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
	of CGEN_CPU_ENDIAN.
	(hash_insns_list): Likewise.

2013-04-10  Jan Kratochvil  <jan.kratochvil@redhat.com>

	* rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
	warning workaround.

2013-04-08  Jan Beulich <jbeulich@suse.com>

	* i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
	* i386-tbl.h: Re-generate.

2013-04-06  David S. Miller  <davem@davemloft.net>

	* sparc-dis.c (compare_opcodes): When encountering multiple aliases
	of an opcode, prefer the one with F_PREFERRED set.
	* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
	lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
	ops.  Make 64-bit VIS logical ops have "d" suffix in their names,
	mark existing mnenomics as aliases.  Add "cc" suffix to edge
	instructions generating condition codes, mark existing mnenomics
	as aliases.  Add "fp" prefix to VIS compare instructions, mark
	existing mnenomics as aliases.

2013-04-03  Nick Clifton  <nickc@redhat.com>

	* v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
	destination address by subtracting the operand from the current
	address.
	* v850-opc.c (insert_u16_loop): Disallow negative offsets.  Store
	a positive value in the insn.
	(extract_u16_loop): Do not negate the returned value.
	(D16_LOOP): Add V850_INVERSE_PCREL flag.

	(ceilf.sw): Remove duplicate entry.
	(cvtf.hs): New entry.
	(cvtf.sh): Likewise.
	(fmaf.s): Likewise.
	(fmsf.s): Likewise.
	(fnmaf.s): Likewise.
	(fnmsf.s): Likewise.
	(maddf.s): Restrict to E3V5 architectures.
	(msubf.s): Likewise.
	(nmaddf.s): Likewise.
	(nmsubf.s): Likewise.

2013-03-27  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (get_sib): Add the sizeflag argument.  Properly
	check address mode.
	(print_insn): Pass sizeflag to get_sib.

2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>

	PR binutils/15068
	* tic6x-dis.c: Add support for displaying 16-bit insns.

2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>

	PR gas/15095
	* tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
	individual msb and lsb halves in src1 & src2 fields.  Discard the
	src1 (lsb) value and only use src2 (msb), discarding bit 0, to
	follow what Ti SDK does in that case as any value in the src1
	field yields the same output with SDK disassembler.

2013-03-12  Michael Eager <eager@eagercon.com>

	* opcodes/mips-dis.c (print_insn_args): Modify def of reg.

2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>

	* nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.

2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>

	* nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.

2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>

	* nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.

2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* arm-dis.c (arm_opcodes): Add entries for CRC instructions.
	(thumb32_opcodes): Likewise.
	(print_insn_thumb32): Handle 'S' control char.

2013-03-08  Yann Sionneau  <yann.sionneau@gmail.com>

	* lm32-desc.c: Regenerate.

2013-03-01  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-reg.tbl (riz): Add RegRex64.
	* i386-tbl.h: Regenerated.

2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
	(aarch64_feature_crc): New static.
	(CRC): New macro.
	(aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
	crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
	* aarch64-asm-2.c: Re-generate.
	* aarch64-dis-2.c: Ditto.
	* aarch64-opc-2.c: Ditto.

2013-02-27  Alan Modra  <amodra@gmail.com>

	* rl78-decode.opc (rl78_decode_opcode): Fix typo.
	* rl78-decode.c: Regenerate.

2013-02-25  Kaushik Phatak  <Kaushik.Phatak@kpitcummins.com>

	* rl78-decode.opc: Fix encoding of DIVWU insn.
	* rl78-decode.c: Regenerate.

2013-02-19  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/15159
	* i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.

	* i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
	(cpu_flags): Add CpuSMAP.

	* i386-opc.h (CpuSMAP): New.
	(i386_cpu_flags): Add cpusmap.

	* i386-opc.tbl: Add clac and stac.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2013-02-15  Markos Chandras  <markos.chandras@imgtec.com>

	* metag-dis.c: Initialize outf->bytes_per_chunk to 4
	which also makes the disassembler output be in little
	endian like it should be.

2013-02-14  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
	fields to NULL.
	(aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.

2013-02-13  Maciej W. Rozycki  <macro@codesourcery.com>

	* mips-dis.c (is_compressed_mode_p): Only match symbols from the
	section disassembled.

2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* arm-dis.c: Update strht pattern.

2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>

	* mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
	single-float.  Disable ll, lld, sc and scd for EE.  Disable the
	trunc.w.s macro for EE.

2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
            Andrew Jenner <andrew@codesourcery.com>

	Based on patches from Altera Corporation.

	* Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
	nios2-opc.c.
	* Makefile.in: Regenerated.
	* configure.in: Add case for bfd_nios2_arch.
	* configure: Regenerated.
	* disassemble.c (ARCH_nios2): Define.
	(disassembler): Add case for bfd_arch_nios2.
	* nios2-dis.c: New file.
	* nios2-opc.c: New file.

2013-02-04  Alan Modra  <amodra@gmail.com>

	* po/POTFILES.in: Regenerate.
	* rl78-decode.c: Regenerate.
	* rx-decode.c: Regenerate.

2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
	ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
	* aarch64-asm.c (convert_xtl_to_shll): New function.
	(convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	calling convert_xtl_to_shll.
	* aarch64-dis.c (convert_shll_to_xtl): New function.
	(convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	calling convert_shll_to_xtl.
	* aarch64-gen.c: Update copyright year.
	* aarch64-asm-2.c: Re-generate.
	* aarch64-dis-2.c: Re-generate.
	* aarch64-opc-2.c: Re-generate.

2013-01-24  Nick Clifton  <nickc@redhat.com>

	* v850-dis.c: Add support for e3v5 architecture.
	* v850-opc.c: Likewise.

2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
	* aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
	* aarch64-opc.c (operand_general_constraint_met_p): For
	AARCH64_MOD_LSL, move the range check on the shift amount before the
	alignment check; change to call set_sft_amount_out_of_range_error
	instead of set_imm_out_of_range_error.
	* aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
	(aarch64_opcode_table): Remove the OP enumerator from the asimdimm
	8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
	SIMD_IMM_SFT.

2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2013-01-15  Nick Clifton  <nickc@redhat.com>

	* v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
	values.
	* v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.

2013-01-14  Will Newton <will.newton@imgtec.com>

	* metag-dis.c (REG_WIDTH): Increase to 64.

2013-01-10  Peter Bergner <bergner@vnet.ibm.com>

	* ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
	* ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
	XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
	(SH6): Update.
	<"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
	"tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
	"treclaim.", "tsr.">: Add POWER8 HTM opcodes.
	<"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.

2013-01-10  Will Newton <will.newton@imgtec.com>

	* Makefile.am: Add Meta.
	* configure.in: Add Meta.
	* disassemble.c: Add Meta support.
	* metag-dis.c: New file.
	* Makefile.in: Regenerate.
	* configure: Regenerate.

2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>

	* cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
	(match_opcode): Rename to cr16_match_opcode.

2013-01-04  Juergen Urban <JuergenUrban@gmx.de>

	* mips-dis.c: Add names for CP0 registers of r5900.
	* mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
	instructions sq and lq.
	Add support for MIPS r5900 CPU.
	Add support for 128 bit MMI (Multimedia Instructions).
	Add support for EE instructions (Emotion Engine).
	Disable unsupported floating point instructions (64 bit and
	undefined compare operations).
	Enable instructions of MIPS ISA IV which are supported by r5900.
	Disable 64 bit co processor instructions.
	Disable 64 bit multiplication and division instructions.
	Disable instructions for co-processor 2 and 3, because these are
	not supported (preparation for later VU0 support (Vector Unit)).
	Disable cvt.w.s because this behaves like trunc.w.s and the
	correct execution can't be ensured on r5900.
	Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
	will confuse less developers and compilers.

2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-opc.c (aarch64_print_operand): Change to print
	AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
	in comment.
	* aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
	from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
	OP_MOV_IMM_WIDE.

2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
	PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.

2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (process_copyright): Update copyright year to 2013.

2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>

	* cr16-dis.c (match_opcode,make_instruction): Remove static
	declaration.
	(dwordU,wordU): Moved typedefs to opcode/cr16.h
	(cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.

For older changes see ChangeLog-2012
\f
Copyright (C) 2013 Free Software Foundation, Inc.

Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.

Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
Commit	Line	Data
e3031850 SL	1	2013-04-24 Sandra Loosemore <sandra@codesourcery.com>
	2
	3	* nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
	4	to "eccinj".
	5
17310e56 NC	6	2013-04-17 Wei-chen Wang <cole945@gmail.com>
	7
	8	PR binutils/15369
	9	* cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
	10	of CGEN_CPU_ENDIAN.
	11	(hash_insns_list): Likewise.
	12
731df338 JK	13	2013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
	14
	15	* rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
	16	warning workaround.
	17
5f77db52 JB	18	2013-04-08 Jan Beulich <jbeulich@suse.com>
	19
	20	* i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
	21	* i386-tbl.h: Re-generate.
	22
0afd1215 DM	23	2013-04-06 David S. Miller <davem@davemloft.net>
	24
	25	* sparc-dis.c (compare_opcodes): When encountering multiple aliases
	26	of an opcode, prefer the one with F_PREFERRED set.
	27	* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
	28	lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
	29	ops. Make 64-bit VIS logical ops have "d" suffix in their names,
	30	mark existing mnenomics as aliases. Add "cc" suffix to edge
	31	instructions generating condition codes, mark existing mnenomics
	32	as aliases. Add "fp" prefix to VIS compare instructions, mark
	33	existing mnenomics as aliases.
	34
41702d50 NC	35	2013-04-03 Nick Clifton <nickc@redhat.com>
	36
	37	* v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
	38	destination address by subtracting the operand from the current
	39	address.
	40	* v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
	41	a positive value in the insn.
	42	(extract_u16_loop): Do not negate the returned value.
	43	(D16_LOOP): Add V850_INVERSE_PCREL flag.
	44
	45	(ceilf.sw): Remove duplicate entry.
	46	(cvtf.hs): New entry.
	47	(cvtf.sh): Likewise.
	48	(fmaf.s): Likewise.
	49	(fmsf.s): Likewise.
	50	(fnmaf.s): Likewise.
	51	(fnmsf.s): Likewise.
	52	(maddf.s): Restrict to E3V5 architectures.
	53	(msubf.s): Likewise.
	54	(nmaddf.s): Likewise.
	55	(nmsubf.s): Likewise.
	56
55cf16e1 L	57	2013-03-27 H.J. Lu <hongjiu.lu@intel.com>
	58
	59	* i386-dis.c (get_sib): Add the sizeflag argument. Properly
	60	check address mode.
	61	(print_insn): Pass sizeflag to get_sib.
	62
51dcdd4d NC	63	2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
	64
	65	PR binutils/15068
	66	* tic6x-dis.c: Add support for displaying 16-bit insns.
	67
795b8e6b NC	68	2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
	69
	70	PR gas/15095
	71	* tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
	72	individual msb and lsb halves in src1 & src2 fields. Discard the
	73	src1 (lsb) value and only use src2 (msb), discarding bit 0, to
	74	follow what Ti SDK does in that case as any value in the src1
	75	field yields the same output with SDK disassembler.
	76
314d60dd ME	77	2013-03-12 Michael Eager <eager@eagercon.com>
314d60dd ME	78
795b8e6b	79	* opcodes/mips-dis.c (print_insn_args): Modify def of reg.
314d60dd	80
dad60f8e SL	81	2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
	82
	83	* nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
	84
f5cb796a SL	85	2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
	86
	87	* nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
	88
21fde85c SL	89	2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
	90
	91	* nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
	92
dd5181d5 KT	93	2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
	94
	95	* arm-dis.c (arm_opcodes): Add entries for CRC instructions.
	96	(thumb32_opcodes): Likewise.
	97	(print_insn_thumb32): Handle 'S' control char.
	98
87a8d6cb NC	99	2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
	100
	101	* lm32-desc.c: Regenerate.
	102
99dce992 L	103	2013-03-01 H.J. Lu <hongjiu.lu@intel.com>
	104
	105	* i386-reg.tbl (riz): Add RegRex64.
	106	* i386-tbl.h: Regenerated.
	107
e60bb1dd YZ	108	2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
	109
	110	* aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
	111	(aarch64_feature_crc): New static.
	112	(CRC): New macro.
	113	(aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
	114	crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
	115	* aarch64-asm-2.c: Re-generate.
	116	* aarch64-dis-2.c: Ditto.
	117	* aarch64-opc-2.c: Ditto.
	118
c7570fcd AM	119	2013-02-27 Alan Modra <amodra@gmail.com>
	120
	121	* rl78-decode.opc (rl78_decode_opcode): Fix typo.
	122	* rl78-decode.c: Regenerate.
	123
151fa98f NC	124	2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
	125
	126	* rl78-decode.opc: Fix encoding of DIVWU insn.
	127	* rl78-decode.c: Regenerate.
	128
5c111e37 L	129	2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
	130
	131	PR gas/15159
	132	* i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
	133
	134	* i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
	135	(cpu_flags): Add CpuSMAP.
	136
	137	* i386-opc.h (CpuSMAP): New.
	138	(i386_cpu_flags): Add cpusmap.
	139
	140	* i386-opc.tbl: Add clac and stac.
	141
	142	* i386-init.h: Regenerated.
	143	* i386-tbl.h: Likewise.
	144
9d1df426 NC	145	2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
	146
	147	* metag-dis.c: Initialize outf->bytes_per_chunk to 4
	148	which also makes the disassembler output be in little
	149	endian like it should be.
	150
a1ccaec9 YZ	151	2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
	152
	153	* aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
	154	fields to NULL.
	155	(aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
	156
ef068ef4	157	2013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
5417f71e MR	158
	159	* mips-dis.c (is_compressed_mode_p): Only match symbols from the
	160	section disassembled.
	161
6fe6ded9 RE	162	2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
	163
	164	* arm-dis.c: Update strht pattern.
	165
0aa27725 RS	166	2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
	167
	168	* mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
	169	single-float. Disable ll, lld, sc and scd for EE. Disable the
	170	trunc.w.s macro for EE.
	171
36591ba1 SL	172	2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
	173	Andrew Jenner <andrew@codesourcery.com>
	174
	175	Based on patches from Altera Corporation.
	176
	177	* Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
	178	nios2-opc.c.
	179	* Makefile.in: Regenerated.
	180	* configure.in: Add case for bfd_nios2_arch.
	181	* configure: Regenerated.
	182	* disassemble.c (ARCH_nios2): Define.
	183	(disassembler): Add case for bfd_arch_nios2.
	184	* nios2-dis.c: New file.
	185	* nios2-opc.c: New file.
	186
545093a4 AM	187	2013-02-04 Alan Modra <amodra@gmail.com>
	188
	189	* po/POTFILES.in: Regenerate.
	190	* rl78-decode.c: Regenerate.
	191	* rx-decode.c: Regenerate.
	192
e30181a5 YZ	193	2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
	194
	195	* aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
	196	ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
	197	* aarch64-asm.c (convert_xtl_to_shll): New function.
	198	(convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	199	calling convert_xtl_to_shll.
	200	* aarch64-dis.c (convert_shll_to_xtl): New function.
	201	(convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	202	calling convert_shll_to_xtl.
	203	* aarch64-gen.c: Update copyright year.
	204	* aarch64-asm-2.c: Re-generate.
	205	* aarch64-dis-2.c: Re-generate.
	206	* aarch64-opc-2.c: Re-generate.
	207
78c8d46c NC	208	2013-01-24 Nick Clifton <nickc@redhat.com>
	209
	210	* v850-dis.c: Add support for e3v5 architecture.
	211	* v850-opc.c: Likewise.
	212
f5555712 YZ	213	2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
	214
	215	* aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
	216	* aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
	217	* aarch64-opc.c (operand_general_constraint_met_p): For
78c8d46c	218	AARCH64_MOD_LSL, move the range check on the shift amount before the
f5555712 YZ	219	alignment check; change to call set_sft_amount_out_of_range_error
	220	instead of set_imm_out_of_range_error.
	221	* aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
	222	(aarch64_opcode_table): Remove the OP enumerator from the asimdimm
	223	8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
	224	SIMD_IMM_SFT.
	225
2f81ff92 L	226	2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
	227
	228	* i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
	229
	230	* i386-init.h: Regenerated.
	231	* i386-tbl.h: Likewise.
	232
dd42f060 NC	233	2013-01-15 Nick Clifton <nickc@redhat.com>
	234
	235	* v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
	236	values.
	237	* v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
	238
a4533ed8 NC	239	2013-01-14 Will Newton <will.newton@imgtec.com>
	240
	241	* metag-dis.c (REG_WIDTH): Increase to 64.
	242
5817ffd1 PB	243	2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
	244
	245	* ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
	246	* ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
	247	XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
	248	(SH6): Update.
	249	<"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
	250	"tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
	251	"treclaim.", "tsr.">: Add POWER8 HTM opcodes.
	252	<"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
	253
a3c62988 NC	254	2013-01-10 Will Newton <will.newton@imgtec.com>
	255
	256	* Makefile.am: Add Meta.
	257	* configure.in: Add Meta.
	258	* disassemble.c: Add Meta support.
	259	* metag-dis.c: New file.
	260	* Makefile.in: Regenerate.
	261	* configure: Regenerate.
	262
73335eae NC	263	2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
	264
	265	* cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
	266	(match_opcode): Rename to cr16_match_opcode.
	267
e407c74b NC	268	2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
	269
	270	* mips-dis.c: Add names for CP0 registers of r5900.
	271	* mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
	272	instructions sq and lq.
	273	Add support for MIPS r5900 CPU.
	274	Add support for 128 bit MMI (Multimedia Instructions).
	275	Add support for EE instructions (Emotion Engine).
	276	Disable unsupported floating point instructions (64 bit and
	277	undefined compare operations).
	278	Enable instructions of MIPS ISA IV which are supported by r5900.
	279	Disable 64 bit co processor instructions.
	280	Disable 64 bit multiplication and division instructions.
	281	Disable instructions for co-processor 2 and 3, because these are
	282	not supported (preparation for later VU0 support (Vector Unit)).
	283	Disable cvt.w.s because this behaves like trunc.w.s and the
	284	correct execution can't be ensured on r5900.
	285	Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
	286	will confuse less developers and compilers.
	287
a32c3ff8 NC	288	2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
a32c3ff8 NC	289
fb098a1e YZ	290	* aarch64-opc.c (aarch64_print_operand): Change to print
	291	AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
	292	in comment.
	293	* aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
	294	from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
	295	OP_MOV_IMM_WIDE.
	296
	297	2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
	298
	299	* aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
	300	PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
a32c3ff8	301
62658407 L	302	2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
	303
	304	* i386-gen.c (process_copyright): Update copyright year to 2013.
	305
bab4becb	306	2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
5bf135a7	307
bab4becb NC	308	* cr16-dis.c (match_opcode,make_instruction): Remove static
	309	declaration.
	310	(dwordU,wordU): Moved typedefs to opcode/cr16.h
	311	(cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
5bf135a7	312
bab4becb	313	For older changes see ChangeLog-2012
252b5132	314	\f
bab4becb	315	Copyright (C) 2013 Free Software Foundation, Inc.
752937aa NC	316
	317	Copying and distribution of this file, with or without modification,
	318	are permitted in any medium without royalty provided the copyright
	319	notice and this notice are preserved.
	320
252b5132	321	Local Variables:
2f6d2f85 NC	322	mode: change-log
	323	left-margin: 8
	324	fill-column: 74
252b5132 RH	325	version-control: never
252b5132 RH	326	End: