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ns32k: remove dupplicate definition of input_line_pointer
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
1fe0971e
TS		 12016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
2
3 * nds32-asm.h: Add extern "C".
4 * sh-opc.h: Likewise.
5
315f180f
GM		 62016-06-01 Graham Markall <graham.markall@embecosm.com>
7
8 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
9 0,b,limm to the rflt instruction.
10
a2b5fccc
TS		 112016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
12
13 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
14 constant.
15
0cbd0046
L		 162016-05-29 H.J. Lu <hongjiu.lu@intel.com>
17
18 PR gas/20145
19 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
20 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
21 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
22 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
23 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
24 * i386-init.h: Regenerated.
25
1848e567
L		 262016-05-27 H.J. Lu <hongjiu.lu@intel.com>
27
28 PR gas/20145
29 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
30 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
31 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
32 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
33 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
34 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
35 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
36 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
37 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
38 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
39 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
40 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
41 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
42 CpuRegMask for AVX512.
43 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
44 and CpuRegMask.
45 (set_bitfield_from_cpu_flag_init): New function.
46 (set_bitfield): Remove const on f. Call
47 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
48 * i386-opc.h (CpuRegMMX): New.
49 (CpuRegXMM): Likewise.
50 (CpuRegYMM): Likewise.
51 (CpuRegZMM): Likewise.
52 (CpuRegMask): Likewise.
53 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
54 and cpuregmask.
55 * i386-init.h: Regenerated.
56 * i386-tbl.h: Likewise.
57
e92bae62
L		 582016-05-27 H.J. Lu <hongjiu.lu@intel.com>
59
60 PR gas/20154
61 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
62 (opcode_modifiers): Add AMD64 and Intel64.
63 (main): Properly verify CpuMax.
64 * i386-opc.h (CpuAMD64): Removed.
65 (CpuIntel64): Likewise.
66 (CpuMax): Set to CpuNo64.
67 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
68 (AMD64): New.
69 (Intel64): Likewise.
70 (i386_opcode_modifier): Add amd64 and intel64.
71 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
72 on call and jmp.
73 * i386-init.h: Regenerated.
74 * i386-tbl.h: Likewise.
75
e89c5eaa
L		 762016-05-27 H.J. Lu <hongjiu.lu@intel.com>
77
78 PR gas/20154
79 * i386-gen.c (main): Fail if CpuMax is incorrect.
80 * i386-opc.h (CpuMax): Set to CpuIntel64.
81 * i386-tbl.h: Regenerated.
82
77d66e7b
NC		 832016-05-27 Nick Clifton <nickc@redhat.com>
84
85 PR target/20150
86 * msp430-dis.c (msp430dis_read_two_bytes): New function.
87 (msp430dis_opcode_unsigned): New function.
88 (msp430dis_opcode_signed): New function.
89 (msp430_singleoperand): Use the new opcode reading functions.
90 Only disassenmble bytes if they were successfully read.
91 (msp430_doubleoperand): Likewise.
92 (msp430_branchinstr): Likewise.
93 (msp430x_callx_instr): Likewise.
94 (print_insn_msp430): Check that it is safe to read bytes before
95 attempting disassembly. Use the new opcode reading functions.
96
19dfcc89
PB		 972016-05-26 Peter Bergner <bergner@vnet.ibm.com>
98
99 * ppc-opc.c (CY): New define. Document it.
100 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
101
f3ad7637
L		 1022016-05-25 H.J. Lu <hongjiu.lu@intel.com>
103
104 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
105 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
106 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
107 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
108 CPU_ANY_AVX_FLAGS.
109 * i386-init.h: Regenerated.
110
f1360d58
L		 1112016-05-25 H.J. Lu <hongjiu.lu@intel.com>
112
113 PR gas/20141
114 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
115 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
116 * i386-init.h: Regenerated.
117
293f5f65
L		 1182016-05-25 H.J. Lu <hongjiu.lu@intel.com>
119
120 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
121 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
122 * i386-init.h: Regenerated.
123
d9eca1df
CZ		 1242016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
125
126 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
127 information.
128 (print_insn_arc): Set insn_type information.
129 * arc-opc.c (C_CC): Add F_CLASS_COND.
130 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
131 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
132 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
133 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
134 (brne, brne_s, jeq_s, jne_s): Likewise.
135
87789e08
CZ		 1362016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
137
138 * arc-tbl.h (neg): New instruction variant.
139
c810e0b8
CZ		 1402016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
141
142 * arc-dis.c (find_format, find_format, get_auxreg)
143 (print_insn_arc): Changed.
144 * arc-ext.h (INSERT_XOP): Likewise.
145
3d207518
TS		 1462016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
147
148 * tic54x-dis.c (sprint_mmr): Adjust.
149 * tic54x-opc.c: Likewise.
150
514e58b7
AM		 1512016-05-19 Alan Modra <amodra@gmail.com>
152
153 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
154
e43de63c
AM		 1552016-05-19 Alan Modra <amodra@gmail.com>
156
157 * ppc-opc.c: Formatting.
158 (NSISIGNOPT): Define.
159 (powerpc_opcodes <subis>): Use NSISIGNOPT.
160
1401d2fe
MR		 1612016-05-18 Maciej W. Rozycki <macro@imgtec.com>
162
163 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
164 replacing references to `micromips_ase' throughout.
165 (_print_insn_mips): Don't use file-level microMIPS annotation to
166 determine the disassembly mode with the symbol table.
167
1178da44
PB		 1682016-05-13 Peter Bergner <bergner@vnet.ibm.com>
169
170 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
171
8f4f9071
MF		 1722016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
173
174 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
175 mips64r6.
176 * mips-opc.c (D34): New macro.
177 (mips_builtin_opcodes): Define bposge32c for DSPr3.
178
8bc52696
AF		 1792016-05-10 Alexander Fomin <alexander.fomin@intel.com>
180
181 * i386-dis.c (prefix_table): Add RDPID instruction.
182 * i386-gen.c (cpu_flag_init): Add RDPID flag.
183 (cpu_flags): Add RDPID bitfield.
184 * i386-opc.h (enum): Add RDPID element.
185 (i386_cpu_flags): Add RDPID field.
186 * i386-opc.tbl: Add RDPID instruction.
187 * i386-init.h: Regenerate.
188 * i386-tbl.h: Regenerate.
189
39d911fc
TP		 1902016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
191
192 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
193 branch type of a symbol.
194 (print_insn): Likewise.
195
16a1fa25
TP		 1962016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
197
198 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
199 Mainline Security Extensions instructions.
200 (thumb_opcodes): Add entries for narrow ARMv8-M Security
201 Extensions instructions.
202 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
203 instructions.
204 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
205 special registers.
206
d751b79e
JM		 2072016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
208
209 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
210
945e0f82
CZ		 2112016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
212
213 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
214 (arcExtMap_genOpcode): Likewise.
215 * arc-opc.c (arg_32bit_rc): Define new variable.
216 (arg_32bit_u6): Likewise.
217 (arg_32bit_limm): Likewise.
218
20f55f38
SN		 2192016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
220
221 * aarch64-gen.c (VERIFIER): Define.
222 * aarch64-opc.c (VERIFIER): Define.
223 (verify_ldpsw): Use static linkage.
224 * aarch64-opc.h (verify_ldpsw): Remove.
225 * aarch64-tbl.h: Use VERIFIER for verifiers.
226
4bd13cde
NC		 2272016-04-28 Nick Clifton <nickc@redhat.com>
228
229 PR target/19722
230 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
231 * aarch64-opc.c (verify_ldpsw): New function.
232 * aarch64-opc.h (verify_ldpsw): New prototype.
233 * aarch64-tbl.h: Add initialiser for verifier field.
234 (LDPSW): Set verifier to verify_ldpsw.
235
c0f92bf9
L		 2362016-04-23 H.J. Lu <hongjiu.lu@intel.com>
237
238 PR binutils/19983
239 PR binutils/19984
240 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
241 smaller than address size.
242
e6c7cdec
TS		 2432016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
244
245 * alpha-dis.c: Regenerate.
246 * crx-dis.c: Likewise.
247 * disassemble.c: Likewise.
248 * epiphany-opc.c: Likewise.
249 * fr30-opc.c: Likewise.
250 * frv-opc.c: Likewise.
251 * ip2k-opc.c: Likewise.
252 * iq2000-opc.c: Likewise.
253 * lm32-opc.c: Likewise.
254 * lm32-opinst.c: Likewise.
255 * m32c-opc.c: Likewise.
256 * m32r-opc.c: Likewise.
257 * m32r-opinst.c: Likewise.
258 * mep-opc.c: Likewise.
259 * mt-opc.c: Likewise.
260 * or1k-opc.c: Likewise.
261 * or1k-opinst.c: Likewise.
262 * tic80-opc.c: Likewise.
263 * xc16x-opc.c: Likewise.
264 * xstormy16-opc.c: Likewise.
265
537aefaf
AB		 2662016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
267
268 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
269 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
270 calcsd, and calcxd instructions.
271 * arc-opc.c (insert_nps_bitop_size): Delete.
272 (extract_nps_bitop_size): Delete.
273 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
274 (extract_nps_qcmp_m3): Define.
275 (extract_nps_qcmp_m2): Define.
276 (extract_nps_qcmp_m1): Define.
277 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
278 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
279 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
280 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
281 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
282 NPS_QCMP_M3.
283
c8f785f2
AB		 2842016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
285
286 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
287
6fd8e7c2
L		 2882016-04-15 H.J. Lu <hongjiu.lu@intel.com>
289
290 * Makefile.in: Regenerated with automake 1.11.6.
291 * aclocal.m4: Likewise.
292
4b0c052e
AB		 2932016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
294
295 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
296 instructions.
297 * arc-opc.c (insert_nps_cmem_uimm16): New function.
298 (extract_nps_cmem_uimm16): New function.
299 (arc_operands): Add NPS_XLDST_UIMM16 operand.
300
cb040366
AB		 3012016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
302
303 * arc-dis.c (arc_insn_length): New function.
304 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
305 (find_format): Change insnLen parameter to unsigned.
306
accc0180
NC		 3072016-04-13 Nick Clifton <nickc@redhat.com>
308
309 PR target/19937
310 * v850-opc.c (v850_opcodes): Correct masks for long versions of
311 the LD.B and LD.BU instructions.
312
f36e33da
CZ		 3132016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
314
315 * arc-dis.c (find_format): Check for extension flags.
316 (print_flags): New function.
317 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
318 .extAuxRegister.
319 * arc-ext.c (arcExtMap_coreRegName): Use
320 LAST_EXTENSION_CORE_REGISTER.
321 (arcExtMap_coreReadWrite): Likewise.
322 (dump_ARC_extmap): Update printing.
323 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
324 (arc_aux_regs): Add cpu field.
325 * arc-regs.h: Add cpu field, lower case name aux registers.
326
1c2e355e
CZ		 3272016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
328
329 * arc-tbl.h: Add rtsc, sleep with no arguments.
330
b99747ae
CZ		 3312016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
332
333 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
334 Initialize.
335 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
336 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
337 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
338 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
339 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
340 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
341 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
342 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
343 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
344 (arc_opcode arc_opcodes): Null terminate the array.
345 (arc_num_opcodes): Remove.
346 * arc-ext.h (INSERT_XOP): Define.
347 (extInstruction_t): Likewise.
348 (arcExtMap_instName): Delete.
349 (arcExtMap_insn): New function.
350 (arcExtMap_genOpcode): Likewise.
351 * arc-ext.c (ExtInstruction): Remove.
352 (create_map): Zero initialize instruction fields.
353 (arcExtMap_instName): Remove.
354 (arcExtMap_insn): New function.
355 (dump_ARC_extmap): More info while debuging.
356 (arcExtMap_genOpcode): New function.
357 * arc-dis.c (find_format): New function.
358 (print_insn_arc): Use find_format.
359 (arc_get_disassembler): Enable dump_ARC_extmap only when
360 debugging.
361
92708cec
MR		 3622016-04-11 Maciej W. Rozycki <macro@imgtec.com>
363
364 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
365 instruction bits out.
366
a42a4f84
AB		 3672016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
368
369 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
370 * arc-opc.c (arc_flag_operands): Add new flags.
371 (arc_flag_classes): Add new classes.
372
1328504b
AB		 3732016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
374
375 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
376
820f03ff
AB		 3772016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
378
379 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
380 encode1, rflt, crc16, and crc32 instructions.
381 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
382 (arc_flag_classes): Add C_NPS_R.
383 (insert_nps_bitop_size_2b): New function.
384 (extract_nps_bitop_size_2b): Likewise.
385 (insert_nps_bitop_uimm8): Likewise.
386 (extract_nps_bitop_uimm8): Likewise.
387 (arc_operands): Add new operand entries.
388
8ddf6b2a
CZ		 3892016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
390
b99747ae
CZ		 391 * arc-regs.h: Add a new subclass field. Add double assist
392 accumulator register values.
393 * arc-tbl.h: Use DPA subclass to mark the double assist
394 instructions. Use DPX/SPX subclas to mark the FPX instructions.
395 * arc-opc.c (RSP): Define instead of SP.
396 (arc_aux_regs): Add the subclass field.
8ddf6b2a 397
589a7d88
JW		 3982016-04-05 Jiong Wang <jiong.wang@arm.com>
399
400 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
401
0a191de9 4022016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 403
404 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
405 NPS_R_SRC1.
406
0a106562
AB		 4072016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
408
409 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
410 issues. No functional changes.
411
bd05ac5f
CZ		 4122016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
413
b99747ae
CZ		 414 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
415 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
416 (RTT): Remove duplicate.
417 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
418 (PCT_CONFIG*): Remove.
419 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 420
9885948f
CZ		 4212016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
422
b99747ae 423 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 424
f2dd8838
CZ		 4252016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
426
b99747ae
CZ		 427 * arc-tbl.h (invld07): Remove.
428 * arc-ext-tbl.h: New file.
429 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
430 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 431
0d2f91fe
JK		 4322016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
433
434 Fix -Wstack-usage warnings.
435 * aarch64-dis.c (print_operands): Substitute size.
436 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
437
a6b71f42
JM		 4382016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
439
440 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
441 to get a proper diagnostic when an invalid ASR register is used.
442
9780e045
NC		 4432016-03-22 Nick Clifton <nickc@redhat.com>
444
445 * configure: Regenerate.
446
e23e8ebe
AB		 4472016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
448
449 * arc-nps400-tbl.h: New file.
450 * arc-opc.c: Add top level comment.
451 (insert_nps_3bit_dst): New function.
452 (extract_nps_3bit_dst): New function.
453 (insert_nps_3bit_src2): New function.
454 (extract_nps_3bit_src2): New function.
455 (insert_nps_bitop_size): New function.
456 (extract_nps_bitop_size): New function.
457 (arc_flag_operands): Add nps400 entries.
458 (arc_flag_classes): Add nps400 entries.
459 (arc_operands): Add nps400 entries.
460 (arc_opcodes): Add nps400 include.
461
1ae8ab47
AB		 4622016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
463
464 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
465 the new class enum values.
466
8699fc3e
AB		 4672016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
468
469 * arc-dis.c (print_insn_arc): Handle nps400.
470
24740d83
AB		 4712016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
472
473 * arc-opc.c (BASE): Delete.
474
8678914f
NC		 4752016-03-18 Nick Clifton <nickc@redhat.com>
476
477 PR target/19721
478 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
479 of MOV insn that aliases an ORR insn.
480
cc933301
JW		 4812016-03-16 Jiong Wang <jiong.wang@arm.com>
482
483 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
484
f86f5863
TS		 4852016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
486
487 * mcore-opc.h: Add const qualifiers.
488 * microblaze-opc.h (struct op_code_struct): Likewise.
489 * sh-opc.h: Likewise.
490 * tic4x-dis.c (tic4x_print_indirect): Likewise.
491 (tic4x_print_op): Likewise.
492
62de1c63
AM		 4932016-03-02 Alan Modra <amodra@gmail.com>
494
d11698cd 495 * or1k-desc.h: Regenerate.
62de1c63 496 * fr30-ibld.c: Regenerate.
c697cf0b 497 * rl78-decode.c: Regenerate.
62de1c63 498
020efce5
NC		 4992016-03-01 Nick Clifton <nickc@redhat.com>
500
501 PR target/19747
502 * rl78-dis.c (print_insn_rl78_common): Fix typo.
503
b0c11777
RL		 5042016-02-24 Renlin Li <renlin.li@arm.com>
505
506 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
507 (print_insn_coprocessor): Support fp16 instructions.
508
3e309328
RL		 5092016-02-24 Renlin Li <renlin.li@arm.com>
510
511 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
512 vminnm, vrint(mpna).
513
8afc7bea
RL		 5142016-02-24 Renlin Li <renlin.li@arm.com>
515
516 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
517 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
518
4fd7268a
L		 5192016-02-15 H.J. Lu <hongjiu.lu@intel.com>
520
521 * i386-dis.c (print_insn): Parenthesize expression to prevent
522 truncated addresses.
523 (OP_J): Likewise.
524
4670103e
CZ		 5252016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
526 Janek van Oirschot <jvanoirs@synopsys.com>
527
b99747ae
CZ		 528 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
529 variable.
4670103e 530
c1d9289f
NC		 5312016-02-04 Nick Clifton <nickc@redhat.com>
532
533 PR target/19561
534 * msp430-dis.c (print_insn_msp430): Add a special case for
535 decoding an RRC instruction with the ZC bit set in the extension
536 word.
537
a143b004
AB		 5382016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
539
540 * cgen-ibld.in (insert_normal): Rework calculation of shift.
541 * epiphany-ibld.c: Regenerate.
542 * fr30-ibld.c: Regenerate.
543 * frv-ibld.c: Regenerate.
544 * ip2k-ibld.c: Regenerate.
545 * iq2000-ibld.c: Regenerate.
546 * lm32-ibld.c: Regenerate.
547 * m32c-ibld.c: Regenerate.
548 * m32r-ibld.c: Regenerate.
549 * mep-ibld.c: Regenerate.
550 * mt-ibld.c: Regenerate.
551 * or1k-ibld.c: Regenerate.
552 * xc16x-ibld.c: Regenerate.
553 * xstormy16-ibld.c: Regenerate.
554
b89807c6
AB		 5552016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
556
557 * epiphany-dis.c: Regenerated from latest cpu files.
558
d8c823c8
MM		 5592016-02-01 Michael McConville <mmcco@mykolab.com>
560
561 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
562 test bit.
563
5bc5ae88
RL		 5642016-01-25 Renlin Li <renlin.li@arm.com>
565
566 * arm-dis.c (mapping_symbol_for_insn): New function.
567 (find_ifthen_state): Call mapping_symbol_for_insn().
568
0bff6e2d
MW		 5692016-01-20 Matthew Wahab <matthew.wahab@arm.com>
570
571 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
572 of MSR UAO immediate operand.
573
100b4f2e
MR		 5742016-01-18 Maciej W. Rozycki <macro@imgtec.com>
575
576 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
577 instruction support.
578
5c14705f
AM		 5792016-01-17 Alan Modra <amodra@gmail.com>
580
581 * configure: Regenerate.
582
4d82fe66
NC		 5832016-01-14 Nick Clifton <nickc@redhat.com>
584
585 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
586 instructions that can support stack pointer operations.
587 * rl78-decode.c: Regenerate.
588 * rl78-dis.c: Fix display of stack pointer in MOVW based
589 instructions.
590
651657fa
MW		 5912016-01-14 Matthew Wahab <matthew.wahab@arm.com>
592
593 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
594 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
595 erxtatus_el1 and erxaddr_el1.
596
105bde57
MW		 5972016-01-12 Matthew Wahab <matthew.wahab@arm.com>
598
599 * arm-dis.c (arm_opcodes): Add "esb".
600 (thumb_opcodes): Likewise.
601
afa8d405
PB		 6022016-01-11 Peter Bergner <bergner@vnet.ibm.com>
603
604 * ppc-opc.c <xscmpnedp>: Delete.
605 <xvcmpnedp>: Likewise.
606 <xvcmpnedp.>: Likewise.
607 <xvcmpnesp>: Likewise.
608 <xvcmpnesp.>: Likewise.
609
83c3256e
AS		 6102016-01-08 Andreas Schwab <schwab@linux-m68k.org>
611
612 PR gas/13050
613 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
614 addition to ISA_A.
615
6f2750fe
AM		 6162016-01-01 Alan Modra <amodra@gmail.com>
617
618 Update year range in copyright notice of all files.
619
3499769a
AM		 620For older changes see ChangeLog-2015
621\f
622Copyright (C) 2016 Free Software Foundation, Inc.
623
624Copying and distribution of this file, with or without modification,
625are permitted in any medium without royalty provided the copyright
626notice and this notice are preserved.
627
628Local Variables:
629mode: change-log
630left-margin: 8
631fill-column: 74
632version-control: never
633End:
GDB Binutils - Deliverables
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