[deliverable/binutils-gdb.git] / opcodes / ChangeLog

2006-05-22  Nick Clifton  <nickc@redhat.com>

	* crx-dis.c (EXTRACT): Make macro work on 64-bit hosts.

2006-05-22  Nick Clifton  <nickc@redhat.com>

	* po/nl.po: Updated translation.

2006-05-18  Alan Modra  <amodra@bigpond.net.au>

	* avr-dis.c: Formatting fix.

2006-05-14  Thiemo Seufer  <ths@mips.com>

	* mips16-opc.c (I1, I32, I64): New shortcut defines.
	(mips16_opcodes): Change membership of instructions to their
	lowest baseline ISA.

2006-05-09  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (grps): Update sgdt/sidt for 64bit.

2006-05-05  Julian Brown  <julian@codesourcery.com>

	* arm-dis.c (coprocessor_opcodes): Don't interpret fldmx/fstmx as
	vldm/vstm.

2006-05-05  Thiemo Seufer  <ths@mips.com>
            David Ung  <davidu@mips.com>

	* mips-opc.c: Add macro for cache instruction.

2006-05-04  Thiemo Seufer  <ths@mips.com>
            Nigel Stephens  <nigel@mips.com>
	    David Ung  <davidu@mips.com>

	* mips-dis.c (mips_arch_choices): Add smartmips instruction
	decoding to MIPS32 and MIPS32R2.  Limit DSP decoding to release
	2 ISAs.  Add MIPS3D decoding to MIPS32R2.  Add MT decoding to
	MIPS64R2.
	* mips-opc.c: fix random typos in comments.
	(INSN_SMARTMIPS): New defines.
	(mips_builtin_opcodes): Add paired single support for MIPS32R2.
	Move bc3f, bc3fl, bc3t, bc3tl downwards.  Move flushi, flushd,
	flushid, wb upwards.  Move cfc3, ctc3 downwards.  Rework the
	FP_S and FP_D flags to denote single and double register
	accesses separately.  Move dmfc3, dmtc3, mfc3, mtc3 downwards.
	Allow jr.hb and jalr.hb for release 1 ISAs.  Allow luxc1, suxc1
	for MIPS32R2.  Add SmartMIPS instructions.  Add two-argument
	variants of bc2f, bc2fl, bc2t, bc2tl.  Add mfhc2, mthc2 to
	release 2 ISAs.
	* mips16-opc.c (mips16_opcodes): Add sdbbp instruction.

2006-05-03  Thiemo Seufer  <ths@mips.com>

	* mips-opc.c (mips_builtin_opcodes): Fix mftr argument order.

2006-05-02  Thiemo Seufer  <ths@mips.com>
            Nigel Stephens  <nigel@mips.com>
            David Ung  <davidu@mips.com>

	* mips-dis.c (print_insn_args): Force mips16 to odd addresses.
	(print_mips16_insn_arg): Force mips16 to odd addresses.

2006-04-30  Thiemo Seufer  <ths@mips.com>
            David Ung  <davidu@mips.com>

	* mips-opc.c (mips_builtin_opcodes): Add udi instructions
	"udi0" to "udi15".
	* mips-dis.c (print_insn_args): Adds udi argument handling.

2006-04-28  James E Wilson  <wilson@specifix.com>

	* m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing
	error message.

2006-04-28  Thiemo Seufer  <ths@mips.com>
            David Ung  <davidu@mips.com>
	    Nigel Stephens  <nigel@mips.com>

	* mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register
	names.

2006-04-28  Thiemo Seufer  <ths@mips.com>
            Nigel Stephens  <nigel@mips.com>
            David Ung  <davidu@mips.com>

	* mips-dis.c (print_insn_args): Add mips_opcode argument.
	(print_insn_mips):  Adjust print_insn_args call.

2006-04-28  Thiemo Seufer  <ths@mips.com>
            Nigel Stephens  <nigel@mips.com>

	* mips-dis.c (print_insn_args): Print $fcc only for FP
	instructions, use $cc elsewise.

2006-04-28  Thiemo Seufer  <ths@mips.com>
            Nigel Stephens  <nigel@mips.com>

	* opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names):
	Map MIPS16 registers to O32 names.
	(print_mips16_insn_arg): Use mips16_reg_names.

2006-04-26  Julian Brown  <julian@codesourcery.com>

	* arm-dis.c (print_insn_neon): Disassemble floating-point constant
	VMOV.

2006-04-26  Nathan Sidwell  <nathan@codesourcery.com>
	    Julian Brown  <julian@codesourcery.com>

	* opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convert
	%<code>[zy] into %[zy]<code>.  Expand meaning of %<bitfield>['`?].
	Add unified load/store instruction names.
	(neon_opcode_table): New.
	(arm_opcodes): Expand meaning of %<bitfield>['`?].
	(arm_decode_bitfield): New.
	(print_insn_coprocessor): Add pc argument. Add %A & %B specifiers.
	Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y.
	(print_insn_neon): New.
	(print_insn_arm): Adjust print_insn_coprocessor call. Call
	print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers.
	(print_insn_thumb32): Likewise.

2006-04-19  Alan Modra  <amodra@bigpond.net.au>

	* Makefile.am: Run "make dep-am".
	* Makefile.in: Regenerate.

2006-04-19  Alan Modra  <amodra@bigpond.net.au>

	* avr-dis.c (avr_operand): Warning fix.

	* configure: Regenerate.

2006-04-16  Daniel Jacobowitz  <dan@codesourcery.com>

	* po/POTFILES.in: Regenerated.

2006-04-12   Hochstein  <hochstein@algo.informatik.tu-darmstadt.de>

	PR binutils/2454
	* avr-dis.c (avr_operand): Arrange for a comment to appear before
	the symolic form of an address, so that the output of objdump -d
	can be reassembled.

2006-04-10  DJ Delorie  <dj@redhat.com>

	* m32c-asm.c: Regenerate.

2006-04-06  Carlos O'Donell  <carlos@codesourcery.com>

	* Makefile.am: Add install-html target.
	* Makefile.in: Regenerate.

2006-04-06  Nick Clifton  <nickc@redhat.com>

	* po/vi/po: Updated Vietnamese translation.

2006-03-31  Paul Koning  <ni1d@arrl.net>

	* pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction.

2006-03-16  Bernd Schmidt  <bernd.schmidt@analog.com>

	* bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the
	logic to identify halfword shifts.

2006-03-16  Paul Brook  <paul@codesourcery.com>

	* arm-dis.c (arm_opcodes): Rename swi to svc.
	(thumb_opcodes): Ditto.

2006-03-13  DJ Delorie  <dj@redhat.com>

	* m32c-asm.c: Regenerate.
	* m32c-desc.c: Likewise.
	* m32c-desc.h: Likewise.
	* m32c-dis.c: Likewise.
	* m32c-ibld.c: Likewise.
	* m32c-opc.c: Likewise.
	* m32c-opc.h: Likewise.

2006-03-10  DJ Delorie  <dj@redhat.com>

	* m32c-desc.c: Regenerate with mul.l, mulu.l.
	* m32c-opc.c: Likewise.
	* m32c-opc.h: Likewise.


2006-03-09  Nick Clifton  <nickc@redhat.com>

	* po/sv.po: Updated Swedish translation.

2006-03-07  H.J. Lu  <hongjiu.lu@intel.com>

	PR binutils/2428
	* i386-dis.c (REP_Fixup): New function.
	(AL): Remove duplicate.
	(Xbr): New.
	(Xvr): Likewise.
	(Ybr): Likewise.
	(Yvr): Likewise.
	(indirDXr): Likewise.
	(ALr): Likewise.
	(eAXr): Likewise.
	(dis386): Updated entries of ins, outs, movs, lods and stos.

2006-03-05  Nick Clifton  <nickc@redhat.com>

	* cgen-ibld.in (insert_normal): Cope with attempts to insert a
	signed 32-bit value into an unsigned 32-bit field when the host is
	a 64-bit machine.
	* fr30-ibld.c: Regenerate.
	* frv-ibld.c: Regenerate.
	* ip2k-ibld.c: Regenerate.
	* iq2000-asm.c: Regenerate.
	* iq2000-ibld.c: Regenerate.
	* m32c-ibld.c: Regenerate.
	* m32r-ibld.c: Regenerate.
	* openrisc-ibld.c: Regenerate.
	* xc16x-ibld.c: Regenerate.
	* xstormy16-ibld.c: Regenerate.

2006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)

	* xc16x-asm.c: Regenerate.
	* xc16x-dis.c: Regenerate.

2006-02-27  Carlos O'Donell  <carlos@codesourcery.com>

	* po/Make-in: Add html target.

2006-02-27  H.J. Lu <hongjiu.lu@intel.com>

	* i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
	Intel Merom New Instructions.
	(THREE_BYTE_0): Likewise.
	(THREE_BYTE_1): Likewise.
	(three_byte_table): Likewise.
	(dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
	THREE_BYTE_1 for entry 0x3a.
	(twobyte_has_modrm): Updated.
	(twobyte_uses_SSE_prefix): Likewise.
	(print_insn): Handle 3-byte opcodes used by Intel Merom New
	Instructions.

2006-02-24  David S. Miller  <davem@sunset.davemloft.net>

	* sparc-dis.c (v9_priv_reg_names): Add "gl" entry.
	(v9_hpriv_reg_names): New table.
	(print_insn_sparc): Allow values up to 16 for '?' and '!'.
	New cases '$' and '%' for read/write hyperprivileged register.
	* sparc-opc.c (sparc_opcodes): Add new entries for UA2005
	window handling and rdhpr/wrhpr instructions.
	
2006-02-24  DJ Delorie  <dj@redhat.com>

	* m32c-desc.c: Regenerate with linker relaxation attributes.
	* m32c-desc.h: Likewise.
	* m32c-dis.c: Likewise.
	* m32c-opc.c: Likewise.

2006-02-24  Paul Brook  <paul@codesourcery.com>

	* arm-dis.c (arm_opcodes): Add V7 instructions.
	(thumb32_opcodes): Ditto.  Handle V7M MSR/MRS variants.
	(print_arm_address): New function.
	(print_insn_arm): Use it.  Add 'P' and 'U' cases.
	(psr_name): New function.
	(print_insn_thumb32): Add 'U', 'C' and 'D' cases.

2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>

	* ia64-opc-i.c (bXc): New.
	(mXc): Likewise.
	(OpX2TaTbYaXcC): Likewise.
	(TF). Likewise.
	(TFCM). Likewise.
	(ia64_opcodes_i): Add instructions for tf.

	* ia64-opc.h (IMMU5b): New.

	* ia64-asmtab.c: Regenerated.

2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>

	* ia64-gen.c: Update copyright years.
	* ia64-opc-b.c: Likewise.

2006-02-22  H.J. Lu  <hongjiu.lu@intel.com>

	* ia64-gen.c (lookup_regindex): Handle ".vm".
	(print_dependency_table): Handle '\"'.

	* ia64-ic.tbl: Updated from SDM 2.2.
	* ia64-raw.tbl: Likewise.
	* ia64-waw.tbl: Likewise.
	* ia64-asmtab.c: Regenerated.

	* ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.

2006-02-17  Shrirang Khisti  <shrirangk@kpitcummins.com>
            Anil Paranjape   <anilp1@kpitcummins.com>
            Shilin Shakti    <shilins@kpitcummins.com>

	* xc16x-desc.h: New file
	* xc16x-desc.c: New file
	* xc16x-opc.h: New file	
	* xc16x-opc.c: New file
	* xc16x-ibld.c: New file
	* xc16x-asm.c: New file
	* xc16x-dis.c: New file
	* Makefile.am: Entries for xc16x 
	* Makefile.in: Regenerate 
	* cofigure.in: Add xc16x target information.
	* configure: Regenerate.
	* disassemble.c: Add xc16x target information.

2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (dis386_twobyte): Use "movZ" for debug register
	moves.

2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c ('Z'): Add a new macro.
	(dis386_twobyte): Use "movZ" for control register moves.

2006-02-10  Nick Clifton  <nickc@redhat.com>

	* iq2000-asm.c: Regenerate.

2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>

	* m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features.

2006-01-26  David Ung  <davidu@mips.com>

	* mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx,
	ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
	floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
	nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
	rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.

2006-01-18  Arnold Metselaar  <arnoldm@sourceware.org>

	* z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d,
	ld_d_r, pref_xd_cb): Use signed char to hold data to be
	disassembled.	
	* z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes
	buffer overflows when disassembling instructions like
	ld (ix+123),0x23
	* z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed
	operand, if the offset is negative.

2006-01-17  Arnold Metselaar  <arnoldm@sourceware.org>

	* z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use
	unsigned char to hold data to be disassembled.

2006-01-17  Andreas Schwab  <schwab@suse.de>

	PR binutils/1486
	* disassemble.c (disassemble_init_for_target): Set
	disassembler_needs_relocs for bfd_arch_arm.

2006-01-16  Paul Brook  <paul@codesourcery.com>

	* m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss,
	f?add?, and f?sub? instructions.

2006-01-16  Nick Clifton  <nickc@redhat.com>

	* po/zh_CN.po: New Chinese (simplified) translation.
	* configure.in (ALL_LINGUAS): Add "zh_CH".
	* configure: Regenerate.

2006-01-05  Paul Brook  <paul@codesourcery.com>

	* m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry.

2006-01-06  DJ Delorie  <dj@redhat.com>

	* m32c-desc.c: Regenerate.
	* m32c-opc.c: Regenerate.
	* m32c-opc.h: Regenerate.

2006-01-03  DJ Delorie  <dj@redhat.com>

	* cgen-ibld.in (extract_normal): Avoid memory range errors.
	* m32c-ibld.c: Regenerated.

For older changes see ChangeLog-2005
\f
Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
Commit	Line	Data
a854efa3 NC	1	2006-05-22 Nick Clifton <nickc@redhat.com>
	2
	3	* crx-dis.c (EXTRACT): Make macro work on 64-bit hosts.
	4
0bd79061 NC	5	2006-05-22 Nick Clifton <nickc@redhat.com>
	6
	7	* po/nl.po: Updated translation.
	8
00988f49 AM	9	2006-05-18 Alan Modra <amodra@bigpond.net.au>
	10
	11	* avr-dis.c: Formatting fix.
	12
9b3f89ee TS	13	2006-05-14 Thiemo Seufer <ths@mips.com>
	14
	15	* mips16-opc.c (I1, I32, I64): New shortcut defines.
	16	(mips16_opcodes): Change membership of instructions to their
	17	lowest baseline ISA.
	18
cb6d3433 L	19	2006-05-09 H.J. Lu <hongjiu.lu@intel.com>
	20
	21	* i386-dis.c (grps): Update sgdt/sidt for 64bit.
	22
1f3c39b9 JB	23	2006-05-05 Julian Brown <julian@codesourcery.com>
	24
	25	* arm-dis.c (coprocessor_opcodes): Don't interpret fldmx/fstmx as
	26	vldm/vstm.
	27
d43b4baf TS	28	2006-05-05 Thiemo Seufer <ths@mips.com>
	29	David Ung <davidu@mips.com>
	30
	31	* mips-opc.c: Add macro for cache instruction.
	32
39a7806d TS	33	2006-05-04 Thiemo Seufer <ths@mips.com>
	34	Nigel Stephens <nigel@mips.com>
	35	David Ung <davidu@mips.com>
	36
	37	* mips-dis.c (mips_arch_choices): Add smartmips instruction
	38	decoding to MIPS32 and MIPS32R2. Limit DSP decoding to release
	39	2 ISAs. Add MIPS3D decoding to MIPS32R2. Add MT decoding to
	40	MIPS64R2.
	41	* mips-opc.c: fix random typos in comments.
	42	(INSN_SMARTMIPS): New defines.
	43	(mips_builtin_opcodes): Add paired single support for MIPS32R2.
	44	Move bc3f, bc3fl, bc3t, bc3tl downwards. Move flushi, flushd,
	45	flushid, wb upwards. Move cfc3, ctc3 downwards. Rework the
	46	FP_S and FP_D flags to denote single and double register
	47	accesses separately. Move dmfc3, dmtc3, mfc3, mtc3 downwards.
	48	Allow jr.hb and jalr.hb for release 1 ISAs. Allow luxc1, suxc1
	49	for MIPS32R2. Add SmartMIPS instructions. Add two-argument
	50	variants of bc2f, bc2fl, bc2t, bc2tl. Add mfhc2, mthc2 to
	51	release 2 ISAs.
	52	* mips16-opc.c (mips16_opcodes): Add sdbbp instruction.
	53
104b4fab TS	54	2006-05-03 Thiemo Seufer <ths@mips.com>
	55
	56	* mips-opc.c (mips_builtin_opcodes): Fix mftr argument order.
	57
022fac6d TS	58	2006-05-02 Thiemo Seufer <ths@mips.com>
	59	Nigel Stephens <nigel@mips.com>
	60	David Ung <davidu@mips.com>
	61
	62	* mips-dis.c (print_insn_args): Force mips16 to odd addresses.
	63	(print_mips16_insn_arg): Force mips16 to odd addresses.
	64
9bcd4f99 TS	65	2006-04-30 Thiemo Seufer <ths@mips.com>
	66	David Ung <davidu@mips.com>
	67
	68	* mips-opc.c (mips_builtin_opcodes): Add udi instructions
	69	"udi0" to "udi15".
	70	* mips-dis.c (print_insn_args): Adds udi argument handling.
	71
f095b97b JW	72	2006-04-28 James E Wilson <wilson@specifix.com>
	73
	74	* m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing
	75	error message.
	76
59c455b3 TS	77	2006-04-28 Thiemo Seufer <ths@mips.com>
59c455b3 TS	78	David Ung <davidu@mips.com>
bdb09db1	79	Nigel Stephens <nigel@mips.com>
59c455b3 TS	80
	81	* mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register
	82	names.
	83
cc0ca239	84	2006-04-28 Thiemo Seufer <ths@mips.com>
bdb09db1	85	Nigel Stephens <nigel@mips.com>
cc0ca239 TS	86	David Ung <davidu@mips.com>
	87
	88	* mips-dis.c (print_insn_args): Add mips_opcode argument.
	89	(print_insn_mips): Adjust print_insn_args call.
	90
0d09bfe6	91	2006-04-28 Thiemo Seufer <ths@mips.com>
bdb09db1	92	Nigel Stephens <nigel@mips.com>
0d09bfe6 TS	93
	94	* mips-dis.c (print_insn_args): Print $fcc only for FP
	95	instructions, use $cc elsewise.
	96
654c225a	97	2006-04-28 Thiemo Seufer <ths@mips.com>
bdb09db1	98	Nigel Stephens <nigel@mips.com>
654c225a TS	99
	100	* opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names):
	101	Map MIPS16 registers to O32 names.
	102	(print_mips16_insn_arg): Use mips16_reg_names.
	103
0dbde4cf JB	104	2006-04-26 Julian Brown <julian@codesourcery.com>
	105
	106	* arm-dis.c (print_insn_neon): Disassemble floating-point constant
	107	VMOV.
	108
16980d0b JB	109	2006-04-26 Nathan Sidwell <nathan@codesourcery.com>
	110	Julian Brown <julian@codesourcery.com>
	111
	112	* opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convert
	113	%<code>[zy] into %[zy]<code>. Expand meaning of %<bitfield>['`?].
	114	Add unified load/store instruction names.
	115	(neon_opcode_table): New.
	116	(arm_opcodes): Expand meaning of %<bitfield>['`?].
	117	(arm_decode_bitfield): New.
	118	(print_insn_coprocessor): Add pc argument. Add %A & %B specifiers.
	119	Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y.
	120	(print_insn_neon): New.
	121	(print_insn_arm): Adjust print_insn_coprocessor call. Call
	122	print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers.
	123	(print_insn_thumb32): Likewise.
	124
ec3fcc56 AM	125	2006-04-19 Alan Modra <amodra@bigpond.net.au>
	126
	127	* Makefile.am: Run "make dep-am".
	128	* Makefile.in: Regenerate.
	129
241a6c40 AM	130	2006-04-19 Alan Modra <amodra@bigpond.net.au>
241a6c40 AM	131
7c6646cd AM	132	* avr-dis.c (avr_operand): Warning fix.
7c6646cd AM	133
241a6c40 AM	134	* configure: Regenerate.
241a6c40 AM	135
e7403566 DJ	136	2006-04-16 Daniel Jacobowitz <dan@codesourcery.com>
	137
	138	* po/POTFILES.in: Regenerated.
	139
52f16a0e NC	140	2006-04-12 Hochstein <hochstein@algo.informatik.tu-darmstadt.de>
	141
	142	PR binutils/2454
	143	* avr-dis.c (avr_operand): Arrange for a comment to appear before
	144	the symolic form of an address, so that the output of objdump -d
	145	can be reassembled.
	146
e78efa90 DD	147	2006-04-10 DJ Delorie <dj@redhat.com>
	148
	149	* m32c-asm.c: Regenerate.
	150
108a6f8e CD	151	2006-04-06 Carlos O'Donell <carlos@codesourcery.com>
	152
	153	* Makefile.am: Add install-html target.
	154	* Makefile.in: Regenerate.
	155
a135cb2c NC	156	2006-04-06 Nick Clifton <nickc@redhat.com>
	157
	158	* po/vi/po: Updated Vietnamese translation.
	159
47426b41 AM	160	2006-03-31 Paul Koning <ni1d@arrl.net>
	161
	162	* pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction.
	163
331f1cbe BS	164	2006-03-16 Bernd Schmidt <bernd.schmidt@analog.com>
	165
	166	* bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the
	167	logic to identify halfword shifts.
	168
c16d2bf0 PB	169	2006-03-16 Paul Brook <paul@codesourcery.com>
	170
	171	* arm-dis.c (arm_opcodes): Rename swi to svc.
	172	(thumb_opcodes): Ditto.
	173
5348b81e DD	174	2006-03-13 DJ Delorie <dj@redhat.com>
5348b81e DD	175
5398310a DD	176	* m32c-asm.c: Regenerate.
	177	* m32c-desc.c: Likewise.
	178	* m32c-desc.h: Likewise.
	179	* m32c-dis.c: Likewise.
	180	* m32c-ibld.c: Likewise.
5348b81e DD	181	* m32c-opc.c: Likewise.
	182	* m32c-opc.h: Likewise.
	183
253d272c DD	184	2006-03-10 DJ Delorie <dj@redhat.com>
	185
	186	* m32c-desc.c: Regenerate with mul.l, mulu.l.
	187	* m32c-opc.c: Likewise.
	188	* m32c-opc.h: Likewise.
	189
	190
f530741d NC	191	2006-03-09 Nick Clifton <nickc@redhat.com>
	192
	193	* po/sv.po: Updated Swedish translation.
	194
35c52694 L	195	2006-03-07 H.J. Lu <hongjiu.lu@intel.com>
	196
	197	PR binutils/2428
	198	* i386-dis.c (REP_Fixup): New function.
	199	(AL): Remove duplicate.
	200	(Xbr): New.
	201	(Xvr): Likewise.
	202	(Ybr): Likewise.
	203	(Yvr): Likewise.
	204	(indirDXr): Likewise.
	205	(ALr): Likewise.
	206	(eAXr): Likewise.
	207	(dis386): Updated entries of ins, outs, movs, lods and stos.
	208
ed963e2d NC	209	2006-03-05 Nick Clifton <nickc@redhat.com>
	210
	211	* cgen-ibld.in (insert_normal): Cope with attempts to insert a
	212	signed 32-bit value into an unsigned 32-bit field when the host is
	213	a 64-bit machine.
	214	* fr30-ibld.c: Regenerate.
	215	* frv-ibld.c: Regenerate.
	216	* ip2k-ibld.c: Regenerate.
	217	* iq2000-asm.c: Regenerate.
	218	* iq2000-ibld.c: Regenerate.
	219	* m32c-ibld.c: Regenerate.
	220	* m32r-ibld.c: Regenerate.
	221	* openrisc-ibld.c: Regenerate.
	222	* xc16x-ibld.c: Regenerate.
	223	* xstormy16-ibld.c: Regenerate.
	224
c7d41dc5 NC	225	2006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)
	226
	227	* xc16x-asm.c: Regenerate.
	228	* xc16x-dis.c: Regenerate.
c7d41dc5	229
f7d9e5c3 CD	230	2006-02-27 Carlos O'Donell <carlos@codesourcery.com>
	231
	232	* po/Make-in: Add html target.
	233
331d2d0d L	234	2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
	235
	236	* i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
	237	Intel Merom New Instructions.
	238	(THREE_BYTE_0): Likewise.
	239	(THREE_BYTE_1): Likewise.
	240	(three_byte_table): Likewise.
	241	(dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
	242	THREE_BYTE_1 for entry 0x3a.
	243	(twobyte_has_modrm): Updated.
	244	(twobyte_uses_SSE_prefix): Likewise.
	245	(print_insn): Handle 3-byte opcodes used by Intel Merom New
	246	Instructions.
	247
ff3f9d5b DM	248	2006-02-24 David S. Miller <davem@sunset.davemloft.net>
	249
	250	* sparc-dis.c (v9_priv_reg_names): Add "gl" entry.
	251	(v9_hpriv_reg_names): New table.
	252	(print_insn_sparc): Allow values up to 16 for '?' and '!'.
	253	New cases '$' and '%' for read/write hyperprivileged register.
	254	* sparc-opc.c (sparc_opcodes): Add new entries for UA2005
	255	window handling and rdhpr/wrhpr instructions.
	256
6772dd07 DD	257	2006-02-24 DJ Delorie <dj@redhat.com>
	258
	259	* m32c-desc.c: Regenerate with linker relaxation attributes.
	260	* m32c-desc.h: Likewise.
	261	* m32c-dis.c: Likewise.
	262	* m32c-opc.c: Likewise.
	263
62b3e311 PB	264	2006-02-24 Paul Brook <paul@codesourcery.com>
	265
	266	* arm-dis.c (arm_opcodes): Add V7 instructions.
	267	(thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
	268	(print_arm_address): New function.
	269	(print_insn_arm): Use it. Add 'P' and 'U' cases.
	270	(psr_name): New function.
	271	(print_insn_thumb32): Add 'U', 'C' and 'D' cases.
	272
59cf82fe L	273	2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
	274
	275	* ia64-opc-i.c (bXc): New.
	276	(mXc): Likewise.
	277	(OpX2TaTbYaXcC): Likewise.
	278	(TF). Likewise.
	279	(TFCM). Likewise.
	280	(ia64_opcodes_i): Add instructions for tf.
	281
	282	* ia64-opc.h (IMMU5b): New.
	283
	284	* ia64-asmtab.c: Regenerated.
	285
19a7219f L	286	2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
	287
	288	* ia64-gen.c: Update copyright years.
	289	* ia64-opc-b.c: Likewise.
	290
7f3dfb9c L	291	2006-02-22 H.J. Lu <hongjiu.lu@intel.com>
	292
	293	* ia64-gen.c (lookup_regindex): Handle ".vm".
	294	(print_dependency_table): Handle '\"'.
	295
	296	* ia64-ic.tbl: Updated from SDM 2.2.
	297	* ia64-raw.tbl: Likewise.
	298	* ia64-waw.tbl: Likewise.
	299	* ia64-asmtab.c: Regenerated.
	300
	301	* ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.
	302
d70c5fc7 NC	303	2006-02-17 Shrirang Khisti <shrirangk@kpitcummins.com>
	304	Anil Paranjape <anilp1@kpitcummins.com>
	305	Shilin Shakti <shilins@kpitcummins.com>
	306
	307	* xc16x-desc.h: New file
	308	* xc16x-desc.c: New file
	309	* xc16x-opc.h: New file
	310	* xc16x-opc.c: New file
	311	* xc16x-ibld.c: New file
	312	* xc16x-asm.c: New file
	313	* xc16x-dis.c: New file
	314	* Makefile.am: Entries for xc16x
	315	* Makefile.in: Regenerate
	316	* cofigure.in: Add xc16x target information.
	317	* configure: Regenerate.
	318	* disassemble.c: Add xc16x target information.
	319
a1cfb73e L	320	2006-02-11 H.J. Lu <hongjiu.lu@intel.com>
	321
	322	* i386-dis.c (dis386_twobyte): Use "movZ" for debug register
	323	moves.
	324
6dd5059a L	325	2006-02-11 H.J. Lu <hongjiu.lu@intel.com>
	326
	327	* i386-dis.c ('Z'): Add a new macro.
	328	(dis386_twobyte): Use "movZ" for control register moves.
	329
8536c657 NC	330	2006-02-10 Nick Clifton <nickc@redhat.com>
	331
	332	* iq2000-asm.c: Regenerate.
	333
266abb8f NS	334	2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
	335
	336	* m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features.
	337
f1a64f49 DU	338	2006-01-26 David Ung <davidu@mips.com>
	339
	340	* mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx,
	341	ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
	342	floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
	343	nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
	344	rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.
	345
9e919b5f AM	346	2006-01-18 Arnold Metselaar <arnoldm@sourceware.org>
	347
	348	* z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d,
	349	ld_d_r, pref_xd_cb): Use signed char to hold data to be
	350	disassembled.
	351	* z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes
	352	buffer overflows when disassembling instructions like
	353	ld (ix+123),0x23
	354	* z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed
	355	operand, if the offset is negative.
	356
c9021189 AM	357	2006-01-17 Arnold Metselaar <arnoldm@sourceware.org>
	358
	359	* z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use
	360	unsigned char to hold data to be disassembled.
	361
d99b6465 AS	362	2006-01-17 Andreas Schwab <schwab@suse.de>
	363
	364	PR binutils/1486
	365	* disassemble.c (disassemble_init_for_target): Set
	366	disassembler_needs_relocs for bfd_arch_arm.
	367
c2fe9327 PB	368	2006-01-16 Paul Brook <paul@codesourcery.com>
c2fe9327 PB	369
e88d958a	370	* m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss,
c2fe9327 PB	371	f?add?, and f?sub? instructions.
c2fe9327 PB	372
32fba81d NC	373	2006-01-16 Nick Clifton <nickc@redhat.com>
	374
	375	* po/zh_CN.po: New Chinese (simplified) translation.
	376	* configure.in (ALL_LINGUAS): Add "zh_CH".
	377	* configure: Regenerate.
	378
1b3a26b5 PB	379	2006-01-05 Paul Brook <paul@codesourcery.com>
	380
	381	* m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry.
	382
db313fa6 DD	383	2006-01-06 DJ Delorie <dj@redhat.com>
	384
	385	* m32c-desc.c: Regenerate.
	386	* m32c-opc.c: Regenerate.
	387	* m32c-opc.h: Regenerate.
	388
54d46aca DD	389	2006-01-03 DJ Delorie <dj@redhat.com>
	390
	391	* cgen-ibld.in (extract_normal): Avoid memory range errors.
	392	* m32c-ibld.c: Regenerated.
	393
e88d958a	394	For older changes see ChangeLog-2005
252b5132 RH	395	\f
252b5132 RH	396	Local Variables:
2f6d2f85 NC	397	mode: change-log
	398	left-margin: 8
	399	fill-column: 74
252b5132 RH	400	version-control: never
252b5132 RH	401	End: