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AArch64/opcodes: Correct an `index' global shadowing error
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
eaf02703
MR		 12016-10-18 Maciej W. Rozycki <macro@imgtec.com>
2
3 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
4 local variable to `index_regno'.
5
decf5bd1
CM		 62016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
7
8 * arc-tbl.h: Removed any "inv.+" instructions from the table.
9
e5b06ef0
CZ		 102016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
11
12 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
13 usage on ISA basis.
14
93562a34
JW		 152016-10-11 Jiong Wang <jiong.wang@arm.com>
16
17 PR target/20666
18 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
19
362c0c4d
JW		 202016-10-07 Jiong Wang <jiong.wang@arm.com>
21
22 PR target/20667
23 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
24 available.
25
1047201f
AM		 262016-10-07 Alan Modra <amodra@gmail.com>
27
28 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
29
1a0670f3
AM		 302016-10-06 Alan Modra <amodra@gmail.com>
31
32 * aarch64-opc.c: Spell fall through comments consistently.
33 * i386-dis.c: Likewise.
34 * aarch64-dis.c: Add missing fall through comments.
35 * aarch64-opc.c: Likewise.
36 * arc-dis.c: Likewise.
37 * arm-dis.c: Likewise.
38 * i386-dis.c: Likewise.
39 * m68k-dis.c: Likewise.
40 * mep-asm.c: Likewise.
41 * ns32k-dis.c: Likewise.
42 * sh-dis.c: Likewise.
43 * tic4x-dis.c: Likewise.
44 * tic6x-dis.c: Likewise.
45 * vax-dis.c: Likewise.
46
2b804145
AM		 472016-10-06 Alan Modra <amodra@gmail.com>
48
49 * arc-ext.c (create_map): Add missing break.
50 * msp430-decode.opc (encode_as): Likewise.
51 * msp430-decode.c: Regenerate.
52
616ec358
AM		 532016-10-06 Alan Modra <amodra@gmail.com>
54
55 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
56 * crx-dis.c (print_insn_crx): Likewise.
57
72da393d
L		 582016-09-30 H.J. Lu <hongjiu.lu@intel.com>
59
60 PR binutils/20657
61 * i386-dis.c (putop): Don't assign alt twice.
62
744ce302
JW		 632016-09-29 Jiong Wang <jiong.wang@arm.com>
64
65 PR target/20553
66 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
67
a5721ba2
AM		 682016-09-29 Alan Modra <amodra@gmail.com>
69
70 * ppc-opc.c (L): Make compulsory.
71 (LOPT): New, optional form of L.
72 (HTM_R): Define as LOPT.
73 (L0, L1): Delete.
74 (L32OPT): New, optional for 32-bit L.
75 (L2OPT): New, 2-bit L for dcbf.
76 (SVC_LEC): Update.
77 (L2): Define.
78 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
79 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
80 <dcbf>: Use L2OPT.
81 <tlbiel, tlbie>: Use LOPT.
82 <wclr, wclrall>: Use L2.
83
c5da1932
VZ		 842016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
85
86 * Makefile.in: Regenerate.
87 * configure: Likewise.
88
2b848ebd
CZ		 892016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
90
91 * arc-ext-tbl.h (EXTINSN2OPF): Define.
92 (EXTINSN2OP): Use EXTINSN2OPF.
93 (bspeekm, bspop, modapp): New extension instructions.
94 * arc-opc.c (F_DNZ_ND): Define.
95 (F_DNZ_D): Likewise.
96 (F_SIZEB1): Changed.
97 (C_DNZ_D): Define.
98 (C_HARD): Changed.
99 * arc-tbl.h (dbnz): New instruction.
100 (prealloc): Allow it for ARC EM.
101 (xbfu): Likewise.
102
ad43e107
RS		 1032016-09-21 Richard Sandiford <richard.sandiford@arm.com>
104
105 * aarch64-opc.c (print_immediate_offset_address): Print spaces
106 after commas in addresses.
107 (aarch64_print_operand): Likewise.
108
ab3b8fcf
RS		 1092016-09-21 Richard Sandiford <richard.sandiford@arm.com>
110
111 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
112 rather than "should be" or "expected to be" in error messages.
113
bb7eff52
RS		 1142016-09-21 Richard Sandiford <richard.sandiford@arm.com>
115
116 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
117 (print_mnemonic_name): ...here.
118 (print_comment): New function.
119 (print_aarch64_insn): Call it.
120 * aarch64-opc.c (aarch64_conds): Add SVE names.
121 (aarch64_print_operand): Print alternative condition names in
122 a comment.
123
c0890d26
RS		 1242016-09-21 Richard Sandiford <richard.sandiford@arm.com>
125
126 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
127 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
128 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
129 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
130 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
131 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
132 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
133 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
134 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
135 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
136 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
137 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
138 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
139 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
140 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
141 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
142 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
143 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
144 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
145 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
146 (OP_SVE_XWU, OP_SVE_XXU): New macros.
147 (aarch64_feature_sve): New variable.
148 (SVE): New macro.
149 (_SVE_INSN): Likewise.
150 (aarch64_opcode_table): Add SVE instructions.
151 * aarch64-opc.h (extract_fields): Declare.
152 * aarch64-opc-2.c: Regenerate.
153 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
154 * aarch64-asm-2.c: Regenerate.
155 * aarch64-dis.c (extract_fields): Make global.
156 (do_misc_decoding): Handle the new SVE aarch64_ops.
157 * aarch64-dis-2.c: Regenerate.
158
116b6019
RS		 1592016-09-21 Richard Sandiford <richard.sandiford@arm.com>
160
161 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
162 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
163 aarch64_field_kinds.
164 * aarch64-opc.c (fields): Add corresponding entries.
165 * aarch64-asm.c (aarch64_get_variant): New function.
166 (aarch64_encode_variant_using_iclass): Likewise.
167 (aarch64_opcode_encode): Call it.
168 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
169 (aarch64_opcode_decode): Call it.
170
047cd301
RS		 1712016-09-21 Richard Sandiford <richard.sandiford@arm.com>
172
173 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
174 and FP register operands.
175 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
176 (FLD_SVE_Vn): New aarch64_field_kinds.
177 * aarch64-opc.c (fields): Add corresponding entries.
178 (aarch64_print_operand): Handle the new SVE core and FP register
179 operands.
180 * aarch64-opc-2.c: Regenerate.
181 * aarch64-asm-2.c: Likewise.
182 * aarch64-dis-2.c: Likewise.
183
165d4950
RS		 1842016-09-21 Richard Sandiford <richard.sandiford@arm.com>
185
186 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
187 immediate operands.
188 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
189 * aarch64-opc.c (fields): Add corresponding entry.
190 (operand_general_constraint_met_p): Handle the new SVE FP immediate
191 operands.
192 (aarch64_print_operand): Likewise.
193 * aarch64-opc-2.c: Regenerate.
194 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
195 (ins_sve_float_zero_one): New inserters.
196 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
197 (aarch64_ins_sve_float_half_two): Likewise.
198 (aarch64_ins_sve_float_zero_one): Likewise.
199 * aarch64-asm-2.c: Regenerate.
200 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
201 (ext_sve_float_zero_one): New extractors.
202 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
203 (aarch64_ext_sve_float_half_two): Likewise.
204 (aarch64_ext_sve_float_zero_one): Likewise.
205 * aarch64-dis-2.c: Regenerate.
206
e950b345
RS		 2072016-09-21 Richard Sandiford <richard.sandiford@arm.com>
208
209 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
210 integer immediate operands.
211 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
212 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
213 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
214 * aarch64-opc.c (fields): Add corresponding entries.
215 (operand_general_constraint_met_p): Handle the new SVE integer
216 immediate operands.
217 (aarch64_print_operand): Likewise.
218 (aarch64_sve_dupm_mov_immediate_p): New function.
219 * aarch64-opc-2.c: Regenerate.
220 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
221 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
222 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
223 (aarch64_ins_limm): ...here.
224 (aarch64_ins_inv_limm): New function.
225 (aarch64_ins_sve_aimm): Likewise.
226 (aarch64_ins_sve_asimm): Likewise.
227 (aarch64_ins_sve_limm_mov): Likewise.
228 (aarch64_ins_sve_shlimm): Likewise.
229 (aarch64_ins_sve_shrimm): Likewise.
230 * aarch64-asm-2.c: Regenerate.
231 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
232 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
233 * aarch64-dis.c (decode_limm): New function, split out from...
234 (aarch64_ext_limm): ...here.
235 (aarch64_ext_inv_limm): New function.
236 (decode_sve_aimm): Likewise.
237 (aarch64_ext_sve_aimm): Likewise.
238 (aarch64_ext_sve_asimm): Likewise.
239 (aarch64_ext_sve_limm_mov): Likewise.
240 (aarch64_top_bit): Likewise.
241 (aarch64_ext_sve_shlimm): Likewise.
242 (aarch64_ext_sve_shrimm): Likewise.
243 * aarch64-dis-2.c: Regenerate.
244
98907a70
RS		 2452016-09-21 Richard Sandiford <richard.sandiford@arm.com>
246
247 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
248 operands.
249 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
250 the AARCH64_MOD_MUL_VL entry.
251 (value_aligned_p): Cope with non-power-of-two alignments.
252 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
253 (print_immediate_offset_address): Likewise.
254 (aarch64_print_operand): Likewise.
255 * aarch64-opc-2.c: Regenerate.
256 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
257 (ins_sve_addr_ri_s9xvl): New inserters.
258 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
259 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
260 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
261 * aarch64-asm-2.c: Regenerate.
262 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
263 (ext_sve_addr_ri_s9xvl): New extractors.
264 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
265 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
266 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
267 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
268 * aarch64-dis-2.c: Regenerate.
269
4df068de
RS		 2702016-09-21 Richard Sandiford <richard.sandiford@arm.com>
271
272 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
273 address operands.
274 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
275 (FLD_SVE_xs_22): New aarch64_field_kinds.
276 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
277 (get_operand_specific_data): New function.
278 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
279 FLD_SVE_xs_14 and FLD_SVE_xs_22.
280 (operand_general_constraint_met_p): Handle the new SVE address
281 operands.
282 (sve_reg): New array.
283 (get_addr_sve_reg_name): New function.
284 (aarch64_print_operand): Handle the new SVE address operands.
285 * aarch64-opc-2.c: Regenerate.
286 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
287 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
288 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
289 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
290 (aarch64_ins_sve_addr_rr_lsl): Likewise.
291 (aarch64_ins_sve_addr_rz_xtw): Likewise.
292 (aarch64_ins_sve_addr_zi_u5): Likewise.
293 (aarch64_ins_sve_addr_zz): Likewise.
294 (aarch64_ins_sve_addr_zz_lsl): Likewise.
295 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
296 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
297 * aarch64-asm-2.c: Regenerate.
298 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
299 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
300 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
301 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
302 (aarch64_ext_sve_addr_ri_u6): Likewise.
303 (aarch64_ext_sve_addr_rr_lsl): Likewise.
304 (aarch64_ext_sve_addr_rz_xtw): Likewise.
305 (aarch64_ext_sve_addr_zi_u5): Likewise.
306 (aarch64_ext_sve_addr_zz): Likewise.
307 (aarch64_ext_sve_addr_zz_lsl): Likewise.
308 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
309 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
310 * aarch64-dis-2.c: Regenerate.
311
2442d846
RS		 3122016-09-21 Richard Sandiford <richard.sandiford@arm.com>
313
314 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
315 AARCH64_OPND_SVE_PATTERN_SCALED.
316 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
317 * aarch64-opc.c (fields): Add a corresponding entry.
318 (set_multiplier_out_of_range_error): New function.
319 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
320 (operand_general_constraint_met_p): Handle
321 AARCH64_OPND_SVE_PATTERN_SCALED.
322 (print_register_offset_address): Use PRIi64 to print the
323 shift amount.
324 (aarch64_print_operand): Likewise. Handle
325 AARCH64_OPND_SVE_PATTERN_SCALED.
326 * aarch64-opc-2.c: Regenerate.
327 * aarch64-asm.h (ins_sve_scale): New inserter.
328 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
329 * aarch64-asm-2.c: Regenerate.
330 * aarch64-dis.h (ext_sve_scale): New inserter.
331 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
332 * aarch64-dis-2.c: Regenerate.
333
245d2e3f
RS		 3342016-09-21 Richard Sandiford <richard.sandiford@arm.com>
335
336 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
337 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
338 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
339 (FLD_SVE_prfop): Likewise.
340 * aarch64-opc.c: Include libiberty.h.
341 (aarch64_sve_pattern_array): New variable.
342 (aarch64_sve_prfop_array): Likewise.
343 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
344 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
345 AARCH64_OPND_SVE_PRFOP.
346 * aarch64-asm-2.c: Regenerate.
347 * aarch64-dis-2.c: Likewise.
348 * aarch64-opc-2.c: Likewise.
349
d50c751e
RS		 3502016-09-21 Richard Sandiford <richard.sandiford@arm.com>
351
352 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
353 AARCH64_OPND_QLF_P_[ZM].
354 (aarch64_print_operand): Print /z and /m where appropriate.
355
f11ad6bc
RS		 3562016-09-21 Richard Sandiford <richard.sandiford@arm.com>
357
358 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
359 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
360 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
361 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
362 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
363 * aarch64-opc.c (fields): Add corresponding entries here.
364 (operand_general_constraint_met_p): Check that SVE register lists
365 have the correct length. Check the ranges of SVE index registers.
366 Check for cases where p8-p15 are used in 3-bit predicate fields.
367 (aarch64_print_operand): Handle the new SVE operands.
368 * aarch64-opc-2.c: Regenerate.
369 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
370 * aarch64-asm.c (aarch64_ins_sve_index): New function.
371 (aarch64_ins_sve_reglist): Likewise.
372 * aarch64-asm-2.c: Regenerate.
373 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
374 * aarch64-dis.c (aarch64_ext_sve_index): New function.
375 (aarch64_ext_sve_reglist): Likewise.
376 * aarch64-dis-2.c: Regenerate.
377
0c608d6b
RS		 3782016-09-21 Richard Sandiford <richard.sandiford@arm.com>
379
380 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
381 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
382 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
383 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
384 tied operands.
385
01dbfe4c
RS		 3862016-09-21 Richard Sandiford <richard.sandiford@arm.com>
387
388 * aarch64-opc.c (get_offset_int_reg_name): New function.
389 (print_immediate_offset_address): Likewise.
390 (print_register_offset_address): Take the base and offset
391 registers as parameters.
392 (aarch64_print_operand): Update caller accordingly. Use
393 print_immediate_offset_address.
394
72e9f319
RS		 3952016-09-21 Richard Sandiford <richard.sandiford@arm.com>
396
397 * aarch64-opc.c (BANK): New macro.
398 (R32, R64): Take a register number as argument
399 (int_reg): Use BANK.
400
8a7f0c1b
RS		 4012016-09-21 Richard Sandiford <richard.sandiford@arm.com>
402
403 * aarch64-opc.c (print_register_list): Add a prefix parameter.
404 (aarch64_print_operand): Update accordingly.
405
aa2aa4c6
RS		 4062016-09-21 Richard Sandiford <richard.sandiford@arm.com>
407
408 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
409 for FPIMM.
410 * aarch64-asm.h (ins_fpimm): New inserter.
411 * aarch64-asm.c (aarch64_ins_fpimm): New function.
412 * aarch64-asm-2.c: Regenerate.
413 * aarch64-dis.h (ext_fpimm): New extractor.
414 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
415 (aarch64_ext_fpimm): New function.
416 * aarch64-dis-2.c: Regenerate.
417
b5464a68
RS		 4182016-09-21 Richard Sandiford <richard.sandiford@arm.com>
419
420 * aarch64-asm.c: Include libiberty.h.
421 (insert_fields): New function.
422 (aarch64_ins_imm): Use it.
423 * aarch64-dis.c (extract_fields): New function.
424 (aarch64_ext_imm): Use it.
425
42408347
RS		 4262016-09-21 Richard Sandiford <richard.sandiford@arm.com>
427
428 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
429 with an esize parameter.
430 (operand_general_constraint_met_p): Update accordingly.
431 Fix misindented code.
432 * aarch64-asm.c (aarch64_ins_limm): Update call to
433 aarch64_logical_immediate_p.
434
4989adac
RS		 4352016-09-21 Richard Sandiford <richard.sandiford@arm.com>
436
437 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
438
bd11d5d8
RS		 4392016-09-21 Richard Sandiford <richard.sandiford@arm.com>
440
441 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
442
f807f43d
CZ		 4432016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
444
445 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
446
fd486b63
PB		 4472016-09-14 Peter Bergner <bergner@vnet.ibm.com>
448
449 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
450 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
451 xor3>: Delete mnemonics.
452 <cp_abort>: Rename mnemonic from ...
453 <cpabort>: ...to this.
454 <setb>: Change to a X form instruction.
455 <sync>: Change to 1 operand form.
456 <copy>: Delete mnemonic.
457 <copy_first>: Rename mnemonic from ...
458 <copy>: ...to this.
459 <paste, paste.>: Delete mnemonics.
460 <paste_last>: Rename mnemonic from ...
461 <paste.>: ...to this.
462
dce08442
AK		 4632016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
464
465 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
466
952c3f51
AK		 4672016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
468
469 * s390-mkopc.c (main): Support alternate arch strings.
470
8b71537b
PS		 4712016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
472
473 * s390-opc.txt: Fix kmctr instruction type.
474
5b64d091
L		 4752016-09-07 H.J. Lu <hongjiu.lu@intel.com>
476
477 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
478 * i386-init.h: Regenerated.
479
7763838e
CM		 4802016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
481
482 * opcodes/arc-dis.c (print_insn_arc): Changed.
483
1b8b6532
JM		 4842016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
485
486 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
487 camellia_fl.
488
1a336194
TP		 4892016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
490
491 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
492 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
493 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
494
6b40c462
L		 4952016-08-24 H.J. Lu <hongjiu.lu@intel.com>
496
497 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
498 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
499 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
500 PREFIX_MOD_3_0FAE_REG_4.
501 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
502 PREFIX_MOD_3_0FAE_REG_4.
503 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
504 (cpu_flags): Add CpuPTWRITE.
505 * i386-opc.h (CpuPTWRITE): New.
506 (i386_cpu_flags): Add cpuptwrite.
507 * i386-opc.tbl: Add ptwrite instruction.
508 * i386-init.h: Regenerated.
509 * i386-tbl.h: Likewise.
510
ab548d2d
AK		 5112016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
512
513 * arc-dis.h: Wrap around in extern "C".
514
344bde0a
RS		 5152016-08-23 Richard Sandiford <richard.sandiford@arm.com>
516
517 * aarch64-tbl.h (V8_2_INSN): New macro.
518 (aarch64_opcode_table): Use it.
519
5ce912d8
RS		 5202016-08-23 Richard Sandiford <richard.sandiford@arm.com>
521
522 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
523 CORE_INSN, __FP_INSN and SIMD_INSN.
524
9d30b0bd
RS		 5252016-08-23 Richard Sandiford <richard.sandiford@arm.com>
526
527 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
528 (aarch64_opcode_table): Update uses accordingly.
529
dfdaec14
AJ		 5302016-07-25 Andrew Jenner <andrew@codesourcery.com>
531 Kwok Cheung Yeung <kcy@codesourcery.com>
532
533 opcodes/
534 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
535 'e_cmplwi' to 'e_cmpli' instead.
536 (OPVUPRT, OPVUPRT_MASK): Define.
537 (powerpc_opcodes): Add E200Z4 insns.
538 (vle_opcodes): Add context save/restore insns.
539
7bd374a4
MR		 5402016-07-27 Maciej W. Rozycki <macro@imgtec.com>
541
542 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
543 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
544 "j".
545
db18dbab
GM		 5462016-07-27 Graham Markall <graham.markall@embecosm.com>
547
548 * arc-nps400-tbl.h: Change block comments to GNU format.
549 * arc-dis.c: Add new globals addrtypenames,
550 addrtypenames_max, and addtypeunknown.
551 (get_addrtype): New function.
552 (print_insn_arc): Print colons and address types when
553 required.
554 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
555 define insert and extract functions for all address types.
556 (arc_operands): Add operands for colon and all address
557 types.
558 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
559 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
560 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
561 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
562 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
563 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
564
fecd57f9
L		 5652016-07-21 H.J. Lu <hongjiu.lu@intel.com>
566
567 * configure: Regenerated.
568
37fd5ef3
CZ		 5692016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
570
571 * arc-dis.c (skipclass): New structure.
572 (decodelist): New variable.
573 (is_compatible_p): New function.
574 (new_element): Likewise.
575 (skip_class_p): Likewise.
576 (find_format_from_table): Use skip_class_p function.
577 (find_format): Decode first the extension instructions.
578 (print_insn_arc): Select either ARCEM or ARCHS based on elf
579 e_flags.
580 (parse_option): New function.
581 (parse_disassembler_options): Likewise.
582 (print_arc_disassembler_options): Likewise.
583 (print_insn_arc): Use parse_disassembler_options function. Proper
584 select ARCv2 cpu variant.
585 * disassemble.c (disassembler_usage): Add ARC disassembler
586 options.
587
92281a5b
MR		 5882016-07-13 Maciej W. Rozycki <macro@imgtec.com>
589
590 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
591 annotation from the "nal" entry and reorder it beyond "bltzal".
592
6e7ced37
JM		 5932016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
594
595 * sparc-opc.c (ldtxa): New macro.
596 (sparc_opcodes): Use the macro defined above to add entries for
597 the LDTXA instructions.
598 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
599 instruction.
600
2f831b9a 6012016-07-07 James Bowman <james.bowman@ftdichip.com>
602
603 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
604 and "jmpc".
605
c07315e0
JB		 6062016-07-01 Jan Beulich <jbeulich@suse.com>
607
608 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
609 (movzb): Adjust to cover all permitted suffixes.
610 (movzw): New.
611 * i386-tbl.h: Re-generate.
612
9243100a
JB		 6132016-07-01 Jan Beulich <jbeulich@suse.com>
614
615 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
616 (lgdt): Remove Tbyte from non-64-bit variant.
617 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
618 xsaves64, xsavec64): Remove Disp16.
619 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
620 Remove Disp32S from non-64-bit variants. Remove Disp16 from
621 64-bit variants.
622 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
623 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
624 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
625 64-bit variants.
626 * i386-tbl.h: Re-generate.
627
8325cc63
JB		 6282016-07-01 Jan Beulich <jbeulich@suse.com>
629
630 * i386-opc.tbl (xlat): Remove RepPrefixOk.
631 * i386-tbl.h: Re-generate.
632
838441e4
YQ		 6332016-06-30 Yao Qi <yao.qi@linaro.org>
634
635 * arm-dis.c (print_insn): Fix typo in comment.
636
dab26bf4
RS		 6372016-06-28 Richard Sandiford <richard.sandiford@arm.com>
638
639 * aarch64-opc.c (operand_general_constraint_met_p): Check the
640 range of ldst_elemlist operands.
641 (print_register_list): Use PRIi64 to print the index.
642 (aarch64_print_operand): Likewise.
643
5703197e
TS		 6442016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
645
646 * mcore-opc.h: Remove sentinal.
647 * mcore-dis.c (print_insn_mcore): Adjust.
648
ce440d63
GM		 6492016-06-23 Graham Markall <graham.markall@embecosm.com>
650
651 * arc-opc.c: Correct description of availability of NPS400
652 features.
653
6fd3a02d
PB		 6542016-06-22 Peter Bergner <bergner@vnet.ibm.com>
655
656 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
657 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
658 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
659 xor3>: New mnemonics.
660 <setb>: Change to a VX form instruction.
661 (insert_sh6): Add support for rldixor.
662 (extract_sh6): Likewise.
663
6b477896
TS		 6642016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
665
666 * arc-ext.h: Wrap in extern C.
667
bdd582db
GM		 6682016-06-21 Graham Markall <graham.markall@embecosm.com>
669
670 * arc-dis.c (arc_insn_length): Add comment on instruction length.
671 Use same method for determining instruction length on ARC700 and
672 NPS-400.
673 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
674 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
675 with the NPS400 subclass.
676 * arc-opc.c: Likewise.
677
96074adc
JM		 6782016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
679
680 * sparc-opc.c (rdasr): New macro.
681 (wrasr): Likewise.
682 (rdpr): Likewise.
683 (wrpr): Likewise.
684 (rdhpr): Likewise.
685 (wrhpr): Likewise.
686 (sparc_opcodes): Use the macros above to fix and expand the
687 definition of read/write instructions from/to
688 asr/privileged/hyperprivileged instructions.
689 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
690 %hva_mask_nz. Prefer softint_set and softint_clear over
691 set_softint and clear_softint.
692 (print_insn_sparc): Support %ver in Rd.
693
7a10c22f
JM		 6942016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
695
696 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
697 architecture according to the hardware capabilities they require.
698
4f26fb3a
JM		 6992016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
700
701 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
702 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
703 bfd_mach_sparc_v9{c,d,e,v,m}.
704 * sparc-opc.c (MASK_V9C): Define.
705 (MASK_V9D): Likewise.
706 (MASK_V9E): Likewise.
707 (MASK_V9V): Likewise.
708 (MASK_V9M): Likewise.
709 (v6): Add MASK_V9{C,D,E,V,M}.
710 (v6notlet): Likewise.
711 (v7): Likewise.
712 (v8): Likewise.
713 (v9): Likewise.
714 (v9andleon): Likewise.
715 (v9a): Likewise.
716 (v9b): Likewise.
717 (v9c): Define.
718 (v9d): Likewise.
719 (v9e): Likewise.
720 (v9v): Likewise.
721 (v9m): Likewise.
722 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
723
3ee6e4fb
NC		 7242016-06-15 Nick Clifton <nickc@redhat.com>
725
726 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
727 constants to match expected behaviour.
728 (nds32_parse_opcode): Likewise. Also for whitespace.
729
02f3be19
AB		 7302016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
731
732 * arc-opc.c (extract_rhv1): Extract value from insn.
733
6f9f37ed 7342016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM		 735
736 * arc-nps400-tbl.h: Add ldbit instruction.
737 * arc-opc.c: Add flag classes required for ldbit.
738
6f9f37ed 7392016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM		 740
741 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
742 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
743 support the above instructions.
744
6f9f37ed 7452016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM		 746
747 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
748 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
749 csma, cbba, zncv, and hofs.
750 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
751 support the above instructions.
752
7532016-06-06 Graham Markall <graham.markall@embecosm.com>
754
755 * arc-nps400-tbl.h: Add andab and orab instructions.
756
7572016-06-06 Graham Markall <graham.markall@embecosm.com>
758
759 * arc-nps400-tbl.h: Add addl-like instructions.
760
7612016-06-06 Graham Markall <graham.markall@embecosm.com>
762
763 * arc-nps400-tbl.h: Add mxb and imxb instructions.
764
7652016-06-06 Graham Markall <graham.markall@embecosm.com>
766
767 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
768 instructions.
769
b2cc3f6f
AK		 7702016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
771
772 * s390-dis.c (option_use_insn_len_bits_p): New file scope
773 variable.
774 (init_disasm): Handle new command line option "insnlength".
775 (print_s390_disassembler_options): Mention new option in help
776 output.
777 (print_insn_s390): Use the encoded insn length when dumping
778 unknown instructions.
779
1857fe72
DC		 7802016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
781
782 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
783 to the address and set as symbol address for LDS/ STS immediate operands.
784
14b57c7c
AM		 7852016-06-07 Alan Modra <amodra@gmail.com>
786
787 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
788 cpu for "vle" to e500.
789 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
790 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
791 (PPCNONE): Delete, substitute throughout.
792 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
793 except for major opcode 4 and 31.
794 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
795
4d1464f2
MW		 7962016-06-07 Matthew Wahab <matthew.wahab@arm.com>
797
798 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
799 ARM_EXT_RAS in relevant entries.
800
026122a6
PB		 8012016-06-03 Peter Bergner <bergner@vnet.ibm.com>
802
803 PR binutils/20196
804 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
805 opcodes for E6500.
806
07f5af7d
L		 8072016-06-03 H.J. Lu <hongjiu.lu@intel.com>
808
809 PR binutis/18386
810 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
811 (indir_v_mode): New.
812 Add comments for '&'.
813 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
814 (putop): Handle '&'.
815 (intel_operand_size): Handle indir_v_mode.
816 (OP_E_register): Likewise.
817 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
818 64-bit indirect call/jmp for AMD64.
819 * i386-tbl.h: Regenerated
820
4eb6f892
AB		 8212016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
822
823 * arc-dis.c (struct arc_operand_iterator): New structure.
824 (find_format_from_table): All the old content from find_format,
825 with some minor adjustments, and parameter renaming.
826 (find_format_long_instructions): New function.
827 (find_format): Rewritten.
828 (arc_insn_length): Add LSB parameter.
829 (extract_operand_value): New function.
830 (operand_iterator_next): New function.
831 (print_insn_arc): Use new functions to find opcode, and iterator
832 over operands.
833 * arc-opc.c (insert_nps_3bit_dst_short): New function.
834 (extract_nps_3bit_dst_short): New function.
835 (insert_nps_3bit_src2_short): New function.
836 (extract_nps_3bit_src2_short): New function.
837 (insert_nps_bitop1_size): New function.
838 (extract_nps_bitop1_size): New function.
839 (insert_nps_bitop2_size): New function.
840 (extract_nps_bitop2_size): New function.
841 (insert_nps_bitop_mod4_msb): New function.
842 (extract_nps_bitop_mod4_msb): New function.
843 (insert_nps_bitop_mod4_lsb): New function.
844 (extract_nps_bitop_mod4_lsb): New function.
845 (insert_nps_bitop_dst_pos3_pos4): New function.
846 (extract_nps_bitop_dst_pos3_pos4): New function.
847 (insert_nps_bitop_ins_ext): New function.
848 (extract_nps_bitop_ins_ext): New function.
849 (arc_operands): Add new operands.
850 (arc_long_opcodes): New global array.
851 (arc_num_long_opcodes): New global.
852 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
853
1fe0971e
TS		 8542016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
855
856 * nds32-asm.h: Add extern "C".
857 * sh-opc.h: Likewise.
858
315f180f
GM		 8592016-06-01 Graham Markall <graham.markall@embecosm.com>
860
861 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
862 0,b,limm to the rflt instruction.
863
a2b5fccc
TS		 8642016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
865
866 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
867 constant.
868
0cbd0046
L		 8692016-05-29 H.J. Lu <hongjiu.lu@intel.com>
870
871 PR gas/20145
872 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
873 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
874 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
875 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
876 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
877 * i386-init.h: Regenerated.
878
1848e567
L		 8792016-05-27 H.J. Lu <hongjiu.lu@intel.com>
880
881 PR gas/20145
882 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
883 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
884 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
885 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
886 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
887 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
888 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
889 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
890 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
891 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
892 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
893 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
894 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
895 CpuRegMask for AVX512.
896 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
897 and CpuRegMask.
898 (set_bitfield_from_cpu_flag_init): New function.
899 (set_bitfield): Remove const on f. Call
900 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
901 * i386-opc.h (CpuRegMMX): New.
902 (CpuRegXMM): Likewise.
903 (CpuRegYMM): Likewise.
904 (CpuRegZMM): Likewise.
905 (CpuRegMask): Likewise.
906 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
907 and cpuregmask.
908 * i386-init.h: Regenerated.
909 * i386-tbl.h: Likewise.
910
e92bae62
L		 9112016-05-27 H.J. Lu <hongjiu.lu@intel.com>
912
913 PR gas/20154
914 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
915 (opcode_modifiers): Add AMD64 and Intel64.
916 (main): Properly verify CpuMax.
917 * i386-opc.h (CpuAMD64): Removed.
918 (CpuIntel64): Likewise.
919 (CpuMax): Set to CpuNo64.
920 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
921 (AMD64): New.
922 (Intel64): Likewise.
923 (i386_opcode_modifier): Add amd64 and intel64.
924 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
925 on call and jmp.
926 * i386-init.h: Regenerated.
927 * i386-tbl.h: Likewise.
928
e89c5eaa
L		 9292016-05-27 H.J. Lu <hongjiu.lu@intel.com>
930
931 PR gas/20154
932 * i386-gen.c (main): Fail if CpuMax is incorrect.
933 * i386-opc.h (CpuMax): Set to CpuIntel64.
934 * i386-tbl.h: Regenerated.
935
77d66e7b
NC		 9362016-05-27 Nick Clifton <nickc@redhat.com>
937
938 PR target/20150
939 * msp430-dis.c (msp430dis_read_two_bytes): New function.
940 (msp430dis_opcode_unsigned): New function.
941 (msp430dis_opcode_signed): New function.
942 (msp430_singleoperand): Use the new opcode reading functions.
943 Only disassenmble bytes if they were successfully read.
944 (msp430_doubleoperand): Likewise.
945 (msp430_branchinstr): Likewise.
946 (msp430x_callx_instr): Likewise.
947 (print_insn_msp430): Check that it is safe to read bytes before
948 attempting disassembly. Use the new opcode reading functions.
949
19dfcc89
PB		 9502016-05-26 Peter Bergner <bergner@vnet.ibm.com>
951
952 * ppc-opc.c (CY): New define. Document it.
953 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
954
f3ad7637
L		 9552016-05-25 H.J. Lu <hongjiu.lu@intel.com>
956
957 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
958 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
959 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
960 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
961 CPU_ANY_AVX_FLAGS.
962 * i386-init.h: Regenerated.
963
f1360d58
L		 9642016-05-25 H.J. Lu <hongjiu.lu@intel.com>
965
966 PR gas/20141
967 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
968 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
969 * i386-init.h: Regenerated.
970
293f5f65
L		 9712016-05-25 H.J. Lu <hongjiu.lu@intel.com>
972
973 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
974 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
975 * i386-init.h: Regenerated.
976
d9eca1df
CZ		 9772016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
978
979 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
980 information.
981 (print_insn_arc): Set insn_type information.
982 * arc-opc.c (C_CC): Add F_CLASS_COND.
983 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
984 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
985 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
986 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
987 (brne, brne_s, jeq_s, jne_s): Likewise.
988
87789e08
CZ		 9892016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
990
991 * arc-tbl.h (neg): New instruction variant.
992
c810e0b8
CZ		 9932016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
994
995 * arc-dis.c (find_format, find_format, get_auxreg)
996 (print_insn_arc): Changed.
997 * arc-ext.h (INSERT_XOP): Likewise.
998
3d207518
TS		 9992016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1000
1001 * tic54x-dis.c (sprint_mmr): Adjust.
1002 * tic54x-opc.c: Likewise.
1003
514e58b7
AM		 10042016-05-19 Alan Modra <amodra@gmail.com>
1005
1006 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1007
e43de63c
AM		 10082016-05-19 Alan Modra <amodra@gmail.com>
1009
1010 * ppc-opc.c: Formatting.
1011 (NSISIGNOPT): Define.
1012 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1013
1401d2fe
MR		 10142016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1015
1016 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1017 replacing references to `micromips_ase' throughout.
1018 (_print_insn_mips): Don't use file-level microMIPS annotation to
1019 determine the disassembly mode with the symbol table.
1020
1178da44
PB		 10212016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1022
1023 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1024
8f4f9071
MF		 10252016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1026
1027 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1028 mips64r6.
1029 * mips-opc.c (D34): New macro.
1030 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1031
8bc52696
AF		 10322016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1033
1034 * i386-dis.c (prefix_table): Add RDPID instruction.
1035 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1036 (cpu_flags): Add RDPID bitfield.
1037 * i386-opc.h (enum): Add RDPID element.
1038 (i386_cpu_flags): Add RDPID field.
1039 * i386-opc.tbl: Add RDPID instruction.
1040 * i386-init.h: Regenerate.
1041 * i386-tbl.h: Regenerate.
1042
39d911fc
TP		 10432016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1044
1045 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1046 branch type of a symbol.
1047 (print_insn): Likewise.
1048
16a1fa25
TP		 10492016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1050
1051 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1052 Mainline Security Extensions instructions.
1053 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1054 Extensions instructions.
1055 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1056 instructions.
1057 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1058 special registers.
1059
d751b79e
JM		 10602016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1061
1062 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1063
945e0f82
CZ		 10642016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1065
1066 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1067 (arcExtMap_genOpcode): Likewise.
1068 * arc-opc.c (arg_32bit_rc): Define new variable.
1069 (arg_32bit_u6): Likewise.
1070 (arg_32bit_limm): Likewise.
1071
20f55f38
SN		 10722016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1073
1074 * aarch64-gen.c (VERIFIER): Define.
1075 * aarch64-opc.c (VERIFIER): Define.
1076 (verify_ldpsw): Use static linkage.
1077 * aarch64-opc.h (verify_ldpsw): Remove.
1078 * aarch64-tbl.h: Use VERIFIER for verifiers.
1079
4bd13cde
NC		 10802016-04-28 Nick Clifton <nickc@redhat.com>
1081
1082 PR target/19722
1083 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1084 * aarch64-opc.c (verify_ldpsw): New function.
1085 * aarch64-opc.h (verify_ldpsw): New prototype.
1086 * aarch64-tbl.h: Add initialiser for verifier field.
1087 (LDPSW): Set verifier to verify_ldpsw.
1088
c0f92bf9
L		 10892016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1090
1091 PR binutils/19983
1092 PR binutils/19984
1093 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1094 smaller than address size.
1095
e6c7cdec
TS		 10962016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1097
1098 * alpha-dis.c: Regenerate.
1099 * crx-dis.c: Likewise.
1100 * disassemble.c: Likewise.
1101 * epiphany-opc.c: Likewise.
1102 * fr30-opc.c: Likewise.
1103 * frv-opc.c: Likewise.
1104 * ip2k-opc.c: Likewise.
1105 * iq2000-opc.c: Likewise.
1106 * lm32-opc.c: Likewise.
1107 * lm32-opinst.c: Likewise.
1108 * m32c-opc.c: Likewise.
1109 * m32r-opc.c: Likewise.
1110 * m32r-opinst.c: Likewise.
1111 * mep-opc.c: Likewise.
1112 * mt-opc.c: Likewise.
1113 * or1k-opc.c: Likewise.
1114 * or1k-opinst.c: Likewise.
1115 * tic80-opc.c: Likewise.
1116 * xc16x-opc.c: Likewise.
1117 * xstormy16-opc.c: Likewise.
1118
537aefaf
AB		 11192016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1120
1121 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1122 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1123 calcsd, and calcxd instructions.
1124 * arc-opc.c (insert_nps_bitop_size): Delete.
1125 (extract_nps_bitop_size): Delete.
1126 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1127 (extract_nps_qcmp_m3): Define.
1128 (extract_nps_qcmp_m2): Define.
1129 (extract_nps_qcmp_m1): Define.
1130 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1131 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1132 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1133 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1134 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1135 NPS_QCMP_M3.
1136
c8f785f2
AB		 11372016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1138
1139 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1140
6fd8e7c2
L		 11412016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1142
1143 * Makefile.in: Regenerated with automake 1.11.6.
1144 * aclocal.m4: Likewise.
1145
4b0c052e
AB		 11462016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1147
1148 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1149 instructions.
1150 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1151 (extract_nps_cmem_uimm16): New function.
1152 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1153
cb040366
AB		 11542016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1155
1156 * arc-dis.c (arc_insn_length): New function.
1157 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1158 (find_format): Change insnLen parameter to unsigned.
1159
accc0180
NC		 11602016-04-13 Nick Clifton <nickc@redhat.com>
1161
1162 PR target/19937
1163 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1164 the LD.B and LD.BU instructions.
1165
f36e33da
CZ		 11662016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1167
1168 * arc-dis.c (find_format): Check for extension flags.
1169 (print_flags): New function.
1170 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1171 .extAuxRegister.
1172 * arc-ext.c (arcExtMap_coreRegName): Use
1173 LAST_EXTENSION_CORE_REGISTER.
1174 (arcExtMap_coreReadWrite): Likewise.
1175 (dump_ARC_extmap): Update printing.
1176 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1177 (arc_aux_regs): Add cpu field.
1178 * arc-regs.h: Add cpu field, lower case name aux registers.
1179
1c2e355e
CZ		 11802016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1181
1182 * arc-tbl.h: Add rtsc, sleep with no arguments.
1183
b99747ae
CZ		 11842016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1185
1186 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1187 Initialize.
1188 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1189 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1190 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1191 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1192 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1193 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1194 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1195 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1196 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1197 (arc_opcode arc_opcodes): Null terminate the array.
1198 (arc_num_opcodes): Remove.
1199 * arc-ext.h (INSERT_XOP): Define.
1200 (extInstruction_t): Likewise.
1201 (arcExtMap_instName): Delete.
1202 (arcExtMap_insn): New function.
1203 (arcExtMap_genOpcode): Likewise.
1204 * arc-ext.c (ExtInstruction): Remove.
1205 (create_map): Zero initialize instruction fields.
1206 (arcExtMap_instName): Remove.
1207 (arcExtMap_insn): New function.
1208 (dump_ARC_extmap): More info while debuging.
1209 (arcExtMap_genOpcode): New function.
1210 * arc-dis.c (find_format): New function.
1211 (print_insn_arc): Use find_format.
1212 (arc_get_disassembler): Enable dump_ARC_extmap only when
1213 debugging.
1214
92708cec
MR		 12152016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1216
1217 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1218 instruction bits out.
1219
a42a4f84
AB		 12202016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1221
1222 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1223 * arc-opc.c (arc_flag_operands): Add new flags.
1224 (arc_flag_classes): Add new classes.
1225
1328504b
AB		 12262016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1227
1228 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1229
820f03ff
AB		 12302016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1231
1232 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1233 encode1, rflt, crc16, and crc32 instructions.
1234 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1235 (arc_flag_classes): Add C_NPS_R.
1236 (insert_nps_bitop_size_2b): New function.
1237 (extract_nps_bitop_size_2b): Likewise.
1238 (insert_nps_bitop_uimm8): Likewise.
1239 (extract_nps_bitop_uimm8): Likewise.
1240 (arc_operands): Add new operand entries.
1241
8ddf6b2a
CZ		 12422016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1243
b99747ae
CZ		 1244 * arc-regs.h: Add a new subclass field. Add double assist
1245 accumulator register values.
1246 * arc-tbl.h: Use DPA subclass to mark the double assist
1247 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1248 * arc-opc.c (RSP): Define instead of SP.
1249 (arc_aux_regs): Add the subclass field.
8ddf6b2a 1250
589a7d88
JW		 12512016-04-05 Jiong Wang <jiong.wang@arm.com>
1252
1253 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1254
0a191de9 12552016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 1256
1257 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1258 NPS_R_SRC1.
1259
0a106562
AB		 12602016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1261
1262 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1263 issues. No functional changes.
1264
bd05ac5f
CZ		 12652016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1266
b99747ae
CZ		 1267 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1268 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1269 (RTT): Remove duplicate.
1270 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1271 (PCT_CONFIG*): Remove.
1272 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 1273
9885948f
CZ		 12742016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1275
b99747ae 1276 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 1277
f2dd8838
CZ		 12782016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1279
b99747ae
CZ		 1280 * arc-tbl.h (invld07): Remove.
1281 * arc-ext-tbl.h: New file.
1282 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1283 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 1284
0d2f91fe
JK		 12852016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1286
1287 Fix -Wstack-usage warnings.
1288 * aarch64-dis.c (print_operands): Substitute size.
1289 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1290
a6b71f42
JM		 12912016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1292
1293 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1294 to get a proper diagnostic when an invalid ASR register is used.
1295
9780e045
NC		 12962016-03-22 Nick Clifton <nickc@redhat.com>
1297
1298 * configure: Regenerate.
1299
e23e8ebe
AB		 13002016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1301
1302 * arc-nps400-tbl.h: New file.
1303 * arc-opc.c: Add top level comment.
1304 (insert_nps_3bit_dst): New function.
1305 (extract_nps_3bit_dst): New function.
1306 (insert_nps_3bit_src2): New function.
1307 (extract_nps_3bit_src2): New function.
1308 (insert_nps_bitop_size): New function.
1309 (extract_nps_bitop_size): New function.
1310 (arc_flag_operands): Add nps400 entries.
1311 (arc_flag_classes): Add nps400 entries.
1312 (arc_operands): Add nps400 entries.
1313 (arc_opcodes): Add nps400 include.
1314
1ae8ab47
AB		 13152016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1316
1317 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1318 the new class enum values.
1319
8699fc3e
AB		 13202016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1321
1322 * arc-dis.c (print_insn_arc): Handle nps400.
1323
24740d83
AB		 13242016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1325
1326 * arc-opc.c (BASE): Delete.
1327
8678914f
NC		 13282016-03-18 Nick Clifton <nickc@redhat.com>
1329
1330 PR target/19721
1331 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1332 of MOV insn that aliases an ORR insn.
1333
cc933301
JW		 13342016-03-16 Jiong Wang <jiong.wang@arm.com>
1335
1336 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1337
f86f5863
TS		 13382016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1339
1340 * mcore-opc.h: Add const qualifiers.
1341 * microblaze-opc.h (struct op_code_struct): Likewise.
1342 * sh-opc.h: Likewise.
1343 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1344 (tic4x_print_op): Likewise.
1345
62de1c63
AM		 13462016-03-02 Alan Modra <amodra@gmail.com>
1347
d11698cd 1348 * or1k-desc.h: Regenerate.
62de1c63 1349 * fr30-ibld.c: Regenerate.
c697cf0b 1350 * rl78-decode.c: Regenerate.
62de1c63 1351
020efce5
NC		 13522016-03-01 Nick Clifton <nickc@redhat.com>
1353
1354 PR target/19747
1355 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1356
b0c11777
RL		 13572016-02-24 Renlin Li <renlin.li@arm.com>
1358
1359 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1360 (print_insn_coprocessor): Support fp16 instructions.
1361
3e309328
RL		 13622016-02-24 Renlin Li <renlin.li@arm.com>
1363
1364 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1365 vminnm, vrint(mpna).
1366
8afc7bea
RL		 13672016-02-24 Renlin Li <renlin.li@arm.com>
1368
1369 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1370 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1371
4fd7268a
L		 13722016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1373
1374 * i386-dis.c (print_insn): Parenthesize expression to prevent
1375 truncated addresses.
1376 (OP_J): Likewise.
1377
4670103e
CZ		 13782016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1379 Janek van Oirschot <jvanoirs@synopsys.com>
1380
b99747ae
CZ		 1381 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1382 variable.
4670103e 1383
c1d9289f
NC		 13842016-02-04 Nick Clifton <nickc@redhat.com>
1385
1386 PR target/19561
1387 * msp430-dis.c (print_insn_msp430): Add a special case for
1388 decoding an RRC instruction with the ZC bit set in the extension
1389 word.
1390
a143b004
AB		 13912016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1392
1393 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1394 * epiphany-ibld.c: Regenerate.
1395 * fr30-ibld.c: Regenerate.
1396 * frv-ibld.c: Regenerate.
1397 * ip2k-ibld.c: Regenerate.
1398 * iq2000-ibld.c: Regenerate.
1399 * lm32-ibld.c: Regenerate.
1400 * m32c-ibld.c: Regenerate.
1401 * m32r-ibld.c: Regenerate.
1402 * mep-ibld.c: Regenerate.
1403 * mt-ibld.c: Regenerate.
1404 * or1k-ibld.c: Regenerate.
1405 * xc16x-ibld.c: Regenerate.
1406 * xstormy16-ibld.c: Regenerate.
1407
b89807c6
AB		 14082016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1409
1410 * epiphany-dis.c: Regenerated from latest cpu files.
1411
d8c823c8
MM		 14122016-02-01 Michael McConville <mmcco@mykolab.com>
1413
1414 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1415 test bit.
1416
5bc5ae88
RL		 14172016-01-25 Renlin Li <renlin.li@arm.com>
1418
1419 * arm-dis.c (mapping_symbol_for_insn): New function.
1420 (find_ifthen_state): Call mapping_symbol_for_insn().
1421
0bff6e2d
MW		 14222016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1423
1424 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1425 of MSR UAO immediate operand.
1426
100b4f2e
MR		 14272016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1428
1429 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1430 instruction support.
1431
5c14705f
AM		 14322016-01-17 Alan Modra <amodra@gmail.com>
1433
1434 * configure: Regenerate.
1435
4d82fe66
NC		 14362016-01-14 Nick Clifton <nickc@redhat.com>
1437
1438 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1439 instructions that can support stack pointer operations.
1440 * rl78-decode.c: Regenerate.
1441 * rl78-dis.c: Fix display of stack pointer in MOVW based
1442 instructions.
1443
651657fa
MW		 14442016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1445
1446 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1447 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1448 erxtatus_el1 and erxaddr_el1.
1449
105bde57
MW		 14502016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1451
1452 * arm-dis.c (arm_opcodes): Add "esb".
1453 (thumb_opcodes): Likewise.
1454
afa8d405
PB		 14552016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1456
1457 * ppc-opc.c <xscmpnedp>: Delete.
1458 <xvcmpnedp>: Likewise.
1459 <xvcmpnedp.>: Likewise.
1460 <xvcmpnesp>: Likewise.
1461 <xvcmpnesp.>: Likewise.
1462
83c3256e
AS		 14632016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1464
1465 PR gas/13050
1466 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1467 addition to ISA_A.
1468
6f2750fe
AM		 14692016-01-01 Alan Modra <amodra@gmail.com>
1470
1471 Update year range in copyright notice of all files.
1472
3499769a
AM		 1473For older changes see ChangeLog-2015
1474\f
1475Copyright (C) 2016 Free Software Foundation, Inc.
1476
1477Copying and distribution of this file, with or without modification,
1478are permitted in any medium without royalty provided the copyright
1479notice and this notice are preserved.
1480
1481Local Variables:
1482mode: change-log
1483left-margin: 8
1484fill-column: 74
1485version-control: never
1486End:
GDB Binutils - Deliverables
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