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[AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALED
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
2442d846
RS		 12016-09-21 Richard Sandiford <richard.sandiford@arm.com>
2
3 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
4 AARCH64_OPND_SVE_PATTERN_SCALED.
5 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
6 * aarch64-opc.c (fields): Add a corresponding entry.
7 (set_multiplier_out_of_range_error): New function.
8 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
9 (operand_general_constraint_met_p): Handle
10 AARCH64_OPND_SVE_PATTERN_SCALED.
11 (print_register_offset_address): Use PRIi64 to print the
12 shift amount.
13 (aarch64_print_operand): Likewise. Handle
14 AARCH64_OPND_SVE_PATTERN_SCALED.
15 * aarch64-opc-2.c: Regenerate.
16 * aarch64-asm.h (ins_sve_scale): New inserter.
17 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
18 * aarch64-asm-2.c: Regenerate.
19 * aarch64-dis.h (ext_sve_scale): New inserter.
20 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
21 * aarch64-dis-2.c: Regenerate.
22
245d2e3f
RS		 232016-09-21 Richard Sandiford <richard.sandiford@arm.com>
24
25 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
26 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
27 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
28 (FLD_SVE_prfop): Likewise.
29 * aarch64-opc.c: Include libiberty.h.
30 (aarch64_sve_pattern_array): New variable.
31 (aarch64_sve_prfop_array): Likewise.
32 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
33 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
34 AARCH64_OPND_SVE_PRFOP.
35 * aarch64-asm-2.c: Regenerate.
36 * aarch64-dis-2.c: Likewise.
37 * aarch64-opc-2.c: Likewise.
38
d50c751e
RS		 392016-09-21 Richard Sandiford <richard.sandiford@arm.com>
40
41 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
42 AARCH64_OPND_QLF_P_[ZM].
43 (aarch64_print_operand): Print /z and /m where appropriate.
44
f11ad6bc
RS		 452016-09-21 Richard Sandiford <richard.sandiford@arm.com>
46
47 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
48 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
49 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
50 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
51 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
52 * aarch64-opc.c (fields): Add corresponding entries here.
53 (operand_general_constraint_met_p): Check that SVE register lists
54 have the correct length. Check the ranges of SVE index registers.
55 Check for cases where p8-p15 are used in 3-bit predicate fields.
56 (aarch64_print_operand): Handle the new SVE operands.
57 * aarch64-opc-2.c: Regenerate.
58 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
59 * aarch64-asm.c (aarch64_ins_sve_index): New function.
60 (aarch64_ins_sve_reglist): Likewise.
61 * aarch64-asm-2.c: Regenerate.
62 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
63 * aarch64-dis.c (aarch64_ext_sve_index): New function.
64 (aarch64_ext_sve_reglist): Likewise.
65 * aarch64-dis-2.c: Regenerate.
66
0c608d6b
RS		 672016-09-21 Richard Sandiford <richard.sandiford@arm.com>
68
69 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
70 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
71 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
72 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
73 tied operands.
74
01dbfe4c
RS		 752016-09-21 Richard Sandiford <richard.sandiford@arm.com>
76
77 * aarch64-opc.c (get_offset_int_reg_name): New function.
78 (print_immediate_offset_address): Likewise.
79 (print_register_offset_address): Take the base and offset
80 registers as parameters.
81 (aarch64_print_operand): Update caller accordingly. Use
82 print_immediate_offset_address.
83
72e9f319
RS		 842016-09-21 Richard Sandiford <richard.sandiford@arm.com>
85
86 * aarch64-opc.c (BANK): New macro.
87 (R32, R64): Take a register number as argument
88 (int_reg): Use BANK.
89
8a7f0c1b
RS		 902016-09-21 Richard Sandiford <richard.sandiford@arm.com>
91
92 * aarch64-opc.c (print_register_list): Add a prefix parameter.
93 (aarch64_print_operand): Update accordingly.
94
aa2aa4c6
RS		 952016-09-21 Richard Sandiford <richard.sandiford@arm.com>
96
97 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
98 for FPIMM.
99 * aarch64-asm.h (ins_fpimm): New inserter.
100 * aarch64-asm.c (aarch64_ins_fpimm): New function.
101 * aarch64-asm-2.c: Regenerate.
102 * aarch64-dis.h (ext_fpimm): New extractor.
103 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
104 (aarch64_ext_fpimm): New function.
105 * aarch64-dis-2.c: Regenerate.
106
b5464a68
RS		 1072016-09-21 Richard Sandiford <richard.sandiford@arm.com>
108
109 * aarch64-asm.c: Include libiberty.h.
110 (insert_fields): New function.
111 (aarch64_ins_imm): Use it.
112 * aarch64-dis.c (extract_fields): New function.
113 (aarch64_ext_imm): Use it.
114
42408347
RS		 1152016-09-21 Richard Sandiford <richard.sandiford@arm.com>
116
117 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
118 with an esize parameter.
119 (operand_general_constraint_met_p): Update accordingly.
120 Fix misindented code.
121 * aarch64-asm.c (aarch64_ins_limm): Update call to
122 aarch64_logical_immediate_p.
123
4989adac
RS		 1242016-09-21 Richard Sandiford <richard.sandiford@arm.com>
125
126 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
127
bd11d5d8
RS		 1282016-09-21 Richard Sandiford <richard.sandiford@arm.com>
129
130 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
131
f807f43d
CZ		 1322016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
133
134 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
135
fd486b63
PB		 1362016-09-14 Peter Bergner <bergner@vnet.ibm.com>
137
138 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
139 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
140 xor3>: Delete mnemonics.
141 <cp_abort>: Rename mnemonic from ...
142 <cpabort>: ...to this.
143 <setb>: Change to a X form instruction.
144 <sync>: Change to 1 operand form.
145 <copy>: Delete mnemonic.
146 <copy_first>: Rename mnemonic from ...
147 <copy>: ...to this.
148 <paste, paste.>: Delete mnemonics.
149 <paste_last>: Rename mnemonic from ...
150 <paste.>: ...to this.
151
dce08442
AK		 1522016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
153
154 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
155
952c3f51
AK		 1562016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
157
158 * s390-mkopc.c (main): Support alternate arch strings.
159
8b71537b
PS		 1602016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
161
162 * s390-opc.txt: Fix kmctr instruction type.
163
5b64d091
L		 1642016-09-07 H.J. Lu <hongjiu.lu@intel.com>
165
166 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
167 * i386-init.h: Regenerated.
168
7763838e
CM		 1692016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
170
171 * opcodes/arc-dis.c (print_insn_arc): Changed.
172
1b8b6532
JM		 1732016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
174
175 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
176 camellia_fl.
177
1a336194
TP		 1782016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
179
180 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
181 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
182 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
183
6b40c462
L		 1842016-08-24 H.J. Lu <hongjiu.lu@intel.com>
185
186 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
187 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
188 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
189 PREFIX_MOD_3_0FAE_REG_4.
190 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
191 PREFIX_MOD_3_0FAE_REG_4.
192 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
193 (cpu_flags): Add CpuPTWRITE.
194 * i386-opc.h (CpuPTWRITE): New.
195 (i386_cpu_flags): Add cpuptwrite.
196 * i386-opc.tbl: Add ptwrite instruction.
197 * i386-init.h: Regenerated.
198 * i386-tbl.h: Likewise.
199
ab548d2d
AK		 2002016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
201
202 * arc-dis.h: Wrap around in extern "C".
203
344bde0a
RS		 2042016-08-23 Richard Sandiford <richard.sandiford@arm.com>
205
206 * aarch64-tbl.h (V8_2_INSN): New macro.
207 (aarch64_opcode_table): Use it.
208
5ce912d8
RS		 2092016-08-23 Richard Sandiford <richard.sandiford@arm.com>
210
211 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
212 CORE_INSN, __FP_INSN and SIMD_INSN.
213
9d30b0bd
RS		 2142016-08-23 Richard Sandiford <richard.sandiford@arm.com>
215
216 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
217 (aarch64_opcode_table): Update uses accordingly.
218
dfdaec14
AJ		 2192016-07-25 Andrew Jenner <andrew@codesourcery.com>
220 Kwok Cheung Yeung <kcy@codesourcery.com>
221
222 opcodes/
223 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
224 'e_cmplwi' to 'e_cmpli' instead.
225 (OPVUPRT, OPVUPRT_MASK): Define.
226 (powerpc_opcodes): Add E200Z4 insns.
227 (vle_opcodes): Add context save/restore insns.
228
7bd374a4
MR		 2292016-07-27 Maciej W. Rozycki <macro@imgtec.com>
230
231 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
232 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
233 "j".
234
db18dbab
GM		 2352016-07-27 Graham Markall <graham.markall@embecosm.com>
236
237 * arc-nps400-tbl.h: Change block comments to GNU format.
238 * arc-dis.c: Add new globals addrtypenames,
239 addrtypenames_max, and addtypeunknown.
240 (get_addrtype): New function.
241 (print_insn_arc): Print colons and address types when
242 required.
243 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
244 define insert and extract functions for all address types.
245 (arc_operands): Add operands for colon and all address
246 types.
247 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
248 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
249 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
250 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
251 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
252 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
253
fecd57f9
L		 2542016-07-21 H.J. Lu <hongjiu.lu@intel.com>
255
256 * configure: Regenerated.
257
37fd5ef3
CZ		 2582016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
259
260 * arc-dis.c (skipclass): New structure.
261 (decodelist): New variable.
262 (is_compatible_p): New function.
263 (new_element): Likewise.
264 (skip_class_p): Likewise.
265 (find_format_from_table): Use skip_class_p function.
266 (find_format): Decode first the extension instructions.
267 (print_insn_arc): Select either ARCEM or ARCHS based on elf
268 e_flags.
269 (parse_option): New function.
270 (parse_disassembler_options): Likewise.
271 (print_arc_disassembler_options): Likewise.
272 (print_insn_arc): Use parse_disassembler_options function. Proper
273 select ARCv2 cpu variant.
274 * disassemble.c (disassembler_usage): Add ARC disassembler
275 options.
276
92281a5b
MR		 2772016-07-13 Maciej W. Rozycki <macro@imgtec.com>
278
279 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
280 annotation from the "nal" entry and reorder it beyond "bltzal".
281
6e7ced37
JM		 2822016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
283
284 * sparc-opc.c (ldtxa): New macro.
285 (sparc_opcodes): Use the macro defined above to add entries for
286 the LDTXA instructions.
287 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
288 instruction.
289
2f831b9a 2902016-07-07 James Bowman <james.bowman@ftdichip.com>
291
292 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
293 and "jmpc".
294
c07315e0
JB		 2952016-07-01 Jan Beulich <jbeulich@suse.com>
296
297 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
298 (movzb): Adjust to cover all permitted suffixes.
299 (movzw): New.
300 * i386-tbl.h: Re-generate.
301
9243100a
JB		 3022016-07-01 Jan Beulich <jbeulich@suse.com>
303
304 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
305 (lgdt): Remove Tbyte from non-64-bit variant.
306 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
307 xsaves64, xsavec64): Remove Disp16.
308 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
309 Remove Disp32S from non-64-bit variants. Remove Disp16 from
310 64-bit variants.
311 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
312 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
313 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
314 64-bit variants.
315 * i386-tbl.h: Re-generate.
316
8325cc63
JB		 3172016-07-01 Jan Beulich <jbeulich@suse.com>
318
319 * i386-opc.tbl (xlat): Remove RepPrefixOk.
320 * i386-tbl.h: Re-generate.
321
838441e4
YQ		 3222016-06-30 Yao Qi <yao.qi@linaro.org>
323
324 * arm-dis.c (print_insn): Fix typo in comment.
325
dab26bf4
RS		 3262016-06-28 Richard Sandiford <richard.sandiford@arm.com>
327
328 * aarch64-opc.c (operand_general_constraint_met_p): Check the
329 range of ldst_elemlist operands.
330 (print_register_list): Use PRIi64 to print the index.
331 (aarch64_print_operand): Likewise.
332
5703197e
TS		 3332016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
334
335 * mcore-opc.h: Remove sentinal.
336 * mcore-dis.c (print_insn_mcore): Adjust.
337
ce440d63
GM		 3382016-06-23 Graham Markall <graham.markall@embecosm.com>
339
340 * arc-opc.c: Correct description of availability of NPS400
341 features.
342
6fd3a02d
PB		 3432016-06-22 Peter Bergner <bergner@vnet.ibm.com>
344
345 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
346 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
347 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
348 xor3>: New mnemonics.
349 <setb>: Change to a VX form instruction.
350 (insert_sh6): Add support for rldixor.
351 (extract_sh6): Likewise.
352
6b477896
TS		 3532016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
354
355 * arc-ext.h: Wrap in extern C.
356
bdd582db
GM		 3572016-06-21 Graham Markall <graham.markall@embecosm.com>
358
359 * arc-dis.c (arc_insn_length): Add comment on instruction length.
360 Use same method for determining instruction length on ARC700 and
361 NPS-400.
362 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
363 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
364 with the NPS400 subclass.
365 * arc-opc.c: Likewise.
366
96074adc
JM		 3672016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
368
369 * sparc-opc.c (rdasr): New macro.
370 (wrasr): Likewise.
371 (rdpr): Likewise.
372 (wrpr): Likewise.
373 (rdhpr): Likewise.
374 (wrhpr): Likewise.
375 (sparc_opcodes): Use the macros above to fix and expand the
376 definition of read/write instructions from/to
377 asr/privileged/hyperprivileged instructions.
378 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
379 %hva_mask_nz. Prefer softint_set and softint_clear over
380 set_softint and clear_softint.
381 (print_insn_sparc): Support %ver in Rd.
382
7a10c22f
JM		 3832016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
384
385 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
386 architecture according to the hardware capabilities they require.
387
4f26fb3a
JM		 3882016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
389
390 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
391 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
392 bfd_mach_sparc_v9{c,d,e,v,m}.
393 * sparc-opc.c (MASK_V9C): Define.
394 (MASK_V9D): Likewise.
395 (MASK_V9E): Likewise.
396 (MASK_V9V): Likewise.
397 (MASK_V9M): Likewise.
398 (v6): Add MASK_V9{C,D,E,V,M}.
399 (v6notlet): Likewise.
400 (v7): Likewise.
401 (v8): Likewise.
402 (v9): Likewise.
403 (v9andleon): Likewise.
404 (v9a): Likewise.
405 (v9b): Likewise.
406 (v9c): Define.
407 (v9d): Likewise.
408 (v9e): Likewise.
409 (v9v): Likewise.
410 (v9m): Likewise.
411 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
412
3ee6e4fb
NC		 4132016-06-15 Nick Clifton <nickc@redhat.com>
414
415 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
416 constants to match expected behaviour.
417 (nds32_parse_opcode): Likewise. Also for whitespace.
418
02f3be19
AB		 4192016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
420
421 * arc-opc.c (extract_rhv1): Extract value from insn.
422
6f9f37ed 4232016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM		 424
425 * arc-nps400-tbl.h: Add ldbit instruction.
426 * arc-opc.c: Add flag classes required for ldbit.
427
6f9f37ed 4282016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM		 429
430 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
431 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
432 support the above instructions.
433
6f9f37ed 4342016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM		 435
436 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
437 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
438 csma, cbba, zncv, and hofs.
439 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
440 support the above instructions.
441
4422016-06-06 Graham Markall <graham.markall@embecosm.com>
443
444 * arc-nps400-tbl.h: Add andab and orab instructions.
445
4462016-06-06 Graham Markall <graham.markall@embecosm.com>
447
448 * arc-nps400-tbl.h: Add addl-like instructions.
449
4502016-06-06 Graham Markall <graham.markall@embecosm.com>
451
452 * arc-nps400-tbl.h: Add mxb and imxb instructions.
453
4542016-06-06 Graham Markall <graham.markall@embecosm.com>
455
456 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
457 instructions.
458
b2cc3f6f
AK		 4592016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
460
461 * s390-dis.c (option_use_insn_len_bits_p): New file scope
462 variable.
463 (init_disasm): Handle new command line option "insnlength".
464 (print_s390_disassembler_options): Mention new option in help
465 output.
466 (print_insn_s390): Use the encoded insn length when dumping
467 unknown instructions.
468
1857fe72
DC		 4692016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
470
471 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
472 to the address and set as symbol address for LDS/ STS immediate operands.
473
14b57c7c
AM		 4742016-06-07 Alan Modra <amodra@gmail.com>
475
476 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
477 cpu for "vle" to e500.
478 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
479 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
480 (PPCNONE): Delete, substitute throughout.
481 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
482 except for major opcode 4 and 31.
483 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
484
4d1464f2
MW		 4852016-06-07 Matthew Wahab <matthew.wahab@arm.com>
486
487 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
488 ARM_EXT_RAS in relevant entries.
489
026122a6
PB		 4902016-06-03 Peter Bergner <bergner@vnet.ibm.com>
491
492 PR binutils/20196
493 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
494 opcodes for E6500.
495
07f5af7d
L		 4962016-06-03 H.J. Lu <hongjiu.lu@intel.com>
497
498 PR binutis/18386
499 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
500 (indir_v_mode): New.
501 Add comments for '&'.
502 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
503 (putop): Handle '&'.
504 (intel_operand_size): Handle indir_v_mode.
505 (OP_E_register): Likewise.
506 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
507 64-bit indirect call/jmp for AMD64.
508 * i386-tbl.h: Regenerated
509
4eb6f892
AB		 5102016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
511
512 * arc-dis.c (struct arc_operand_iterator): New structure.
513 (find_format_from_table): All the old content from find_format,
514 with some minor adjustments, and parameter renaming.
515 (find_format_long_instructions): New function.
516 (find_format): Rewritten.
517 (arc_insn_length): Add LSB parameter.
518 (extract_operand_value): New function.
519 (operand_iterator_next): New function.
520 (print_insn_arc): Use new functions to find opcode, and iterator
521 over operands.
522 * arc-opc.c (insert_nps_3bit_dst_short): New function.
523 (extract_nps_3bit_dst_short): New function.
524 (insert_nps_3bit_src2_short): New function.
525 (extract_nps_3bit_src2_short): New function.
526 (insert_nps_bitop1_size): New function.
527 (extract_nps_bitop1_size): New function.
528 (insert_nps_bitop2_size): New function.
529 (extract_nps_bitop2_size): New function.
530 (insert_nps_bitop_mod4_msb): New function.
531 (extract_nps_bitop_mod4_msb): New function.
532 (insert_nps_bitop_mod4_lsb): New function.
533 (extract_nps_bitop_mod4_lsb): New function.
534 (insert_nps_bitop_dst_pos3_pos4): New function.
535 (extract_nps_bitop_dst_pos3_pos4): New function.
536 (insert_nps_bitop_ins_ext): New function.
537 (extract_nps_bitop_ins_ext): New function.
538 (arc_operands): Add new operands.
539 (arc_long_opcodes): New global array.
540 (arc_num_long_opcodes): New global.
541 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
542
1fe0971e
TS		 5432016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
544
545 * nds32-asm.h: Add extern "C".
546 * sh-opc.h: Likewise.
547
315f180f
GM		 5482016-06-01 Graham Markall <graham.markall@embecosm.com>
549
550 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
551 0,b,limm to the rflt instruction.
552
a2b5fccc
TS		 5532016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
554
555 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
556 constant.
557
0cbd0046
L		 5582016-05-29 H.J. Lu <hongjiu.lu@intel.com>
559
560 PR gas/20145
561 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
562 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
563 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
564 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
565 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
566 * i386-init.h: Regenerated.
567
1848e567
L		 5682016-05-27 H.J. Lu <hongjiu.lu@intel.com>
569
570 PR gas/20145
571 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
572 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
573 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
574 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
575 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
576 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
577 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
578 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
579 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
580 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
581 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
582 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
583 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
584 CpuRegMask for AVX512.
585 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
586 and CpuRegMask.
587 (set_bitfield_from_cpu_flag_init): New function.
588 (set_bitfield): Remove const on f. Call
589 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
590 * i386-opc.h (CpuRegMMX): New.
591 (CpuRegXMM): Likewise.
592 (CpuRegYMM): Likewise.
593 (CpuRegZMM): Likewise.
594 (CpuRegMask): Likewise.
595 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
596 and cpuregmask.
597 * i386-init.h: Regenerated.
598 * i386-tbl.h: Likewise.
599
e92bae62
L		 6002016-05-27 H.J. Lu <hongjiu.lu@intel.com>
601
602 PR gas/20154
603 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
604 (opcode_modifiers): Add AMD64 and Intel64.
605 (main): Properly verify CpuMax.
606 * i386-opc.h (CpuAMD64): Removed.
607 (CpuIntel64): Likewise.
608 (CpuMax): Set to CpuNo64.
609 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
610 (AMD64): New.
611 (Intel64): Likewise.
612 (i386_opcode_modifier): Add amd64 and intel64.
613 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
614 on call and jmp.
615 * i386-init.h: Regenerated.
616 * i386-tbl.h: Likewise.
617
e89c5eaa
L		 6182016-05-27 H.J. Lu <hongjiu.lu@intel.com>
619
620 PR gas/20154
621 * i386-gen.c (main): Fail if CpuMax is incorrect.
622 * i386-opc.h (CpuMax): Set to CpuIntel64.
623 * i386-tbl.h: Regenerated.
624
77d66e7b
NC		 6252016-05-27 Nick Clifton <nickc@redhat.com>
626
627 PR target/20150
628 * msp430-dis.c (msp430dis_read_two_bytes): New function.
629 (msp430dis_opcode_unsigned): New function.
630 (msp430dis_opcode_signed): New function.
631 (msp430_singleoperand): Use the new opcode reading functions.
632 Only disassenmble bytes if they were successfully read.
633 (msp430_doubleoperand): Likewise.
634 (msp430_branchinstr): Likewise.
635 (msp430x_callx_instr): Likewise.
636 (print_insn_msp430): Check that it is safe to read bytes before
637 attempting disassembly. Use the new opcode reading functions.
638
19dfcc89
PB		 6392016-05-26 Peter Bergner <bergner@vnet.ibm.com>
640
641 * ppc-opc.c (CY): New define. Document it.
642 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
643
f3ad7637
L		 6442016-05-25 H.J. Lu <hongjiu.lu@intel.com>
645
646 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
647 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
648 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
649 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
650 CPU_ANY_AVX_FLAGS.
651 * i386-init.h: Regenerated.
652
f1360d58
L		 6532016-05-25 H.J. Lu <hongjiu.lu@intel.com>
654
655 PR gas/20141
656 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
657 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
658 * i386-init.h: Regenerated.
659
293f5f65
L		 6602016-05-25 H.J. Lu <hongjiu.lu@intel.com>
661
662 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
663 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
664 * i386-init.h: Regenerated.
665
d9eca1df
CZ		 6662016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
667
668 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
669 information.
670 (print_insn_arc): Set insn_type information.
671 * arc-opc.c (C_CC): Add F_CLASS_COND.
672 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
673 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
674 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
675 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
676 (brne, brne_s, jeq_s, jne_s): Likewise.
677
87789e08
CZ		 6782016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
679
680 * arc-tbl.h (neg): New instruction variant.
681
c810e0b8
CZ		 6822016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
683
684 * arc-dis.c (find_format, find_format, get_auxreg)
685 (print_insn_arc): Changed.
686 * arc-ext.h (INSERT_XOP): Likewise.
687
3d207518
TS		 6882016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
689
690 * tic54x-dis.c (sprint_mmr): Adjust.
691 * tic54x-opc.c: Likewise.
692
514e58b7
AM		 6932016-05-19 Alan Modra <amodra@gmail.com>
694
695 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
696
e43de63c
AM		 6972016-05-19 Alan Modra <amodra@gmail.com>
698
699 * ppc-opc.c: Formatting.
700 (NSISIGNOPT): Define.
701 (powerpc_opcodes <subis>): Use NSISIGNOPT.
702
1401d2fe
MR		 7032016-05-18 Maciej W. Rozycki <macro@imgtec.com>
704
705 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
706 replacing references to `micromips_ase' throughout.
707 (_print_insn_mips): Don't use file-level microMIPS annotation to
708 determine the disassembly mode with the symbol table.
709
1178da44
PB		 7102016-05-13 Peter Bergner <bergner@vnet.ibm.com>
711
712 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
713
8f4f9071
MF		 7142016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
715
716 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
717 mips64r6.
718 * mips-opc.c (D34): New macro.
719 (mips_builtin_opcodes): Define bposge32c for DSPr3.
720
8bc52696
AF		 7212016-05-10 Alexander Fomin <alexander.fomin@intel.com>
722
723 * i386-dis.c (prefix_table): Add RDPID instruction.
724 * i386-gen.c (cpu_flag_init): Add RDPID flag.
725 (cpu_flags): Add RDPID bitfield.
726 * i386-opc.h (enum): Add RDPID element.
727 (i386_cpu_flags): Add RDPID field.
728 * i386-opc.tbl: Add RDPID instruction.
729 * i386-init.h: Regenerate.
730 * i386-tbl.h: Regenerate.
731
39d911fc
TP		 7322016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
733
734 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
735 branch type of a symbol.
736 (print_insn): Likewise.
737
16a1fa25
TP		 7382016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
739
740 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
741 Mainline Security Extensions instructions.
742 (thumb_opcodes): Add entries for narrow ARMv8-M Security
743 Extensions instructions.
744 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
745 instructions.
746 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
747 special registers.
748
d751b79e
JM		 7492016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
750
751 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
752
945e0f82
CZ		 7532016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
754
755 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
756 (arcExtMap_genOpcode): Likewise.
757 * arc-opc.c (arg_32bit_rc): Define new variable.
758 (arg_32bit_u6): Likewise.
759 (arg_32bit_limm): Likewise.
760
20f55f38
SN		 7612016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
762
763 * aarch64-gen.c (VERIFIER): Define.
764 * aarch64-opc.c (VERIFIER): Define.
765 (verify_ldpsw): Use static linkage.
766 * aarch64-opc.h (verify_ldpsw): Remove.
767 * aarch64-tbl.h: Use VERIFIER for verifiers.
768
4bd13cde
NC		 7692016-04-28 Nick Clifton <nickc@redhat.com>
770
771 PR target/19722
772 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
773 * aarch64-opc.c (verify_ldpsw): New function.
774 * aarch64-opc.h (verify_ldpsw): New prototype.
775 * aarch64-tbl.h: Add initialiser for verifier field.
776 (LDPSW): Set verifier to verify_ldpsw.
777
c0f92bf9
L		 7782016-04-23 H.J. Lu <hongjiu.lu@intel.com>
779
780 PR binutils/19983
781 PR binutils/19984
782 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
783 smaller than address size.
784
e6c7cdec
TS		 7852016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
786
787 * alpha-dis.c: Regenerate.
788 * crx-dis.c: Likewise.
789 * disassemble.c: Likewise.
790 * epiphany-opc.c: Likewise.
791 * fr30-opc.c: Likewise.
792 * frv-opc.c: Likewise.
793 * ip2k-opc.c: Likewise.
794 * iq2000-opc.c: Likewise.
795 * lm32-opc.c: Likewise.
796 * lm32-opinst.c: Likewise.
797 * m32c-opc.c: Likewise.
798 * m32r-opc.c: Likewise.
799 * m32r-opinst.c: Likewise.
800 * mep-opc.c: Likewise.
801 * mt-opc.c: Likewise.
802 * or1k-opc.c: Likewise.
803 * or1k-opinst.c: Likewise.
804 * tic80-opc.c: Likewise.
805 * xc16x-opc.c: Likewise.
806 * xstormy16-opc.c: Likewise.
807
537aefaf
AB		 8082016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
809
810 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
811 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
812 calcsd, and calcxd instructions.
813 * arc-opc.c (insert_nps_bitop_size): Delete.
814 (extract_nps_bitop_size): Delete.
815 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
816 (extract_nps_qcmp_m3): Define.
817 (extract_nps_qcmp_m2): Define.
818 (extract_nps_qcmp_m1): Define.
819 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
820 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
821 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
822 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
823 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
824 NPS_QCMP_M3.
825
c8f785f2
AB		 8262016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
827
828 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
829
6fd8e7c2
L		 8302016-04-15 H.J. Lu <hongjiu.lu@intel.com>
831
832 * Makefile.in: Regenerated with automake 1.11.6.
833 * aclocal.m4: Likewise.
834
4b0c052e
AB		 8352016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
836
837 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
838 instructions.
839 * arc-opc.c (insert_nps_cmem_uimm16): New function.
840 (extract_nps_cmem_uimm16): New function.
841 (arc_operands): Add NPS_XLDST_UIMM16 operand.
842
cb040366
AB		 8432016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
844
845 * arc-dis.c (arc_insn_length): New function.
846 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
847 (find_format): Change insnLen parameter to unsigned.
848
accc0180
NC		 8492016-04-13 Nick Clifton <nickc@redhat.com>
850
851 PR target/19937
852 * v850-opc.c (v850_opcodes): Correct masks for long versions of
853 the LD.B and LD.BU instructions.
854
f36e33da
CZ		 8552016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
856
857 * arc-dis.c (find_format): Check for extension flags.
858 (print_flags): New function.
859 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
860 .extAuxRegister.
861 * arc-ext.c (arcExtMap_coreRegName): Use
862 LAST_EXTENSION_CORE_REGISTER.
863 (arcExtMap_coreReadWrite): Likewise.
864 (dump_ARC_extmap): Update printing.
865 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
866 (arc_aux_regs): Add cpu field.
867 * arc-regs.h: Add cpu field, lower case name aux registers.
868
1c2e355e
CZ		 8692016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
870
871 * arc-tbl.h: Add rtsc, sleep with no arguments.
872
b99747ae
CZ		 8732016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
874
875 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
876 Initialize.
877 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
878 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
879 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
880 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
881 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
882 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
883 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
884 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
885 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
886 (arc_opcode arc_opcodes): Null terminate the array.
887 (arc_num_opcodes): Remove.
888 * arc-ext.h (INSERT_XOP): Define.
889 (extInstruction_t): Likewise.
890 (arcExtMap_instName): Delete.
891 (arcExtMap_insn): New function.
892 (arcExtMap_genOpcode): Likewise.
893 * arc-ext.c (ExtInstruction): Remove.
894 (create_map): Zero initialize instruction fields.
895 (arcExtMap_instName): Remove.
896 (arcExtMap_insn): New function.
897 (dump_ARC_extmap): More info while debuging.
898 (arcExtMap_genOpcode): New function.
899 * arc-dis.c (find_format): New function.
900 (print_insn_arc): Use find_format.
901 (arc_get_disassembler): Enable dump_ARC_extmap only when
902 debugging.
903
92708cec
MR		 9042016-04-11 Maciej W. Rozycki <macro@imgtec.com>
905
906 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
907 instruction bits out.
908
a42a4f84
AB		 9092016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
910
911 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
912 * arc-opc.c (arc_flag_operands): Add new flags.
913 (arc_flag_classes): Add new classes.
914
1328504b
AB		 9152016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
916
917 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
918
820f03ff
AB		 9192016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
920
921 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
922 encode1, rflt, crc16, and crc32 instructions.
923 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
924 (arc_flag_classes): Add C_NPS_R.
925 (insert_nps_bitop_size_2b): New function.
926 (extract_nps_bitop_size_2b): Likewise.
927 (insert_nps_bitop_uimm8): Likewise.
928 (extract_nps_bitop_uimm8): Likewise.
929 (arc_operands): Add new operand entries.
930
8ddf6b2a
CZ		 9312016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
932
b99747ae
CZ		 933 * arc-regs.h: Add a new subclass field. Add double assist
934 accumulator register values.
935 * arc-tbl.h: Use DPA subclass to mark the double assist
936 instructions. Use DPX/SPX subclas to mark the FPX instructions.
937 * arc-opc.c (RSP): Define instead of SP.
938 (arc_aux_regs): Add the subclass field.
8ddf6b2a 939
589a7d88
JW		 9402016-04-05 Jiong Wang <jiong.wang@arm.com>
941
942 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
943
0a191de9 9442016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 945
946 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
947 NPS_R_SRC1.
948
0a106562
AB		 9492016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
950
951 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
952 issues. No functional changes.
953
bd05ac5f
CZ		 9542016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
955
b99747ae
CZ		 956 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
957 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
958 (RTT): Remove duplicate.
959 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
960 (PCT_CONFIG*): Remove.
961 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 962
9885948f
CZ		 9632016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
964
b99747ae 965 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 966
f2dd8838
CZ		 9672016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
968
b99747ae
CZ		 969 * arc-tbl.h (invld07): Remove.
970 * arc-ext-tbl.h: New file.
971 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
972 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 973
0d2f91fe
JK		 9742016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
975
976 Fix -Wstack-usage warnings.
977 * aarch64-dis.c (print_operands): Substitute size.
978 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
979
a6b71f42
JM		 9802016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
981
982 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
983 to get a proper diagnostic when an invalid ASR register is used.
984
9780e045
NC		 9852016-03-22 Nick Clifton <nickc@redhat.com>
986
987 * configure: Regenerate.
988
e23e8ebe
AB		 9892016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
990
991 * arc-nps400-tbl.h: New file.
992 * arc-opc.c: Add top level comment.
993 (insert_nps_3bit_dst): New function.
994 (extract_nps_3bit_dst): New function.
995 (insert_nps_3bit_src2): New function.
996 (extract_nps_3bit_src2): New function.
997 (insert_nps_bitop_size): New function.
998 (extract_nps_bitop_size): New function.
999 (arc_flag_operands): Add nps400 entries.
1000 (arc_flag_classes): Add nps400 entries.
1001 (arc_operands): Add nps400 entries.
1002 (arc_opcodes): Add nps400 include.
1003
1ae8ab47
AB		 10042016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1005
1006 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1007 the new class enum values.
1008
8699fc3e
AB		 10092016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1010
1011 * arc-dis.c (print_insn_arc): Handle nps400.
1012
24740d83
AB		 10132016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1014
1015 * arc-opc.c (BASE): Delete.
1016
8678914f
NC		 10172016-03-18 Nick Clifton <nickc@redhat.com>
1018
1019 PR target/19721
1020 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1021 of MOV insn that aliases an ORR insn.
1022
cc933301
JW		 10232016-03-16 Jiong Wang <jiong.wang@arm.com>
1024
1025 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1026
f86f5863
TS		 10272016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1028
1029 * mcore-opc.h: Add const qualifiers.
1030 * microblaze-opc.h (struct op_code_struct): Likewise.
1031 * sh-opc.h: Likewise.
1032 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1033 (tic4x_print_op): Likewise.
1034
62de1c63
AM		 10352016-03-02 Alan Modra <amodra@gmail.com>
1036
d11698cd 1037 * or1k-desc.h: Regenerate.
62de1c63 1038 * fr30-ibld.c: Regenerate.
c697cf0b 1039 * rl78-decode.c: Regenerate.
62de1c63 1040
020efce5
NC		 10412016-03-01 Nick Clifton <nickc@redhat.com>
1042
1043 PR target/19747
1044 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1045
b0c11777
RL		 10462016-02-24 Renlin Li <renlin.li@arm.com>
1047
1048 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1049 (print_insn_coprocessor): Support fp16 instructions.
1050
3e309328
RL		 10512016-02-24 Renlin Li <renlin.li@arm.com>
1052
1053 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1054 vminnm, vrint(mpna).
1055
8afc7bea
RL		 10562016-02-24 Renlin Li <renlin.li@arm.com>
1057
1058 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1059 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1060
4fd7268a
L		 10612016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1062
1063 * i386-dis.c (print_insn): Parenthesize expression to prevent
1064 truncated addresses.
1065 (OP_J): Likewise.
1066
4670103e
CZ		 10672016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1068 Janek van Oirschot <jvanoirs@synopsys.com>
1069
b99747ae
CZ		 1070 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1071 variable.
4670103e 1072
c1d9289f
NC		 10732016-02-04 Nick Clifton <nickc@redhat.com>
1074
1075 PR target/19561
1076 * msp430-dis.c (print_insn_msp430): Add a special case for
1077 decoding an RRC instruction with the ZC bit set in the extension
1078 word.
1079
a143b004
AB		 10802016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1081
1082 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1083 * epiphany-ibld.c: Regenerate.
1084 * fr30-ibld.c: Regenerate.
1085 * frv-ibld.c: Regenerate.
1086 * ip2k-ibld.c: Regenerate.
1087 * iq2000-ibld.c: Regenerate.
1088 * lm32-ibld.c: Regenerate.
1089 * m32c-ibld.c: Regenerate.
1090 * m32r-ibld.c: Regenerate.
1091 * mep-ibld.c: Regenerate.
1092 * mt-ibld.c: Regenerate.
1093 * or1k-ibld.c: Regenerate.
1094 * xc16x-ibld.c: Regenerate.
1095 * xstormy16-ibld.c: Regenerate.
1096
b89807c6
AB		 10972016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1098
1099 * epiphany-dis.c: Regenerated from latest cpu files.
1100
d8c823c8
MM		 11012016-02-01 Michael McConville <mmcco@mykolab.com>
1102
1103 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1104 test bit.
1105
5bc5ae88
RL		 11062016-01-25 Renlin Li <renlin.li@arm.com>
1107
1108 * arm-dis.c (mapping_symbol_for_insn): New function.
1109 (find_ifthen_state): Call mapping_symbol_for_insn().
1110
0bff6e2d
MW		 11112016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1112
1113 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1114 of MSR UAO immediate operand.
1115
100b4f2e
MR		 11162016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1117
1118 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1119 instruction support.
1120
5c14705f
AM		 11212016-01-17 Alan Modra <amodra@gmail.com>
1122
1123 * configure: Regenerate.
1124
4d82fe66
NC		 11252016-01-14 Nick Clifton <nickc@redhat.com>
1126
1127 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1128 instructions that can support stack pointer operations.
1129 * rl78-decode.c: Regenerate.
1130 * rl78-dis.c: Fix display of stack pointer in MOVW based
1131 instructions.
1132
651657fa
MW		 11332016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1134
1135 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1136 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1137 erxtatus_el1 and erxaddr_el1.
1138
105bde57
MW		 11392016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1140
1141 * arm-dis.c (arm_opcodes): Add "esb".
1142 (thumb_opcodes): Likewise.
1143
afa8d405
PB		 11442016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1145
1146 * ppc-opc.c <xscmpnedp>: Delete.
1147 <xvcmpnedp>: Likewise.
1148 <xvcmpnedp.>: Likewise.
1149 <xvcmpnesp>: Likewise.
1150 <xvcmpnesp.>: Likewise.
1151
83c3256e
AS		 11522016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1153
1154 PR gas/13050
1155 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1156 addition to ISA_A.
1157
6f2750fe
AM		 11582016-01-01 Alan Modra <amodra@gmail.com>
1159
1160 Update year range in copyright notice of all files.
1161
3499769a
AM		 1162For older changes see ChangeLog-2015
1163\f
1164Copyright (C) 2016 Free Software Foundation, Inc.
1165
1166Copying and distribution of this file, with or without modification,
1167are permitted in any medium without royalty provided the copyright
1168notice and this notice are preserved.
1169
1170Local Variables:
1171mode: change-log
1172left-margin: 8
1173fill-column: 74
1174version-control: never
1175End:
GDB Binutils - Deliverables
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