[deliverable/binutils-gdb.git] / opcodes / ChangeLog

2013-03-27  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (get_sib): Add the sizeflag argument.  Properly
	check address mode.
	(print_insn): Pass sizeflag to get_sib.

2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>

	PR binutils/15068
	* tic6x-dis.c: Add support for displaying 16-bit insns.

2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>

	PR gas/15095
	* tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
	individual msb and lsb halves in src1 & src2 fields.  Discard the
	src1 (lsb) value and only use src2 (msb), discarding bit 0, to
	follow what Ti SDK does in that case as any value in the src1
	field yields the same output with SDK disassembler.

2013-03-12  Michael Eager <eager@eagercon.com>

	* opcodes/mips-dis.c (print_insn_args): Modify def of reg.

2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>

	* nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.

2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>

	* nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.

2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>

	* nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.

2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* arm-dis.c (arm_opcodes): Add entries for CRC instructions.
	(thumb32_opcodes): Likewise.
	(print_insn_thumb32): Handle 'S' control char.

2013-03-08  Yann Sionneau  <yann.sionneau@gmail.com>

	* lm32-desc.c: Regenerate.

2013-03-01  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-reg.tbl (riz): Add RegRex64.
	* i386-tbl.h: Regenerated.

2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
	(aarch64_feature_crc): New static.
	(CRC): New macro.
	(aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
	crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
	* aarch64-asm-2.c: Re-generate.
	* aarch64-dis-2.c: Ditto.
	* aarch64-opc-2.c: Ditto.

2013-02-27  Alan Modra  <amodra@gmail.com>

	* rl78-decode.opc (rl78_decode_opcode): Fix typo.
	* rl78-decode.c: Regenerate.

2013-02-25  Kaushik Phatak  <Kaushik.Phatak@kpitcummins.com>

	* rl78-decode.opc: Fix encoding of DIVWU insn.
	* rl78-decode.c: Regenerate.

2013-02-19  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/15159
	* i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.

	* i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
	(cpu_flags): Add CpuSMAP.

	* i386-opc.h (CpuSMAP): New.
	(i386_cpu_flags): Add cpusmap.

	* i386-opc.tbl: Add clac and stac.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2013-02-15  Markos Chandras  <markos.chandras@imgtec.com>

	* metag-dis.c: Initialize outf->bytes_per_chunk to 4
	which also makes the disassembler output be in little
	endian like it should be.

2013-02-14  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
	fields to NULL.
	(aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.

2013-02-13  Maciej W. Rozycki  <macro@codesourcery.com>

	* mips-dis.c (is_compressed_mode_p): Only match symbols from the
	section disassembled.

2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* arm-dis.c: Update strht pattern.

2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>

	* mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
	single-float.  Disable ll, lld, sc and scd for EE.  Disable the
	trunc.w.s macro for EE.

2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
            Andrew Jenner <andrew@codesourcery.com>

	Based on patches from Altera Corporation.

	* Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
	nios2-opc.c.
	* Makefile.in: Regenerated.
	* configure.in: Add case for bfd_nios2_arch.
	* configure: Regenerated.
	* disassemble.c (ARCH_nios2): Define.
	(disassembler): Add case for bfd_arch_nios2.
	* nios2-dis.c: New file.
	* nios2-opc.c: New file.

2013-02-04  Alan Modra  <amodra@gmail.com>

	* po/POTFILES.in: Regenerate.
	* rl78-decode.c: Regenerate.
	* rx-decode.c: Regenerate.

2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
	ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
	* aarch64-asm.c (convert_xtl_to_shll): New function.
	(convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	calling convert_xtl_to_shll.
	* aarch64-dis.c (convert_shll_to_xtl): New function.
	(convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	calling convert_shll_to_xtl.
	* aarch64-gen.c: Update copyright year.
	* aarch64-asm-2.c: Re-generate.
	* aarch64-dis-2.c: Re-generate.
	* aarch64-opc-2.c: Re-generate.

2013-01-24  Nick Clifton  <nickc@redhat.com>

	* v850-dis.c: Add support for e3v5 architecture.
	* v850-opc.c: Likewise.

2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
	* aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
	* aarch64-opc.c (operand_general_constraint_met_p): For
	AARCH64_MOD_LSL, move the range check on the shift amount before the
	alignment check; change to call set_sft_amount_out_of_range_error
	instead of set_imm_out_of_range_error.
	* aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
	(aarch64_opcode_table): Remove the OP enumerator from the asimdimm
	8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
	SIMD_IMM_SFT.

2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2013-01-15  Nick Clifton  <nickc@redhat.com>

	* v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
	values.
	* v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.

2013-01-14  Will Newton <will.newton@imgtec.com>

	* metag-dis.c (REG_WIDTH): Increase to 64.

2013-01-10  Peter Bergner <bergner@vnet.ibm.com>

	* ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
	* ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
	XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
	(SH6): Update.
	<"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
	"tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
	"treclaim.", "tsr.">: Add POWER8 HTM opcodes.
	<"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.

2013-01-10  Will Newton <will.newton@imgtec.com>

	* Makefile.am: Add Meta.
	* configure.in: Add Meta.
	* disassemble.c: Add Meta support.
	* metag-dis.c: New file.
	* Makefile.in: Regenerate.
	* configure: Regenerate.

2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>

	* cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
	(match_opcode): Rename to cr16_match_opcode.

2013-01-04  Juergen Urban <JuergenUrban@gmx.de>

	* mips-dis.c: Add names for CP0 registers of r5900.
	* mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
	instructions sq and lq.
	Add support for MIPS r5900 CPU.
	Add support for 128 bit MMI (Multimedia Instructions).
	Add support for EE instructions (Emotion Engine).
	Disable unsupported floating point instructions (64 bit and
	undefined compare operations).
	Enable instructions of MIPS ISA IV which are supported by r5900.
	Disable 64 bit co processor instructions.
	Disable 64 bit multiplication and division instructions.
	Disable instructions for co-processor 2 and 3, because these are
	not supported (preparation for later VU0 support (Vector Unit)).
	Disable cvt.w.s because this behaves like trunc.w.s and the
	correct execution can't be ensured on r5900.
	Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
	will confuse less developers and compilers.

2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-opc.c (aarch64_print_operand): Change to print
	AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
	in comment.
	* aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
	from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
	OP_MOV_IMM_WIDE.

2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
	PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.

2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (process_copyright): Update copyright year to 2013.

2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>

	* cr16-dis.c (match_opcode,make_instruction): Remove static
	declaration.
	(dwordU,wordU): Moved typedefs to opcode/cr16.h
	(cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.

For older changes see ChangeLog-2012
\f
Copyright (C) 2013 Free Software Foundation, Inc.

Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.

Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
Commit	Line	Data
55cf16e1 L	1	2013-03-27 H.J. Lu <hongjiu.lu@intel.com>
	2
	3	* i386-dis.c (get_sib): Add the sizeflag argument. Properly
	4	check address mode.
	5	(print_insn): Pass sizeflag to get_sib.
	6
51dcdd4d NC	7	2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
	8
	9	PR binutils/15068
	10	* tic6x-dis.c: Add support for displaying 16-bit insns.
	11
795b8e6b NC	12	2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
	13
	14	PR gas/15095
	15	* tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
	16	individual msb and lsb halves in src1 & src2 fields. Discard the
	17	src1 (lsb) value and only use src2 (msb), discarding bit 0, to
	18	follow what Ti SDK does in that case as any value in the src1
	19	field yields the same output with SDK disassembler.
	20
314d60dd ME	21	2013-03-12 Michael Eager <eager@eagercon.com>
314d60dd ME	22
795b8e6b	23	* opcodes/mips-dis.c (print_insn_args): Modify def of reg.
314d60dd	24
dad60f8e SL	25	2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
	26
	27	* nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
	28
f5cb796a SL	29	2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
	30
	31	* nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
	32
21fde85c SL	33	2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
	34
	35	* nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
	36
dd5181d5 KT	37	2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
	38
	39	* arm-dis.c (arm_opcodes): Add entries for CRC instructions.
	40	(thumb32_opcodes): Likewise.
	41	(print_insn_thumb32): Handle 'S' control char.
	42
87a8d6cb NC	43	2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
	44
	45	* lm32-desc.c: Regenerate.
	46
99dce992 L	47	2013-03-01 H.J. Lu <hongjiu.lu@intel.com>
	48
	49	* i386-reg.tbl (riz): Add RegRex64.
	50	* i386-tbl.h: Regenerated.
	51
e60bb1dd YZ	52	2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
	53
	54	* aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
	55	(aarch64_feature_crc): New static.
	56	(CRC): New macro.
	57	(aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
	58	crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
	59	* aarch64-asm-2.c: Re-generate.
	60	* aarch64-dis-2.c: Ditto.
	61	* aarch64-opc-2.c: Ditto.
	62
c7570fcd AM	63	2013-02-27 Alan Modra <amodra@gmail.com>
	64
	65	* rl78-decode.opc (rl78_decode_opcode): Fix typo.
	66	* rl78-decode.c: Regenerate.
	67
151fa98f NC	68	2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
	69
	70	* rl78-decode.opc: Fix encoding of DIVWU insn.
	71	* rl78-decode.c: Regenerate.
	72
5c111e37 L	73	2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
	74
	75	PR gas/15159
	76	* i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
	77
	78	* i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
	79	(cpu_flags): Add CpuSMAP.
	80
	81	* i386-opc.h (CpuSMAP): New.
	82	(i386_cpu_flags): Add cpusmap.
	83
	84	* i386-opc.tbl: Add clac and stac.
	85
	86	* i386-init.h: Regenerated.
	87	* i386-tbl.h: Likewise.
	88
9d1df426 NC	89	2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
	90
	91	* metag-dis.c: Initialize outf->bytes_per_chunk to 4
	92	which also makes the disassembler output be in little
	93	endian like it should be.
	94
a1ccaec9 YZ	95	2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
	96
	97	* aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
	98	fields to NULL.
	99	(aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
	100
ef068ef4	101	2013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
5417f71e MR	102
	103	* mips-dis.c (is_compressed_mode_p): Only match symbols from the
	104	section disassembled.
	105
6fe6ded9 RE	106	2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
	107
	108	* arm-dis.c: Update strht pattern.
	109
0aa27725 RS	110	2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
	111
	112	* mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
	113	single-float. Disable ll, lld, sc and scd for EE. Disable the
	114	trunc.w.s macro for EE.
	115
36591ba1 SL	116	2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
	117	Andrew Jenner <andrew@codesourcery.com>
	118
	119	Based on patches from Altera Corporation.
	120
	121	* Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
	122	nios2-opc.c.
	123	* Makefile.in: Regenerated.
	124	* configure.in: Add case for bfd_nios2_arch.
	125	* configure: Regenerated.
	126	* disassemble.c (ARCH_nios2): Define.
	127	(disassembler): Add case for bfd_arch_nios2.
	128	* nios2-dis.c: New file.
	129	* nios2-opc.c: New file.
	130
545093a4 AM	131	2013-02-04 Alan Modra <amodra@gmail.com>
	132
	133	* po/POTFILES.in: Regenerate.
	134	* rl78-decode.c: Regenerate.
	135	* rx-decode.c: Regenerate.
	136
e30181a5 YZ	137	2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
	138
	139	* aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
	140	ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
	141	* aarch64-asm.c (convert_xtl_to_shll): New function.
	142	(convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	143	calling convert_xtl_to_shll.
	144	* aarch64-dis.c (convert_shll_to_xtl): New function.
	145	(convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	146	calling convert_shll_to_xtl.
	147	* aarch64-gen.c: Update copyright year.
	148	* aarch64-asm-2.c: Re-generate.
	149	* aarch64-dis-2.c: Re-generate.
	150	* aarch64-opc-2.c: Re-generate.
	151
78c8d46c NC	152	2013-01-24 Nick Clifton <nickc@redhat.com>
	153
	154	* v850-dis.c: Add support for e3v5 architecture.
	155	* v850-opc.c: Likewise.
	156
f5555712 YZ	157	2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
	158
	159	* aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
	160	* aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
	161	* aarch64-opc.c (operand_general_constraint_met_p): For
78c8d46c	162	AARCH64_MOD_LSL, move the range check on the shift amount before the
f5555712 YZ	163	alignment check; change to call set_sft_amount_out_of_range_error
	164	instead of set_imm_out_of_range_error.
	165	* aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
	166	(aarch64_opcode_table): Remove the OP enumerator from the asimdimm
	167	8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
	168	SIMD_IMM_SFT.
	169
2f81ff92 L	170	2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
	171
	172	* i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
	173
	174	* i386-init.h: Regenerated.
	175	* i386-tbl.h: Likewise.
	176
dd42f060 NC	177	2013-01-15 Nick Clifton <nickc@redhat.com>
	178
	179	* v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
	180	values.
	181	* v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
	182
a4533ed8 NC	183	2013-01-14 Will Newton <will.newton@imgtec.com>
	184
	185	* metag-dis.c (REG_WIDTH): Increase to 64.
	186
5817ffd1 PB	187	2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
	188
	189	* ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
	190	* ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
	191	XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
	192	(SH6): Update.
	193	<"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
	194	"tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
	195	"treclaim.", "tsr.">: Add POWER8 HTM opcodes.
	196	<"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
	197
a3c62988 NC	198	2013-01-10 Will Newton <will.newton@imgtec.com>
	199
	200	* Makefile.am: Add Meta.
	201	* configure.in: Add Meta.
	202	* disassemble.c: Add Meta support.
	203	* metag-dis.c: New file.
	204	* Makefile.in: Regenerate.
	205	* configure: Regenerate.
	206
73335eae NC	207	2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
	208
	209	* cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
	210	(match_opcode): Rename to cr16_match_opcode.
	211
e407c74b NC	212	2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
	213
	214	* mips-dis.c: Add names for CP0 registers of r5900.
	215	* mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
	216	instructions sq and lq.
	217	Add support for MIPS r5900 CPU.
	218	Add support for 128 bit MMI (Multimedia Instructions).
	219	Add support for EE instructions (Emotion Engine).
	220	Disable unsupported floating point instructions (64 bit and
	221	undefined compare operations).
	222	Enable instructions of MIPS ISA IV which are supported by r5900.
	223	Disable 64 bit co processor instructions.
	224	Disable 64 bit multiplication and division instructions.
	225	Disable instructions for co-processor 2 and 3, because these are
	226	not supported (preparation for later VU0 support (Vector Unit)).
	227	Disable cvt.w.s because this behaves like trunc.w.s and the
	228	correct execution can't be ensured on r5900.
	229	Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
	230	will confuse less developers and compilers.
	231
a32c3ff8 NC	232	2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
a32c3ff8 NC	233
fb098a1e YZ	234	* aarch64-opc.c (aarch64_print_operand): Change to print
	235	AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
	236	in comment.
	237	* aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
	238	from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
	239	OP_MOV_IMM_WIDE.
	240
	241	2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
	242
	243	* aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
	244	PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
a32c3ff8	245
62658407 L	246	2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
	247
	248	* i386-gen.c (process_copyright): Update copyright year to 2013.
	249
bab4becb	250	2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
5bf135a7	251
bab4becb NC	252	* cr16-dis.c (match_opcode,make_instruction): Remove static
	253	declaration.
	254	(dwordU,wordU): Moved typedefs to opcode/cr16.h
	255	(cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
5bf135a7	256
bab4becb	257	For older changes see ChangeLog-2012
252b5132	258	\f
bab4becb	259	Copyright (C) 2013 Free Software Foundation, Inc.
752937aa NC	260
	261	Copying and distribution of this file, with or without modification,
	262	are permitted in any medium without royalty provided the copyright
	263	notice and this notice are preserved.
	264
252b5132	265	Local Variables:
2f6d2f85 NC	266	mode: change-log
	267	left-margin: 8
	268	fill-column: 74
252b5132 RH	269	version-control: never
252b5132 RH	270	End: