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Handle x32 in dump_dwarf
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
9a176a4a
TT		 12012-10-18 Tom Tromey <tromey@redhat.com>
2
3 * tic54x-dis.c (print_instruction): Don't use K&R style.
4 (print_parallel_instruction, sprint_dual_address)
5 (sprint_indirect_address, sprint_direct_address, sprint_mmr)
6 (sprint_cc2, sprint_condition): Likewise.
7
4ad3b7ef
KT		 82012-10-18 Kai Tietz <ktietz@redhat.com>
9
10 * aarch64-asm.c (aarch64_ins_ldst_reglist): Initialize
11 value with a default.
12 (do_special_encoding): Likewise.
13 (aarch64_ins_ldst_elemlist): Pre-initialize QSsize, and opcodeh2
14 variables with default.
15 * arc-dis.c (write_comments_): Don't use strncat due
16 size of state->commentBuffer pointer isn't predictable.
17
b7a54b55
YZ		 182012-10-15 Yufeng Zhang <yufeng.zhang@arm.com>
19
20 * aarch64-opc.c (aarch64_sys_regs): Add rmr_el1, rmr_el2 and
21 rmr_el3; remove daifset and daifclr.
22
9b61754a
YZ		 232012-10-15 Yufeng Zhang <yufeng.zhang@arm.com>
24
25 * aarch64-opc.c (operand_general_constraint_met_p): Change to check
26 the alignment of addr.offset.imm instead of that of shifter.amount for
27 operand type AARCH64_OPND_ADDR_UIMM12.
28
f8ece37f
RE		 292012-10-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
30
31 * arm-dis.c: Use preferred form of vrint instruction variants
32 for disassembly.
33
5e5c50d3
NE		 342012-10-09 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
35
36 * i386-gen.c (cpu_flag_init): Add CPU_BDVER3_FLAGS.
37 * i386-init.h: Regenerated.
38
c7a5aa9c
PB		 392012-10-05 Peter Bergner <bergner@vnet.ibm.com>
40
41 * ppc-dis.c (ppc_opts) <altivec>: Use PPC_OPCODE_ALTIVEC2;
42 * ppc-opc.c (VBA): New define.
43 (powerpc_opcodes) <vcuxwfp, vcsxwfp, vcfpuxws, vcfpsxsw, vmr, vnot,
44 mfppr, mfppr32, mtppr, mtppr32>: New extended mnemonics.
45
04ee5257
NC		 462012-10-04 Nick Clifton <nickc@redhat.com>
47
48 * v850-dis.c (disassemble): Place square parentheses around second
49 register operand of clr1, not1, set1 and tst1 instructions.
50
cfc72779
AK		 512012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
52
53 * s390-mkopc.c: Support new option zEC12.
54 * s390-opc.c: Add new instruction formats.
55 * s390-opc.txt: Add new instructions for zEC12.
56
1415a2a7
AG		 572012-09-27 Anthony Green <green@moxielogic.com>
58
59 * moxie-dis.c (print_insn_moxie): Print 'bad' instructions.
60 * moxie-opc.c: All 'bad' instructions have the itype MOXIE_BAD.
61
160a30bb
L		 622012-09-25 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
63
04ee5257
NC		 64 * i386-gen.c (cpu_flag_init): Add missing Cpu flags in
65 CPU_BDVER1_FLAGS, CPU_BDVER2_FLAGS, CPU_BTVER1_FLAGS
160a30bb
L		 66 and CPU_BTVER2_FLAGS.
67 * i386-init.h: Regenerated.
68
60aa667e
L		 692012-09-20 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
70
71 * i386-gen.c (cpu_flag_init): Add CpuCX16 to CPU_NOCONA_FLAGS,
72 CPU_CORE_FLAGS, CPU_CORE2_FLAGS, CPU_COREI7_FLAGS,
73 CPU_BDVER1_FLAGS, CPU_BDVER2_FLAGS, CPU_BTVER1_FLAGS,
74 CPU_BTVER2_FLAGS. Add CPU_CX16_FLAGS.
75 (cpu_flags): Add CpuCX16.
76 * i386-opc.h (CpuCX16): New.
77 (i386_cpu_flags): Add cpucx16.
78 * i386-opc.tbl: Replace CpuSSE3 with CpuCX16 for cmpxchg16b.
79 * i386-tbl.h: Regenerate.
80 * i386-init.h: Likewise.
81
4b8c8c02
RE		 822012-09-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
83
60aa667e 84 * arm-dis.c: Changed ldra and strl-form mnemonics
4b8c8c02
RE		 85 to lda and stl-form.
86
83ea18d0
MR		 872012-09-18 Chao-ying Fu <fu@mips.com>
88
89 * micromips-opc.c (micromips_opcodes): Correct the encoding of
90 the "swxc1" instruction.
91
062f38fa
RE		 922012-09-17 Yufeng Zhang <yufeng.zhang@arm.com>
93
94 * aarch64-asm.c (aarch64_ins_imm_half): Remove ATTRIBUTE_UNUSED from
95 the parameter 'inst'.
96 (aarch64_ins_addr_simm): Add ATTRIBUTE_UNUSED to the parameter 'inst'.
97 (convert_mov_to_movewide): Change to assert (0) when
98 aarch64_wide_constant_p returns FALSE.
99
b132a67d
DE		 1002012-09-14 David Edelsohn <dje.gcc@gmail.com>
101
102 * configure: Regenerate.
103
1f9b75dd
AG		 1042012-09-14 Anthony Green <green@moxielogic.com>
105
106 * moxie-dis.c (print_insn_moxie): Branch targets are relative to
107 the address after the branch instruction.
108
e202fa84
AG		 1092012-09-13 Anthony Green <green@moxielogic.com>
110
111 * moxie-dis.c (print_insn_moxie): Handle bi-endian encodings.
112
00716ab1
AM		 1132012-09-10 Matthias Klose <doko@ubuntu.com>
114
115 * config.in: Disable sanity check for kfreebsd.
116
6d2920c8
L		 1172012-09-10 H.J. Lu <hongjiu.lu@intel.com>
118
119 * configure: Regenerated.
120
b3e14eda
L		 1212012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
122
123 * ia64-asmtab.h (completer_index): Extend bitfield to full uint.
124 * ia64-gen.c: Promote completer index type to longlong.
125 (irf_operand): Add new register recognition.
126 (in_iclass_mov_x): Add an entry for the new mov_* instruction type.
127 (lookup_specifier): Add new resource recognition.
128 (insert_bit_table_ent): Relax abort condition according to the
129 changed completer index type.
130 (print_dis_table): Fix printf format for completer index.
131 * ia64-ic.tbl: Add a new instruction class.
132 * ia64-opc-i.c (ia64_opcodes_i): Define new I-instructions.
133 * ia64-opc-m.c (ia64_opcodes_m): Define new M-instructions.
134 * ia64-opc.h: Define short names for new operand types.
135 * ia64-raw.tbl: Add new RAW resource for DAHR register.
136 * ia64-waw.tbl: Add new WAW resource for DAHR register.
137 * ia64-asmtab.c: Regenerate.
138
382c72e9
PB		 1392012-08-29 Peter Bergner <bergner@vnet.ibm.com>
140
141 * ppc-opc.c (VXASHB_MASK): New define.
142 (powerpc_opcodes) <vsldoi>: Use VXASHB_MASK.
143
fb048c26
PB		 1442012-08-28 Peter Bergner <bergner@vnet.ibm.com>
145
146 * ppc-opc.c (UIMM4, UIMM3, UIMM2, VXVA_MASK, VXVB_MASK, VXVAVB_MASK,
147 VXVDVA_MASK, VXUIMM4_MASK, VXUIMM3_MASK, VXUIMM2_MASK): New defines.
148 (powerpc_opcodes) <vexptefp, vlogefp, vrefp, vrfim, vrfin, vrfip,
149 vrfiz, vrsqrtefp, vupkhpx, vupkhsb, vupkhsh, vupklpx, vupklsb,
150 vupklsh>: Use VXVA_MASK.
151 <vspltisb, vspltish, vspltisw>: Use VXVB_MASK.
152 <mfvscr>: Use VXVAVB_MASK.
153 <mtvscr>: Use VXVDVA_MASK.
154 <vspltb>: Use VXUIMM4_MASK.
155 <vsplth>: Use VXUIMM3_MASK.
156 <vspltw>: Use VXUIMM2_MASK.
157
3c9017d2
MGD		 1582012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
159
160 * arm-dis.c (neon_opcodes): Add 2 operand sha instructions.
161
48adcd8e
MGD		 1622012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
163
164 * arm-dis.c (neon_opcodes): Add SHA 3-operand instructions.
165
4f51b4bd
MGD		 1662012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
167
168 * arm-dis.c (neon_opcodes): Handle VMULL.P64.
169
91ff7894
MGD		 1702012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
171
172 * arm-dis.c (neon_opcodes): Add support for AES instructions.
173
c70a8987
MGD		 1742012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
175
176 * arm-dis.c (coprocessor_opcodes): Add support for HP/DP
177 conversions.
178
30bdf752
MGD		 1792012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
180
181 * arm-dis.c (coprocessor_opcodes): Add VRINT.
182 (neon_opcodes): Likewise.
183
7e8e6784
MGD		 1842012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
185
186 * arm-dis.c (coprocessor_opcodes): Add support for new VCVT
187 variants.
188 (neon_opcodes): Likewise.
189
73924fbc
MGD		 1902012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
191
192 * arm-dis.c (coprocessor_opcodes): Add VMAXNM/VMINNM.
193 (neon_opcodes): Likewise.
194
33399f07
MGD		 1952012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
196
197 * arm-dis.c (coprocessor_opcodes): Add VSEL.
198 (print_insn_coprocessor): Add new %<>c bitfield format
199 specifier.
200
9eb6c0f1
MGD		 2012012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
202
203 * arm-dis.c (arm_opcodes): Add LDRA/STRL instructions.
204 (thumb32_opcodes): Likewise.
205 (print_arm_insn): Add support for %<>T formatter.
206
8884b720
MGD		 2072012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
208
209 * arm-dis.c (arm_opcodes): Add HLT.
210 (thumb_opcodes): Likewise.
211
b79f7053
MGD		 2122012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
213
214 * arm-dis.c (thumb32_opcodes): Add DCPS instruction.
215
53c4b28b
MGD		 2162012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
217
218 * arm-dis.c (arm_opcodes): Add SEVL.
219 (thumb_opcodes): Likewise.
220 (thumb32_opcodes): Likewise.
221
e797f7e0
MGD		 2222012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
223
224 * arm-dis.c (data_barrier_option): New function.
225 (print_insn_arm): Use data_barrier_option.
226 (print_insn_thumb32): Use data_barrier_option.
227
e2efe87d
MGD		 2282012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com
229
230 * arm-dis.c (COND_UNCOND): New constant.
231 (print_insn_coprocessor): Add support for %u format specifier.
232 (print_insn_neon): Likewise.
233
2c63854f
DM		 2342012-08-21 David S. Miller <davem@davemloft.net>
235
236 * sparc-opc.c (4-argument crypto instructions): Fix encoding using
237 F3F4 macro.
238
e67ed0e8
AM		 2392012-08-20 Edmar Wienskoski <edmar@freescale.com>
240
241 * ppc-opc.c (powerpc_opcodes): Changed opcode for vabsdub,
242 vabsduh, vabsduw, mviwsplt.
243
7b458c12
L		 2442012-08-17 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
245
246 * i386-gen.c (cpu_flag_init): Add CPU_BTVER1_FLAGS and
247 CPU_BTVER2_FLAGS.
248
e67ed0e8 249 * i386-opc.h: Update CpuPRFCHW comment.
7b458c12
L		 250
251 * i386-opc.tbl: Enable prefetch instruction for CpuPRFCHW.
252 * i386-init.h: Regenerated.
253 * i386-tbl.h: Likewise.
254
eb80cb87
NC		 2552012-08-17 Nick Clifton <nickc@redhat.com>
256
257 * po/uk.po: New Ukranian translation.
258 * configure.in (ALL_LINGUAS): Add uk.
259 * configure: Regenerate.
260
8baf7b78
PB		 2612012-08-16 Peter Bergner <bergner@vnet.ibm.com>
262
263 * ppc-opc.c (powerpc_opcodes) <"lswx">: Use RAX for the second and
264 RBX for the third operand.
265 <"lswi">: Use RAX for second and NBI for the third operand.
266
3d557b4c
DD		 2672012-08-15 DJ Delorie <dj@redhat.com>
268
269 * rl78-decode.opc (rl78_decode_opcode): Merge %e and %[01]
270 operands, so that data addresses can be corrected when not
271 ES-overridden.
272 * rl78-decode.c: Regenerate.
273 * rl78-dis.c (print_insn_rl78): Make order of modifiers
274 irrelevent. When the 'e' specifier is used on an operand and no
275 ES prefix is provided, adjust address to make it absolute.
276
588925d0
PB		 2772012-08-15 Peter Bergner <bergner@vnet.ibm.com>
278
279 * ppc-opc.c <RSQ, RTQ>: Use PPC_OPERAND_GPR.
280
9f6a6cc0
PB		 2812012-08-15 Peter Bergner <bergner@vnet.ibm.com>
282
283 * ppc-opc.c <xnop, yield, mdoio, mdoom>: New extended mnemonics.
284
fc8c4fd1
MR		 2852012-08-14 Maciej W. Rozycki <macro@codesourcery.com>
286
287 * mips-dis.c (print_insn_args): Add GET_OP and GET_OP_S local
288 macros, use local variables for info struct member accesses,
289 update the type of the variable used to hold the instruction
290 word.
291 (print_insn_mips, print_mips16_insn_arg): Likewise.
292 (print_insn_mips16): Add GET_OP and GET_OP_S local macros, use
293 local variables for info struct member accesses.
294 (print_insn_micromips): Add GET_OP_S local macro.
295 (_print_insn_mips): Update the type of the variable used to hold
296 the instruction word.
297
a06ea964 2982012-08-13 Ian Bolton <ian.bolton@arm.com>
e67ed0e8
AM		 299 Laurent Desnogues <laurent.desnogues@arm.com>
300 Jim MacArthur <jim.macarthur@arm.com>
301 Marcus Shawcroft <marcus.shawcroft@arm.com>
302 Nigel Stephens <nigel.stephens@arm.com>
303 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
304 Richard Earnshaw <rearnsha@arm.com>
305 Sofiane Naci <sofiane.naci@arm.com>
306 Tejas Belagod <tejas.belagod@arm.com>
307 Yufeng Zhang <yufeng.zhang@arm.com>
a06ea964
NC		 308
309 * Makefile.am: Add AArch64.
310 * Makefile.in: Regenerate.
311 * aarch64-asm.c: New file.
312 * aarch64-asm.h: New file.
313 * aarch64-dis.c: New file.
314 * aarch64-dis.h: New file.
315 * aarch64-gen.c: New file.
316 * aarch64-opc.c: New file.
317 * aarch64-opc.h: New file.
318 * aarch64-tbl.h: New file.
319 * configure.in: Add AArch64.
320 * configure: Regenerate.
321 * disassemble.c: Add AArch64.
322 * aarch64-asm-2.c: New file (automatically generated).
323 * aarch64-dis-2.c: New file (automatically generated).
324 * aarch64-opc-2.c: New file (automatically generated).
325 * po/POTFILES.in: Regenerate.
326
35d0a169
MR		 3272012-08-13 Maciej W. Rozycki <macro@codesourcery.com>
328
329 * micromips-opc.c (micromips_opcodes): Update comment.
330 * mips-opc.c (mips_builtin_opcodes): Likewise. Mark coprocessor
331 instructions for IOCT as appropriate.
332 * mips-dis.c (print_insn_mips): Replace OPCODE_IS_MEMBER with
333 opcode_is_member.
334 * configure.in: Substitute NO_WMISSING_FIELD_INITIALIZERS with
335 the result of a check for the -Wno-missing-field-initializers
336 GCC option.
337 * Makefile.am (NO_WMISSING_FIELD_INITIALIZERS): New variable.
338 (mips-opc.lo): Pass $(NO_WMISSING_FIELD_INITIALIZERS) to
339 compilation.
340 (mips16-opc.lo): Likewise.
341 (micromips-opc.lo): Likewise.
342 * aclocal.m4: Regenerate.
343 * configure: Regenerate.
344 * Makefile.in: Regenerate.
345
5c5acbbd
L		 3462012-08-11 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
347
348 PR gas/14423
349 * i386-gen.c (cpu_flag_init): Add CpuFMA in CPU_BDVER2_FLAGS.
350 * i386-init.h: Regenerated.
351
3c892704
NC		 3522012-08-09 Nick Clifton <nickc@redhat.com>
353
354 * po/vi.po: Updated Vietnamese translation.
355
d7189fa5
RM		 3562012-08-07 Roland McGrath <mcgrathr@google.com>
357
358 * i386-dis.c (reg_table): Fill out REG_0F0D table with
359 AMD-reserved cases as "prefetch".
360 (MOD_0F18_REG_4, MOD_0F18_REG_5): New enum constants.
361 (MOD_0F18_REG_6, MOD_0F18_REG_7): Likewise.
362 (reg_table): Use those under REG_0F18.
363 (mod_table): Add those cases as "nop/reserved".
364
4c692bc7
JB		 3652012-08-07 Jan Beulich <jbeulich@suse.com>
366
367 * i386-opc.tbl: Remove "FIXME" comments from SVME instructions.
368
de882298
RM		 3692012-08-06 Roland McGrath <mcgrathr@google.com>
370
371 * i386-dis.c (print_insn): Print spaces between multiple excess
372 prefixes. Return actual number of excess prefixes consumed,
373 not always one.
374
375 * i386-dis.c (OP_REG): Ignore REX_B for segment register cases.
376
7bb15c6f
RM		 3772012-08-06 Roland McGrath <mcgrathr@google.com>
378 Victor Khimenko <khim@google.com>
379 H.J. Lu <hongjiu.lu@intel.com>
380
381 * i386-dis.c (OP_sI): In b_T_mode and v_mode, REX_W trumps DFLAG.
382 (putop): For 'T', 'U', and 'V', treat REX_W like DFLAG.
383 (intel_operand_size): For stack_v_mode, treat REX_W like DFLAG.
384 (OP_E_register): Likewise.
385 (OP_REG): For low 8 whole registers, treat REX_W like DFLAG.
386
3843081d
JBG		 3872012-08-02 Jan-Benedict Glaw <jbglaw@lug-owl.de>
388
389 * configure.in: Formatting.
390 * configure: Regenerate.
391
48891606
AM		 3922012-08-01 Alan Modra <amodra@gmail.com>
393
394 * h8300-dis.c: Fix printf arg warnings.
395 * i960-dis.c: Likewise.
396 * mips-dis.c: Likewise.
397 * pdp11-dis.c: Likewise.
398 * sh-dis.c: Likewise.
399 * v850-dis.c: Likewise.
400 * configure.in: Formatting.
401 * configure: Regenerate.
402 * rl78-decode.c: Regenerate.
403 * po/POTFILES.in: Regenerate.
404
03f66e8a 4052012-07-31 Chao-Ying Fu <fu@mips.com>
e67ed0e8
AM		 406 Catherine Moore <clm@codesourcery.com>
407 Maciej W. Rozycki <macro@codesourcery.com>
03f66e8a
MR		 408
409 * micromips-opc.c (WR_a, RD_a, MOD_a): New macros.
410 (DSP_VOLA): Likewise.
411 (D32, D33): Likewise.
412 (micromips_opcodes): Add DSP ASE instructions.
48891606 413 * mips-dis.c (print_insn_micromips) <'2', '3'>: New cases.
03f66e8a
MR		 414 <'4', '5', '6', '7', '8', '0', '^', '@'>: Likewise.
415
94948e64
JB		 4162012-07-31 Jan Beulich <jbeulich@suse.com>
417
418 * i386-opc.tbl (vmovntdqa): Move up into 256-bit integer AVX2
419 instruction group. Mark as requiring AVX2.
420 * i386-tbl.h: Re-generate.
421
a6dc81d2
NC		 4222012-07-30 Nick Clifton <nickc@redhat.com>
423
424 * po/opcodes.pot: Updated template.
425 * po/es.po: Updated Spanish translation.
426 * po/fi.po: Updated Finnish translation.
427
c4dd807e
MF		 4282012-07-27 Mike Frysinger <vapier@gentoo.org>
429
430 * configure.in (BFD_VERSION): Run bfd/configure --version and
431 parse the output of that.
432 * configure: Regenerate.
433
03edbe3b
JL		 4342012-07-25 James Lemke <jwlemke@codesourcery.com>
435
436 * ppc-opc.c (powerpc_opcodes): Add/remove PPCVLE for some 32-bit insns.
437
63d08c68
NC		 4382012-07-24 Stephan McCamant <smcc@cs.berkeley.edu>
439 Dr David Alan Gilbert <dave@treblig.org>
d908c8af
NC		 440
441 PR binutils/13135
442 * arm-dis.c: Add necessary casts for printing integer values.
443 Use %s when printing string values.
444 * hppa-dis.c: Likewise.
445 * m68k-dis.c: Likewise.
446 * microblaze-dis.c: Likewise.
447 * mips-dis.c: Likewise.
448 * sparc-dis.c: Likewise.
449
ff688e1f
L		 4502012-07-19 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
451
452 PR binutils/14355
453 * i386-dis.c (VEX_LEN_0FXOP_08_CC): New.
454 (VEX_LEN_0FXOP_08_CD): Likewise.
455 (VEX_LEN_0FXOP_08_CE): Likewise.
456 (VEX_LEN_0FXOP_08_CF): Likewise.
457 (VEX_LEN_0FXOP_08_EC): Likewise.
458 (VEX_LEN_0FXOP_08_ED): Likewise.
459 (VEX_LEN_0FXOP_08_EE): Likewise.
460 (VEX_LEN_0FXOP_08_EF): Likewise.
461 (xop_table): Fix entries for vpcomb, vpcomw, vpcomd, vpcomq,
462 vpcomub, vpcomuw, vpcomud, vpcomuq.
463 (vex_len_table): Add entries for VEX_LEN_0FXOP_08_CC,
464 VEX_LEN_0FXOP_08_CD, VEX_LEN_0FXOP_08_CE, VEX_LEN_0FXOP_08_CF,
465 VEX_LEN_0FXOP_08_EC, VEX_LEN_0FXOP_08_ED, VEX_LEN_0FXOP_08_EE,
466 VEX_LEN_0FXOP_08_EF.
467
e2e1fcde
L		 4682012-07-16 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
469
470 * i386-dis.c (PREFIX_0F38F6): New.
471 (prefix_table): Add adcx, adox instructions.
472 (three_byte_table): Use PREFIX_0F38F6.
473 (mod_table): Add rdseed instruction.
474 * i386-gen.c (cpu_flag_init): Add CpuADX, CpuRDSEED, CpuPRFCHW.
475 (cpu_flags): Likewise.
476 * i386-opc.h: Add CpuADX, CpuRDSEED, CpuPRFCHW.
477 (i386_cpu_flags): Add fields cpurdseed, cpuadx, cpuprfchw.
478 * i386-opc.tbl: Add instrcutions adcx, adox, rdseed. Extend
479 prefetchw.
480 * i386-tbl.h: Regenerate.
481 * i386-init.h: Likewise.
482
8b99bf0b
TS		 4832012-07-05 Thomas Schwinge <thomas@codesourcery.com>
484
f4263ca2 485 * mips-dis.c: Remove gratuitous newline.
8b99bf0b 486
416cf80a
SK		 4872012-07-05 Sean Keys <skeys@ipdatasys.com>
488
489 * xgate-dis.c: Removed an IF statement that will
e67ed0e8
AM		 490 always be false due to overlapping operand masks.
491 * xgate-opc.c: Corrected 'com' opcode entry and
492 fixed spacing.
416cf80a 493
9fa0f14a
RM		 4942012-07-02 Roland McGrath <mcgrathr@google.com>
495
496 * i386-opc.tbl: Add RepPrefixOk to nop.
497 * i386-tbl.h: Regenerate.
498
4c6a93d3
NC		 4992012-06-28 Nick Clifton <nickc@redhat.com>
500
501 * po/vi.po: Updated Vietnamese translation.
502
29c048b6
RM		 5032012-06-22 Roland McGrath <mcgrathr@google.com>
504
fe13e45b
RM		 505 * i386-opc.tbl: Add RepPrefixOk to ret.
506 * i386-tbl.h: Regenerate.
507
29c048b6
RM		 508 * i386-opc.h (RepPrefixOk): New enum constant.
509 (i386_opcode_modifier): New bitfield 'repprefixok'.
510 * i386-gen.c (opcode_modifiers): Add RepPrefixOk.
511 * i386-opc.tbl: Add RepPrefixOk to bsf, bsr, and to all
512 instructions that have IsString.
513 * i386-tbl.h: Regenerate.
514
c7a8dbf9
AS		 5152012-06-11 Andreas Schwab <schwab@linux-m68k.org>
516
517 * ppc-opc.c (lvsl, lvebx, isellt, icbt, ldepx, lwepx, lvsr, lvehx)
518 (iselgt, lvewx, iseleq, isel, dcbst, dcbstep, dcbfl, dcbf, lbepx)
519 (lvx, dcbfep, dcbtstls, stvebx, dcbtstlse, stdepx, stwepx, dcbtls)
520 (stvehx, dcbtlse, stvewx, stbepx, icblc, stvx, dcbtstt, dcbtst)
521 (dcbtst, dcbtstep, dcbtt, dcbt, dcbt, lhepx, eciwx, dcbtep)
522 (dcread, lxvdsx, lvxl, dcblc, sthepx, ecowx, dcbi, dcread, icbtls)
523 (stvxl, lxsdx, lfdepx, stxsdx, stfdepx, dcba, dcbal, lxvw4x)
524 (tlbivax, lfdpx, lxvd2x, tlbsrx., stxvw4x, tlbsx, tlbsx., stfdpx)
525 (stfqx, stxvd2x, icbi, icbiep, icread, dcbzep): Change RA to RA0.
526
94caa966
AM		 5272012-05-19 Alan Modra <amodra@gmail.com>
528
529 * ppc-dis.c: Don't include elf32-ppc.h, do include elf/ppc.h.
530 (get_powerpc_dialect): Detect VLE sections from ELF sh_flags.
531
5eb3690e
AM		 5322012-05-18 Alan Modra <amodra@gmail.com>
533
71fe7bab
AM		 534 * ia64-opc.c: Remove #include "ansidecl.h".
535 * z8kgen.c: Include sysdep.h first.
536
5eb3690e
AM		 537 * arc-dis.c: Include sysdep.h first, remove some redundant includes.
538 * bfin-dis.c: Likewise.
539 * i860-dis.c: Likewise.
540 * ia64-dis.c: Likewise.
541 * ia64-gen.c: Likewise.
542 * m68hc11-dis.c: Likewise.
543 * mmix-dis.c: Likewise.
544 * msp430-dis.c: Likewise.
545 * or32-dis.c: Likewise.
546 * rl78-dis.c: Likewise.
547 * rx-dis.c: Likewise.
548 * tic4x-dis.c: Likewise.
549 * tilegx-opc.c: Likewise.
550 * tilepro-opc.c: Likewise.
551 * rx-decode.c: Regenerate.
552
a4ebc835
AM		 5532012-05-17 James Lemke <jwlemke@codesourcery.com>
554
555 * ppc-opc.c (powerpc_macros): Add entries for e_extlwi to e_clrlslwi.
556
98c76446
AM		 5572012-05-17 James Lemke <jwlemke@codesourcery.com>
558
559 * ppc-opc.c (extract_sprg): Use ALLOW8_SPRG to include VLE.
560
df7b86aa
NC		 5612012-05-17 Daniel Richard G. <skunk@iskunk.org>
562 Nick Clifton <nickc@redhat.com>
563
564 PR 14072
565 * configure.in: Add check that sysdep.h has been included before
566 any system header files.
567 * configure: Regenerate.
568 * config.in: Regenerate.
569 * sysdep.h: Generate an error if included before config.h.
570 * alpha-opc.c: Include sysdep.h before any other header file.
571 * alpha-dis.c: Likewise.
572 * avr-dis.c: Likewise.
573 * cgen-opc.c: Likewise.
574 * cr16-dis.c: Likewise.
575 * cris-dis.c: Likewise.
576 * crx-dis.c: Likewise.
577 * d10v-dis.c: Likewise.
578 * d10v-opc.c: Likewise.
579 * d30v-dis.c: Likewise.
580 * d30v-opc.c: Likewise.
581 * h8500-dis.c: Likewise.
582 * i370-dis.c: Likewise.
583 * i370-opc.c: Likewise.
584 * m10200-dis.c: Likewise.
585 * m10300-dis.c: Likewise.
586 * micromips-opc.c: Likewise.
587 * mips-opc.c: Likewise.
588 * mips61-opc.c: Likewise.
589 * moxie-dis.c: Likewise.
590 * or32-opc.c: Likewise.
591 * pj-dis.c: Likewise.
592 * ppc-dis.c: Likewise.
593 * ppc-opc.c: Likewise.
594 * s390-dis.c: Likewise.
595 * sh-dis.c: Likewise.
596 * sh64-dis.c: Likewise.
597 * sparc-dis.c: Likewise.
598 * sparc-opc.c: Likewise.
599 * spu-dis.c: Likewise.
600 * tic30-dis.c: Likewise.
601 * tic54x-dis.c: Likewise.
602 * tic80-dis.c: Likewise.
603 * tic80-opc.c: Likewise.
604 * tilegx-dis.c: Likewise.
605 * tilepro-dis.c: Likewise.
606 * v850-dis.c: Likewise.
607 * v850-opc.c: Likewise.
608 * vax-dis.c: Likewise.
609 * w65-dis.c: Likewise.
610 * xgate-dis.c: Likewise.
611 * xtensa-dis.c: Likewise.
612 * rl78-decode.opc: Likewise.
613 * rl78-decode.c: Regenerate.
614 * rx-decode.opc: Likewise.
615 * rx-decode.c: Regenerate.
616
e1dad58d
AM		 6172012-05-17 Alan Modra <amodra@gmail.com>
618
619 * ppc_dis.c: Don't include elf/ppc.h.
620
101af531
NC		 6212012-05-16 Meador Inge <meadori@codesourcery.com>
622
623 * arm-dis.c (arm_opcodes): Don't disassemble STMFD/LDMIA sp!, {reg}
624 to PUSH/POP {reg}.
625
6927f982
NC		 6262012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
627 Stephane Carrez <stcarrez@nerim.fr>
628
629 * configure.in: Add S12X and XGATE co-processor support to m68hc11
630 target.
631 * disassemble.c: Likewise.
632 * configure: Regenerate.
633 * m68hc11-dis.c: Make objdump output more consistent, use hex
634 instead of decimal and use 0x prefix for hex.
635 * m68hc11-opc.c: Add S12X and XGATE opcodes.
636
b9c361e0
JL		 6372012-05-14 James Lemke <jwlemke@codesourcery.com>
638
639 * ppc-dis.c (get_powerpc_dialect): Use is_ppc_vle.
640 (PPC_OPCD_SEGS, VLE_OPCD_SEGS): New defines.
641 (vle_opcd_indices): New array.
642 (lookup_vle): New function.
643 (disassemble_init_powerpc): Revise for second (VLE) opcode table.
644 (print_insn_powerpc): Likewise.
645 * ppc-opc.c: Likewise.
646
6472012-05-14 Catherine Moore <clm@codesourcery.com>
648 Maciej W. Rozycki <macro@codesourcery.com>
649 Rhonda Wittels <rhonda@codesourcery.com>
650 Nathan Froyd <froydnj@codesourcery.com>
651
652 * ppc-opc.c (insert_arx, extract_arx): New functions.
653 (insert_ary, extract_ary): New functions.
654 (insert_li20, extract_li20): New functions.
655 (insert_rx, extract_rx): New functions.
656 (insert_ry, extract_ry): New functions.
657 (insert_sci8, extract_sci8): New functions.
658 (insert_sci8n, extract_sci8n): New functions.
659 (insert_sd4h, extract_sd4h): New functions.
660 (insert_sd4w, extract_sd4w): New functions.
661 (insert_vlesi, extract_vlesi): New functions.
662 (insert_vlensi, extract_vlensi): New functions.
663 (insert_vleui, extract_vleui): New functions.
664 (insert_vleil, extract_vleil): New functions.
665 (BI_MASK, BB_MASK, BT): Use PPC_OPERAND_CR_BIT.
666 (BI16, BI32, BO32, B8): New.
667 (B15, B24, CRD32, CRS): New.
668 (CRD, OBF, BFA, CR, CRFS): Use PPC_OPERAND_CR_REG.
669 (DB, IMM20, RD, Rx, ARX, RY, RZ): New.
670 (ARY, SCLSCI8, SCLSCI8N, SE_SD, SE_SDH): New.
671 (SH6_MASK): Use PPC_OPSHIFT_INV.
672 (SI8, UI5, OIMM5, UI7, BO16): New.
673 (VLESIMM, VLENSIMM, VLEUIMM, VLEUIMML): New.
674 (XT6, XA6, XB6, XB6S, XC6): Use PPC_OPSHIFT_INV.
675 (ALLOW8_SPRG): New.
676 (insert_sprg, extract_sprg): Check ALLOW8_SPRG.
677 (OPVUP, OPVUP_MASK OPVUP): New
678 (BD8, BD8_MASK, BD8IO, BD8IO_MASK): New.
679 (EBD8IO, EBD8IO1_MASK, EBD8IO2_MASK, EBD8IO3_MASK): New.
680 (BD15, BD15_MASK, EBD15, EBD15_MASK, EBD15BI, EBD15BI_MASK): New.
681 (BD24,BD24_MASK, C_LK, C_LK_MASK, C, C_MASK): New.
682 (IA16, IA16_MASK, I16A, I16A_MASK, I16L, I16L_MASK): New.
683 (IM7, IM7_MASK, LI20, LI20_MASK, SCI8, SCI8_MASK): New.
684 (SCI8BF, SCI8BF_MASK, SD4, SD4_MASK): New.
685 (SE_IM5, SE_IM5_MASK): New.
686 (SE_R, SE_R_MASK, SE_RR, SE_RR_MASK): New.
687 (EX, EX_MASK, BO16F, BO16T, BO32F, BO32T): New.
688 (BO32DNZ, BO32DZ): New.
689 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW): Include PPC_OPCODE_VLE.
690 (PPCVLE): New.
691 (powerpc_opcodes): Add new VLE instructions. Update existing
692 instruction to include PPCVLE if supported.
693 * ppc-dis.c (ppc_opts): Add vle entry.
694 (get_powerpc_dialect): New function.
695 (powerpc_init_dialect): VLE support.
696 (print_insn_big_powerpc): Call get_powerpc_dialect.
697 (print_insn_little_powerpc): Likewise.
698 (operand_value_powerpc): Handle negative shift counts.
699 (print_insn_powerpc): Handle 2-byte instruction lengths.
700
208a4923
NC		 7012012-05-11 Daniel Richard G. <skunk@iskunk.org>
702
703 PR binutils/14028
704 * configure.in: Invoke ACX_HEADER_STRING.
705 * configure: Regenerate.
706 * config.in: Regenerate.
707 * sysdep.h: If STRINGS_WITH_STRING is defined then include both
708 string.h and strings.h.
709
6750a3a7
NC		 7102012-05-11 Nick Clifton <nickc@redhat.com>
711
712 PR binutils/14006
713 * arm-dis.c (print_insn): Fix detection of instruction mode in
714 files containing multiple executable sections.
715
f6c1a2d5
NC		 7162012-05-03 Sean Keys <skeys@ipdatasys.com>
717
718 * Makefile.in, configure: regenerate
719 * disassemble.c (disassembler): Recognize ARCH_XGATE.
720 * xgate-dis.c (read_memory, print_insn, print_insn_xgate):
721 New functions.
722 * configure.in: Recognize xgate.
723 * xgate-dis.c, xgate-opc.c: New files for support of xgate
724 * Makefile.am (CFILES, ALL_MACHINES): New files for disassembly
725 and opcode generation for xgate.
726
78e98aab
DD		 7272012-04-30 DJ Delorie <dj@redhat.com>
728
729 * rx-decode.opc (MOV): Do not sign-extend immediates which are
730 already the maximum bit size.
731 * rx-decode.c: Regenerate.
732
ec668d69
DM		 7332012-04-27 David S. Miller <davem@davemloft.net>
734
2e52845b
DM		 735 * sparc-dis.c (v9a_asr_reg_names): Add 'cfr'.
736 * sparc-opc.c (sparc_opcodes): Add rd/wr cases for %cfr.
737
58004e23
DM		 738 * sparc-opc.c (sparc_opcodes): Add 'wr X, %pause' and 'pause'.
739 * sparc-dis.c (v9a_asr_reg_names): Add 'pause'.
740
698544e1
DM		 741 * sparc-opc.c (CBCOND): New define.
742 (CBCOND_XCC): Likewise.
743 (cbcond): New helper macro.
744 (sparc_opcodes): Add compare-and-branch instructions.
745
6cda1326
DM		 746 * sparc-dis.c (print_insn_sparc): Handle ')'.
747 * sparc-opc.c (sparc_opcodes): Add crypto instructions.
748
ec668d69
DM		 749 * sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
750 into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
751
2615994e
DM		 7522012-04-12 David S. Miller <davem@davemloft.net>
753
754 * sparc-dis.c (X_DISP10): Define.
755 (print_insn_sparc): Handle '='.
756
5de10af0
MF		 7572012-04-01 Mike Frysinger <vapier@gentoo.org>
758
759 * bfin-dis.c (fmtconst): Replace decimal handling with a single
760 sprintf call and the '*' field width.
761
55a36193
MK		 7622012-03-23 Maxim Kuvyrkov <maxim@codesourcery.com>
763
764 * mips-dis.c (mips_arch_choices): Add entry for Broadcom XLP.
765
d6688282
AM		 7662012-03-16 Alan Modra <amodra@gmail.com>
767
768 * ppc-dis.c (PPC_OPC_SEGS, PPC_OP_TO_SEG): Delete.
769 (powerpc_opcd_indices): Bump array size.
770 (disassemble_init_powerpc): Set powerpc_opcd_indices entries
771 corresponding to unused opcodes to following entry.
772 (lookup_powerpc): New function, extracted and optimised from..
773 (print_insn_powerpc): ..here.
774
b240011a
AM		 7752012-03-15 Alan Modra <amodra@gmail.com>
776 James Lemke <jwlemke@codesourcery.com>
777
778 * disassemble.c (disassemble_init_for_target): Handle ppc init.
779 * ppc-dis.c (private): New var.
780 (powerpc_init_dialect): Don't return calloc failure, instead use
781 private.
782 (PPC_OPCD_SEGS, PPC_OP_TO_SEG): Define.
783 (powerpc_opcd_indices): New array.
784 (disassemble_init_powerpc): New function.
785 (print_insn_big_powerpc): Don't init dialect here.
786 (print_insn_little_powerpc): Likewise.
787 (print_insn_powerpc): Start search using powerpc_opcd_indices.
788
aea77599
AM		 7892012-03-10 Edmar Wienskoski <edmar@freescale.com>
790
791 * ppc-dis.c (ppc_opts): Add entries for "e5500" and "e6500".
792 * ppc-opc.c (insert_ls, TMR, ESYNC, XSYNCLE_MASK): New.
793 (PPCVEC2, PPCTMR, E6500): New short names.
794 (powerpc_opcodes): Add vabsdub, vabsduh, vabsduw, dni, mvidsplt,
795 mviwsplt, icblq., mftmr, mttmr, dcblq., miso, lvexbx, lvexhx,
796 lvexwx, stvexbx, stvexhx, stvexwx, lvepx, lvepxl, stvepx, stvepxl,
797 lvtrx, lvtrxl, lvtlx, lvtlxl, stvfrx, stvfrxl, stvflx, stvflxl,
798 lvswx, lvswxl, stvswx, stvswxl, lvsm mnemonics. Accept LS, ESYNC
799 optional operands on sync instruction for E6500 target.
800
5333187a
AK		 8012012-03-08 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
802
803 * s390-opc.txt: Set instruction type of pku to SS_L2RDRD.
804
a597d2d3
AM		 8052012-02-27 Alan Modra <amodra@gmail.com>
806
807 * mt-dis.c: Regenerate.
808
3f26eb3a
AM		 8092012-02-27 Alan Modra <amodra@gmail.com>
810
811 * v850-opc.c (extract_v8): Rearrange to make it obvious this
812 is the inverse of corresponding insert function.
813 (extract_d22, extract_u9, extract_r4): Likewise.
814 (extract_d9): Correct sign extension.
815 (extract_d16_15): Don't assume "long" is 32 bits, and don't
816 rely on implementation defined behaviour for shift right of
817 signed types.
818 (extract_d16_16, extract_d17_16, extract_i9): Likewise.
819 (extract_d23): Likewise, and correct mask.
820
1f42f8b3
AM		 8212012-02-27 Alan Modra <amodra@gmail.com>
822
823 * crx-dis.c (print_arg): Mask constant to 32 bits.
824 * crx-opc.c (cst4_map): Use int array.
825
cdb06235
AM		 8262012-02-27 Alan Modra <amodra@gmail.com>
827
828 * arc-dis.c (BITS): Don't use shifts to mask off bits.
829 (FIELDD): Sign extend with xor,sub.
830
6f7be959
WL		 8312012-02-25 Walter Lee <walt@tilera.com>
832
833 * tilegx-opc.c: Handle TILEGX_OPC_LD4S_TLS and TILEGX_OPC_LD_TLS.
834 * tilepro-opc.c: Handle TILEPRO_OPC_LW_TLS and
835 TILEPRO_OPC_LW_TLS_SN.
836
82c2def5
L		 8372012-02-21 H.J. Lu <hongjiu.lu@intel.com>
838
839 * i386-opc.h (HLEPrefixNone): New.
840 (HLEPrefixLock): Likewise.
841 (HLEPrefixAny): Likewise.
842 (HLEPrefixRelease): Likewise.
843
42164a71
L		 8442012-02-08 H.J. Lu <hongjiu.lu@intel.com>
845
846 * i386-dis.c (HLE_Fixup1): New.
847 (HLE_Fixup2): Likewise.
848 (HLE_Fixup3): Likewise.
849 (Ebh1): Likewise.
850 (Evh1): Likewise.
851 (Ebh2): Likewise.
852 (Evh2): Likewise.
853 (Ebh3): Likewise.
854 (Evh3): Likewise.
855 (MOD_C6_REG_7): Likewise.
856 (MOD_C7_REG_7): Likewise.
857 (RM_C6_REG_7): Likewise.
858 (RM_C7_REG_7): Likewise.
859 (XACQUIRE_PREFIX): Likewise.
860 (XRELEASE_PREFIX): Likewise.
861 (dis386): Use Ebh1/Evh1 on add, adc, and, btc, btr, bts,
862 cmpxchg, dec, inc, neg, not, or, sbb, sub, xor and xadd. Use
863 Ebh2/Evh2 on xchg. Use Ebh3/Evh3 on mov.
864 (reg_table): Use Ebh1/Evh1 on add, adc, and, dec, inc, neg,
865 not, or, sbb, sub and xor. Use Ebh3/Evh3 on mov. Use
866 MOD_C6_REG_7 and MOD_C7_REG_7.
867 (mod_table): Add MOD_C6_REG_7 and MOD_C7_REG_7.
868 (rm_table): Add RM_C6_REG_7 and RM_C7_REG_7. Add xend and
869 xtest.
870 (prefix_name): Handle XACQUIRE_PREFIX and XRELEASE_PREFIX.
871 (CMPXCHG8B_Fixup): Handle HLE prefix on cmpxchg8b.
872
873 * i386-gen.c (cpu_flag_init): Add CPU_HLE_FLAGS and
874 CPU_RTM_FLAGS.
875 (cpu_flags): Add CpuHLE and CpuRTM.
876 (opcode_modifiers): Add HLEPrefixOk.
877
878 * i386-opc.h (CpuHLE): New.
879 (CpuRTM): Likewise.
880 (HLEPrefixOk): Likewise.
881 (i386_cpu_flags): Add cpuhle and cpurtm.
882 (i386_opcode_modifier): Add hleprefixok.
883
884 * i386-opc.tbl: Add HLEPrefixOk=3 to mov. Add HLEPrefixOk to
885 add, adc, and, btc, btr, bts, cmpxchg, dec, inc, neg, not, or,
886 sbb, sub, xor and xadd. Add HLEPrefixOk=2 to xchg with memory
887 operand. Add xacquire, xrelease, xabort, xbegin, xend and
888 xtest.
889 * i386-init.h: Regenerated.
890 * i386-tbl.h: Likewise.
891
21abe33a
DD		 8922012-01-24 DJ Delorie <dj@redhat.com>
893
894 * rl78-decode.opc (rl78_decode_opcode): Add NOT1.
895 * rl78-decode.c: Regenerate.
896
e20cc039
AM		 8972012-01-17 James Murray <jsm@jsm-net.demon.co.uk>
898
899 PR binutils/10173
900 * cr16-dis.c (print_arg): Test symtab_size not num_symbols.
901
e143d25c
AS		 9022012-01-17 Andreas Schwab <schwab@linux-m68k.org>
903
904 * m68k-opc.c (m68k_opcodes): Fix entries for pmove with BADx/BACx
905 register and move them after pmove with PSR/PCSR register.
906
8729a6f6
L		 9072012-01-13 H.J. Lu <hongjiu.lu@intel.com>
908
909 * i386-dis.c (mod_table): Add vmfunc.
910
911 * i386-gen.c (cpu_flag_init): Add CPU_VMFUNC_FLAGS.
912 (cpu_flags): CpuVMFUNC.
913
914 * i386-opc.h (CpuVMFUNC): New.
915 (i386_cpu_flags): Add cpuvmfunc.
916
917 * i386-opc.tbl: Add vmfunc.
918 * i386-init.h: Regenerated.
919 * i386-tbl.h: Likewise.
5011093d 920
23e1d329 921For older changes see ChangeLog-2011
252b5132
RH		 922\f
923Local Variables:
2f6d2f85
NC		 924mode: change-log
925left-margin: 8
926fill-column: 74
252b5132
RH		 927version-control: never
928End:
GDB Binutils - Deliverables
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