projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Use target_read_code in skip_prologue (amd64)
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
61d4014c
NC		 12013-12-05 Nick Clifton <nickc@redhat.com>
2
3 * s390-mkopc.c (dumpTable): Provide a format string to printf so
4 that compiling with -Werror=format-security does not produce an
5 error.
6
87b8eed7
YZ		 72013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
8
9 * aarch64-opc.c (aarch64_pstatefields): Update.
10
8f8c3854
CM		 112013-11-19 Catherine Moore <clm@codesourcery.com>
12
13 * micromips-opc.c (LM): Define.
14 (micromips_opcodes): Add LM to load instructions.
15 * mips-opc.c (prefe): Add LM attribute.
16
a203d9b7
YZ		 172013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
18
19 Revert
20
21 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
22
23 * aarch64-opc.c (CPENT): New define.
24 (F_READONLY, F_WRITEONLY): Likewise.
25 (aarch64_sys_regs): Add trace unit registers.
26 (aarch64_sys_reg_readonly_p): New function.
27 (aarch64_sys_reg_writeonly_p): Ditto.
28
75468c93
YZ		 292013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
30
31 * aarch64-opc.c (CPENT): New define.
32 (F_READONLY, F_WRITEONLY): Likewise.
33 (aarch64_sys_regs): Add trace unit registers.
34 (aarch64_sys_reg_readonly_p): New function.
35 (aarch64_sys_reg_writeonly_p): Ditto.
36
caeba11c
MR		 372013-11-15 Maciej W. Rozycki <macro@codesourcery.com>
38
39 * mips-opc.c (mips_builtin_opcodes): Add RD_2 to "mfcr" and
40 "mtcr".
41
b83a9376
CM		 422013-11-11 Catherine Moore <clm@codesourcery.com>
43
44 * mips-dis.c (print_insn_mips): Use
45 INSN_LOAD_MEMORY instead of INSN_LOAD_MEMORY_DELAY.
46 (print_insn_micromips): Likewise.
47 * mips-opc.c (LDD): Remove.
48 (CLD): Include INSN_LOAD_MEMORY.
49 (LM): New.
50 (mips_builtin_opcodes): Use LM instead of LDD.
51 Add LM to load instructions.
52
d56da83e
L		 532013-11-08 H.J. Lu <hongjiu.lu@intel.com>
54
55 PR gas/16140
56 * i386-gen.c (cpu_flag_init): Remove CpuNop from CPU_K6_2_FLAGS.
57 * i386-init.h: Regenerated.
58
49eec193
YZ		 592013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
60
61 * aarch64-opc.c (F_DEPRECATED): New macro.
62 (aarch64_sys_regs): Update; flag "spsr_svc" and "spsr_hyp" with
63 F_DEPRECATED.
64 (aarch64_print_operand): Call aarch64_sys_reg_deprecated_p on
65 AARCH64_OPND_SYSREG.
66
68a64283
YZ		 672013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
68
69 * aarch64-dis.c (convert_ubfm_to_lsl): Check for cond != '111x'.
70 (convert_from_csel): Likewise.
71 * aarch64-opc.c (operand_general_constraint_met_p): Handle
72 AARCH64_OPND_CLASS_COND and AARCH64_OPND_COND1.
73 (aarch64_print_operand): Handle AARCH64_OPND_COND1.
74 * aarch64-tbl.h (aarch64_opcode_table): Use COND1 instead of
75 COND for cinc, cset, cinv, csetm and cneg.
76 (AARCH64_OPERANDS): Add entry for AARCH64_OPND_COND1.
77 * aarch64-asm-2.c: Re-generated.
78 * aarch64-dis-2.c: Ditto.
79 * aarch64-opc-2.c: Ditto.
80
4e50d5f8
YZ		 812013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
82
83 * aarch64-opc.c (set_syntax_error): New function.
84 (operand_general_constraint_met_p): Replace set_other_error
85 with set_syntax_error.
86
7d4a7d10
AA		 872013-10-30 Andreas Arnez <arnez@linux.vnet.ibm.com>
88
89 * s390-dis.c (init_disasm): Default to full 'zarch' opcode
90 availability even for 31-bit programs.
91
85181173
RR		 922013-10-15 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
93
94 * arm-dis.c (neon_opcodes): Adjust print string for vshll.
95
4edbb8e3
CF		 962013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
97
98 * micromips-opc.c (decode_micromips_operand): Add +T, +U, +V, +W,
99 +d, +e, +h, +k, +l, +n, +o, +u, +v, +w, +x,
100 +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
101 (MSA): New define.
102 (MSA64): New define.
103 (micromips_opcodes): Add MSA instructions.
104 * mips-dis.c (msa_control_names): New array.
105 (mips_abi_choice): Add ASE_MSA to mips32r2.
106 Remove ASE_MDMX from mips64r2.
107 Add ASE_MSA and ASE_MSA64 to mips64r2.
108 (parse_mips_dis_option): Handle -Mmsa.
109 (print_reg): Handle cases for OP_REG_MSA and OP_REG_MSA_CTRL.
110 (print_insn_arg): Handle cases for OP_IMM_INDEX and OP_REG_INDEX.
111 (print_mips_disassembler_options): Print -Mmsa.
112 * mips-opc.c (decode_mips_operand): Add +T, +U, +V, +W, +d, +e, +h, +k,
113 +l, +n, +o, +u, +v, +w, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
114 (MSA): New define.
115 (MSA64): New define.
116 (mips_builtin_op): Add MSA instructions.
117
ae335a4e
SL		 1182013-10-13 Sandra Loosemore <sandra@codesourcery.com>
119
120 * nios2-opc.c (nios2_builtin_reg): Use "sstatus" rather than "ba"
121 as the primary name of r30.
122
6c75cc62
L		 1232013-10-12 Jan Beulich <jbeulich@suse.com>
124
125 * i386-dis.c (intel_operand_size): Move v_bnd_mode alongside the
126 default case.
127 (OP_E_register): Move v_bnd_mode alongside m_mode.
128 * i386-opc.tbl (bndcl, bndcu, bndcn): Split 32- and 64-bit variants.
129 Drop Reg16 and Disp16. Add NoRex64.
130 (bndmk, bndmov, bndldx, bndstx): Drop Disp16.
131 * i386-tbl.h: Re-generate.
132
0e1c2434
SK		 1332013-10-10 Sean Keys <skeys@ipdatasys.com>
134
135 * xgate-opc.c (xgate_opcode): Remove short_hand field from opcode
136 table.
137 * xgate-dis.c (print_insn): Refactor to work with table change.
138
7903e530
RM		 1392013-10-10 Roland McGrath <mcgrathr@google.com>
140
9ce09ba2
RM		 141 * i386-dis.c (oappend_maybe_intel): New function.
142 (OP_ST, OP_STi, append_seg, OP_I, OP_I64, OP_sI, OP_ESreg): Use it.
143 (OP_C, OP_T, CMP_Fixup, OP_EX_VexImmW): Likewise.
144 (VCMP_Fixup, VPCMP_Fixup, PCLMUL_Fixup): Likewise.
145
2b4e983c
RM		 146 * cr16-opc.c (REG): Cast NAME to 'reg' enum type to suppress
147 possible compiler warnings when the union's initializer is
148 actually meant for the 'preg' enum typed member.
149 * crx-opc.c (REG): Likewise.
150
7903e530
RM		 151 * v850-dis.c (v850_cacheop_codes, v850_prefop_codes):
152 Remove duplicate const qualifier.
153
79e0e31d
JB		 1542013-10-08 Jan Beulich <jbeulich@suse.com>
155
156 * i386-opc.tbl (invlpg): Use Anysize instead of Unspecified.
157 (clflush): Use Anysize instead of Byte|Unspecified.
158 (prefetch*): Likewise.
159 * i386-tbl.h: Re-generate.
160
45099dfa
CF		 1612013-10-07 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
162
163 * micromips-opc.c (micromips_opcodes): Fix dmfgc0 and dmtgc0.
164
916fae91
L		 1652013-09-30 H.J. Lu <hongjiu.lu@intel.com>
166
167 * i386-opc.tbl: Add Size64 to movq/vmovq with Reg64 operand.
168 * i386-init.h: Regenerated.
169
c7b0bd56
SE		 1702013-09-30 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
171
172 * i386-gen.c (cpu_flag_init): Add CPU_BDVER4_FLAGS.
173 * i386-init.h: Regenerated.
174
cc9afea3
AM		 1752013-09-20 Alan Modra <amodra@gmail.com>
176
177 * configure: Regenerate.
178
e3f9e852
RS		 1792013-09-17 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
180
181 * s390-opc.txt (clih): Make the immediate unsigned.
182
74db7efb
NC		 1832013-09-04 Roland McGrath <mcgrathr@google.com>
184
185 PR gas/15914
186 * arm-dis.c (arm_opcodes): Add udf.
187 (thumb_opcodes): Use "udf" mnemonic rather than UNDEFINED_INSTRUCTION.
188 (thumb32_opcodes): Add udf.w.
189 (print_insn_thumb32): Handle %H as the thumb32_opcodes comment says.
190
c8094e01
AK		 1912013-09-02 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
192
193 * s390-opc.txt: Fix description for fiebra, fidbra, and fixbra.
194 For the load fp integer instructions only the suppression flag was
195 new with z196 version.
196
7e105031
NC		 1972013-08-28 Nick Clifton <nickc@redhat.com>
198
199 * aarch64-opc.c (aarch64_logical_immediate_p): Return FALSE if the
200 immediate is not suitable for the 32-bit ABI.
201
fb6f3895
MR		 2022013-08-23 Maciej W. Rozycki <macro@codesourcery.com>
203
204 * micromips-opc.c (micromips_opcodes): Use RD_4 for "alnv.ps",
205 replacing NODS.
206
9aff4b7a
NC		 2072013-08-23 Yuri Chornoivan <yurchor@ukr.net>
208
209 PR binutils/15834
210 * aarch64-asm.c: Fix typos.
211 * aarch64-dis.c: Likewise.
212 * msp430-dis.c: Likewise.
213
5e0dc5ba
RS		 2142013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
215
216 * micromips-opc.c (micromips_opcodes): Replace "dext" and "dins"
217 macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases.
218 Use +H rather than +C for the real "dext".
219 * mips-opc.c (mips_builtin_opcodes): Likewise.
220
0f35dbc4
RS		 2212013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
222
223 * mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros.
224 * micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG
225 and OPTIONAL_MAPPED_REG.
226 * mips-opc.c (decode_mips_operand): Likewise.
227 * mips16-opc.c (decode_mips16_operand): Likewise.
228 * mips-dis.c (print_insn_arg): Handle OP_OPTIONAL_REG.
229
79ceb7cb
L		 2302013-08-19 H.J. Lu <hongjiu.lu@intel.com>
231
232 * i386-dis.c (PREFIX_EVEX_0F3A3E): Removed.
233 (PREFIX_EVEX_0F3A3F): Likewise.
234 * i386-dis-evex.h (evex_table): Updated.
235
ee5734f0
RS		 2362013-08-06 Jürgen Urban <JuergenUrban@gmx.de>
237
238 * mips-opc.c (mips_builtin_opcodes): Add a suffixless version of
239 VCLIPW.
240
d6787ef9
EB		 2412013-08-05 Eric Botcazou <ebotcazou@adacore.com>
242 Konrad Eisele <konrad@gaisler.com>
243
244 * sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for
245 bfd_mach_sparc.
246 * sparc-opc.c (MASK_LEON): Define.
247 (v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON.
248 (letandleon): New macro.
249 (v9andleon): Likewise.
250 (sparc_opc): Add leon.
251 (umac): Enable for letandleon.
252 (smac): Likewise.
253 (casa): Enable for v9andleon.
254 (cas): Likewise.
255 (casl): Likewise.
256
14daeee3
RS		 2572013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
258 Richard Sandiford <rdsandiford@googlemail.com>
259
260 * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
261 OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
262 (print_vu0_channel): New function.
263 (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
264 (print_insn_args): Handle '#'.
265 (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
266 * mips-opc.c (mips_vu0_channel_mask): New constant.
267 (decode_mips_operand): Handle new VU0 operand types.
268 (VU0, VU0CH): New macros.
269 (mips_builtin_opcodes): Add VU0 opcodes. Use "+7" rather than "E"
270 for LQC2 and SQC2. Use "+9" rather than "G" for EE CFC2 and CTC2.
271 Use "+6" rather than "G" for QMFC2 and QMTC2.
272
3ccad066
RS		 2732013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
274
275 * mips-formats.h (PCREL): Reorder parameters and update the definition
276 to match new mips_pcrel_operand layout.
277 (JUMP, JALX, BRANCH): Update accordingly.
278 * mips16-opc.c (decode_mips16_operand): Likewise.
279
df34fbcc
RS		 2802013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
281
282 * micromips-opc.c (WR_s): Delete.
283
fc76e730
RS		 2842013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
285
286 * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
287 New macros.
288 (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
289 (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
290 (mips_builtin_opcodes): Use the new position-based read-write flags
291 instead of field-based ones. Use UDI for "udi..." instructions.
292 * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
293 New macros.
294 (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
295 (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
296 (WR_SP, RD_16): New macros.
297 (RD_SP): Redefine as an INSN2_* flag.
298 (MOD_SP): Redefine in terms of RD_SP and WR_SP.
299 (mips16_opcodes): Use the new position-based read-write flags
300 instead of field-based ones. Use RD_16 for "nop". Move RD_SP to
301 pinfo2 field.
302 * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
303 New macros.
304 (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
305 (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
306 (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
307 (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
308 (micromips_opcodes): Use the new position-based read-write flags
309 instead of field-based ones.
310 * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
311 (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
312 of field-based flags.
313
26545944
RS		 3142013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
315
316 * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
317 (WR_SP): Replace with...
318 (MOD_SP): ...this.
319 (mips16_opcodes): Update accordingly.
320 * mips-dis.c (print_insn_mips16): Likewise.
321
a8d92fc6
RS		 3222013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
323
324 * mips16-opc.c (mips16_opcodes): Reformat.
325
6a819047
RS		 3262013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
327
328 * mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
329 for operands that are hard-coded to $0.
330 * micromips-opc.c (micromips_opcodes): Likewise.
331
344c74a6
RS		 3322013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
333
334 * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
335 for the single-operand forms of JALR and JALR.HB.
336 * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
337 and JALRS.HB.
338
41989114
RS		 3392013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
340
341 * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
342 instructions. Fix them to use WR_MACC instead of WR_CC and
343 add missing RD_MACCs.
344
6d075bce
RS		 3452013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
346
347 * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
348
4f6ffcd3
PB		 3492013-07-29 Peter Bergner <bergner@vnet.ibm.com>
350
351 * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
352
43234a1e
L		 3532013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
354 Alexander Ivchenko <alexander.ivchenko@intel.com>
355 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
356 Sergey Lega <sergey.s.lega@intel.com>
357 Anna Tikhonova <anna.tikhonova@intel.com>
358 Ilya Tocar <ilya.tocar@intel.com>
359 Andrey Turetskiy <andrey.turetskiy@intel.com>
360 Ilya Verbin <ilya.verbin@intel.com>
361 Kirill Yukhin <kirill.yukhin@intel.com>
362 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
363
364 * i386-dis-evex.h: New.
365 * i386-dis.c (OP_Rounding): New.
366 (VPCMP_Fixup): New.
367 (OP_Mask): New.
368 (Rdq): New.
369 (XMxmmq): New.
370 (EXdScalarS): New.
371 (EXymm): New.
372 (EXEvexHalfBcstXmmq): New.
373 (EXxmm_mdq): New.
374 (EXEvexXGscat): New.
375 (EXEvexXNoBcst): New.
376 (VPCMP): New.
377 (EXxEVexR): New.
378 (EXxEVexS): New.
379 (XMask): New.
380 (MaskG): New.
381 (MaskE): New.
382 (MaskR): New.
383 (MaskVex): New.
384 (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
385 evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
386 evex_rounding_mode, evex_sae_mode, mask_mode.
387 (USE_EVEX_TABLE): New.
388 (EVEX_TABLE): New.
389 (EVEX enum): New.
390 (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
391 REG_EVEX_0F38C7.
392 (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
393 MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
394 MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
395 MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
396 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5,
397 MOD_EVEX_0F38C7_REG_6.
398 (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
399 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
400 PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
401 PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
402 PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
403 PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
404 PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
405 PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
406 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
407 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
408 PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
409 PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
410 PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
411 PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
412 PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
413 PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
414 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
415 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
416 PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
417 PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
418 PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
419 PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
420 PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
421 PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
422 PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
423 PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
424 PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
425 PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
426 PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
427 PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
428 PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
429 PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
430 PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
431 PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
432 PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
433 PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
434 PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
435 PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
436 PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
437 PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
438 PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
439 PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
440 PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
441 PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
442 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
443 PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
444 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
445 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
446 PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
447 PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
448 PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
449 PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
450 PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
451 PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
452 PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
453 PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
454 PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
455 PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
456 PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
457 PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
458 PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
459 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
460 PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
461 PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
462 PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
463 PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
464 PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
465 PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
466 PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
467 PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
468 PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
469 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
470 PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
471 PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
472 PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
473 PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
474 PREFIX_EVEX_0F3A55.
475 (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
476 VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
477 VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
478 VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
479 VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
480 VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
481 VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
482 VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
483 VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
484 VEX_W_0F3A32_P_2_LEN_0.
485 (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
486 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
487 EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
488 EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
489 EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
490 EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
491 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
492 EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
493 EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
494 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
495 EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
496 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
497 EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
498 EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
499 EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
500 EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
501 EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
502 EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
503 EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
504 EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
505 EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
506 EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
507 EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
508 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
509 EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
510 EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
511 EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
512 EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
513 EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
514 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
515 EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
516 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
517 EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
518 EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
519 EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
520 EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
521 EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
522 EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
523 EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
524 EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
525 EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
526 EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
527 EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
528 EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
529 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
530 EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
531 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
532 EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
533 EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
534 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
535 EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
536 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
537 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
538 EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
539 (struct vex): Add fields evex, r, v, mask_register_specifier,
540 zeroing, ll, b.
541 (intel_names_xmm): Add upper 16 registers.
542 (att_names_xmm): Ditto.
543 (intel_names_ymm): Ditto.
544 (att_names_ymm): Ditto.
545 (names_zmm): New.
546 (intel_names_zmm): Ditto.
547 (att_names_zmm): Ditto.
548 (names_mask): Ditto.
549 (intel_names_mask): Ditto.
550 (att_names_mask): Ditto.
551 (names_rounding): Ditto.
552 (names_broadcast): Ditto.
553 (x86_64_table): Add escape to evex-table.
554 (reg_table): Include reg_table evex-entries from
555 i386-dis-evex.h. Fix prefetchwt1 instruction.
556 (prefix_table): Add entries for new instructions.
557 (vex_table): Ditto.
558 (vex_len_table): Ditto.
559 (vex_w_table): Ditto.
560 (mod_table): Ditto.
561 (get_valid_dis386): Properly handle new instructions.
562 (print_insn): Handle zmm and mask registers, print mask operand.
563 (intel_operand_size): Support EVEX, new modes and sizes.
564 (OP_E_register): Handle new modes.
565 (OP_E_memory): Ditto.
566 (OP_G): Ditto.
567 (OP_XMM): Ditto.
568 (OP_EX): Ditto.
569 (OP_VEX): Ditto.
570 * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
571 CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
572 CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
573 (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
574 CpuAVX512PF and CpuVREX.
575 (operand_type_init): Add OPERAND_TYPE_REGZMM,
576 OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
577 (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
578 StaticRounding, SAE, Disp8MemShift, NoDefMask.
579 (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
580 * i386-init.h: Regenerate.
581 * i386-opc.h (CpuAVX512F): New.
582 (CpuAVX512CD): New.
583 (CpuAVX512ER): New.
584 (CpuAVX512PF): New.
585 (CpuVREX): New.
586 (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
587 cpuavx512pf and cpuvrex fields.
588 (VecSIB): Add VecSIB512.
589 (EVex): New.
590 (Masking): New.
591 (VecESize): New.
592 (Broadcast): New.
593 (StaticRounding): New.
594 (SAE): New.
595 (Disp8MemShift): New.
596 (NoDefMask): New.
597 (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
598 staticrounding, sae, disp8memshift and nodefmask.
599 (RegZMM): New.
600 (Zmmword): Ditto.
601 (Vec_Disp8): Ditto.
602 (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
603 fields.
604 (RegVRex): New.
605 * i386-opc.tbl: Add AVX512 instructions.
606 * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
607 registers, mask registers.
608 * i386-tbl.h: Regenerate.
609
1d2db237
RS		 6102013-07-25 Aaro Koskinen <aaro.koskinen@iki.fi>
611
612 PR gas/15220
613 * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
614 Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
615
a0046408
L		 6162013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
617
618 * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
619 PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
620 PREFIX_0F3ACC.
621 (prefix_table): Updated.
622 (three_byte_table): Likewise.
623 * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
624 (cpu_flags): Add CpuSHA.
625 (i386_cpu_flags): Add cpusha.
626 * i386-init.h: Regenerate.
627 * i386-opc.h (CpuSHA): New.
628 (CpuUnused): Restored.
629 (i386_cpu_flags): Add cpusha.
630 * i386-opc.tbl: Add SHA instructions.
631 * i386-tbl.h: Regenerate.
632
7e8b059b
L		 6332013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
634 Kirill Yukhin <kirill.yukhin@intel.com>
635 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
636
637 * i386-dis.c (BND_Fixup): New.
638 (Ebnd): New.
639 (Ev_bnd): New.
640 (Gbnd): New.
641 (BND): New.
642 (v_bnd_mode): New.
643 (bnd_mode): New.
c623f86c
L		 644 (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
645 MOD_0F1B_PREFIX_1.
646 (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
7e8b059b
L		 647 (dis tables): Replace XX with BND for near branch and call
648 instructions.
649 (prefix_table): Add new entries.
650 (mod_table): Likewise.
651 (names_bnd): New.
652 (intel_names_bnd): New.
653 (att_names_bnd): New.
654 (BND_PREFIX): New.
655 (prefix_name): Handle BND_PREFIX.
656 (print_insn): Initialize names_bnd.
657 (intel_operand_size): Handle new modes.
658 (OP_E_register): Likewise.
659 (OP_E_memory): Likewise.
660 (OP_G): Likewise.
661 * i386-gen.c (cpu_flag_init): Add CpuMPX.
662 (cpu_flags): Add CpuMPX.
663 (operand_type_init): Add RegBND.
664 (opcode_modifiers): Add BNDPrefixOk.
665 (operand_types): Add RegBND.
666 * i386-init.h: Regenerate.
667 * i386-opc.h (CpuMPX): New.
668 (CpuUnused): Comment out.
669 (i386_cpu_flags): Add cpumpx.
670 (BNDPrefixOk): New.
671 (i386_opcode_modifier): Add bndprefixok.
672 (RegBND): New.
673 (i386_operand_type): Add regbnd.
674 * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
675 Add MPX instructions and bnd prefix.
676 * i386-reg.tbl: Add bnd0-bnd3 registers.
677 * i386-tbl.h: Regenerate.
678
b56e23fb
RS		 6792013-07-17 Richard Sandiford <rdsandiford@googlemail.com>
680
681 * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
682 ATTRIBUTE_UNUSED.
683
e7ae278d
RS		 6842013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
685
686 * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
687 special rules.
688 * Makefile.in: Regenerate.
689 * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
690 all fields. Reformat.
691
c3c07478
RS		 6922013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
693
694 * mips16-opc.c: Include mips-formats.h.
695 (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
696 static arrays.
697 (decode_mips16_operand): New function.
698 * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
699 (print_insn_arg): Handle OP_ENTRY_EXIT list.
700 Abort for OP_SAVE_RESTORE_LIST.
701 (print_mips16_insn_arg): Change interface. Use mips_operand
702 structures. Delete GET_OP_S. Move GET_OP definition to...
703 (print_insn_mips16): ...here. Call init_print_arg_state.
704 Update the call to print_mips16_insn_arg.
705
ab902481
RS		 7062013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
707
708 * mips-formats.h: New file.
709 * mips-opc.c: Include mips-formats.h.
710 (reg_0_map): New static array.
711 (decode_mips_operand): New function.
712 * micromips-opc.c: Remove <stdio.h> include. Include mips-formats.h.
713 (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
714 (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
715 (int_c_map): New static arrays.
716 (decode_micromips_operand): New function.
717 * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
718 (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
719 (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
720 (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
721 (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
722 (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
723 (micromips_imm_b_map, micromips_imm_c_map): Delete.
724 (print_reg): New function.
725 (mips_print_arg_state): New structure.
726 (init_print_arg_state, print_insn_arg): New functions.
727 (print_insn_args): Change interface and use mips_operand structures.
728 Delete GET_OP_S. Move GET_OP definition to...
729 (print_insn_mips): ...here. Update the call to print_insn_args.
730 (print_insn_micromips): Use print_insn_args.
731
cc537e56
RS		 7322013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
733
734 * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
735 in macros.
736
7a5f87ce
RS		 7372013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
738
739 * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
740 ADDA.S, MULA.S and SUBA.S.
741
41741fa4
L		 7422013-07-08 H.J. Lu <hongjiu.lu@intel.com>
743
744 PR gas/13572
745 * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
746 * i386-tbl.h: Regenerated.
747
f2ae14a1
RS		 7482013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
749
750 * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
751 and SD A(B) macros up.
752 * micromips-opc.c (micromips_opcodes): Likewise.
753
04c9d415
RS		 7542013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
755
756 * mips16-opc.c: Add entries for argumentless "entry" and "exit"
757 instructions.
758
5c324c16
RS		 7592013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
760
761 * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
762 MDMX-like instructions.
763 * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
764 printing "Q" operands for INSN_5400 instructions.
765
23e69e47
RS		 7662013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
767
768 * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
769 "+S" for "cins".
770 * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
771 Combine cases.
772
27c5c572
RS		 7732013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
774
775 * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
776 "jalx".
777 * mips16-opc.c (mips16_opcodes): Likewise.
778 * micromips-opc.c (micromips_opcodes): Likewise.
779 * mips-dis.c (print_insn_args, print_mips16_insn_arg)
780 (print_insn_mips16): Handle "+i".
781 (print_insn_micromips): Likewise. Conditionally preserve the
782 ISA bit for "a" but not for "+i".
783
e76ff5ab
RS		 7842013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
785
786 * micromips-opc.c (WR_mhi): Rename to..
787 (WR_mh): ...this.
788 (micromips_opcodes): Update "movep" entry accordingly. Replace
789 "mh,mi" with "mh".
790 * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
791 (micromips_to_32_reg_h_map1): ...this.
792 (micromips_to_32_reg_i_map): Rename to...
793 (micromips_to_32_reg_h_map2): ...this.
794 (print_micromips_insn): Remove "mi" case. Print both registers
795 in the pair for "mh".
796
fa7616a4
RS		 7972013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
798
799 * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
800 * micromips-opc.c (micromips_opcodes): Likewise.
801 * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
802 and "+T" handling. Check for a "0" suffix when deciding whether to
803 use coprocessor 0 names. In that case, also check for ",H" selectors.
804
fb798c50
AK		 8052013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
806
807 * s390-opc.c (J12_12, J24_24): New macros.
808 (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
809 (MASK_MII_UPI): Rename to MASK_MII_UPP.
810 * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
811
58ae08f2
AM		 8122013-07-04 Alan Modra <amodra@gmail.com>
813
814 * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
815
b5e04c2b
NC		 8162013-06-26 Nick Clifton <nickc@redhat.com>
817
818 * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
819 field when checking for type 2 nop.
820 * rx-decode.c: Regenerate.
821
833794fc
MR		 8222013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
823
824 * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
825 and "movep" macros.
826
1bbce132
MR		 8272013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
828
829 * mips-dis.c (is_mips16_plt_tail): New function.
830 (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
831 word.
832 (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
833
34c911a4
NC		 8342013-06-21 DJ Delorie <dj@redhat.com>
835
836 * msp430-decode.opc: New.
837 * msp430-decode.c: New/generated.
838 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
839 (MAINTAINER_CLEANFILES): Likewise.
840 Add rule to build msp430-decode.c frommsp430decode.opc
841 using the opc2c program.
842 * Makefile.in: Regenerate.
843 * configure.in: Add msp430-decode.lo to msp430 architecture files.
844 * configure: Regenerate.
845
b9eead84
YZ		 8462013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
847
848 * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
849 (SYMTAB_AVAILABLE): Removed.
850 (#include "elf/aarch64.h): Ditto.
851
7f3c4072
CM		 8522013-06-17 Catherine Moore <clm@codesourcery.com>
853 Maciej W. Rozycki <macro@codesourcery.com>
854 Chao-Ying Fu <fu@mips.com>
855
856 * micromips-opc.c (EVA): Define.
857 (TLBINV): Define.
858 (micromips_opcodes): Add EVA opcodes.
859 * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
860 (print_insn_args): Handle EVA offsets.
861 (print_insn_micromips): Likewise.
862 * mips-opc.c (EVA): Define.
863 (TLBINV): Define.
864 (mips_builtin_opcodes): Add EVA opcodes.
865
de40ceb6
AM		 8662013-06-17 Alan Modra <amodra@gmail.com>
867
868 * Makefile.am (mips-opc.lo): Add rules to create automatic
869 dependency files. Pass archdefs.
870 (micromips-opc.lo, mips16-opc.lo): Likewise.
871 * Makefile.in: Regenerate.
872
3531d549
DD		 8732013-06-14 DJ Delorie <dj@redhat.com>
874
875 * rx-decode.opc (rx_decode_opcode): Bit operations on
876 registers are 32-bit operations, not 8-bit operations.
877 * rx-decode.c: Regenerate.
878
ba92f7fb
CF		 8792013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
880
881 * micromips-opc.c (IVIRT): New define.
882 (IVIRT64): New define.
883 (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
884 tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
885
886 * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
887 dmtgc0 to print cp0 names.
888
9daf7bab
SL		 8892013-06-09 Sandra Loosemore <sandra@codesourcery.com>
890
891 * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
892 argument.
893
d301a56b
RS		 8942013-06-08 Catherine Moore <clm@codesourcery.com>
895 Richard Sandiford <rdsandiford@googlemail.com>
896
897 * micromips-opc.c (D32, D33, MC): Update definitions.
898 (micromips_opcodes): Initialize ase field.
899 * mips-dis.c (mips_arch_choice): Add ase field.
900 (mips_arch_choices): Initialize ase field.
901 (set_default_mips_dis_options): Declare and setup mips_ase.
902 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
903 MT32, MC): Update definitions.
904 (mips_builtin_opcodes): Initialize ase field.
905
a3dcb6c5
RS		 9062013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
907
908 * s390-opc.txt (flogr): Require a register pair destination.
909
6cf1d90c
AK		 9102013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
911
912 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
913 instruction format.
914
c77c0862
RS		 9152013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
916
917 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
918
c0637f3a
PB		 9192013-05-20 Peter Bergner <bergner@vnet.ibm.com>
920
921 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
922 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
923 XLS_MASK, PPCVSX2): New defines.
924 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
925 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
926 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
927 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
928 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
929 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
930 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
931 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
932 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
933 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
934 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
935 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
936 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
937 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
938 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
939 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
940 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
941 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
942 <lxvx, stxvx>: New extended mnemonics.
943
4934fdaf
AM		 9442013-05-17 Alan Modra <amodra@gmail.com>
945
946 * ia64-raw.tbl: Replace non-ASCII char.
947 * ia64-waw.tbl: Likewise.
948 * ia64-asmtab.c: Regenerate.
949
6091d651
SE		 9502013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
951
952 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
953 * i386-init.h: Regenerated.
954
d2865ed3
YZ		 9552013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
956
957 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
958 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
959 check from [0, 255] to [-128, 255].
960
b015e599
AP		 9612013-05-09 Andrew Pinski <apinski@cavium.com>
962
963 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
964 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
965 (parse_mips_dis_option): Handle the virt option.
966 (print_insn_args): Handle "+J".
967 (print_mips_disassembler_options): Print out message about virt64.
968 * mips-opc.c (IVIRT): New define.
969 (IVIRT64): New define.
970 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
971 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
972 Move rfe to the bottom as it conflicts with tlbgp.
973
9f0682fe
AM		 9742013-05-09 Alan Modra <amodra@gmail.com>
975
976 * ppc-opc.c (extract_vlesi): Properly sign extend.
977 (extract_vlensi): Likewise. Comment reason for setting invalid.
978
13761a11
NC		 9792013-05-02 Nick Clifton <nickc@redhat.com>
980
981 * msp430-dis.c: Add support for MSP430X instructions.
982
e3031850
SL		 9832013-04-24 Sandra Loosemore <sandra@codesourcery.com>
984
985 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
986 to "eccinj".
987
17310e56
NC		 9882013-04-17 Wei-chen Wang <cole945@gmail.com>
989
990 PR binutils/15369
991 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
992 of CGEN_CPU_ENDIAN.
993 (hash_insns_list): Likewise.
994
731df338
JK		 9952013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
996
997 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
998 warning workaround.
999
5f77db52
JB		 10002013-04-08 Jan Beulich <jbeulich@suse.com>
1001
1002 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
1003 * i386-tbl.h: Re-generate.
1004
0afd1215
DM		 10052013-04-06 David S. Miller <davem@davemloft.net>
1006
1007 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
1008 of an opcode, prefer the one with F_PREFERRED set.
1009 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
1010 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
1011 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
1012 mark existing mnenomics as aliases. Add "cc" suffix to edge
1013 instructions generating condition codes, mark existing mnenomics
1014 as aliases. Add "fp" prefix to VIS compare instructions, mark
1015 existing mnenomics as aliases.
1016
41702d50
NC		 10172013-04-03 Nick Clifton <nickc@redhat.com>
1018
1019 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
1020 destination address by subtracting the operand from the current
1021 address.
1022 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
1023 a positive value in the insn.
1024 (extract_u16_loop): Do not negate the returned value.
1025 (D16_LOOP): Add V850_INVERSE_PCREL flag.
1026
1027 (ceilf.sw): Remove duplicate entry.
1028 (cvtf.hs): New entry.
1029 (cvtf.sh): Likewise.
1030 (fmaf.s): Likewise.
1031 (fmsf.s): Likewise.
1032 (fnmaf.s): Likewise.
1033 (fnmsf.s): Likewise.
1034 (maddf.s): Restrict to E3V5 architectures.
1035 (msubf.s): Likewise.
1036 (nmaddf.s): Likewise.
1037 (nmsubf.s): Likewise.
1038
55cf16e1
L		 10392013-03-27 H.J. Lu <hongjiu.lu@intel.com>
1040
1041 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
1042 check address mode.
1043 (print_insn): Pass sizeflag to get_sib.
1044
51dcdd4d
NC		 10452013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
1046
1047 PR binutils/15068
1048 * tic6x-dis.c: Add support for displaying 16-bit insns.
1049
795b8e6b
NC		 10502013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
1051
1052 PR gas/15095
1053 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
1054 individual msb and lsb halves in src1 & src2 fields. Discard the
1055 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
1056 follow what Ti SDK does in that case as any value in the src1
1057 field yields the same output with SDK disassembler.
1058
314d60dd
ME		 10592013-03-12 Michael Eager <eager@eagercon.com>
1060
795b8e6b 1061 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
314d60dd 1062
dad60f8e
SL		 10632013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
1064
1065 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
1066
f5cb796a
SL		 10672013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
1068
1069 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
1070
21fde85c
SL		 10712013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
1072
1073 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
1074
dd5181d5
KT		 10752013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1076
1077 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
1078 (thumb32_opcodes): Likewise.
1079 (print_insn_thumb32): Handle 'S' control char.
1080
87a8d6cb
NC		 10812013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
1082
1083 * lm32-desc.c: Regenerate.
1084
99dce992
L		 10852013-03-01 H.J. Lu <hongjiu.lu@intel.com>
1086
1087 * i386-reg.tbl (riz): Add RegRex64.
1088 * i386-tbl.h: Regenerated.
1089
e60bb1dd
YZ		 10902013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
1091
1092 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
1093 (aarch64_feature_crc): New static.
1094 (CRC): New macro.
1095 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
1096 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
1097 * aarch64-asm-2.c: Re-generate.
1098 * aarch64-dis-2.c: Ditto.
1099 * aarch64-opc-2.c: Ditto.
1100
c7570fcd
AM		 11012013-02-27 Alan Modra <amodra@gmail.com>
1102
1103 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
1104 * rl78-decode.c: Regenerate.
1105
151fa98f
NC		 11062013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
1107
1108 * rl78-decode.opc: Fix encoding of DIVWU insn.
1109 * rl78-decode.c: Regenerate.
1110
5c111e37
L		 11112013-02-19 H.J. Lu <hongjiu.lu@intel.com>
1112
1113 PR gas/15159
1114 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
1115
1116 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
1117 (cpu_flags): Add CpuSMAP.
1118
1119 * i386-opc.h (CpuSMAP): New.
1120 (i386_cpu_flags): Add cpusmap.
1121
1122 * i386-opc.tbl: Add clac and stac.
1123
1124 * i386-init.h: Regenerated.
1125 * i386-tbl.h: Likewise.
1126
9d1df426
NC		 11272013-02-15 Markos Chandras <markos.chandras@imgtec.com>
1128
1129 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
1130 which also makes the disassembler output be in little
1131 endian like it should be.
1132
a1ccaec9
YZ		 11332013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
1134
1135 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
1136 fields to NULL.
1137 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
1138
ef068ef4 11392013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
5417f71e
MR		 1140
1141 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
1142 section disassembled.
1143
6fe6ded9
RE		 11442013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1145
1146 * arm-dis.c: Update strht pattern.
1147
0aa27725
RS		 11482013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
1149
1150 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
1151 single-float. Disable ll, lld, sc and scd for EE. Disable the
1152 trunc.w.s macro for EE.
1153
36591ba1
SL		 11542013-02-06 Sandra Loosemore <sandra@codesourcery.com>
1155 Andrew Jenner <andrew@codesourcery.com>
1156
1157 Based on patches from Altera Corporation.
1158
1159 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
1160 nios2-opc.c.
1161 * Makefile.in: Regenerated.
1162 * configure.in: Add case for bfd_nios2_arch.
1163 * configure: Regenerated.
1164 * disassemble.c (ARCH_nios2): Define.
1165 (disassembler): Add case for bfd_arch_nios2.
1166 * nios2-dis.c: New file.
1167 * nios2-opc.c: New file.
1168
545093a4
AM		 11692013-02-04 Alan Modra <amodra@gmail.com>
1170
1171 * po/POTFILES.in: Regenerate.
1172 * rl78-decode.c: Regenerate.
1173 * rx-decode.c: Regenerate.
1174
e30181a5
YZ		 11752013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
1176
1177 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
1178 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
1179 * aarch64-asm.c (convert_xtl_to_shll): New function.
1180 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1181 calling convert_xtl_to_shll.
1182 * aarch64-dis.c (convert_shll_to_xtl): New function.
1183 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1184 calling convert_shll_to_xtl.
1185 * aarch64-gen.c: Update copyright year.
1186 * aarch64-asm-2.c: Re-generate.
1187 * aarch64-dis-2.c: Re-generate.
1188 * aarch64-opc-2.c: Re-generate.
1189
78c8d46c
NC		 11902013-01-24 Nick Clifton <nickc@redhat.com>
1191
1192 * v850-dis.c: Add support for e3v5 architecture.
1193 * v850-opc.c: Likewise.
1194
f5555712
YZ		 11952013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
1196
1197 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
1198 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
1199 * aarch64-opc.c (operand_general_constraint_met_p): For
78c8d46c 1200 AARCH64_MOD_LSL, move the range check on the shift amount before the
f5555712
YZ		 1201 alignment check; change to call set_sft_amount_out_of_range_error
1202 instead of set_imm_out_of_range_error.
1203 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
1204 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
1205 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
1206 SIMD_IMM_SFT.
1207
2f81ff92
L		 12082013-01-16 H.J. Lu <hongjiu.lu@intel.com>
1209
1210 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
1211
1212 * i386-init.h: Regenerated.
1213 * i386-tbl.h: Likewise.
1214
dd42f060
NC		 12152013-01-15 Nick Clifton <nickc@redhat.com>
1216
1217 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
1218 values.
1219 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
1220
a4533ed8
NC		 12212013-01-14 Will Newton <will.newton@imgtec.com>
1222
1223 * metag-dis.c (REG_WIDTH): Increase to 64.
1224
5817ffd1
PB		 12252013-01-10 Peter Bergner <bergner@vnet.ibm.com>
1226
1227 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
1228 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
1229 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
1230 (SH6): Update.
1231 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
1232 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
1233 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
1234 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
1235
a3c62988
NC		 12362013-01-10 Will Newton <will.newton@imgtec.com>
1237
1238 * Makefile.am: Add Meta.
1239 * configure.in: Add Meta.
1240 * disassemble.c: Add Meta support.
1241 * metag-dis.c: New file.
1242 * Makefile.in: Regenerate.
1243 * configure: Regenerate.
1244
73335eae
NC		 12452013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
1246
1247 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
1248 (match_opcode): Rename to cr16_match_opcode.
1249
e407c74b
NC		 12502013-01-04 Juergen Urban <JuergenUrban@gmx.de>
1251
1252 * mips-dis.c: Add names for CP0 registers of r5900.
1253 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
1254 instructions sq and lq.
1255 Add support for MIPS r5900 CPU.
1256 Add support for 128 bit MMI (Multimedia Instructions).
1257 Add support for EE instructions (Emotion Engine).
1258 Disable unsupported floating point instructions (64 bit and
1259 undefined compare operations).
1260 Enable instructions of MIPS ISA IV which are supported by r5900.
1261 Disable 64 bit co processor instructions.
1262 Disable 64 bit multiplication and division instructions.
1263 Disable instructions for co-processor 2 and 3, because these are
1264 not supported (preparation for later VU0 support (Vector Unit)).
1265 Disable cvt.w.s because this behaves like trunc.w.s and the
1266 correct execution can't be ensured on r5900.
1267 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
1268 will confuse less developers and compilers.
1269
a32c3ff8
NC		 12702013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
1271
fb098a1e
YZ		 1272 * aarch64-opc.c (aarch64_print_operand): Change to print
1273 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
1274 in comment.
1275 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
1276 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
1277 OP_MOV_IMM_WIDE.
1278
12792013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
1280
1281 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
1282 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
a32c3ff8 1283
62658407
L		 12842013-01-02 H.J. Lu <hongjiu.lu@intel.com>
1285
1286 * i386-gen.c (process_copyright): Update copyright year to 2013.
1287
bab4becb 12882013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
5bf135a7 1289
bab4becb
NC		 1290 * cr16-dis.c (match_opcode,make_instruction): Remove static
1291 declaration.
1292 (dwordU,wordU): Moved typedefs to opcode/cr16.h
1293 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
5bf135a7 1294
bab4becb 1295For older changes see ChangeLog-2012
252b5132 1296\f
bab4becb 1297Copyright (C) 2013 Free Software Foundation, Inc.
752937aa
NC		 1298
1299Copying and distribution of this file, with or without modification,
1300are permitted in any medium without royalty provided the copyright
1301notice and this notice are preserved.
1302
252b5132 1303Local Variables:
2f6d2f85
NC		 1304mode: change-log
1305left-margin: 8
1306fill-column: 74
252b5132
RH		 1307version-control: never
1308End:
GDB Binutils - Deliverables
This page took 0.684751 seconds and 4 git commands to generate.