[deliverable/binutils-gdb.git] / opcodes / ChangeLog

2015-06-01  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (print_insn): Swap rounding mode specifier and
	general purpose register in Intel mode.

2015-06-01  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
	* i386-tbl.h: Regenerate.

2015-05-18  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
	* i386-init.h: Regenerated.

2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>

	PR binutis/18386
	* i386-dis.c: Add comments for '@'.
	(x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
	(enum x86_64_isa): New.
	(isa64): Likewise.
	(print_i386_disassembler_options): Add amd64 and intel64.
	(print_insn): Handle amd64 and intel64.
	(putop): Handle '@'.
	(OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
	* i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
	* i386-opc.h (AMD64): New.
	(CpuIntel64): Likewise.
	(i386_cpu_flags): Add cpuamd64 and cpuintel64.
	* i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
	Mark direct call/jmp without Disp16|Disp32 as Intel64.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2015-05-14  Peter Bergner  <bergner@vnet.ibm.com>

	* ppc-opc.c (IH) New define.
	(powerpc_opcodes) <wait>: Do not enable for POWER7.
	<tlbie>: Add RS operand for POWER7.
	<slbia>: Add IH operand for POWER6.

2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>

	* opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
	direct branch.
	(jmp): Likewise.
	* i386-tbl.h: Regenerated.

2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>

	* configure.ac: Support bfd_iamcu_arch.
	* disassemble.c (disassembler): Support bfd_iamcu_arch.
	* i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
	CPU_IAMCU_COMPAT_FLAGS.
	(cpu_flags): Add CpuIAMCU.
	* i386-opc.h (CpuIAMCU): New.
	(i386_cpu_flags): Add cpuiamcu.
	* configure: Regenerated.
	* i386-init.h: Likewise.
	* i386-tbl.h: Likewise.

2015-05-08  H.J. Lu  <hongjiu.lu@intel.com>

	PR binutis/18386
	* i386-dis.c (X86_64_E8): New.
	(X86_64_E9): Likewise.
	Update comments on 'T', 'U', 'V'.  Add comments for '^'.
	(dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
	(x86_64_table): Add X86_64_E8 and X86_64_E9.
	(mod_table): Replace {T|} with ^ on Jcall/Jmp.
	(putop): Handle '^'.
	(OP_J): Ignore the operand size prefix in 64-bit.  Don't check
	REX_W.

2015-04-30  DJ Delorie  <dj@redhat.com>

	* disassemble.c (disassembler): Choose suitable disassembler based
	on E_ABI.
	* rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
	it to decode mul/div insns.
	* rl78-decode.c: Regenerate.
	* rl78-dis.c (print_insn_rl78): Rename to...
	(print_insn_rl78_common): ...this, take ISA parameter.
	(print_insn_rl78): New.
	(print_insn_rl78_g10): New.
	(print_insn_rl78_g13): New.
	(print_insn_rl78_g14): New.
	(rl78_get_disassembler): New.

2015-04-29  Nick Clifton  <nickc@redhat.com>

	* po/fr.po: Updated French translation.

2015-04-27  Peter Bergner  <bergner@vnet.ibm.com>

	* ppc-opc.c (DCBT_EO): New define.
	(powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
	<lharx>: Likewise.
	<stbcx.>: Likewise.
	<sthcx.>: Likewise.
	<waitrsv>: Do not enable for POWER7 and later.
	<waitimpl>: Likewise.
	<dcbt>: Default to the two operand form of the instruction for all
	"old" cpus.  For "new" cpus, use the operand ordering that matches
	whether the cpu is server or embedded.
	<dcbtst>: Likewise.

2015-04-27  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* s390-opc.c: New instruction type VV0UU2.
	* s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
	and WFC.

2015-04-23  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
	* i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
	vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
	(vfpclasspd, vfpclassps): Add %XZ.

2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (PREFIX_UD_SHIFT): Removed.
	(PREFIX_UD_REPZ): Likewise.
	(PREFIX_UD_REPNZ): Likewise.
	(PREFIX_UD_DATA): Likewise.
	(PREFIX_UD_ADDR): Likewise.
	(PREFIX_UD_LOCK): Likewise.

2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (prefix_requirement): Removed.
	(print_insn): Don't set prefix_requirement.  Check
	dp->prefix_requirement instead of prefix_requirement.

2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>

	PR binutils/17898
	* i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
	(PREFIX_MOD_0_0FC7_REG_6): This.
	(PREFIX_MOD_3_0FC7_REG_6): New.
	(PREFIX_MOD_3_0FC7_REG_7): Likewise.
	(prefix_table): Replace PREFIX_0FC7_REG_6 with
	PREFIX_MOD_0_0FC7_REG_6.  Add PREFIX_MOD_3_0FC7_REG_6 and
	PREFIX_MOD_3_0FC7_REG_7.
	(mod_table): Replace PREFIX_0FC7_REG_6 with
	PREFIX_MOD_0_0FC7_REG_6.  Use PREFIX_MOD_3_0FC7_REG_6 and
	PREFIX_MOD_3_0FC7_REG_7.

2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
	(PREFIX_MANDATORY_REPNZ): Likewise.
	(PREFIX_MANDATORY_DATA): Likewise.
	(PREFIX_MANDATORY_ADDR): Likewise.
	(PREFIX_MANDATORY_LOCK): Likewise.
	(PREFIX_MANDATORY): Likewise.
	(PREFIX_UD_SHIFT): Set to 8
	(PREFIX_UD_REPZ): Updated.
	(PREFIX_UD_REPNZ): Likewise.
	(PREFIX_UD_DATA): Likewise.
	(PREFIX_UD_ADDR): Likewise.
	(PREFIX_UD_LOCK): Likewise.
	(PREFIX_IGNORED_SHIFT): New.
	(PREFIX_IGNORED_REPZ): Likewise.
	(PREFIX_IGNORED_REPNZ): Likewise.
	(PREFIX_IGNORED_DATA): Likewise.
	(PREFIX_IGNORED_ADDR): Likewise.
	(PREFIX_IGNORED_LOCK): Likewise.
	(PREFIX_OPCODE): Likewise.
	(PREFIX_IGNORED): Likewise.
	(Bad_Opcode): Replace PREFIX_MANDATORY with 0.
	(dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
	(three_byte_table): Likewise.
	(mod_table): Likewise.
	(mandatory_prefix): Renamed to ...
	(prefix_requirement): This.
	(prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
	Update PREFIX_90 entry.
	(get_valid_dis386): Check prefix_requirement to see if a prefix
	should be ignored.
	(print_insn): Replace mandatory_prefix with prefix_requirement.

2015-04-15  Renlin Li  <renlin.li@arm.com>

	* arm-dis.c (thumb32_opcodes): Define 'D' format control code,
	use it for ssat and ssat16.
	(print_insn_thumb32): Add handle case for 'D' control code.

2015-04-06  Ilya Tocar  <ilya.tocar@intel.com>
	    H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis-evex.h (evex_table): Fill prefix_requirement field.
	* i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
	PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
	PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
	PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
	(Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
	Fill prefix_requirement field.
	(struct dis386): Add prefix_requirement field.
	(dis386): Fill prefix_requirement field.
	(dis386_twobyte): Ditto.
	(twobyte_has_mandatory_prefix_: Remove.
	(reg_table): Fill prefix_requirement field.
	(prefix_table): Ditto.
	(x86_64_table): Ditto.
	(three_byte_table): Ditto.
	(xop_table): Ditto.
	(vex_table): Ditto.
	(vex_len_table): Ditto.
	(vex_w_table): Ditto.
	(mod_table): Ditto.
	(bad_opcode): Ditto.
	(print_insn): Use prefix_requirement.
	(FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
	FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
	(float_reg): Ditto.

2015-03-30  Mike Frysinger  <vapier@gentoo.org>

	* d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.

2015-03-29  H.J. Lu  <hongjiu.lu@intel.com>

	* Makefile.in: Regenerated.

2015-03-25  Anton Blanchard  <anton@samba.org>

	* ppc-dis.c (disassemble_init_powerpc): Only initialise
	powerpc_opcd_indices and vle_opcd_indices once.

2015-03-25  Anton Blanchard  <anton@samba.org>

	* ppc-opc.c (powerpc_opcodes): Add slbfee.

2015-03-24  Terry Guo  <terry.guo@arm.com>

	* arm-dis.c (opcode32): Updated to use new arm feature struct.
	(opcode16): Likewise.
	(coprocessor_opcodes): Replace bit with feature struct.
	(neon_opcodes): Likewise.
	(arm_opcodes): Likewise.
	(thumb_opcodes): Likewise.
	(thumb32_opcodes): Likewise.
	(print_insn_coprocessor): Likewise.
	(print_insn_arm): Likewise.
	(select_arm_features): Follow new feature struct.

2015-03-17  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>

	* i386-dis.c (rm_table): Add clzero.
	* i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
	Add CPU_CLZERO_FLAGS.
	(cpu_flags): Add CpuCLZERO.
	* i386-opc.h: Add CpuCLZERO.
	* i386-opc.tbl: Add clzero.
	* i386-init.h: Re-generated.
	* i386-tbl.h: Re-generated.

2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>

	* mips-opc.c (decode_mips_operand): Fix constraint issues
	with u and y operands.

2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>

	* mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.

2015-03-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* s390-opc.c: Add new IBM z13 instructions.
	* s390-opc.txt: Likewise.

2015-03-10  Renlin Li  <renlin.li@arm.com>

	* aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
	stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
	related alias.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Likewise.
	* aarch64-opc-2.c: Likewise.

2015-03-03  Jiong Wang  <jiong.wang@arm.com>

	* arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.

2015-02-25  Oleg Endo  <olegendo@gcc.gnu.org>

	* sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
	arch_sh_up.
	(pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
	arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.

2015-02-23  Vinay  <Vinay.G@kpit.com>

	* rl78-decode.opc (MOV): Added space between two operands for
	'mov' instruction in index addressing mode.
	* rl78-decode.c: Regenerate.

2015-02-19  Pedro Alves  <palves@redhat.com>

	* microblaze-dis.h [__cplusplus]: Wrap in extern "C".

2015-02-10  Pedro Alves  <palves@redhat.com>
	    Tom Tromey  <tromey@redhat.com>

	* microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
	microblaze_and, microblaze_xor.
	* microblaze-opc.h (opcodes): Adjust.

2015-01-28  James Bowman  <james.bowman@ftdichip.com>

	* Makefile.am: Add FT32 files.
	* configure.ac: Handle FT32.
	* disassemble.c (disassembler): Call print_insn_ft32.
	* ft32-dis.c: New file.
	* ft32-opc.c: New file.
	* Makefile.in: Regenerate.
	* configure: Regenerate.
	* po/POTFILES.in: Regenerate.

2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>

	* nds32-asm.c (keyword_sr): Add new system registers.

2015-01-16  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* s390-dis.c (s390_extract_operand): Support vector register
	operands.
	(s390_print_insn_with_opcode): Support new operands types and add
	new handling of optional operands.
	* s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
	and include opcode/s390.h instead.
	(struct op_struct): New field `flags'.
	(insertOpcode, insertExpandedMnemonic): New parameter `flags'.
	(dumpTable): Dump flags.
	(main): Parse flags from the s390-opc.txt file.  Add z13 as cpu
	string.
	* s390-opc.c: Add new operands types, instruction formats, and
	instruction masks.
	(s390_opformats): Add new formats for .insn.
	* s390-opc.txt: Add new instructions.

2015-01-01  Alan Modra  <amodra@gmail.com>

	Update year range in copyright notice of all files.

For older changes see ChangeLog-2014
\f
Copyright (C) 2015 Free Software Foundation, Inc.

Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.

Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
Commit	Line	Data
3a8547d2 JB	1	2015-06-01 Jan Beulich <jbeulich@suse.com>
	2
	3	* i386-dis.c (print_insn): Swap rounding mode specifier and
	4	general purpose register in Intel mode.
	5
015c54d5 JB	6	2015-06-01 Jan Beulich <jbeulich@suse.com>
	7
	8	* i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
	9	* i386-tbl.h: Regenerate.
	10
071f0063 L	11	2015-05-18 H.J. Lu <hongjiu.lu@intel.com>
	12
	13	* i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
	14	* i386-init.h: Regenerated.
	15
5db04b09 L	16	2015-05-15 H.J. Lu <hongjiu.lu@intel.com>
	17
	18	PR binutis/18386
	19	* i386-dis.c: Add comments for '@'.
	20	(x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
	21	(enum x86_64_isa): New.
	22	(isa64): Likewise.
	23	(print_i386_disassembler_options): Add amd64 and intel64.
	24	(print_insn): Handle amd64 and intel64.
	25	(putop): Handle '@'.
	26	(OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
	27	* i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
	28	* i386-opc.h (AMD64): New.
	29	(CpuIntel64): Likewise.
	30	(i386_cpu_flags): Add cpuamd64 and cpuintel64.
	31	* i386-opc.tbl: Add direct call/jmp with Disp16\|Disp32 for AMD64.
	32	Mark direct call/jmp without Disp16\|Disp32 as Intel64.
	33	* i386-init.h: Regenerated.
	34	* i386-tbl.h: Likewise.
	35
4bc0608a PB	36	2015-05-14 Peter Bergner <bergner@vnet.ibm.com>
	37
	38	* ppc-opc.c (IH) New define.
	39	(powerpc_opcodes) <wait>: Do not enable for POWER7.
	40	<tlbie>: Add RS operand for POWER7.
	41	<slbia>: Add IH operand for POWER6.
	42
70cead07 L	43	2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
	44
	45	* opcodes/i386-opc.tbl (call): Remove Disp16\|Disp32 from 64-bit
	46	direct branch.
	47	(jmp): Likewise.
	48	* i386-tbl.h: Regenerated.
	49
7b6d09fb L	50	2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
	51
	52	* configure.ac: Support bfd_iamcu_arch.
	53	* disassemble.c (disassembler): Support bfd_iamcu_arch.
	54	* i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
	55	CPU_IAMCU_COMPAT_FLAGS.
	56	(cpu_flags): Add CpuIAMCU.
	57	* i386-opc.h (CpuIAMCU): New.
	58	(i386_cpu_flags): Add cpuiamcu.
	59	* configure: Regenerated.
	60	* i386-init.h: Likewise.
	61	* i386-tbl.h: Likewise.
	62
31955f99 L	63	2015-05-08 H.J. Lu <hongjiu.lu@intel.com>
	64
	65	PR binutis/18386
	66	* i386-dis.c (X86_64_E8): New.
	67	(X86_64_E9): Likewise.
	68	Update comments on 'T', 'U', 'V'. Add comments for '^'.
	69	(dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
	70	(x86_64_table): Add X86_64_E8 and X86_64_E9.
	71	(mod_table): Replace {T\|} with ^ on Jcall/Jmp.
	72	(putop): Handle '^'.
	73	(OP_J): Ignore the operand size prefix in 64-bit. Don't check
	74	REX_W.
	75
0952813b DD	76	2015-04-30 DJ Delorie <dj@redhat.com>
	77
	78	* disassemble.c (disassembler): Choose suitable disassembler based
	79	on E_ABI.
	80	* rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
	81	it to decode mul/div insns.
	82	* rl78-decode.c: Regenerate.
	83	* rl78-dis.c (print_insn_rl78): Rename to...
	84	(print_insn_rl78_common): ...this, take ISA parameter.
	85	(print_insn_rl78): New.
	86	(print_insn_rl78_g10): New.
	87	(print_insn_rl78_g13): New.
	88	(print_insn_rl78_g14): New.
	89	(rl78_get_disassembler): New.
	90
f9d3ecaa NC	91	2015-04-29 Nick Clifton <nickc@redhat.com>
	92
	93	* po/fr.po: Updated French translation.
	94
4fff86c5 PB	95	2015-04-27 Peter Bergner <bergner@vnet.ibm.com>
	96
	97	* ppc-opc.c (DCBT_EO): New define.
	98	(powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
	99	<lharx>: Likewise.
	100	<stbcx.>: Likewise.
	101	<sthcx.>: Likewise.
	102	<waitrsv>: Do not enable for POWER7 and later.
	103	<waitimpl>: Likewise.
	104	<dcbt>: Default to the two operand form of the instruction for all
	105	"old" cpus. For "new" cpus, use the operand ordering that matches
	106	whether the cpu is server or embedded.
	107	<dcbtst>: Likewise.
	108
3b78cfe1 AK	109	2015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
	110
	111	* s390-opc.c: New instruction type VV0UU2.
	112	* s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
	113	and WFC.
	114
04d824a4 JB	115	2015-04-23 Jan Beulich <jbeulich@suse.com>
	116
	117	* i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
	118	* i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
	119	vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
	120	(vfpclasspd, vfpclassps): Add %XZ.
	121
09708981 L	122	2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
	123
	124	* i386-dis.c (PREFIX_UD_SHIFT): Removed.
	125	(PREFIX_UD_REPZ): Likewise.
	126	(PREFIX_UD_REPNZ): Likewise.
	127	(PREFIX_UD_DATA): Likewise.
	128	(PREFIX_UD_ADDR): Likewise.
	129	(PREFIX_UD_LOCK): Likewise.
	130
3888916d L	131	2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
	132
	133	* i386-dis.c (prefix_requirement): Removed.
	134	(print_insn): Don't set prefix_requirement. Check
	135	dp->prefix_requirement instead of prefix_requirement.
	136
f24bcbaa L	137	2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
	138
	139	PR binutils/17898
	140	* i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
	141	(PREFIX_MOD_0_0FC7_REG_6): This.
	142	(PREFIX_MOD_3_0FC7_REG_6): New.
	143	(PREFIX_MOD_3_0FC7_REG_7): Likewise.
	144	(prefix_table): Replace PREFIX_0FC7_REG_6 with
	145	PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
	146	PREFIX_MOD_3_0FC7_REG_7.
	147	(mod_table): Replace PREFIX_0FC7_REG_6 with
	148	PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
	149	PREFIX_MOD_3_0FC7_REG_7.
	150
507bd325 L	151	2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
	152
	153	* i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
	154	(PREFIX_MANDATORY_REPNZ): Likewise.
	155	(PREFIX_MANDATORY_DATA): Likewise.
	156	(PREFIX_MANDATORY_ADDR): Likewise.
	157	(PREFIX_MANDATORY_LOCK): Likewise.
	158	(PREFIX_MANDATORY): Likewise.
	159	(PREFIX_UD_SHIFT): Set to 8
	160	(PREFIX_UD_REPZ): Updated.
	161	(PREFIX_UD_REPNZ): Likewise.
	162	(PREFIX_UD_DATA): Likewise.
	163	(PREFIX_UD_ADDR): Likewise.
	164	(PREFIX_UD_LOCK): Likewise.
	165	(PREFIX_IGNORED_SHIFT): New.
	166	(PREFIX_IGNORED_REPZ): Likewise.
	167	(PREFIX_IGNORED_REPNZ): Likewise.
	168	(PREFIX_IGNORED_DATA): Likewise.
	169	(PREFIX_IGNORED_ADDR): Likewise.
	170	(PREFIX_IGNORED_LOCK): Likewise.
	171	(PREFIX_OPCODE): Likewise.
	172	(PREFIX_IGNORED): Likewise.
	173	(Bad_Opcode): Replace PREFIX_MANDATORY with 0.
	174	(dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
	175	(three_byte_table): Likewise.
	176	(mod_table): Likewise.
	177	(mandatory_prefix): Renamed to ...
	178	(prefix_requirement): This.
	179	(prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
	180	Update PREFIX_90 entry.
	181	(get_valid_dis386): Check prefix_requirement to see if a prefix
	182	should be ignored.
	183	(print_insn): Replace mandatory_prefix with prefix_requirement.
	184
f0fba320 RL	185	2015-04-15 Renlin Li <renlin.li@arm.com>
	186
	187	* arm-dis.c (thumb32_opcodes): Define 'D' format control code,
	188	use it for ssat and ssat16.
	189	(print_insn_thumb32): Add handle case for 'D' control code.
	190
bf890a93 IT	191	2015-04-06 Ilya Tocar <ilya.tocar@intel.com>
	192	H.J. Lu <hongjiu.lu@intel.com>
	193
	194	* i386-dis-evex.h (evex_table): Fill prefix_requirement field.
	195	* i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
	196	PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
	197	PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
	198	PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
	199	(Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
	200	Fill prefix_requirement field.
	201	(struct dis386): Add prefix_requirement field.
	202	(dis386): Fill prefix_requirement field.
	203	(dis386_twobyte): Ditto.
	204	(twobyte_has_mandatory_prefix_: Remove.
	205	(reg_table): Fill prefix_requirement field.
	206	(prefix_table): Ditto.
	207	(x86_64_table): Ditto.
	208	(three_byte_table): Ditto.
	209	(xop_table): Ditto.
	210	(vex_table): Ditto.
	211	(vex_len_table): Ditto.
	212	(vex_w_table): Ditto.
	213	(mod_table): Ditto.
	214	(bad_opcode): Ditto.
	215	(print_insn): Use prefix_requirement.
	216	(FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
	217	FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
	218	(float_reg): Ditto.
	219
2f783c1f MF	220	2015-03-30 Mike Frysinger <vapier@gentoo.org>
	221
	222	* d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
	223
b9d94d62 L	224	2015-03-29 H.J. Lu <hongjiu.lu@intel.com>
	225
	226	* Makefile.in: Regenerated.
	227
27c49e9a AB	228	2015-03-25 Anton Blanchard <anton@samba.org>
	229
	230	* ppc-dis.c (disassemble_init_powerpc): Only initialise
	231	powerpc_opcd_indices and vle_opcd_indices once.
	232
c4e676f1 AB	233	2015-03-25 Anton Blanchard <anton@samba.org>
	234
	235	* ppc-opc.c (powerpc_opcodes): Add slbfee.
	236
823d2571 TG	237	2015-03-24 Terry Guo <terry.guo@arm.com>
	238
	239	* arm-dis.c (opcode32): Updated to use new arm feature struct.
	240	(opcode16): Likewise.
	241	(coprocessor_opcodes): Replace bit with feature struct.
	242	(neon_opcodes): Likewise.
	243	(arm_opcodes): Likewise.
	244	(thumb_opcodes): Likewise.
	245	(thumb32_opcodes): Likewise.
	246	(print_insn_coprocessor): Likewise.
	247	(print_insn_arm): Likewise.
	248	(select_arm_features): Follow new feature struct.
	249
029f3522 GG	250	2015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
	251
	252	* i386-dis.c (rm_table): Add clzero.
	253	* i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
	254	Add CPU_CLZERO_FLAGS.
	255	(cpu_flags): Add CpuCLZERO.
	256	* i386-opc.h: Add CpuCLZERO.
	257	* i386-opc.tbl: Add clzero.
	258	* i386-init.h: Re-generated.
	259	* i386-tbl.h: Re-generated.
	260
6914869a AB	261	2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
	262
	263	* mips-opc.c (decode_mips_operand): Fix constraint issues
	264	with u and y operands.
	265
21e20815 AB	266	2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
	267
	268	* mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
	269
6b1d7593 AK	270	2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
	271
	272	* s390-opc.c: Add new IBM z13 instructions.
	273	* s390-opc.txt: Likewise.
	274
c8f89a34 JW	275	2015-03-10 Renlin Li <renlin.li@arm.com>
	276
	277	* aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
	278	stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
	279	related alias.
	280	* aarch64-asm-2.c: Regenerate.
	281	* aarch64-dis-2.c: Likewise.
	282	* aarch64-opc-2.c: Likewise.
	283
d8282f0e JW	284	2015-03-03 Jiong Wang <jiong.wang@arm.com>
	285
	286	* arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
	287
ac994365 OE	288	2015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
	289
	290	* sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
	291	arch_sh_up.
	292	(pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
	293	arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
	294
fd63f640 V	295	2015-02-23 Vinay <Vinay.G@kpit.com>
	296
	297	* rl78-decode.opc (MOV): Added space between two operands for
	298	'mov' instruction in index addressing mode.
	299	* rl78-decode.c: Regenerate.
	300
f63c1776 PA	301	2015-02-19 Pedro Alves <palves@redhat.com>
	302
	303	* microblaze-dis.h [__cplusplus]: Wrap in extern "C".
	304
07774fcc PA	305	2015-02-10 Pedro Alves <palves@redhat.com>
	306	Tom Tromey <tromey@redhat.com>
	307
	308	* microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
	309	microblaze_and, microblaze_xor.
	310	* microblaze-opc.h (opcodes): Adjust.
	311
3f8107ab AM	312	2015-01-28 James Bowman <james.bowman@ftdichip.com>
	313
	314	* Makefile.am: Add FT32 files.
	315	* configure.ac: Handle FT32.
	316	* disassemble.c (disassembler): Call print_insn_ft32.
	317	* ft32-dis.c: New file.
	318	* ft32-opc.c: New file.
	319	* Makefile.in: Regenerate.
	320	* configure: Regenerate.
	321	* po/POTFILES.in: Regenerate.
	322
e5fe4957 KLC	323	2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
	324
	325	* nds32-asm.c (keyword_sr): Add new system registers.
	326
1e2e8c52 AK	327	2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
	328
	329	* s390-dis.c (s390_extract_operand): Support vector register
	330	operands.
	331	(s390_print_insn_with_opcode): Support new operands types and add
	332	new handling of optional operands.
	333	* s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
	334	and include opcode/s390.h instead.
	335	(struct op_struct): New field `flags'.
	336	(insertOpcode, insertExpandedMnemonic): New parameter `flags'.
	337	(dumpTable): Dump flags.
	338	(main): Parse flags from the s390-opc.txt file. Add z13 as cpu
	339	string.
	340	* s390-opc.c: Add new operands types, instruction formats, and
	341	instruction masks.
	342	(s390_opformats): Add new formats for .insn.
	343	* s390-opc.txt: Add new instructions.
	344
b90efa5b	345	2015-01-01 Alan Modra <amodra@gmail.com>
bffb6004	346
b90efa5b	347	Update year range in copyright notice of all files.
bffb6004	348
b90efa5b	349	For older changes see ChangeLog-2014
252b5132	350	\f
b90efa5b	351	Copyright (C) 2015 Free Software Foundation, Inc.
752937aa NC	352
	353	Copying and distribution of this file, with or without modification,
	354	are permitted in any medium without royalty provided the copyright
	355	notice and this notice are preserved.
	356
252b5132	357	Local Variables:
2f6d2f85 NC	358	mode: change-log
	359	left-margin: 8
	360	fill-column: 74
252b5132 RH	361	version-control: never
252b5132 RH	362	End: