* ppc-tdep.h (ppc_num_vrs): New enum constant.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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12004-07-13 Elvis Chiang <elvisfb@gmail.com>
2
3 * arm-opc.h: Fix typo in comment.
4
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52004-07-11 Andreas Schwab <schwab@suse.de>
6
7 * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
8
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92004-07-09 Andreas Schwab <schwab@suse.de>
10
11 * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
12
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132004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
14
15 * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
16 (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
17 (crx-dis.lo): New target.
18 (crx-opc.lo): Likewise.
19 * Makefile.in: Regenerate.
20 * configure.in: Handle bfd_crx_arch.
21 * configure: Regenerate.
22 * crx-dis.c: New file.
23 * crx-opc.c: New file.
24 * disassemble.c (ARCH_crx): Define.
25 (disassembler): Handle ARCH_crx.
26
7a33b495
JW
272004-06-29 James E Wilson <wilson@specifixinc.com>
28
29 * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
30 * ia64-asmtab.c: Regnerate.
31
98e69875
AM
322004-06-28 Alan Modra <amodra@bigpond.net.au>
33
34 * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
35 (extract_fxm): Don't test dialect.
36 (XFXFXM_MASK): Include the power4 bit.
37 (XFXM): Add p4 param.
38 (powerpc_opcodes): Add mfocrf and mtocrf. Adjust mtcr.
39
a53b85e2
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402004-06-27 Alexandre Oliva <aoliva@redhat.com>
41
42 2003-07-21 Richard Sandiford <rsandifo@redhat.com>
43 * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
44
d0618d1c
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452004-06-26 Alan Modra <amodra@bigpond.net.au>
46
47 * ppc-opc.c (BH, XLBH_MASK): Define.
48 (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
49
1d9f512f
AM
502004-06-24 Alan Modra <amodra@bigpond.net.au>
51
52 * i386-dis.c (x_mode): Comment.
53 (two_source_ops): File scope.
54 (float_mem): Correct fisttpll and fistpll.
55 (float_mem_mode): New table.
56 (dofloat): Use it.
57 (OP_E): Correct intel mode PTR output.
58 (ptr_reg): Use open_char and close_char.
59 (PNI_Fixup): Handle possible suffix on sidt. Use op1out etc. for
60 operands. Set two_source_ops.
61
52886d70
AM
622004-06-15 Alan Modra <amodra@bigpond.net.au>
63
64 * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
65 instead of _raw_size.
66
bad9ceea
JJ
672004-06-08 Jakub Jelinek <jakub@redhat.com>
68
69 * ia64-gen.c (in_iclass): Handle more postinc st
70 and ld variants.
71 * ia64-asmtab.c: Rebuilt.
72
0451f5df
MS
732004-06-01 Martin Schwidefsky <schwidefsky@de.ibm.com>
74
75 * s390-opc.txt: Correct architecture mask for some opcodes.
76 lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
77 in the esa mode as well.
78
f6f9408f
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792004-05-28 Andrew Stubbs <andrew.stubbs@superh.com>
80
81 * sh-dis.c (target_arch): Make unsigned.
82 (print_insn_sh): Replace (most of) switch with a call to
83 sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
84 * sh-opc.h: Redefine architecture flags values.
85 Add sh3-nommu architecture.
86 Reorganise <arch>_up macros so they make more visual sense.
87 (SH_MERGE_ARCH_SET): Define new macro.
88 (SH_VALID_BASE_ARCH_SET): Likewise.
89 (SH_VALID_MMU_ARCH_SET): Likewise.
90 (SH_VALID_CO_ARCH_SET): Likewise.
91 (SH_VALID_ARCH_SET): Likewise.
92 (SH_MERGE_ARCH_SET_VALID): Likewise.
93 (SH_ARCH_SET_HAS_FPU): Likewise.
94 (SH_ARCH_SET_HAS_DSP): Likewise.
95 (SH_ARCH_UNKNOWN_ARCH): Likewise.
96 (sh_get_arch_from_bfd_mach): Add prototype.
97 (sh_get_arch_up_from_bfd_mach): Likewise.
98 (sh_get_bfd_mach_from_arch_set): Likewise.
99 (sh_merge_bfd_arc): Likewise.
100
be8c092b
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1012004-05-24 Peter Barada <peter@the-baradas.com>
102
103 * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
104 into new match_insn_m68k function. Loop over canidate
105 matches and select first that completely matches.
106 * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
107 * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
108 to verify addressing for MAC/EMAC.
109 * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
110 reigster halves since 'fpu' and 'spl' look misleading.
111 * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
112 * m68k-opc.c: Rearragne mac/emac cases to use longest for
113 first, tighten up match masks.
114 * m68k-opc.c: Add 'size' field to struct m68k_opcode. Produce
115 'size' from special case code in print_insn_m68k to
116 determine decode size of insns.
117
a30e9cc4
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1182004-05-19 Alan Modra <amodra@bigpond.net.au>
119
120 * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
121 well as when -mpower4.
122
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1232004-05-13 Nick Clifton <nickc@redhat.com>
124
125 * po/fr.po: Updated French translation.
126
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1272004-05-05 Peter Barada <peter@the-baradas.com>
128
129 * m68k-dis.c(print_insn_m68k): Add new chips, use core
130 variants in arch_mask. Only set m68881/68851 for 68k chips.
131 * m68k-op.c: Switch from ColdFire chips to core variants.
132
a404d431
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1332004-05-05 Alan Modra <amodra@bigpond.net.au>
134
a30e9cc4 135 PR 147.
a404d431
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136 * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
137
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1382004-04-29 Ben Elliston <bje@au.ibm.com>
139
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BE
140 * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
141 (powerpc_opcodes): Add "dbczl" instruction for PPC970.
f3806e43 142
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KK
1432004-04-22 Kaz Kojima <kkojima@rr.iij4u.or.jp>
144
145 * sh-dis.c (print_insn_sh): Print the value in constant pool
146 as a symbol if it looks like a symbol.
147
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1482004-04-22 Peter Barada <peter@the-baradas.com>
149
150 * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
151 appropriate ColdFire architectures.
152 (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
153 mask addressing.
154 Add EMAC instructions, fix MAC instructions. Remove
155 macmw/macml/msacmw/msacml instructions since mask addressing now
156 supported.
157
b4781d44
JJ
1582004-04-20 Jakub Jelinek <jakub@redhat.com>
159
160 * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
161 (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
162 suffix. Use fmov*x macros, create all 3 fpsize variants in one
163 macro. Adjust all users.
164
91809fda
NC
1652004-04-15 Anil Paranjpe <anilp1@kpitcummins.com>
166
167 * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
168 separately.
169
f4453dfa
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1702004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
171
172 * m32r-asm.c: Regenerate.
173
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1742004-03-29 Stan Shebs <shebs@apple.com>
175
176 * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
177 used.
178
e20c0b3d
AM
1792004-03-19 Alan Modra <amodra@bigpond.net.au>
180
181 * aclocal.m4: Regenerate.
182 * config.in: Regenerate.
183 * configure: Regenerate.
184 * po/POTFILES.in: Regenerate.
185 * po/opcodes.pot: Regenerate.
186
fdd12ef3
AM
1872004-03-16 Alan Modra <amodra@bigpond.net.au>
188
189 * ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
190 PPC_OPERANDS_GPR_0.
191 * ppc-opc.c (RA0): Define.
192 (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
193 (RAOPT): Rename from RAO. Update all uses.
a9c3619e 194 (powerpc_opcodes): Use RA0 as appropriate.
fdd12ef3 195
2dc111b3 1962004-03-15 Aldy Hernandez <aldyh@redhat.com>
fdd12ef3
AM
197
198 * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
2dc111b3 199
7bfeee7b
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2002004-03-15 Alan Modra <amodra@bigpond.net.au>
201
202 * sparc-dis.c (print_insn_sparc): Update getword prototype.
203
7ffdda93
ML
2042004-03-12 Michal Ludvig <mludvig@suse.cz>
205
206 * i386-dis.c (GRPPLOCK): Delete.
7bfeee7b 207 (grps): Delete GRPPLOCK entry.
7ffdda93 208
cc0ec051
AM
2092004-03-12 Alan Modra <amodra@bigpond.net.au>
210
211 * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
212 (M, Mp): Use OP_M.
213 (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
214 (GRPPADLCK): Define.
215 (dis386): Use NOP_Fixup on "nop".
216 (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
217 (twobyte_has_modrm): Set for 0xa7.
218 (padlock_table): Delete. Move to..
219 (grps): ..here, using OP_0f07. Use OP_Ofae on lfence, mfence
220 and clflush.
221 (print_insn): Revert PADLOCK_SPECIAL code.
222 (OP_E): Delete sfence, lfence, mfence checks.
223
4fd61dcb
JJ
2242004-03-12 Jakub Jelinek <jakub@redhat.com>
225
226 * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
227 (INVLPG_Fixup): New function.
228 (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
229
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ML
2302004-03-12 Michal Ludvig <mludvig@suse.cz>
231
232 * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
233 (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
234 (padlock_table): New struct with PadLock instructions.
235 (print_insn): Handle PADLOCK_SPECIAL.
236
c02908d2
AM
2372004-03-12 Alan Modra <amodra@bigpond.net.au>
238
239 * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
240 (OP_E): Twiddle clflush to sfence here.
241
d5bb7600
NC
2422004-03-08 Nick Clifton <nickc@redhat.com>
243
244 * po/de.po: Updated German translation.
245
ae51a426
JR
2462003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>
247
248 * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
249 nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu.
250 * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
251 accordingly.
252
676a64f4
RS
2532004-03-01 Richard Sandiford <rsandifo@redhat.com>
254
255 * frv-asm.c: Regenerate.
256 * frv-desc.c: Regenerate.
257 * frv-desc.h: Regenerate.
258 * frv-dis.c: Regenerate.
259 * frv-ibld.c: Regenerate.
260 * frv-opc.c: Regenerate.
261 * frv-opc.h: Regenerate.
262
c7a48b9a
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2632004-03-01 Richard Sandiford <rsandifo@redhat.com>
264
265 * frv-desc.c, frv-opc.c: Regenerate.
266
8ae0baa2
RS
2672004-03-01 Richard Sandiford <rsandifo@redhat.com>
268
269 * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
270
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JR
2712004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
272
273 * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
274 Also correct mistake in the comment.
275
6a5709a5
JR
2762004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
277
278 * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
279 ensure that double registers have even numbers.
280 Add REG_N_B01 for nn01 (binary 01) nibble to ensure
281 that reserved instruction 0xfffd does not decode the same
282 as 0xfdfd (ftrv).
283 * sh-opc.h: Add REG_N_D nibble type and use it whereever
284 REG_N refers to a double register.
285 Add REG_N_B01 nibble type and use it instead of REG_NM
286 in ftrv.
287 Adjust the bit patterns in a few comments.
288
e5d2b64f 2892004-02-25 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM
290
291 * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
e5d2b64f 292
1f04b05f
AH
2932004-02-20 Aldy Hernandez <aldyh@redhat.com>
294
295 * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
296
2f3b8700
AH
2972004-02-20 Aldy Hernandez <aldyh@redhat.com>
298
299 * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
300
f0b26da6 3012004-02-20 Aldy Hernandez <aldyh@redhat.com>
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302
303 * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
304 mtivor32, mtivor33, mtivor34.
f0b26da6 305
23d59c56 3062004-02-19 Aldy Hernandez <aldyh@redhat.com>
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307
308 * ppc-opc.c (powerpc_opcodes): Add mfmcar.
23d59c56 309
34920d91
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3102004-02-10 Petko Manolov <petkan@nucleusys.com>
311
312 * arm-opc.h Maverick accumulator register opcode fixes.
313
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BE
3142004-02-13 Ben Elliston <bje@wasabisystems.com>
315
316 * m32r-dis.c: Regenerate.
317
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3182004-01-27 Michael Snyder <msnyder@redhat.com>
319
320 * sh-opc.h (sh_table): "fsrra", not "fssra".
321
fe3a9bc4
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3222004-01-23 Andrew Over <andrew.over@cs.anu.edu.au>
323
324 * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
325 contraints.
326
ff24f124
JJ
3272004-01-19 Andrew Over <andrew.over@cs.anu.edu.au>
328
329 * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
330
a02a862a
AM
3312004-01-19 Alan Modra <amodra@bigpond.net.au>
332
333 * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
334 1. Don't print scale factor on AT&T mode when index missing.
335
d164ea7f
AO
3362004-01-16 Alexandre Oliva <aoliva@redhat.com>
337
338 * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
339 when loaded into XR registers.
340
cb10e79a
RS
3412004-01-14 Richard Sandiford <rsandifo@redhat.com>
342
343 * frv-desc.h: Regenerate.
344 * frv-desc.c: Regenerate.
345 * frv-opc.c: Regenerate.
346
f532f3fa
MS
3472004-01-13 Michael Snyder <msnyder@redhat.com>
348
349 * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
350
e45d0630
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3512004-01-09 Paul Brook <paul@codesourcery.com>
352
353 * arm-opc.h (arm_opcodes): Move generic mcrr after known
354 specific opcodes.
355
3ba7a1aa
DJ
3562004-01-07 Daniel Jacobowitz <drow@mvista.com>
357
358 * Makefile.am (libopcodes_la_DEPENDENCIES)
359 (libopcodes_la_LIBADD): Revert 2003-05-17 change. Add explanatory
360 comment about the problem.
361 * Makefile.in: Regenerate.
362
ba2d3f07
AO
3632004-01-06 Alexandre Oliva <aoliva@redhat.com>
364
365 2003-12-19 Alexandre Oliva <aoliva@redhat.com>
366 * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
367 cut&paste errors in shifting/truncating numerical operands.
368 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
369 * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
370 (parse_uslo16): Likewise.
371 (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
372 (parse_d12): Parse gotoff12 and gotofffuncdesc12.
373 (parse_s12): Likewise.
374 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
375 * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
376 (parse_uslo16): Likewise.
377 (parse_uhi16): Parse gothi and gotfuncdeschi.
378 (parse_d12): Parse got12 and gotfuncdesc12.
379 (parse_s12): Likewise.
380
3ab48931
NC
3812004-01-02 Albert Bartoszko <albar@nt.kegel.com.pl>
382
383 * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
384 instruction which looks similar to an 'rla' instruction.
a0bd404e 385
c9e214e5 386For older changes see ChangeLog-0203
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387\f
388Local Variables:
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389mode: change-log
390left-margin: 8
391fill-column: 74
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392version-control: never
393End:
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