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ld: Replace --rpath with -Wl,--rpath
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
b28b8b5e
L		 12017-08-07 H.J. Lu <hongjiu.lu@intel.com>
2
3 * disassemble.c (disassembler): Mark big and mach with
4 ATTRIBUTE_UNUSED.
5
e347efc3
MR		 62017-08-07 Maciej W. Rozycki <macro@imgtec.com>
7
8 * disassemble.c (disassembler): Remove arch/mach/endian
9 assertions.
10
7cbc739c
NC		 112017-07-25 Nick Clifton <nickc@redhat.com>
12
13 PR 21739
14 * arc-opc.c (insert_rhv2): Use lower case first letter in error
15 message.
16 (insert_r0): Likewise.
17 (insert_r1): Likewise.
18 (insert_r2): Likewise.
19 (insert_r3): Likewise.
20 (insert_sp): Likewise.
21 (insert_gp): Likewise.
22 (insert_pcl): Likewise.
23 (insert_blink): Likewise.
24 (insert_ilink1): Likewise.
25 (insert_ilink2): Likewise.
26 (insert_ras): Likewise.
27 (insert_rbs): Likewise.
28 (insert_rcs): Likewise.
29 (insert_simm3s): Likewise.
30 (insert_rrange): Likewise.
31 (insert_r13el): Likewise.
32 (insert_fpel): Likewise.
33 (insert_blinkel): Likewise.
34 (insert_pclel): Likewise.
35 (insert_nps_bitop_size_2b): Likewise.
36 (insert_nps_imm_offset): Likewise.
37 (insert_nps_imm_entry): Likewise.
38 (insert_nps_size_16bit): Likewise.
39 (insert_nps_##NAME##_pos): Likewise.
40 (insert_nps_##NAME): Likewise.
41 (insert_nps_bitop_ins_ext): Likewise.
42 (insert_nps_##NAME): Likewise.
43 (insert_nps_min_hofs): Likewise.
44 (insert_nps_##NAME): Likewise.
45 (insert_nps_rbdouble_64): Likewise.
46 (insert_nps_misc_imm_offset): Likewise.
47 * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
48 option description.
49
7684e580
JW		 502017-07-24 Laurent Desnogues <laurent.desnogues@arm.com>
51 Jiong Wang <jiong.wang@arm.com>
52
53 * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
54 correct the print.
55 * aarch64-dis-2.c: Regenerated.
56
47826cdb
AK		 572017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
58
59 * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
60 table.
61
2d2dbad0
NC		 622017-07-20 Nick Clifton <nickc@redhat.com>
63
64 * po/de.po: Updated German translation.
65
70b448ba 662017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
67
68 * arc-regs.h (sec_stat): New aux register.
69 (aux_kernel_sp): Likewise.
70 (aux_sec_u_sp): Likewise.
71 (aux_sec_k_sp): Likewise.
72 (sec_vecbase_build): Likewise.
73 (nsc_table_top): Likewise.
74 (nsc_table_base): Likewise.
75 (ersec_stat): Likewise.
76 (aux_sec_except): Likewise.
77
7179e0e6
CZ		 782017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
79
80 * arc-opc.c (extract_uimm12_20): New function.
81 (UIMM12_20): New operand.
82 (SIMM3_5_S): Adjust.
83 * arc-tbl.h (sjli): Add new instruction.
84
684d5a10
JEM		 852017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
86 John Eric Martin <John.Martin@emmicro-us.com>
87
88 * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
89 (UIMM3_23): Adjust accordingly.
90 * arc-regs.h: Add/correct jli_base register.
91 * arc-tbl.h (jli_s): Likewise.
92
de194d85
YC		 932017-07-18 Nick Clifton <nickc@redhat.com>
94
95 PR 21775
96 * aarch64-opc.c: Fix spelling typos.
97 * i386-dis.c: Likewise.
98
0f6329bd
RB		 992017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
100
101 * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
102 max_addr_offset and octets variables to size_t.
103
429d795d
AM		 1042017-07-12 Alan Modra <amodra@gmail.com>
105
106 * po/da.po: Update from translationproject.org/latest/opcodes/.
107 * po/de.po: Likewise.
108 * po/es.po: Likewise.
109 * po/fi.po: Likewise.
110 * po/fr.po: Likewise.
111 * po/id.po: Likewise.
112 * po/it.po: Likewise.
113 * po/nl.po: Likewise.
114 * po/pt_BR.po: Likewise.
115 * po/ro.po: Likewise.
116 * po/sv.po: Likewise.
117 * po/tr.po: Likewise.
118 * po/uk.po: Likewise.
119 * po/vi.po: Likewise.
120 * po/zh_CN.po: Likewise.
121
4162bb66
AM		 1222017-07-11 Yao Qi <yao.qi@linaro.org>
123 Alan Modra <amodra@gmail.com>
124
125 * cgen.sh: Mark generated files read-only.
126 * epiphany-asm.c: Regenerate.
127 * epiphany-desc.c: Regenerate.
128 * epiphany-desc.h: Regenerate.
129 * epiphany-dis.c: Regenerate.
130 * epiphany-ibld.c: Regenerate.
131 * epiphany-opc.c: Regenerate.
132 * epiphany-opc.h: Regenerate.
133 * fr30-asm.c: Regenerate.
134 * fr30-desc.c: Regenerate.
135 * fr30-desc.h: Regenerate.
136 * fr30-dis.c: Regenerate.
137 * fr30-ibld.c: Regenerate.
138 * fr30-opc.c: Regenerate.
139 * fr30-opc.h: Regenerate.
140 * frv-asm.c: Regenerate.
141 * frv-desc.c: Regenerate.
142 * frv-desc.h: Regenerate.
143 * frv-dis.c: Regenerate.
144 * frv-ibld.c: Regenerate.
145 * frv-opc.c: Regenerate.
146 * frv-opc.h: Regenerate.
147 * ip2k-asm.c: Regenerate.
148 * ip2k-desc.c: Regenerate.
149 * ip2k-desc.h: Regenerate.
150 * ip2k-dis.c: Regenerate.
151 * ip2k-ibld.c: Regenerate.
152 * ip2k-opc.c: Regenerate.
153 * ip2k-opc.h: Regenerate.
154 * iq2000-asm.c: Regenerate.
155 * iq2000-desc.c: Regenerate.
156 * iq2000-desc.h: Regenerate.
157 * iq2000-dis.c: Regenerate.
158 * iq2000-ibld.c: Regenerate.
159 * iq2000-opc.c: Regenerate.
160 * iq2000-opc.h: Regenerate.
161 * lm32-asm.c: Regenerate.
162 * lm32-desc.c: Regenerate.
163 * lm32-desc.h: Regenerate.
164 * lm32-dis.c: Regenerate.
165 * lm32-ibld.c: Regenerate.
166 * lm32-opc.c: Regenerate.
167 * lm32-opc.h: Regenerate.
168 * lm32-opinst.c: Regenerate.
169 * m32c-asm.c: Regenerate.
170 * m32c-desc.c: Regenerate.
171 * m32c-desc.h: Regenerate.
172 * m32c-dis.c: Regenerate.
173 * m32c-ibld.c: Regenerate.
174 * m32c-opc.c: Regenerate.
175 * m32c-opc.h: Regenerate.
176 * m32r-asm.c: Regenerate.
177 * m32r-desc.c: Regenerate.
178 * m32r-desc.h: Regenerate.
179 * m32r-dis.c: Regenerate.
180 * m32r-ibld.c: Regenerate.
181 * m32r-opc.c: Regenerate.
182 * m32r-opc.h: Regenerate.
183 * m32r-opinst.c: Regenerate.
184 * mep-asm.c: Regenerate.
185 * mep-desc.c: Regenerate.
186 * mep-desc.h: Regenerate.
187 * mep-dis.c: Regenerate.
188 * mep-ibld.c: Regenerate.
189 * mep-opc.c: Regenerate.
190 * mep-opc.h: Regenerate.
191 * mt-asm.c: Regenerate.
192 * mt-desc.c: Regenerate.
193 * mt-desc.h: Regenerate.
194 * mt-dis.c: Regenerate.
195 * mt-ibld.c: Regenerate.
196 * mt-opc.c: Regenerate.
197 * mt-opc.h: Regenerate.
198 * or1k-asm.c: Regenerate.
199 * or1k-desc.c: Regenerate.
200 * or1k-desc.h: Regenerate.
201 * or1k-dis.c: Regenerate.
202 * or1k-ibld.c: Regenerate.
203 * or1k-opc.c: Regenerate.
204 * or1k-opc.h: Regenerate.
205 * or1k-opinst.c: Regenerate.
206 * xc16x-asm.c: Regenerate.
207 * xc16x-desc.c: Regenerate.
208 * xc16x-desc.h: Regenerate.
209 * xc16x-dis.c: Regenerate.
210 * xc16x-ibld.c: Regenerate.
211 * xc16x-opc.c: Regenerate.
212 * xc16x-opc.h: Regenerate.
213 * xstormy16-asm.c: Regenerate.
214 * xstormy16-desc.c: Regenerate.
215 * xstormy16-desc.h: Regenerate.
216 * xstormy16-dis.c: Regenerate.
217 * xstormy16-ibld.c: Regenerate.
218 * xstormy16-opc.c: Regenerate.
219 * xstormy16-opc.h: Regenerate.
220
7639175c
AM		 2212017-07-07 Alan Modra <amodra@gmail.com>
222
223 * cgen-dis.in: Include disassemble.h, not dis-asm.h.
224 * m32c-dis.c: Regenerate.
225 * mep-dis.c: Regenerate.
226
e4bdd679
BP		 2272017-07-05 Borislav Petkov <bp@suse.de>
228
229 * i386-dis.c: Enable ModRM.reg /6 aliases.
230
60c96dbf
RR		 2312017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
232
233 * opcodes/arm-dis.c: Support MVFR2 in disassembly
234 with vmrs and vmsr.
235
0d702cfe
TG		 2362017-07-04 Tristan Gingold <gingold@adacore.com>
237
238 * configure: Regenerate.
239
15e6ed8c
TG		 2402017-07-03 Tristan Gingold <gingold@adacore.com>
241
242 * po/opcodes.pot: Regenerate.
243
b1d3c886
MR		 2442017-06-30 Maciej W. Rozycki <macro@imgtec.com>
245
246 * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
247 entries to the MSA ASE instruction block.
248
909b4e3d
MR		 2492017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
250 Maciej W. Rozycki <macro@imgtec.com>
251
252 * micromips-opc.c (XPA, XPAVZ): New macros.
253 (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
254 "mthgc0".
255
f5b2fd52
MR		 2562017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
257 Maciej W. Rozycki <macro@imgtec.com>
258
259 * micromips-opc.c (I36): New macro.
260 (micromips_opcodes): Add "eretnc".
261
9785fc2a
MR		 2622017-06-30 Maciej W. Rozycki <macro@imgtec.com>
263 Andrew Bennett <andrew.bennett@imgtec.com>
264
265 * mips-dis.c (mips_calculate_combination_ases): Handle the
266 ASE_XPA_VIRT flag.
267 (parse_mips_ase_option): New function.
268 (parse_mips_dis_option): Factor out ASE option handling to the
269 new function. Call `mips_calculate_combination_ases'.
270 * mips-opc.c (XPAVZ): New macro.
271 (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
272 "mfhgc0", "mthc0" and "mthgc0".
273
60804c53
MR		 2742017-06-29 Maciej W. Rozycki <macro@imgtec.com>
275
276 * mips-dis.c (mips_calculate_combination_ases): New function.
277 (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
278 calculation to the new function.
279 (set_default_mips_dis_options): Call the new function.
280
2e74f9dd
AK		 2812017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
282
283 * arc-dis.c (parse_disassembler_options): Use
284 FOR_EACH_DISASSEMBLER_OPTION.
285
e1e94c49
AK		 2862017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
287
288 * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
289 disassembler option strings.
290 (parse_cpu_option): Likewise.
291
65a55fbb
TC		 2922017-06-28 Tamar Christina <tamar.christina@arm.com>
293
294 * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
295 * aarch64-dis.c (aarch64_ext_reglane): Likewise.
296 * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
297 (aarch64_feature_dotprod, DOT_INSN): New.
298 (udot, sdot): New.
299 * aarch64-dis-2.c: Regenerated.
300
c604a79a
JW		 3012017-06-28 Jiong Wang <jiong.wang@arm.com>
302
303 * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
304
38bf472a
MR		 3052017-06-28 Maciej W. Rozycki <macro@imgtec.com>
306 Matthew Fortune <matthew.fortune@imgtec.com>
4151f684 307 Andrew Bennett <andrew.bennett@imgtec.com>
38bf472a
MR		 308
309 * mips-formats.h (INT_BIAS): New macro.
310 (INT_ADJ): Redefine in INT_BIAS terms.
311 * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
312 (mips_print_save_restore): New function.
313 (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
314 (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
315 call.
316 (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
317 (print_mips16_insn_arg): Call `mips_print_save_restore' for
318 OP_SAVE_RESTORE_LIST handling, factored out from here.
319 * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
320 (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
321 (mips_builtin_opcodes): Add "restore" and "save" entries.
322 * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
323 (IAMR2): New macro.
324 (mips16_opcodes): Add "copyw" and "ucopyw" entries.
325
9bdfdbf9
AW		 3262017-06-23 Andrew Waterman <andrew@sifive.com>
327
328 * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
329 alias; do not mark SLTI instruction as an alias.
330
2234eee6
L		 3312017-06-21 H.J. Lu <hongjiu.lu@intel.com>
332
333 * i386-dis.c (RM_0FAE_REG_5): Removed.
334 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
335 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
336 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
337 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
338 PREFIX_MOD_3_0F01_REG_5_RM_0.
339 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
340 PREFIX_MOD_3_0FAE_REG_5.
341 (mod_table): Update MOD_0FAE_REG_5.
342 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
343 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
344 * i386-tbl.h: Regenerated.
345
c2f76402
L		 3462017-06-21 H.J. Lu <hongjiu.lu@intel.com>
347
348 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
349 * i386-opc.tbl: Likewise.
350 * i386-tbl.h: Regenerated.
351
9fef80d6
L		 3522017-06-21 H.J. Lu <hongjiu.lu@intel.com>
353
354 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
355 and "jmp{&|}".
356 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
357 prefix.
358
0f6d864d
NC		 3592017-06-19 Nick Clifton <nickc@redhat.com>
360
361 PR binutils/21614
362 * score-dis.c (score_opcodes): Add sentinel.
363
e197589b
AM		 3642017-06-16 Alan Modra <amodra@gmail.com>
365
366 * rx-decode.c: Regenerate.
367
0d96e4df
L		 3682017-06-15 H.J. Lu <hongjiu.lu@intel.com>
369
370 PR binutils/21594
371 * i386-dis.c (OP_E_register): Check valid bnd register.
372 (OP_G): Likewise.
373
cd3ea7c6
NC		 3742017-06-15 Nick Clifton <nickc@redhat.com>
375
376 PR binutils/21595
377 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
378 range value.
379
63323b5b
NC		 3802017-06-15 Nick Clifton <nickc@redhat.com>
381
382 PR binutils/21588
383 * rl78-decode.opc (OP_BUF_LEN): Define.
384 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
385 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
386 array.
387 * rl78-decode.c: Regenerate.
388
08c7881b
NC		 3892017-06-15 Nick Clifton <nickc@redhat.com>
390
391 PR binutils/21586
392 * bfin-dis.c (gregs): Clip index to prevent overflow.
393 (regs): Likewise.
394 (regs_lo): Likewise.
395 (regs_hi): Likewise.
396
e64519d1
NC		 3972017-06-14 Nick Clifton <nickc@redhat.com>
398
399 PR binutils/21576
400 * score7-dis.c (score_opcodes): Add sentinel.
401
6394c606
YQ		 4022017-06-14 Yao Qi <yao.qi@linaro.org>
403
404 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
405 * arm-dis.c: Likewise.
406 * ia64-dis.c: Likewise.
407 * mips-dis.c: Likewise.
408 * spu-dis.c: Likewise.
409 * disassemble.h (print_insn_aarch64): New declaration, moved from
410 include/dis-asm.h.
411 (print_insn_big_arm, print_insn_big_mips): Likewise.
412 (print_insn_i386, print_insn_ia64): Likewise.
413 (print_insn_little_arm, print_insn_little_mips): Likewise.
414
db5fa770
NC		 4152017-06-14 Nick Clifton <nickc@redhat.com>
416
417 PR binutils/21587
418 * rx-decode.opc: Include libiberty.h
419 (GET_SCALE): New macro - validates access to SCALE array.
420 (GET_PSCALE): New macro - validates access to PSCALE array.
421 (DIs, SIs, S2Is, rx_disp): Use new macros.
422 * rx-decode.c: Regenerate.
423
05c966f3
AV		 4242017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
425
426 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
427
10045478
AK		 4282017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
429
430 * arc-dis.c (enforced_isa_mask): Declare.
431 (cpu_types): Likewise.
432 (parse_cpu_option): New function.
433 (parse_disassembler_options): Use it.
434 (print_insn_arc): Use enforced_isa_mask.
435 (print_arc_disassembler_options): Document new options.
436
88c1242d
YQ		 4372017-05-24 Yao Qi <yao.qi@linaro.org>
438
439 * alpha-dis.c: Include disassemble.h, don't include
440 dis-asm.h.
441 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
442 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
443 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
444 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
445 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
446 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
447 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
448 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
449 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
450 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
451 * moxie-dis.c, msp430-dis.c, mt-dis.c:
452 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
453 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
454 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
455 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
456 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
457 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
458 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
459 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
460 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
461 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
462 * z80-dis.c, z8k-dis.c: Likewise.
463 * disassemble.h: New file.
464
ab20fa4a
YQ		 4652017-05-24 Yao Qi <yao.qi@linaro.org>
466
467 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
468 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
469
003ca0fd
YQ		 4702017-05-24 Yao Qi <yao.qi@linaro.org>
471
472 * disassemble.c (disassembler): Add arguments a, big and mach.
473 Use them.
474
04ef582a
L		 4752017-05-22 H.J. Lu <hongjiu.lu@intel.com>
476
477 * i386-dis.c (NOTRACK_Fixup): New.
478 (NOTRACK): Likewise.
479 (NOTRACK_PREFIX): Likewise.
480 (last_active_prefix): Likewise.
481 (reg_table): Use NOTRACK on indirect call and jmp.
482 (ckprefix): Set last_active_prefix.
483 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
484 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
485 * i386-opc.h (NoTrackPrefixOk): New.
486 (i386_opcode_modifier): Add notrackprefixok.
487 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
488 Add notrack.
489 * i386-tbl.h: Regenerated.
490
64517994
JM		 4912017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
492
493 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
494 (X_IMM2): Define.
495 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
496 bfd_mach_sparc_v9m8.
497 (print_insn_sparc): Handle new operand types.
498 * sparc-opc.c (MASK_M8): Define.
499 (v6): Add MASK_M8.
500 (v6notlet): Likewise.
501 (v7): Likewise.
502 (v8): Likewise.
503 (v9): Likewise.
504 (v9a): Likewise.
505 (v9b): Likewise.
506 (v9c): Likewise.
507 (v9d): Likewise.
508 (v9e): Likewise.
509 (v9v): Likewise.
510 (v9m): Likewise.
511 (v9andleon): Likewise.
512 (m8): Define.
513 (HWS_VM8): Define.
514 (HWS2_VM8): Likewise.
515 (sparc_opcode_archs): Add entry for "m8".
516 (sparc_opcodes): Add OSA2017 and M8 instructions
517 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
518 fpx{ll,ra,rl}64x,
519 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
520 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
521 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
522 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
523 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
524 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
525 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
526 ASI_CORE_SELECT_COMMIT_NHT.
527
535b785f
AM		 5282017-05-18 Alan Modra <amodra@gmail.com>
529
530 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
531 * aarch64-dis.c: Likewise.
532 * aarch64-gen.c: Likewise.
533 * aarch64-opc.c: Likewise.
534
25499ac7
MR		 5352017-05-15 Maciej W. Rozycki <macro@imgtec.com>
536 Matthew Fortune <matthew.fortune@imgtec.com>
537
538 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
539 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
540 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
541 (print_insn_arg) <OP_REG28>: Add handler.
542 (validate_insn_args) <OP_REG28>: Handle.
543 (print_mips16_insn_arg): Handle MIPS16 instructions that require
544 32-bit encoding and 9-bit immediates.
545 (print_insn_mips16): Handle MIPS16 instructions that require
546 32-bit encoding and MFC0/MTC0 operand decoding.
547 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
548 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
549 (RD_C0, WR_C0, E2, E2MT): New macros.
550 (mips16_opcodes): Add entries for MIPS16e2 instructions:
551 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
552 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
553 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
554 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
555 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
556 instructions, "swl", "swr", "sync" and its "sync_acquire",
557 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
558 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
559 regular/extended entries for original MIPS16 ISA revision
560 instructions whose extended forms are subdecoded in the MIPS16e2
561 ISA revision: "li", "sll" and "srl".
562
fdfb4752
MR		 5632017-05-15 Maciej W. Rozycki <macro@imgtec.com>
564
565 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
566 reference in CP0 move operand decoding.
567
a4f89915
MR		 5682017-05-12 Maciej W. Rozycki <macro@imgtec.com>
569
570 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
571 type to hexadecimal.
572 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
573
99e2d67a
MR		 5742017-05-11 Maciej W. Rozycki <macro@imgtec.com>
575
576 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
577 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
578 "sync_rmb" and "sync_wmb" as aliases.
579 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
580 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
581
53a346d8
CZ		 5822017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
583
584 * arc-dis.c (parse_option): Update quarkse_em option..
585 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
586 QUARKSE1.
587 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
588
f91d48de
KC		 5892017-05-03 Kito Cheng <kito.cheng@gmail.com>
590
591 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
592
43e379d7
MC		 5932017-05-01 Michael Clark <michaeljclark@mac.com>
594
595 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
596 register.
597
a4ddc54e
MR		 5982017-05-02 Maciej W. Rozycki <macro@imgtec.com>
599
600 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
601 and branches and not synthetic data instructions.
602
fe50e98c
BE		 6032017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
604
605 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
606
126124cc
CZ		 6072017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
608
609 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
610 * arc-opc.c (insert_r13el): New function.
611 (R13_EL): Define.
612 * arc-tbl.h: Add new enter/leave variants.
613
be6a24d8
CZ		 6142017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
615
616 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
617
0348fd79
MR		 6182017-04-25 Maciej W. Rozycki <macro@imgtec.com>
619
620 * mips-dis.c (print_mips_disassembler_options): Add
621 `no-aliases'.
622
6e3d1f07
MR		 6232017-04-25 Maciej W. Rozycki <macro@imgtec.com>
624
625 * mips16-opc.c (AL): New macro.
626 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
627 of "ld" and "lw" as aliases.
628
957f6b39
TC		 6292017-04-24 Tamar Christina <tamar.christina@arm.com>
630
631 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
632 arguments.
633
a8cc8a54
AM		 6342017-04-22 Alexander Fedotov <alfedotov@gmail.com>
635 Alan Modra <amodra@gmail.com>
636
637 * ppc-opc.c (ELEV): Define.
638 (vle_opcodes): Add se_rfgi and e_sc.
639 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
640 for E200Z4.
641
3ab87b68
JM		 6422017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
643
644 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
645
792f174f
NC		 6462017-04-21 Nick Clifton <nickc@redhat.com>
647
648 PR binutils/21380
649 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
650 LD3R and LD4R.
651
42742084
AM		 6522017-04-13 Alan Modra <amodra@gmail.com>
653
654 * epiphany-desc.c: Regenerate.
655 * fr30-desc.c: Regenerate.
656 * frv-desc.c: Regenerate.
657 * ip2k-desc.c: Regenerate.
658 * iq2000-desc.c: Regenerate.
659 * lm32-desc.c: Regenerate.
660 * m32c-desc.c: Regenerate.
661 * m32r-desc.c: Regenerate.
662 * mep-desc.c: Regenerate.
663 * mt-desc.c: Regenerate.
664 * or1k-desc.c: Regenerate.
665 * xc16x-desc.c: Regenerate.
666 * xstormy16-desc.c: Regenerate.
667
9a85b496
AM		 6682017-04-11 Alan Modra <amodra@gmail.com>
669
ef85eab0 670 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
c03dc33b
AM		 671 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
672 PPC_OPCODE_TMR for e6500.
9a85b496
AM		 673 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
674 (PPCVEC3): Define as PPC_OPCODE_POWER9.
9570835e
AM		 675 (PPCVSX2): Define as PPC_OPCODE_POWER8.
676 (PPCVSX3): Define as PPC_OPCODE_POWER9.
ef85eab0 677 (PPCHTM): Define as PPC_OPCODE_POWER8.
c03dc33b 678 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
9a85b496 679
62adc510
AM		 6802017-04-10 Alan Modra <amodra@gmail.com>
681
682 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
683 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
684 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
685 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
686
aa808707
PC		 6872017-04-09 Pip Cet <pipcet@gmail.com>
688
689 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
690 appropriate floating-point precision directly.
691
ac8f0f72
AM		 6922017-04-07 Alan Modra <amodra@gmail.com>
693
694 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
695 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
696 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
697 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
698 vector instructions with E6500 not PPCVEC2.
699
62ecb94c
PC		 7002017-04-06 Pip Cet <pipcet@gmail.com>
701
702 * Makefile.am: Add wasm32-dis.c.
703 * configure.ac: Add wasm32-dis.c to wasm32 target.
704 * disassemble.c: Add wasm32 disassembler code.
705 * wasm32-dis.c: New file.
706 * Makefile.in: Regenerate.
707 * configure: Regenerate.
708 * po/POTFILES.in: Regenerate.
709 * po/opcodes.pot: Regenerate.
710
f995bbe8
PA		 7112017-04-05 Pedro Alves <palves@redhat.com>
712
713 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
714 * arm-dis.c (parse_arm_disassembler_options): Constify.
715 * ppc-dis.c (powerpc_init_dialect): Constify local.
716 * vax-dis.c (parse_disassembler_options): Constify.
717
b5292032
PD		 7182017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
719
720 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
721 RISCV_GP_SYMBOL.
722
f96bd6c2
PC		 7232017-03-30 Pip Cet <pipcet@gmail.com>
724
725 * configure.ac: Add (empty) bfd_wasm32_arch target.
726 * configure: Regenerate
727 * po/opcodes.pot: Regenerate.
728
f7c514a3
JM		 7292017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
730
731 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
732 OSA2015.
733 * opcodes/sparc-opc.c (asi_table): New ASIs.
734
52be03fd
AM		 7352017-03-29 Alan Modra <amodra@gmail.com>
736
737 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
738 "raw" option.
739 (lookup_powerpc): Don't special case -1 dialect. Handle
740 PPC_OPCODE_RAW.
741 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
742 lookup_powerpc call, pass it on second.
743
9b753937
AM		 7442017-03-27 Alan Modra <amodra@gmail.com>
745
746 PR 21303
747 * ppc-dis.c (struct ppc_mopt): Comment.
748 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
749
c0c31e91
RZ		 7502017-03-27 Rinat Zelig <rinat@mellanox.com>
751
752 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
753 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
754 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
755 (insert_nps_misc_imm_offset): New function.
756 (extract_nps_misc imm_offset): New function.
757 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
758 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
759
2253c8f0
AK		 7602017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
761
762 * s390-mkopc.c (main): Remove vx2 check.
763 * s390-opc.txt: Remove vx2 instruction flags.
764
645d3342
RZ		 7652017-03-21 Rinat Zelig <rinat@mellanox.com>
766
767 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
768 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
769 (insert_nps_imm_offset): New function.
770 (extract_nps_imm_offset): New function.
771 (insert_nps_imm_entry): New function.
772 (extract_nps_imm_entry): New function.
773
4b94dd2d
AM		 7742017-03-17 Alan Modra <amodra@gmail.com>
775
776 PR 21248
777 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
778 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
779 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
780
b416fe87
KC		 7812017-03-14 Kito Cheng <kito.cheng@gmail.com>
782
783 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
784 <c.andi>: Likewise.
785 <c.addiw> Likewise.
786
03b039a5
KC		 7872017-03-14 Kito Cheng <kito.cheng@gmail.com>
788
789 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
790
2c232b83
AW		 7912017-03-13 Andrew Waterman <andrew@sifive.com>
792
793 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
794 <srl> Likewise.
795 <srai> Likewise.
796 <sra> Likewise.
797
86fa6981
L		 7982017-03-09 H.J. Lu <hongjiu.lu@intel.com>
799
800 * i386-gen.c (opcode_modifiers): Replace S with Load.
801 * i386-opc.h (S): Removed.
802 (Load): New.
803 (i386_opcode_modifier): Replace s with load.
804 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
805 and {evex}. Replace S with Load.
806 * i386-tbl.h: Regenerated.
807
c1fe188b
L		 8082017-03-09 H.J. Lu <hongjiu.lu@intel.com>
809
810 * i386-opc.tbl: Use CpuCET on rdsspq.
811 * i386-tbl.h: Regenerated.
812
4b8b687e
PB		 8132017-03-08 Peter Bergner <bergner@vnet.ibm.com>
814
815 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
816 <vsx>: Do not use PPC_OPCODE_VSX3;
817
1437d063
PB		 8182017-03-08 Peter Bergner <bergner@vnet.ibm.com>
819
820 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
821
603555e5
L		 8222017-03-06 H.J. Lu <hongjiu.lu@intel.com>
823
824 * i386-dis.c (REG_0F1E_MOD_3): New enum.
825 (MOD_0F1E_PREFIX_1): Likewise.
826 (MOD_0F38F5_PREFIX_2): Likewise.
827 (MOD_0F38F6_PREFIX_0): Likewise.
828 (RM_0F1E_MOD_3_REG_7): Likewise.
829 (PREFIX_MOD_0_0F01_REG_5): Likewise.
830 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
831 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
832 (PREFIX_0F1E): Likewise.
833 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
834 (PREFIX_0F38F5): Likewise.
835 (dis386_twobyte): Use PREFIX_0F1E.
836 (reg_table): Add REG_0F1E_MOD_3.
837 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
838 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
839 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
840 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
841 (three_byte_table): Use PREFIX_0F38F5.
842 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
843 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
844 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
845 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
846 PREFIX_MOD_3_0F01_REG_5_RM_2.
847 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
848 (cpu_flags): Add CpuCET.
849 * i386-opc.h (CpuCET): New enum.
850 (CpuUnused): Commented out.
851 (i386_cpu_flags): Add cpucet.
852 * i386-opc.tbl: Add Intel CET instructions.
853 * i386-init.h: Regenerated.
854 * i386-tbl.h: Likewise.
855
73f07bff
AM		 8562017-03-06 Alan Modra <amodra@gmail.com>
857
858 PR 21124
859 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
860 (extract_raq, extract_ras, extract_rbx): New functions.
861 (powerpc_operands): Use opposite corresponding insert function.
862 (Q_MASK): Define.
863 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
864 register restriction.
865
65b48a81
PB		 8662017-02-28 Peter Bergner <bergner@vnet.ibm.com>
867
868 * disassemble.c Include "safe-ctype.h".
869 (disassemble_init_for_target): Handle s390 init.
870 (remove_whitespace_and_extra_commas): New function.
871 (disassembler_options_cmp): Likewise.
872 * arm-dis.c: Include "libiberty.h".
873 (NUM_ELEM): Delete.
874 (regnames): Use long disassembler style names.
875 Add force-thumb and no-force-thumb options.
876 (NUM_ARM_REGNAMES): Rename from this...
877 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
878 (get_arm_regname_num_options): Delete.
879 (set_arm_regname_option): Likewise.
880 (get_arm_regnames): Likewise.
881 (parse_disassembler_options): Likewise.
882 (parse_arm_disassembler_option): Rename from this...
883 (parse_arm_disassembler_options): ...to this. Make static.
884 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
885 (print_insn): Use parse_arm_disassembler_options.
886 (disassembler_options_arm): New function.
887 (print_arm_disassembler_options): Handle updated regnames.
888 * ppc-dis.c: Include "libiberty.h".
889 (ppc_opts): Add "32" and "64" entries.
890 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
891 (powerpc_init_dialect): Add break to switch statement.
892 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
893 (disassembler_options_powerpc): New function.
894 (print_ppc_disassembler_options): Use ARRAY_SIZE.
895 Remove printing of "32" and "64".
896 * s390-dis.c: Include "libiberty.h".
897 (init_flag): Remove unneeded variable.
898 (struct s390_options_t): New structure type.
899 (options): New structure.
900 (init_disasm): Rename from this...
901 (disassemble_init_s390): ...to this. Add initializations for
902 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
903 (print_insn_s390): Delete call to init_disasm.
904 (disassembler_options_s390): New function.
905 (print_s390_disassembler_options): Print using information from
906 struct 'options'.
907 * po/opcodes.pot: Regenerate.
908
15c7c1d8
JB		 9092017-02-28 Jan Beulich <jbeulich@suse.com>
910
911 * i386-dis.c (PCMPESTR_Fixup): New.
912 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
913 (prefix_table): Use PCMPESTR_Fixup.
914 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
915 PCMPESTR_Fixup.
916 (vex_w_table): Delete VPCMPESTR{I,M} entries.
917 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
918 Split 64-bit and non-64-bit variants.
919 * opcodes/i386-tbl.h: Re-generate.
920
582e12bf
RS		 9212017-02-24 Richard Sandiford <richard.sandiford@arm.com>
922
923 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
924 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
925 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
926 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
927 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
928 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
929 (OP_SVE_V_HSD): New macros.
930 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
931 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
932 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
933 (aarch64_opcode_table): Add new SVE instructions.
934 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
935 for rotation operands. Add new SVE operands.
936 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
937 (ins_sve_quad_index): Likewise.
938 (ins_imm_rotate): Split into...
939 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
940 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
941 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
942 functions.
943 (aarch64_ins_sve_addr_ri_s4): New function.
944 (aarch64_ins_sve_quad_index): Likewise.
945 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
946 * aarch64-asm-2.c: Regenerate.
947 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
948 (ext_sve_quad_index): Likewise.
949 (ext_imm_rotate): Split into...
950 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
951 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
952 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
953 functions.
954 (aarch64_ext_sve_addr_ri_s4): New function.
955 (aarch64_ext_sve_quad_index): Likewise.
956 (aarch64_ext_sve_index): Allow quad indices.
957 (do_misc_decoding): Likewise.
958 * aarch64-dis-2.c: Regenerate.
959 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
960 aarch64_field_kinds.
961 (OPD_F_OD_MASK): Widen by one bit.
962 (OPD_F_NO_ZR): Bump accordingly.
963 (get_operand_field_width): New function.
964 * aarch64-opc.c (fields): Add new SVE fields.
965 (operand_general_constraint_met_p): Handle new SVE operands.
966 (aarch64_print_operand): Likewise.
967 * aarch64-opc-2.c: Regenerate.
968
f482d304
RS		 9692017-02-24 Richard Sandiford <richard.sandiford@arm.com>
970
971 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
972 (aarch64_feature_compnum): ...this.
973 (SIMD_V8_3): Replace with...
974 (COMPNUM): ...this.
975 (CNUM_INSN): New macro.
976 (aarch64_opcode_table): Use it for the complex number instructions.
977
7db2c588
JB		 9782017-02-24 Jan Beulich <jbeulich@suse.com>
979
980 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
981
1e9d41d4
SL		 9822017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
983
984 Add support for associating SPARC ASIs with an architecture level.
985 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
986 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
987 decoding of SPARC ASIs.
988
53c4d625
JB		 9892017-02-23 Jan Beulich <jbeulich@suse.com>
990
991 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
992 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
993
11648de5
JB		 9942017-02-21 Jan Beulich <jbeulich@suse.com>
995
996 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
997 1 (instead of to itself). Correct typo.
998
f98d33be
AW		 9992017-02-14 Andrew Waterman <andrew@sifive.com>
1000
1001 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1002 pseudoinstructions.
1003
773fb663
RS		 10042017-02-15 Richard Sandiford <richard.sandiford@arm.com>
1005
1006 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1007 (aarch64_sys_reg_supported_p): Handle them.
1008
cc07cda6
CZ		 10092017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
1010
1011 * arc-opc.c (UIMM6_20R): Define.
1012 (SIMM12_20): Use above.
1013 (SIMM12_20R): Define.
1014 (SIMM3_5_S): Use above.
1015 (UIMM7_A32_11R_S): Define.
1016 (UIMM7_9_S): Use above.
1017 (UIMM3_13R_S): Define.
1018 (SIMM11_A32_7_S): Use above.
1019 (SIMM9_8R): Define.
1020 (UIMM10_A32_8_S): Use above.
1021 (UIMM8_8R_S): Define.
1022 (W6): Use above.
1023 (arc_relax_opcodes): Use all above defines.
1024
66a5a740
VG		 10252017-02-15 Vineet Gupta <vgupta@synopsys.com>
1026
1027 * arc-regs.h: Distinguish some of the registers different on
1028 ARC700 and HS38 cpus.
1029
7e0de605
AM		 10302017-02-14 Alan Modra <amodra@gmail.com>
1031
1032 PR 21118
1033 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1034 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
1035
54064fdb
AM		 10362017-02-11 Stafford Horne <shorne@gmail.com>
1037 Alan Modra <amodra@gmail.com>
1038
1039 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1040 Use insn_bytes_value and insn_int_value directly instead. Don't
1041 free allocated memory until function exit.
1042
dce75bf9
NP		 10432017-02-10 Nicholas Piggin <npiggin@gmail.com>
1044
1045 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1046
1b7e3d2f
NC		 10472017-02-03 Nick Clifton <nickc@redhat.com>
1048
1049 PR 21096
1050 * aarch64-opc.c (print_register_list): Ensure that the register
1051 list index will fir into the tb buffer.
1052 (print_register_offset_address): Likewise.
1053 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1054
8ec5cf65
AD		 10552017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
1056
1057 PR 21056
1058 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1059 instructions when the previous fetch packet ends with a 32-bit
1060 instruction.
1061
a1aa5e81
DD		 10622017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
1063
1064 * pru-opc.c: Remove vague reference to a future GDB port.
1065
add3afb2
NC		 10662017-01-20 Nick Clifton <nickc@redhat.com>
1067
1068 * po/ga.po: Updated Irish translation.
1069
c13a63b0
SN		 10702017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
1071
1072 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1073
9608051a
YQ		 10742017-01-13 Yao Qi <yao.qi@linaro.org>
1075
1076 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
1077 if FETCH_DATA returns 0.
1078 (m68k_scan_mask): Likewise.
1079 (print_insn_m68k): Update code to handle -1 return value.
1080
f622ea96
YQ		 10812017-01-13 Yao Qi <yao.qi@linaro.org>
1082
1083 * m68k-dis.c (enum print_insn_arg_error): New.
1084 (NEXTBYTE): Replace -3 with
1085 PRINT_INSN_ARG_MEMORY_ERROR.
1086 (NEXTULONG): Likewise.
1087 (NEXTSINGLE): Likewise.
1088 (NEXTDOUBLE): Likewise.
1089 (NEXTDOUBLE): Likewise.
1090 (NEXTPACKED): Likewise.
1091 (FETCH_ARG): Likewise.
1092 (FETCH_DATA): Update comments.
1093 (print_insn_arg): Update comments. Replace magic numbers with
1094 enum.
1095 (match_insn_m68k): Likewise.
1096
620214f7
IT		 10972017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1098
1099 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1100 * i386-dis-evex.h (evex_table): Updated.
1101 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1102 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1103 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1104 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1105 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1106 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1107 * i386-init.h: Regenerate.
1108 * i386-tbl.h: Ditto.
1109
d95014a2
YQ		 11102017-01-12 Yao Qi <yao.qi@linaro.org>
1111
1112 * msp430-dis.c (msp430_singleoperand): Return -1 if
1113 msp430dis_opcode_signed returns false.
1114 (msp430_doubleoperand): Likewise.
1115 (msp430_branchinstr): Return -1 if
1116 msp430dis_opcode_unsigned returns false.
1117 (msp430x_calla_instr): Likewise.
1118 (print_insn_msp430): Likewise.
1119
0ae60c3e
NC		 11202017-01-05 Nick Clifton <nickc@redhat.com>
1121
1122 PR 20946
1123 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1124 could not be matched.
1125 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1126 NULL.
1127
d74d4880
SN		 11282017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
1129
1130 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1131 (aarch64_opcode_table): Use RCPC_INSN.
1132
cc917fd9
KC		 11332017-01-03 Kito Cheng <kito.cheng@gmail.com>
1134
1135 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1136 extension.
1137 * riscv-opcodes/all-opcodes: Likewise.
1138
b52d3cfc
DP		 11392017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
1140
1141 * riscv-dis.c (print_insn_args): Add fall through comment.
1142
f90c58d5
NC		 11432017-01-03 Nick Clifton <nickc@redhat.com>
1144
1145 * po/sr.po: New Serbian translation.
1146 * configure.ac (ALL_LINGUAS): Add sr.
1147 * configure: Regenerate.
1148
f47b0d4a
AM		 11492017-01-02 Alan Modra <amodra@gmail.com>
1150
1151 * epiphany-desc.h: Regenerate.
1152 * epiphany-opc.h: Regenerate.
1153 * fr30-desc.h: Regenerate.
1154 * fr30-opc.h: Regenerate.
1155 * frv-desc.h: Regenerate.
1156 * frv-opc.h: Regenerate.
1157 * ip2k-desc.h: Regenerate.
1158 * ip2k-opc.h: Regenerate.
1159 * iq2000-desc.h: Regenerate.
1160 * iq2000-opc.h: Regenerate.
1161 * lm32-desc.h: Regenerate.
1162 * lm32-opc.h: Regenerate.
1163 * m32c-desc.h: Regenerate.
1164 * m32c-opc.h: Regenerate.
1165 * m32r-desc.h: Regenerate.
1166 * m32r-opc.h: Regenerate.
1167 * mep-desc.h: Regenerate.
1168 * mep-opc.h: Regenerate.
1169 * mt-desc.h: Regenerate.
1170 * mt-opc.h: Regenerate.
1171 * or1k-desc.h: Regenerate.
1172 * or1k-opc.h: Regenerate.
1173 * xc16x-desc.h: Regenerate.
1174 * xc16x-opc.h: Regenerate.
1175 * xstormy16-desc.h: Regenerate.
1176 * xstormy16-opc.h: Regenerate.
1177
2571583a
AM		 11782017-01-02 Alan Modra <amodra@gmail.com>
1179
1180 Update year range in copyright notice of all files.
1181
5c1ad6b5 1182For older changes see ChangeLog-2016
3499769a 1183\f
5c1ad6b5 1184Copyright (C) 2017 Free Software Foundation, Inc.
3499769a
AM		 1185
1186Copying and distribution of this file, with or without modification,
1187are permitted in any medium without royalty provided the copyright
1188notice and this notice are preserved.
1189
1190Local Variables:
1191mode: change-log
1192left-margin: 8
1193fill-column: 74
1194version-control: never
1195End:
GDB Binutils - Deliverables
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