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[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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19590ef7
RE		 12005-10-08 James Lemke <jim@wasabisystems.com>
2
3 * arm-dis.c (coprocessor_opcodes): Fix mask for various Maverick CDP
4 operations.
5
6edfbbad
DJ		 62005-10-06 Daniel Jacobowitz <dan@codesourcery.com>
7
8 * ppc-dis.c (struct dis_private): Remove.
9 (powerpc_dialect): Avoid aliasing warnings.
10 (print_insn_big_powerpc, print_insn_little_powerpc): Likewise.
11
095f2843
NC		 122005-09-30 Nick Clifton <nickc@redhat.com>
13
14 * po/ga.po: New Irish translation.
15 * configure.in (ALL_LINGUAS): Add "ga".
16 * configure: Regenerate.
17
fdd3b9b3
L		 182005-09-30 H.J. Lu <hongjiu.lu@intel.com>
19
20 * Makefile.am: Run "make dep-am".
21 * Makefile.in: Regenerated.
22 * aclocal.m4: Likewise.
23 * configure: Likewise.
24
4b7f6baa
CM		 252005-09-30 Catherine Moore <clm@cm00re.com>
26
27 * Makefile.am: Bfin support.
28 * Makefile.in: Regenerated.
29 * aclocal.m4: Regenerated.
30 * bfin-dis.c: New file.
31 * configure.in: Bfin support.
32 * configure: Regenerated.
33 * disassemble.c (ARCH_bfin): Define.
34 (disassembler): Add case for bfd_arch_bfin.
35
1a114b12
JB		 362005-09-28 Jan Beulich <jbeulich@novell.com>
37
38 * i386-dis.c (stack_v_mode): Renamed from branch_v_mode.
39 (indirEv): Use it.
40 (stackEv): New.
41 (Ob64, Ov64): Rename to Ob, Ov. Delete unused original definitions.
42 (dis386): Document and use new 'V' meta character. Use it for
43 single-byte push/pop opcode forms. Use stackEv for mod-r/m push/pop
44 opcode forms. Correct typo in 'pop ss'. Replace Ob64/Ov64 by Ob/Ov.
45 (putop): 'q' suffix for 'T' and 'U' meta depends on DFLAG. Mark
46 data prefix as used whenever DFLAG was examined. Handle 'V'.
47 (intel_operand_size): Use stack_v_mode.
48 (OP_E): Use stack_v_mode, but handle only the special case of
49 64-bit mode without operand size override here; fall through to
50 v_mode case otherwise.
51 (OP_REG): Special case rAX_reg ... rDI_reg only when 64-bit mode
52 and no operand size override is present.
53 (OP_J): Use get32s for obtaining the displacement also when rex64
54 is present.
55
3eb17e6b
PB		 562005-09-08 Paul Brook <paul@codesourcery.com>
57
58 * arm-dis.c (arm_opcodes, thumb32_opcodes): Rename smi to smc.
59
61cc0267
CF		 602005-09-06 Chao-ying Fu <fu@mips.com>
61
62 * mips-opc.c (MT32): New define.
63 (mips_builtin_opcodes): Move "bc0f", "bc0fl", "bc0t", "bc0tl" to the
64 bottom to avoid opcode collision with "mftr" and "mttr".
65 Add MT instructions.
66 * mips-dis.c (mips_arch_choices): Enable INSN_MT for mips32r2.
67 (print_insn_args): Add supports for +t, +T, !, $, *, &, g operand
68 formats.
69
b13dd07a
PB		 702005-09-02 Paul Brook <paul@codesourcery.com>
71
72 * arm-dis.c (coprocessor_opcodes): Add null terminator.
73
8f06b2d8
PB		 742005-09-02 Paul Brook <paul@codesourcery.com>
75
76 * arm-dis.c (coprocessor_opcodes): New.
77 (arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
78 (print_insn_coprocessor): New function.
79 (print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
80 format characters.
81 (print_insn_thumb32): Use print_insn_coprocessor.
82
a2dfd01f
PB		 832005-08-30 Paul Brook <paul@codesourcery.com>
84
85 * arm-dis.c (thumb_opcodes): Disassemble sub(3) as subs.
86
3f31e633
JB		 872005-08-26 Jan Beulich <jbeulich@novell.com>
88
89 * i386-dis.c (intel_operand_size): New, broken out from OP_E for
90 re-use.
91 (OP_E): Call intel_operand_size, move call site out of mode
92 dependent code.
93 (OP_OFF): Call intel_operand_size if suffix_always. Remove
94 ATTRIBUTE_UNUSED from parameters.
95 (OP_OFF64): Likewise.
96 (OP_ESreg): Call intel_operand_size.
97 (OP_DSreg): Likewise.
98 (OP_DIR): Use colon rather than semicolon as separator of far
99 jump/call operands.
100
fd25c5a9
CF		 1012005-08-25 Chao-ying Fu <fu@mips.com>
102
103 * mips-opc.c (WR_a, RD_a, MOD_a, DSP_VOLA, D32): New define.
104 (mips_builtin_opcodes): Add DSP instructions.
105 * mips-dis.c (mips_arch_choices): Enable INSN_DSP for mips32, mips32r2,
106 mips64, mips64r2.
107 (print_insn_args): Add supports for 3, 4, 5, 6, 7, 8, 9, 0, :, ', @
108 operand formats.
109
dd8b7c22
DU		 1102005-08-23 David Ung <davidu@mips.com>
111
112 * mips16-opc.c (mips16_opcodes): Add the MIPS16e jalrc/jrc
113 instructions to the table.
114
c17ae8a2
AM		 1152005-08-18 Alan Modra <amodra@bigpond.net.au>
116
848cf006 117 * a29k-dis.c: Delete.
c17ae8a2
AM		 118 * Makefile.am: Remove a29k support.
119 * configure.in: Likewise.
120 * disassemble.c: Likewise.
121 * Makefile.in: Regenerate.
122 * configure: Regenerate.
123 * po/POTFILES.in: Regenerate.
124
36ae0db3
DJ		 1252005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
126
127 * ppc-dis.c (powerpc_dialect): Handle e300.
128 (print_ppc_disassembler_options): Likewise.
129 * ppc-opc.c (PPCE300): Define.
130 (powerpc_opcodes): Mark icbt as available for the e300.
131
63a3357b
DA		 1322005-08-13 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
133
134 * hppa-dis.c (print_insn_hppa): Don't print '%' before register names.
135 Use "rp" instead of "%r2" in "b,l" insns.
136
ad101263
MS		 1372005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
138
139 * s390-dis.c (print_insn_s390): Print unsigned operands with %u.
140 * s390-mkopc.c (s390_opcode_cpu_val): Add support for cpu type z9-109.
141 (main): Likewise.
142 * s390-opc.c (I32_16, U32_16, M_16): Add defines 32 bit immediates
143 and 4 bit optional masks.
144 (INSTR_RIL_RI, INSTR_RIL_RU, INSTR_RRF_M0RR, INSTR_RSE_CCRD,
145 INSTR_RSY_CCRD, INSTR_SSF_RRDRD): Add new instruction formats.
146 (MASK_RIL_RI, MASK_RIL_RU, MASK_RRF_M0RR, MASK_RSE_CCRD,
147 MASK_RSY_CCRD, MASK_SSF_RRDRD): Likewise.
148 (s390_opformats): Likewise.
149 * s390-opc.txt: Add new instructions for cpu type z9-109.
150
f1fa1093
DA		 1512005-08-05 John David Anglin <dave.anglin@nrc-crnc.gc.ca>
152
153 * hppa-dis.c (print_insn_hppa): Prefix 21-bit values with "L%".
154
e9f89963
PB		 1552005-07-29 Paul Brook <paul@codesourcery.com>
156
157 * arm-dis.c: Fix disassebly of thumb2 writeback addressing modes.
158
92e90b6e
PB		 1592005-07-29 Paul Brook <paul@codesourcery.com>
160
161 * arm-dis.c (thumb32_opc): Fix addressing mode for tbh.
162 (print_insn_thumb32): Fix decoding of thumb2 'I' operands.
163
fd54057a
DD		 1642005-07-25 DJ Delorie <dj@redhat.com>
165
166 * m32c-asm.c Regenerate.
167 * m32c-dis.c Regenerate.
168
760c0f6a
DD		 1692005-07-20 DJ Delorie <dj@redhat.com>
170
171 * disassemble.c (disassemble_init_for_target): M32C ISAs are
172 enums, so convert them to bit masks, which attributes are.
173
85da3a56
NC		 1742005-07-18 Nick Clifton <nickc@redhat.com>
175
176 * configure.in: Restore alpha ordering to list of arches.
177 * configure: Regenerate.
178 * disassemble.c: Restore alpha ordering to list of arches.
179
1802005-07-18 Nick Clifton <nickc@redhat.com>
181
182 * m32c-asm.c: Regenerate.
183 * m32c-desc.c: Regenerate.
184 * m32c-desc.h: Regenerate.
185 * m32c-dis.c: Regenerate.
186 * m32c-ibld.h: Regenerate.
187 * m32c-opc.c: Regenerate.
188 * m32c-opc.h: Regenerate.
189
22cbf2e7
L		 1902005-07-18 H.J. Lu <hongjiu.lu@intel.com>
191
192 * i386-dis.c (PNI_Fixup): Update comment.
193 (VMX_Fixup): Properly handle the suffix check.
194
0aea0460
DA		 1952005-07-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
196
197 * hppa-dis.c (print_insn_hppa): Add space after 'w' in wide-mode
198 mfctl disassembly.
199
0f82ff91
AM		 2002005-07-16 Alan Modra <amodra@bigpond.net.au>
201
202 * Makefile.am: Run "make dep-am".
203 (stamp-m32c): Fix cpu dependencies.
204 * Makefile.in: Regenerate.
205 * ip2k-dis.c: Regenerate.
206
90700ea2
L		 2072007-07-15 H.J. Lu <hongjiu.lu@intel.com>
208
209 * i386-dis.c (OP_VMX): New. Handle Intel VMX Instructions.
210 (VMX_Fixup): New. Fix up Intel VMX Instructions.
211 (Em): New.
212 (Gm): New.
213 (VM): New.
214 (dis386_twobyte): Updated entries 0x78 and 0x79.
215 (twobyte_has_modrm): Likewise.
216 (grps): Use OP_VMX in the "sgdtIQ" entry. Updated GRP9.
217 (OP_G): Handle m_mode.
218
49f58d10
JB		 2192005-07-14 Jim Blandy <jimb@redhat.com>
220
221 Add support for the Renesas M32C and M16C.
222 * m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c, m32c-opc.c: New.
223 * m32c-desc.h, m32c-opc.h: New.
224 * Makefile.am (HFILES): List m32c-desc.h and m32c-opc.h.
225 (CFILES): List m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c,
226 m32c-opc.c.
227 (ALL_MACHINES): List m32c-asm.lo, m32c-desc.lo, m32c-dis.lo,
228 m32c-ibld.lo, m32c-opc.lo.
229 (CLEANFILES): List stamp-m32c.
230 (M32C_DEPS): List stamp-m32c, if CGEN_MAINT.
231 (CGEN_CPUS): Add m32c.
232 (m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c, m32c-opc.c)
233 (m32c-desc.h, m32c-opc.h): Depend on M32C_DEPS.
234 (m32c_opc_h): New variable.
235 (stamp-m32c, m32c-asm.lo, m32c-desc.lo, m32c-dis.lo, m32c-ibld.lo)
236 (m32c-opc.lo): New rules.
237 * Makefile.in: Regenerated.
238 * configure.in: Add case for bfd_m32c_arch.
239 * configure: Regenerated.
240 * disassemble.c (ARCH_m32c): New.
241 [ARCH_m32c]: #include "m32c-desc.h".
242 (disassembler) [ARCH_m32c]: Add case for bfd_arch_m32c.
243 (disassemble_init_for_target) [ARCH_m32c]: Same.
244
245 * cgen-ops.h, cgen-types.h: New files.
246 * Makefile.am (HFILES): List them.
247 * Makefile.in: Regenerated.
248
0fd3a477
JW		 2492005-07-07 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
250
251 * arc-dis.c, arm-dis.c, cris-dis.c, crx-dis.c, d10v-dis.c,
252 d30v-dis.c, fr30-dis.c, h8300-dis.c, h8500-dis.c, i860-dis.c,
253 ia64-dis.c, ip2k-dis.c, m10200-dis.c, m10300-dis.c,
254 m88k-dis.c, mcore-dis.c, mips-dis.c, ms1-dis.c, or32-dis.c,
255 ppc-dis.c, sh64-dis.c, sparc-dis.c, tic4x-dis.c, tic80-dis.c,
256 v850-dis.c: Fix format bugs.
257 * ia64-gen.c (fail, warn): Add format attribute.
258 * or32-opc.c (debug): Likewise.
259
22f8fcbd
NC		 2602005-07-07 Khem Raj <kraj@mvista.com>
261
262 * arm-dis.c (opcode32 arm_opcodes): Fix ARM VFP fadds instruction
263 disassembly pattern.
264
d125c27b
AM		 2652005-07-06 Alan Modra <amodra@bigpond.net.au>
266
267 * Makefile.am (stamp-m32r): Fix path to cpu files.
268 (stamp-m32r, stamp-iq2000): Likewise.
269 * Makefile.in: Regenerate.
270 * m32r-asm.c: Regenerate.
271 * po/POTFILES.in: Remove arm-opc.h. Add ms1-asm.c, ms1-desc.c,
272 ms1-desc.h, ms1-dis.c, ms1-ibld.c, ms1-opc.c, ms1-opc.h.
273
3ec2b351
NC		 2742005-07-05 Nick Clifton <nickc@redhat.com>
275
276 * iq2000-asm.c: Regenerate.
277 * ms1-asm.c: Regenerate.
278
30123838
JB		 2792005-07-05 Jan Beulich <jbeulich@novell.com>
280
281 * i386-dis.c (SVME_Fixup): New.
282 (grps): Use it for the lidt entry.
283 (PNI_Fixup): Call OP_M rather than OP_E.
284 (INVLPG_Fixup): Likewise.
285
b0eec63e
L		 2862005-07-04 H.J. Lu <hongjiu.lu@intel.com>
287
288 * tic30-dis.c (cnvt_tmsfloat_ieee): Use HUGE_VALF if defined.
289
47b0e7ad
NC		 2902005-07-01 Nick Clifton <nickc@redhat.com>
291
292 * a29k-dis.c: Update to ISO C90 style function declarations and
293 fix formatting.
294 * alpha-opc.c: Likewise.
295 * arc-dis.c: Likewise.
296 * arc-opc.c: Likewise.
297 * avr-dis.c: Likewise.
298 * cgen-asm.in: Likewise.
299 * cgen-dis.in: Likewise.
300 * cgen-ibld.in: Likewise.
301 * cgen-opc.c: Likewise.
302 * cris-dis.c: Likewise.
303 * d10v-dis.c: Likewise.
304 * d30v-dis.c: Likewise.
305 * d30v-opc.c: Likewise.
306 * dis-buf.c: Likewise.
307 * dlx-dis.c: Likewise.
308 * h8300-dis.c: Likewise.
309 * h8500-dis.c: Likewise.
310 * hppa-dis.c: Likewise.
311 * i370-dis.c: Likewise.
312 * i370-opc.c: Likewise.
313 * m10200-dis.c: Likewise.
314 * m10300-dis.c: Likewise.
315 * m68k-dis.c: Likewise.
316 * m88k-dis.c: Likewise.
317 * mips-dis.c: Likewise.
318 * mmix-dis.c: Likewise.
319 * msp430-dis.c: Likewise.
320 * ns32k-dis.c: Likewise.
321 * or32-dis.c: Likewise.
322 * or32-opc.c: Likewise.
323 * pdp11-dis.c: Likewise.
324 * pj-dis.c: Likewise.
325 * s390-dis.c: Likewise.
326 * sh-dis.c: Likewise.
327 * sh64-dis.c: Likewise.
328 * sparc-dis.c: Likewise.
329 * sparc-opc.c: Likewise.
330 * sysdep.h: Likewise.
331 * tic30-dis.c: Likewise.
332 * tic4x-dis.c: Likewise.
333 * tic80-dis.c: Likewise.
334 * v850-dis.c: Likewise.
335 * v850-opc.c: Likewise.
336 * vax-dis.c: Likewise.
337 * w65-dis.c: Likewise.
338 * z8kgen.c: Likewise.
339
340 * fr30-*: Regenerate.
341 * frv-*: Regenerate.
342 * ip2k-*: Regenerate.
343 * iq2000-*: Regenerate.
344 * m32r-*: Regenerate.
345 * ms1-*: Regenerate.
346 * openrisc-*: Regenerate.
347 * xstormy16-*: Regenerate.
348
cc16ba8c
BE		 3492005-06-23 Ben Elliston <bje@gnu.org>
350
351 * m68k-dis.c: Use ISC C90.
352 * m68k-opc.c: Formatting fixes.
353
4b185e97
DU		 3542005-06-16 David Ung <davidu@mips.com>
355
356 * mips16-opc.c (mips16_opcodes): Add the following MIPS16e
357 instructions to the table; seb/seh/sew/zeb/zeh/zew.
358
ac188222
DB		 3592005-06-15 Dave Brolley <brolley@redhat.com>
360
361 Contribute Morpho ms1 on behalf of Red Hat
362 * ms1-asm.c, ms1-desc.c, ms1-dis.c, ms1-ibld.c, ms1-opc.c,
363 ms1-opc.h: New files, Morpho ms1 target.
364
365 2004-05-14 Stan Cox <scox@redhat.com>
366
367 * disassemble.c (ARCH_ms1): Define.
368 (disassembler): Handle bfd_arch_ms1
369
370 2004-05-13 Michael Snyder <msnyder@redhat.com>
371
372 * Makefile.am, Makefile.in: Add ms1 target.
373 * configure.in: Ditto.
374
6b5d3a4d
ZW		 3752005-06-08 Zack Weinberg <zack@codesourcery.com>
376
377 * arm-opc.h: Delete; fold contents into ...
378 * arm-dis.c: ... here. Move includes of internal COFF headers
379 next to includes of internal ELF headers.
380 (streq, WORD_ADDRESS, BDISP, BDISP23): Delete, unused.
381 (struct arm_opcode): Rename struct opcode32. Make 'assembler' const.
382 (struct thumb_opcode): Rename struct opcode16. Make 'assembler' const.
383 (arm_conditional, arm_fp_const, arm_shift, arm_regname, regnames)
384 (iwmmxt_wwnames, iwmmxt_wwssnames):
385 Make const.
386 (regnames): Remove iWMMXt coprocessor register sets.
387 (iwmmxt_regnames, iwmmxt_cregnames): New statics.
388 (get_arm_regnames): Adjust fourth argument to match above changes.
389 (set_iwmmxt_regnames): Delete.
390 (print_insn_arm): Constify 'c'. Use ISO syntax for function
391 pointer calls. Expand sole use of BDISP. Use iwmmxt_regnames
392 and iwmmxt_cregnames, not set_iwmmxt_regnames.
393 (print_insn_thumb16, print_insn_thumb32): Constify 'c'. Use
394 ISO syntax for function pointer calls.
395
4a5329c6
ZW		 3962005-06-07 Zack Weinberg <zack@codesourcery.com>
397
398 * arm-dis.c: Split up the comments describing the format codes, so
399 that the ARM and 16-bit Thumb opcode tables each have comments
400 preceding them that describe all the codes, and only the codes,
401 valid in those tables. (32-bit Thumb table is already like this.)
402 Reorder the lists in all three comments to match the order in
403 which the codes are implemented.
404 Remove all forward declarations of static functions. Convert all
405 function definitions to ISO C format.
406 (print_insn_arm, print_insn_thumb16, print_insn_thumb32):
407 Return nothing.
408 (print_insn_thumb16): Remove unused case 'I'.
409 (print_insn): Update for changed calling convention of subroutines.
410
3d456fa1
JB		 4112005-05-25 Jan Beulich <jbeulich@novell.com>
412
413 * i386-dis.c (OP_E): In Intel mode, display 32-bit displacements in
414 hex (but retain it being displayed as signed). Remove redundant
415 checks. Add handling of displacements for 16-bit addressing in Intel
416 mode.
417
2888cb7a
JB		 4182005-05-25 Jan Beulich <jbeulich@novell.com>
419
420 * i386-dis.c (prefix_name): Remove pointless mode_64bit check.
421 (OP_E): Remove redundant REX_EXTZ handling. Remove pointless
422 masking of 'rm' in 16-bit memory address handling.
423
1ed8e1e4
AM		 4242005-05-19 Anton Blanchard <anton@samba.org>
425
426 * ppc-dis.c (powerpc_dialect): Handle "-Mpower5".
427 (print_ppc_disassembler_options): Document it.
428 * ppc-opc.c (SVC_LEV): Define.
429 (LEV): Allow optional operand.
430 (POWER5): Define.
431 (powerpc_opcodes): Extend "sc". Adjust "svc" and "svcl". Add
432 "hrfid", "popcntb", "fsqrtes", "fsqrtes.", "fre" and "fre.".
433
49cc2e69
KC		 4342005-05-19 Kelley Cook <kcook@gcc.gnu.org>
435
436 * Makefile.in: Regenerate.
437
c19d1205
ZW		 4382005-05-17 Zack Weinberg <zack@codesourcery.com>
439
440 * arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
441 instructions. Adjust disassembly of some opcodes to match
442 unified syntax.
443 (thumb32_opcodes): New table.
444 (print_insn_thumb): Rename print_insn_thumb16; don't handle
445 two-halfword branches here.
446 (print_insn_thumb32): New function.
447 (print_insn): Choose among print_insn_arm, print_insn_thumb16,
448 and print_insn_thumb32. Be consistent about order of
449 halfwords when printing 32-bit instructions.
450
003519a7
L		 4512005-05-07 H.J. Lu <hongjiu.lu@intel.com>
452
453 PR 843
454 * i386-dis.c (branch_v_mode): New.
455 (indirEv): Use branch_v_mode instead of v_mode.
456 (OP_E): Handle branch_v_mode.
457
920a34a7
L		 4582005-05-07 H.J. Lu <hongjiu.lu@intel.com>
459
460 * d10v-dis.c (dis_2_short): Support 64bit host.
461
5de773c1
NC		 4622005-05-07 Nick Clifton <nickc@redhat.com>
463
464 * po/nl.po: Updated translation.
465
f4321104
NC		 4662005-05-07 Nick Clifton <nickc@redhat.com>
467
468 * Update the address and phone number of the FSF organization in
469 the GPL notices in the following files:
470 a29k-dis.c, aclocal.m4, alpha-dis.c, alpha-opc.c, arc-dis.c,
471 arc-dis.h, arc-ext.c, arc-ext.h, arc-opc.c, arm-dis.c, arm-opc.h,
472 avr-dis.c, cgen-asm.c, cgen-asm.in, cgen-dis.c, cgen-dis.in,
473 cgen-ibld.in, cgen-opc.c, cgen.sh, cris-dis.c, cris-opc.c,
474 crx-dis.c, crx-opc.c, d10v-dis.c, d10v-opc.c, d30v-dis.c,
475 d30v-opc.c, dis-buf.c, dis-init.c, disassemble.c, dlx-dis.c,
476 fr30-asm.c, fr30-desc.c, fr30-desc.h, fr30-dis.c, fr30-ibld.c,
477 fr30-opc.c, fr30-opc.h, frv-asm.c, frv-desc.c, frv-desc.h,
478 frv-dis.c, frv-ibld.c, frv-opc.c, frv-opc.h, h8300-dis.c,
479 h8500-dis.c, h8500-opc.h, hppa-dis.c, i370-dis.c, i370-opc.c,
480 i386-dis.c, i860-dis.c, i960-dis.c, ia64-asmtab.h, ia64-dis.c,
481 ia64-gen.c, ia64-opc-a.c, ia64-opc-b.c, ia64-opc-d.c,
482 ia64-opc-f.c, ia64-opc-i.c, ia64-opc-m.c, ia64-opc-x.c,
483 ia64-opc.c, ia64-opc.h, ip2k-asm.c, ip2k-desc.c, ip2k-desc.h,
484 ip2k-dis.c, ip2k-ibld.c, ip2k-opc.c, ip2k-opc.h, iq2000-asm.c,
485 iq2000-desc.c, iq2000-desc.h, iq2000-dis.c, iq2000-ibld.c,
486 iq2000-opc.c, iq2000-opc.h, m10200-dis.c, m10200-opc.c,
487 m10300-dis.c, m10300-opc.c, m32r-asm.c, m32r-desc.c, m32r-desc.h,
488 m32r-dis.c, m32r-ibld.c, m32r-opc.c, m32r-opc.h, m32r-opinst.c,
489 m68hc11-dis.c, m68hc11-opc.c, m68k-dis.c, m68k-opc.c, m88k-dis.c,
490 maxq-dis.c, mcore-dis.c, mcore-opc.h, mips-dis.c, mips-opc.c,
491 mips16-opc.c, mmix-dis.c, mmix-opc.c, msp430-dis.c, ns32k-dis.c,
492 openrisc-asm.c, openrisc-desc.c, openrisc-desc.h, openrisc-dis.c,
493 openrisc-ibld.c, openrisc-opc.c, openrisc-opc.h, opintl.h,
494 or32-dis.c, or32-opc.c, pdp11-dis.c, pdp11-opc.c, pj-dis.c,
495 pj-opc.c, ppc-dis.c, ppc-opc.c, s390-dis.c, s390-mkopc.c,
496 s390-opc.c, sh-dis.c, sh-opc.h, sh64-dis.c, sh64-opc.c,
497 sh64-opc.h, sparc-dis.c, sparc-opc.c, sysdep.h, tic30-dis.c,
498 tic4x-dis.c, tic54x-dis.c, tic54x-opc.c, tic80-dis.c, tic80-opc.c,
499 v850-dis.c, v850-opc.c, vax-dis.c, w65-dis.c, w65-opc.h,
500 xstormy16-asm.c, xstormy16-desc.c, xstormy16-desc.h,
501 xstormy16-dis.c, xstormy16-ibld.c, xstormy16-opc.c,
502 xstormy16-opc.h, xtensa-dis.c, z8k-dis.c, z8kgen.c
503
10b076a2
JW		 5042005-05-05 James E Wilson <wilson@specifixinc.com>
505
506 * ia64-opc.c: Include sysdep.h before libiberty.h.
507
022716b6
NC		 5082005-05-05 Nick Clifton <nickc@redhat.com>
509
510 * configure.in (ALL_LINGUAS): Add vi.
511 * configure: Regenerate.
512 * po/vi.po: New.
513
db5152b4
JG		 5142005-04-26 Jerome Guitton <guitton@gnat.com>
515
516 * configure.in: Fix the check for basename declaration.
517 * configure: Regenerate.
518
eed0d89a
AM		 5192005-04-19 Alan Modra <amodra@bigpond.net.au>
520
521 * ppc-opc.c (RTO): Define.
522 (powerpc_opcodes <tlbsx, tlbsx., tlbre>): Combine PPC403 and BOOKE
523 entries to suit PPC440.
524
791fe849
MK		 5252005-04-18 Mark Kettenis <kettenis@gnu.org>
526
527 * i386-dis.c: Insert hyphens into selected VIA PadLock extensions.
528 Add xcrypt-ctr.
529
ffe58f7c
NC		 5302005-04-14 Nick Clifton <nickc@redhat.com>
531
532 * po/fi.po: New translation: Finnish.
533 * configure.in (ALL_LINGUAS): Add fi.
534 * configure: Regenerate.
535
9e9b66a9
AM		 5362005-04-14 Alan Modra <amodra@bigpond.net.au>
537
538 * Makefile.am (NO_WERROR): Define.
539 * configure.in: Invoke AM_BINUTILS_WARNINGS.
540 * Makefile.in: Regenerate.
541 * aclocal.m4: Regenerate.
542 * configure: Regenerate.
543
9494d739
NC		 5442005-04-04 Nick Clifton <nickc@redhat.com>
545
546 * fr30-asm.c: Regenerate.
547 * frv-asm.c: Regenerate.
548 * iq2000-asm.c: Regenerate.
549 * m32r-asm.c: Regenerate.
550 * openrisc-asm.c: Regenerate.
551
6128c599
JB		 5522005-04-01 Jan Beulich <jbeulich@novell.com>
553
554 * i386-dis.c (PNI_Fixup): Neither mwait nor monitor have any
555 visible operands in Intel mode. The first operand of monitor is
556 %rax in 64-bit mode.
557
373ff435
JB		 5582005-04-01 Jan Beulich <jbeulich@novell.com>
559
560 * i386-dis.c (INVLPG_Fixup): Decode rdtscp; change code to allow for
561 easier future additions.
562
4bd60896
JG		 5632005-03-31 Jerome Guitton <guitton@gnat.com>
564
565 * configure.in: Check for basename.
566 * configure: Regenerate.
567 * config.in: Ditto.
568
4cc91dba
L		 5692005-03-29 H.J. Lu <hongjiu.lu@intel.com>
570
571 * i386-dis.c (SEG_Fixup): New.
572 (Sv): New.
573 (dis386): Use "Sv" for 0x8c and 0x8e.
574
ec72cfe5
NC		 5752005-03-21 Jan-Benedict Glaw <jbglaw@lug-owl.de>
576 Nick Clifton <nickc@redhat.com>
c19d1205 577
ec72cfe5
NC		 578 * vax-dis.c: (entry_addr): New varible: An array of user supplied
579 function entry mask addresses.
580 (entry_addr_occupied_slots): New variable: The number of occupied
c19d1205 581 elements in entry_addr.
ec72cfe5
NC		 582 (entry_addr_total_slots): New variable: The total number of
583 elements in entry_addr.
584 (parse_disassembler_options): New function. Fills in the entry_addr
585 array.
586 (free_entry_array): New function. Release the memory used by the
587 entry addr array. Suppressed because there is no way to call it.
588 (is_function_entry): Check if a given address is a function's
589 start address by looking at supplied entry mask addresses and
590 symbol information, if available.
591 (print_insn_vax): Use parse_disassembler_options and is_function_entry.
592
85064c79
L		 5932005-03-23 H.J. Lu <hongjiu.lu@intel.com>
594
595 * cris-dis.c (print_with_operands): Use ~31L for long instead
596 of ~31.
597
de7141c7
L		 5982005-03-20 H.J. Lu <hongjiu.lu@intel.com>
599
600 * mmix-opc.c (O): Revert the last change.
601 (Z): Likewise.
602
e493ab45
L		 6032005-03-19 H.J. Lu <hongjiu.lu@intel.com>
604
605 * mmix-opc.c (O): Use 24UL instead of 24 for unsigned long.
606 (Z): Likewise.
607
d8d7c459
HPN		 6082005-03-19 Hans-Peter Nilsson <hp@bitrange.com>
609
610 * mmix-opc.c (O, Z): Force expression as unsigned long.
611
ebdb0383
NC		 6122005-03-18 Nick Clifton <nickc@redhat.com>
613
614 * ip2k-asm.c: Regenerate.
615 * op/opcodes.pot: Regenerate.
616
1ad12f97
NC		 6172005-03-16 Nick Clifton <nickc@redhat.com>
618 Ben Elliston <bje@au.ibm.com>
619
569acd2c 620 * configure.in (werror): New switch: Add -Werror to the
1ad12f97 621 compiler command line. Enabled by default. Disable via
569acd2c 622 --disable-werror.
1ad12f97
NC		 623 * configure: Regenerate.
624
4eb30afc
AM		 6252005-03-16 Alan Modra <amodra@bigpond.net.au>
626
627 * ppc-dis.c (powerpc_dialect): Don't set PPC_OPCODE_ALTIVEC when
628 BOOKE.
629
ea8409f7
AM		 6302005-03-15 Alan Modra <amodra@bigpond.net.au>
631
729ae8d2
AM		 632 * po/es.po: Commit new Spanish translation.
633
ea8409f7
AM		 634 * po/fr.po: Commit new French translation.
635
4f495e61
NC		 6362005-03-14 Jan-Benedict Glaw <jbglaw@lug-owl.de>
637
638 * vax-dis.c: Fix spelling error
639 (print_insn_vax): Use ".word 0x0012 # Entry mask: r1 r2 >" instead
640 of just "Entry mask: < r1 ... >"
641
0a003adc
ZW		 6422005-03-12 Zack Weinberg <zack@codesourcery.com>
643
644 * arm-dis.c (arm_opcodes): Document %E and %V.
645 Add entries for v6T2 ARM instructions:
646 bfc bfi mls strht ldrht ldrsht ldrsbt movw movt rbit ubfx sbfx.
647 (print_insn_arm): Add support for %E and %V.
885fc257 648 (thumb_opcodes): Add ARMv6K instructions nop, sev, wfe, wfi, yield.
0a003adc 649
da99ee72
AM		 6502005-03-10 Jeff Baker <jbaker@qnx.com>
651 Alan Modra <amodra@bigpond.net.au>
652
653 * ppc-opc.c (insert_sprg, extract_sprg): New Functions.
654 (powerpc_operands <SPRG>): Call the above. Bit field is 5 bits.
655 (SPRG_MASK): Delete.
656 (XSPRG_MASK): Mask off extra bits now part of sprg field.
0a003adc 657 (powerpc_opcodes): Asjust mfsprg and mtsprg to suit new mask. Move
da99ee72
AM		 658 mfsprg4..7 after msprg and consolidate.
659
220abb21
AM		 6602005-03-09 Jan-Benedict Glaw <jbglaw@lug-owl.de>
661
662 * vax-dis.c (entry_mask_bit): New array.
663 (print_insn_vax): Decode function entry mask.
664
0e06657a
AH		 6652005-03-07 Aldy Hernandez <aldyh@redhat.com>
666
667 * ppc-opc.c (powerpc_opcodes): Fix encoding of efscfd.
668
06647dfd
AM		 6692005-03-05 Alan Modra <amodra@bigpond.net.au>
670
671 * po/opcodes.pot: Regenerate.
672
82b829a7
RR		 6732005-03-03 Ramana Radhakrishnan <ramana.radhakrishnan@codito.com>
674
220abb21 675 * arc-dis.c (a4_decoding_class): New enum.
06647dfd
AM		 676 (dsmOneArcInst): Use the enum values for the decoding class.
677 Remove redundant case in the switch for decodingClass value 11.
82b829a7 678
c4a530c5
JB		 6792005-03-02 Jan Beulich <jbeulich@novell.com>
680
681 * i386-dis.c (print_insn): Suppress lock prefix printing for cr8...15
682 accesses.
683 (OP_C): Consider lock prefix in non-64-bit modes.
684
47d8304e
AM		 6852005-02-24 Alan Modra <amodra@bigpond.net.au>
686
687 * cris-dis.c (format_hex): Remove ineffective warning fix.
688 * crx-dis.c (make_instruction): Warning fix.
689 * frv-asm.c: Regenerate.
690
ec36c4a4
NC		 6912005-02-23 Nick Clifton <nickc@redhat.com>
692
33b71eeb
NC		 693 * cgen-dis.in: Use bfd_byte for buffers that are passed to
694 read_memory.
06647dfd 695
33b71eeb 696 * ia64-opc.c (locate_opcode_ent): Initialise opval array.
06647dfd 697
ec36c4a4
NC		 698 * crx-dis.c (make_instruction): Move argument structure into inner
699 scope and ensure that all of its fields are initialised before
700 they are used.
701
33b71eeb
NC		 702 * fr30-asm.c: Regenerate.
703 * fr30-dis.c: Regenerate.
704 * frv-asm.c: Regenerate.
705 * frv-dis.c: Regenerate.
706 * ip2k-asm.c: Regenerate.
707 * ip2k-dis.c: Regenerate.
708 * iq2000-asm.c: Regenerate.
709 * iq2000-dis.c: Regenerate.
710 * m32r-asm.c: Regenerate.
711 * m32r-dis.c: Regenerate.
712 * openrisc-asm.c: Regenerate.
713 * openrisc-dis.c: Regenerate.
714 * xstormy16-asm.c: Regenerate.
715 * xstormy16-dis.c: Regenerate.
716
53c9ebc5
AM		 7172005-02-22 Alan Modra <amodra@bigpond.net.au>
718
719 * arc-ext.c: Warning fixes.
720 * arc-ext.h: Likewise.
721 * cgen-opc.c: Likewise.
722 * ia64-gen.c: Likewise.
723 * maxq-dis.c: Likewise.
724 * ns32k-dis.c: Likewise.
725 * w65-dis.c: Likewise.
726 * ia64-asmtab.c: Regenerate.
727
610ad19b
AM		 7282005-02-22 Alan Modra <amodra@bigpond.net.au>
729
730 * fr30-desc.c: Regenerate.
731 * fr30-desc.h: Regenerate.
732 * fr30-opc.c: Regenerate.
733 * fr30-opc.h: Regenerate.
734 * frv-desc.c: Regenerate.
735 * frv-desc.h: Regenerate.
736 * frv-opc.c: Regenerate.
737 * frv-opc.h: Regenerate.
738 * ip2k-desc.c: Regenerate.
739 * ip2k-desc.h: Regenerate.
740 * ip2k-opc.c: Regenerate.
741 * ip2k-opc.h: Regenerate.
742 * iq2000-desc.c: Regenerate.
743 * iq2000-desc.h: Regenerate.
744 * iq2000-opc.c: Regenerate.
745 * iq2000-opc.h: Regenerate.
746 * m32r-desc.c: Regenerate.
747 * m32r-desc.h: Regenerate.
748 * m32r-opc.c: Regenerate.
749 * m32r-opc.h: Regenerate.
750 * m32r-opinst.c: Regenerate.
751 * openrisc-desc.c: Regenerate.
752 * openrisc-desc.h: Regenerate.
753 * openrisc-opc.c: Regenerate.
754 * openrisc-opc.h: Regenerate.
755 * xstormy16-desc.c: Regenerate.
756 * xstormy16-desc.h: Regenerate.
757 * xstormy16-opc.c: Regenerate.
758 * xstormy16-opc.h: Regenerate.
759
db9db6f2
AM		 7602005-02-21 Alan Modra <amodra@bigpond.net.au>
761
762 * Makefile.am: Run "make dep-am"
763 * Makefile.in: Regenerate.
764
bf143b25
NC		 7652005-02-15 Nick Clifton <nickc@redhat.com>
766
767 * cgen-dis.in (print_address): Add an ATTRIBUTE_UNUSED to prevent
768 compile time warnings.
769 (print_keyword): Likewise.
770 (default_print_insn): Likewise.
771
772 * fr30-desc.c: Regenerated.
773 * fr30-desc.h: Regenerated.
774 * fr30-dis.c: Regenerated.
775 * fr30-opc.c: Regenerated.
776 * fr30-opc.h: Regenerated.
777 * frv-desc.c: Regenerated.
778 * frv-dis.c: Regenerated.
779 * frv-opc.c: Regenerated.
780 * ip2k-asm.c: Regenerated.
781 * ip2k-desc.c: Regenerated.
782 * ip2k-desc.h: Regenerated.
783 * ip2k-dis.c: Regenerated.
784 * ip2k-opc.c: Regenerated.
785 * ip2k-opc.h: Regenerated.
786 * iq2000-desc.c: Regenerated.
787 * iq2000-dis.c: Regenerated.
788 * iq2000-opc.c: Regenerated.
789 * m32r-asm.c: Regenerated.
790 * m32r-desc.c: Regenerated.
791 * m32r-desc.h: Regenerated.
792 * m32r-dis.c: Regenerated.
793 * m32r-opc.c: Regenerated.
794 * m32r-opc.h: Regenerated.
795 * m32r-opinst.c: Regenerated.
796 * openrisc-desc.c: Regenerated.
797 * openrisc-desc.h: Regenerated.
798 * openrisc-dis.c: Regenerated.
799 * openrisc-opc.c: Regenerated.
800 * openrisc-opc.h: Regenerated.
801 * xstormy16-desc.c: Regenerated.
802 * xstormy16-desc.h: Regenerated.
803 * xstormy16-dis.c: Regenerated.
804 * xstormy16-opc.c: Regenerated.
805 * xstormy16-opc.h: Regenerated.
806
d6098898
L		 8072005-02-14 H.J. Lu <hongjiu.lu@intel.com>
808
809 * dis-buf.c (perror_memory): Use sprintf_vma to print out
810 address.
811
5a84f3e0
NC		 8122005-02-11 Nick Clifton <nickc@redhat.com>
813
bc18c937
NC		 814 * iq2000-asm.c: Regenerate.
815
5a84f3e0
NC		 816 * frv-dis.c: Regenerate.
817
0a40490e
JB		 8182005-02-07 Jim Blandy <jimb@redhat.com>
819
820 * Makefile.am (CGEN): Load guile.scm before calling the main
821 application script.
822 * Makefile.in: Regenerated.
823 * cgen.sh: Be prepared for the 'cgen' argument to contain spaces.
824 Simply pass the cgen-opc.scm path to ${cgen} as its first
825 argument; ${cgen} itself now contains the '-s', or whatever is
826 appropriate for the Scheme being used.
827
c46f8c51
AC		 8282005-01-31 Andrew Cagney <cagney@gnu.org>
829
830 * configure: Regenerate to track ../gettext.m4.
831
60b9a617
JB		 8322005-01-31 Jan Beulich <jbeulich@novell.com>
833
834 * ia64-gen.c (NELEMS): Define.
835 (shrink): Generate alias with missing second predicate register when
836 opcode has two outputs and these are both predicates.
837 * ia64-opc-i.c (FULL17): Define.
838 (ia64_opcodes_i): Add mov-to-pr alias without second input. Use FULL17
839 here to generate output template.
840 (TBITCM, TNATCM): Undefine after use.
841 * ia64-opc-m.c (ia64_opcodes_i): Add alloc alias without ar.pfs as
842 first input. Add ld16 aliases without ar.csd as second output. Add
843 st16 aliases without ar.csd as second input. Add cmpxchg aliases
844 without ar.ccv as third input. Add cmp8xchg16 aliases without ar.csd/
845 ar.ccv as third/fourth inputs. Consolidate through...
846 (CMPXCHG_acq, CMPXCHG_rel, CMPXCHG_1, CMPXCHG_2, CMPXCHG_4, CMPXCHG_8,
847 CMPXCHGn, CMP8XCHG16, CMPXCHG_ALL): Define.
848 * ia64-asmtab.c: Regenerate.
849
a53bf506
AC		 8502005-01-27 Andrew Cagney <cagney@gnu.org>
851
852 * configure: Regenerate to track ../gettext.m4 change.
853
90219bd0
AO		 8542005-01-25 Alexandre Oliva <aoliva@redhat.com>
855
856 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
857 * frv-asm.c: Rebuilt.
858 * frv-desc.c: Rebuilt.
859 * frv-desc.h: Rebuilt.
860 * frv-dis.c: Rebuilt.
861 * frv-ibld.c: Rebuilt.
862 * frv-opc.c: Rebuilt.
863 * frv-opc.h: Rebuilt.
864
45181ed1
AC		 8652005-01-24 Andrew Cagney <cagney@gnu.org>
866
867 * configure: Regenerate, ../gettext.m4 was updated.
868
9e836e3d
FF		 8692005-01-21 Fred Fish <fnf@specifixinc.com>
870
871 * mips-opc.c: Change INSN_ALIAS to INSN2_ALIAS.
872 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
873 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
874 * mips-dis.c: Ditto.
875
5e8cb021
AM		 8762005-01-20 Alan Modra <amodra@bigpond.net.au>
877
878 * ppc-opc.c (powerpc_opcodes): Add optional 'l' arg to tlbiel.
879
986e18a5
FF		 8802005-01-19 Fred Fish <fnf@specifixinc.com>
881
882 * mips-dis.c (no_aliases): New disassembly option flag.
883 (set_default_mips_dis_options): Init no_aliases to zero.
884 (parse_mips_dis_option): Handle no-aliases option.
885 (print_insn_mips): Ignore table entries that are aliases
886 if no_aliases is set.
887 (print_insn_mips16): Ditto.
888 * mips-opc.c (mips_builtin_opcodes): Add initializer column for
889 new pinfo2 member and add INSN_ALIAS initializers as needed. Also
890 move WR_MACC and RD_MACC initializers from pinfo to pinfo2.
891 * mips16-opc.c (mips16_opcodes): Ditto.
892
e38bc3b5
NC		 8932005-01-17 Andrew Stubbs <andrew.stubbs@st.com>
894
895 * sh-opc.h (arch_sh2a_or_sh3e,arch_sh2a_or_sh4): Correct definition.
896 (inheritance diagram): Add missing edge.
897 (arch_sh1_up): Rename arch_sh_up to match external name to make life
898 easier for the testsuite.
899 (arch_sh4_nofp_up): Likewise, rename arch_sh4_nofpu_up.
900 (arch_sh4a_nofp_up): Likewise, rename arch_sh4a_nofpu_up.
610ad19b 901 (arch_sh2a_nofpu_or_sh4_nommu_nofpu_up): Add missing
e38bc3b5
NC		 902 arch_sh2a_or_sh4_up child.
903 (sh_table): Do renaming as above.
904 Correct comment for ldc.l for gas testsuite to read.
905 Remove rogue mul.l from sh1 (duplicate of the one for sh2).
906 Correct comments for movy.w and movy.l for gas testsuite to read.
907 Correct comments for fmov.d and fmov.s for gas testsuite to read.
908
9df48ba9
L		 9092005-01-12 H.J. Lu <hongjiu.lu@intel.com>
910
911 * i386-dis.c (OP_E): Don't ignore scale in SIB for 64 bit mode.
912
2033b4b9
L		 9132005-01-12 H.J. Lu <hongjiu.lu@intel.com>
914
915 * i386-dis.c (OP_E): Ignore scale when index == 0x4 in SIB.
916
0bcb06d2
AS		 9172005-01-10 Andreas Schwab <schwab@suse.de>
918
919 * disassemble.c (disassemble_init_for_target) <case
920 bfd_arch_ia64>: Set skip_zeroes to 16.
921 <case bfd_arch_tic4x>: Set skip_zeroes to 32.
922
47add74d
TL		 9232004-12-23 Tomer Levi <Tomer.Levi@nsc.com>
924
925 * crx-opc.c: Mark 'bcop' instruction as RELAXABLE.
926
246f4c05
SS		 9272004-12-14 Svein E. Seldal <Svein.Seldal@solidas.com>
928
929 * avr-dis.c: Prettyprint. Added printing of symbol names in all
930 memory references. Convert avr_operand() to C90 formatting.
931
0e1200e5
TL		 9322004-12-05 Tomer Levi <Tomer.Levi@nsc.com>
933
934 * crx-dis.c (print_arg): Use 'info->print_address_func' for address printing.
935
89a649f7
TL		 9362004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
937
938 * crx-opc.c (crx_optab): Mark all rbase_disps* operands as signed.
939 (no_op_insn): Initialize array with instructions that have no
940 operands.
941 * crx-dis.c (make_instruction): Get rid of COP_BRANCH_INS operand swapping.
942
6255809c
RE		 9432004-11-29 Richard Earnshaw <rearnsha@arm.com>
944
945 * arm-dis.c: Correct top-level comment.
946
2fbad815
RE		 9472004-11-27 Richard Earnshaw <rearnsha@arm.com>
948
949 * arm-opc.h (arm_opcode, thumb_opcode): Add extra field for the
950 architecuture defining the insn.
951 (arm_opcodes, thumb_opcodes): Delete. Move to ...
6b8725b9
RE		 952 * arm-dis.c (arm_opcodes, thumb_opcodes): Here. Add architecutre
953 field.
2fbad815
RE		 954 Also include opcode/arm.h.
955 * Makefile.am (arm-dis.lo): Update dependency list.
956 * Makefile.in: Regenerate.
957
d81acc42
NC		 9582004-11-22 Ravi Ramaseshan <ravi.ramaseshan@codito.com>
959
960 * opcode/arc-opc.c (insert_base): Modify ls_operand[LS_OFFSET] to
961 reflect the change to the short immediate syntax.
962
ca4f2377
AM		 9632004-11-19 Alan Modra <amodra@bigpond.net.au>
964
5da8bf1b
AM		 965 * or32-opc.c (debug): Warning fix.
966 * po/POTFILES.in: Regenerate.
967
ca4f2377
AM		 968 * maxq-dis.c: Formatting.
969 (print_insn): Warning fix.
970
b7693d02
DJ		 9712004-11-17 Daniel Jacobowitz <dan@codesourcery.com>
972
973 * arm-dis.c (WORD_ADDRESS): Define.
974 (print_insn): Use it. Correct big-endian end-of-section handling.
975
300dac7e
NC		 9762004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
977 Vineet Sharma <vineets@noida.hcltech.com>
978
979 * maxq-dis.c: New file.
980 * disassemble.c (ARCH_maxq): Define.
610ad19b 981 (disassembler): Add 'print_insn_maxq_little' for handling maxq
300dac7e
NC		 982 instructions..
983 * configure.in: Add case for bfd_maxq_arch.
984 * configure: Regenerate.
985 * Makefile.am: Add support for maxq-dis.c
986 * Makefile.in: Regenerate.
987 * aclocal.m4: Regenerate.
988
42048ee7
TL		 9892004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
990
991 * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
992 mode.
993 * crx-dis.c: Likewise.
994
bd21e58e
HPN		 9952004-11-04 Hans-Peter Nilsson <hp@axis.com>
996
997 Generally, handle CRISv32.
998 * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
999 (struct cris_disasm_data): New type.
1000 (format_reg, format_hex, cris_constraint, print_flags)
1001 (get_opcode_entry): Add struct cris_disasm_data * parameter. All
1002 callers changed.
1003 (format_sup_reg, print_insn_crisv32_with_register_prefix)
1004 (print_insn_crisv32_without_register_prefix)
1005 (print_insn_crisv10_v32_with_register_prefix)
1006 (print_insn_crisv10_v32_without_register_prefix)
1007 (cris_parse_disassembler_options): New functions.
1008 (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
1009 parameter. All callers changed.
1010 (get_opcode_entry): Call malloc, not xmalloc. Return NULL on
1011 failure.
1012 (cris_constraint) <case 'Y', 'U'>: New cases.
1013 (bytes_to_skip): Handle 'Y' and 'N' as 's'. Skip size is 4 bytes
1014 for constraint 'n'.
1015 (print_with_operands) <case 'Y'>: New case.
1016 (print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
1017 <case 'N', 'Y', 'Q'>: New cases.
1018 (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
1019 (print_insn_cris_with_register_prefix)
1020 (print_insn_cris_without_register_prefix): Call
1021 cris_parse_disassembler_options.
1022 * cris-opc.c (cris_spec_regs): Mention that this table isn't used
1023 for CRISv32 and the size of immediate operands. New v32-only
1024 entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
1025 spc. Add v32-only 4-byte entries for p2, p3, p5 and p6. Change
1026 ccr, ibr, irp to be v0..v10. Change bar, dccr to be v8..v10.
1027 Change brp to be v3..v10.
1028 (cris_support_regs): New vector.
1029 (cris_opcodes): Update head comment. New format characters '[',
1030 ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
1031 Add new opcodes for v32 and adjust existing opcodes to accommodate
1032 differences to earlier variants.
1033 (cris_cond15s): New vector.
1034
9306ca4a
JB		 10352004-11-04 Jan Beulich <jbeulich@novell.com>
1036
1037 * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
1038 (indirEb): Remove.
1039 (Mp): Use f_mode rather than none at all.
1040 (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
1041 replaces what previously was x_mode; x_mode now means 128-bit SSE
1042 operands.
1043 (dis386): Make far jumps and calls have an 'l' prefix only in AT&T
1044 mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
1045 pinsrw's second operand is Edqw.
1046 (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
1047 operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
1048 fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
1049 mode when an operand size override is present or always suffixing.
1050 More instructions will need to be added to this group.
1051 (putop): Handle new macro chars 'C' (short/long suffix selector),
1052 'I' (Intel mode override for following macro char), and 'J' (for
1053 adding the 'l' prefix to far branches in AT&T mode). When an
1054 alternative was specified in the template, honor macro character when
1055 specified for Intel mode.
1056 (OP_E): Handle new *_mode values. Correct pointer specifications for
1057 memory operands. Consolidate output of index register.
1058 (OP_G): Handle new *_mode values.
1059 (OP_I): Handle const_1_mode.
1060 (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
1061 respective opcode prefix bits have been consumed.
1062 (OP_EM, OP_EX): Provide some default handling for generating pointer
1063 specifications.
1064
f39c96a9
TL		 10652004-10-28 Tomer Levi <Tomer.Levi@nsc.com>
1066
1067 * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
1068 COP_INST macro.
1069
812337be
TL		 10702004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1071
1072 * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
1073 (getregliststring): Support HI/LO and user registers.
610ad19b 1074 * crx-opc.c (crx_instruction): Update data structure according to the
812337be
TL		 1075 rearrangement done in CRX opcode header file.
1076 (crx_regtab): Likewise.
1077 (crx_optab): Likewise.
610ad19b 1078 (crx_instruction): Reorder load/stor instructions, remove unsupported
812337be
TL		 1079 formats.
1080 support new Co-Processor instruction 'cpi'.
1081
4030fa5a
NC		 10822004-10-27 Nick Clifton <nickc@redhat.com>
1083
1084 * opcodes/iq2000-asm.c: Regenerate.
1085 * opcodes/iq2000-desc.c: Regenerate.
1086 * opcodes/iq2000-desc.h: Regenerate.
1087 * opcodes/iq2000-dis.c: Regenerate.
1088 * opcodes/iq2000-ibld.c: Regenerate.
1089 * opcodes/iq2000-opc.c: Regenerate.
1090 * opcodes/iq2000-opc.h: Regenerate.
1091
fc3d45e8
TL		 10922004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1093
1094 * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
1095 us4, us5 (respectively).
1096 Remove unsupported 'popa' instruction.
1097 Reverse operands order in store co-processor instructions.
1098
3c55da70
AM		 10992004-10-15 Alan Modra <amodra@bigpond.net.au>
1100
1101 * Makefile.am: Run "make dep-am"
1102 * Makefile.in: Regenerate.
1103
7fa3d080
BW		 11042004-10-12 Bob Wilson <bob.wilson@acm.org>
1105
1106 * xtensa-dis.c: Use ISO C90 formatting.
1107
e612bb4d
AM		 11082004-10-09 Alan Modra <amodra@bigpond.net.au>
1109
1110 * ppc-opc.c: Revert 2004-09-09 change.
1111
43cd72b9
BW		 11122004-10-07 Bob Wilson <bob.wilson@acm.org>
1113
1114 * xtensa-dis.c (state_names): Delete.
1115 (fetch_data): Use xtensa_isa_maxlength.
1116 (print_xtensa_operand): Replace operand parameter with opcode/operand
1117 pair. Remove print_sr_name parameter. Use new xtensa-isa.h functions.
1118 (print_insn_xtensa): Use new xtensa-isa.h functions. Handle multislot
1119 instruction bundles. Use xmalloc instead of malloc.
1120
bbac1f2a
NC		 11212004-10-07 David Gibson <david@gibson.dropbear.id.au>
1122
1123 * ppc-opc.c: Replace literal "0"s with NULLs in pointer
1124 initializers.
1125
48c9f030
NC		 11262004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1127
1128 * crx-opc.c (crx_instruction): Support Co-processor insns.
1129 * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
1130 (getregliststring): Change function to use the above enum.
1131 (print_arg): Handle CO-Processor insns.
1132 (crx_cinvs): Add 'b' option to invalidate the branch-target
1133 cache.
1134
12c64a4e
AH		 11352004-10-06 Aldy Hernandez <aldyh@redhat.com>
1136
1137 * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
1138 efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
1139 efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
1140 efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
1141 efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
1142
14127cc4
NC		 11432004-10-01 Bill Farmer <Bill@the-farmers.freeserve.co.uk>
1144
1145 * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
1146 rather than add it.
1147
0dd132b6
NC		 11482004-09-30 Paul Brook <paul@codesourcery.com>
1149
1150 * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
1151 * arm-opc.h: Document %e. Add ARMv6ZK instructions.
1152
3f85e526
L		 11532004-09-17 H.J. Lu <hongjiu.lu@intel.com>
1154
1155 * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
1156 (CONFIG_STATUS_DEPENDENCIES): New.
1157 (Makefile): Removed.
1158 (config.status): Likewise.
1159 * Makefile.in: Regenerated.
1160
8ae85421
AM		 11612004-09-17 Alan Modra <amodra@bigpond.net.au>
1162
1163 * Makefile.am: Run "make dep-am".
1164 * Makefile.in: Regenerate.
1165 * aclocal.m4: Regenerate.
1166 * configure: Regenerate.
1167 * po/POTFILES.in: Regenerate.
1168 * po/opcodes.pot: Regenerate.
1169
24443139
AS		 11702004-09-11 Andreas Schwab <schwab@suse.de>
1171
1172 * configure: Rebuild.
1173
2a309db0
AM		 11742004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1175
1176 * ppc-opc.c (L): Make this field not optional.
1177
42851540
NC		 11782004-09-03 Tomer Levi <Tomer.Levi@nsc.com>
1179
1180 * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
1181 Fix parameter to 'm[t|f]csr' insns.
1182
979273e3
NN		 11832004-08-30 Nathanael Nerode <neroden@gcc.gnu.org>
1184
1185 * configure.in: Autoupdate to autoconf 2.59.
1186 * aclocal.m4: Rebuild with aclocal 1.4p6.
1187 * configure: Rebuild with autoconf 2.59.
1188 * Makefile.in: Rebuild with automake 1.4p6 (picking up
1189 bfd changes for autoconf 2.59 on the way).
1190 * config.in: Rebuild with autoheader 2.59.
1191
ac28a1cb
RS		 11922004-08-27 Richard Sandiford <rsandifo@redhat.com>
1193
1194 * frv-desc.[ch], frv-opc.[ch]: Regenerated.
1195
30d1c836
ML		 11962004-07-30 Michal Ludvig <mludvig@suse.cz>
1197
1198 * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
1199 (GRPPADLCK2): New define.
1200 (twobyte_has_modrm): True for 0xA6.
1201 (grps): GRPPADLCK2 for opcode 0xA6.
1202
0b0ac059
AO		 12032004-07-29 Alexandre Oliva <aoliva@redhat.com>
1204
1205 Introduce SH2a support.
1206 * sh-opc.h (arch_sh2a_base): Renumber.
1207 (arch_sh2a_nofpu_base): Remove.
1208 (arch_sh_base_mask): Adjust.
1209 (arch_opann_mask): New.
1210 (arch_sh2a, arch_sh2a_nofpu): Adjust.
1211 (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
1212 (sh_table): Adjust whitespace.
1213 2004-02-24 Corinna Vinschen <vinschen@redhat.com>
1214 * sh-opc.h (arch_sh2a_nofpu_up): New. Use instead of arch_sh2a_up in
1215 instruction list throughout.
1216 (arch_sh2a_up): Redefine to include fpu instruction set. Use instead
1217 of arch_sh2a in instruction list throughout.
1218 (arch_sh2e_up): Accomodate above changes.
1219 (arch_sh2_up): Ditto.
1220 2004-02-20 Corinna Vinschen <vinschen@redhat.com>
1221 * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
1222 2004-02-18 Corinna Vinschen <vinschen@redhat.com>
1223 * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
1224 * sh-opc.h (arch_sh2a_nofpu): New.
1225 (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
1226 (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
1227 instruction.
1228 2004-01-20 DJ Delorie <dj@redhat.com>
1229 * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
1230 2003-12-29 DJ Delorie <dj@redhat.com>
1231 * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
1232 sh_opcode_info, sh_table): Add sh2a support.
1233 (arch_op32): New, to tag 32-bit opcodes.
1234 * sh-dis.c (print_insn_sh): Support sh2a opcodes.
1235 2003-12-02 Michael Snyder <msnyder@redhat.com>
1236 * sh-opc.h (arch_sh2a): Add.
1237 * sh-dis.c (arch_sh2a): Handle.
1238 * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
1239
670ec21d
NC		 12402004-07-27 Tomer Levi <Tomer.Levi@nsc.com>
1241
1242 * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
1243
ed049af3
NC		 12442004-07-22 Nick Clifton <nickc@redhat.com>
1245
1246 PR/280
1247 * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
1248 insns - this is done by objdump itself.
1249 * h8500-dis.c (print_insn_h8500): Likewise.
1250
20f0a1fc
NC		 12512004-07-21 Jan Beulich <jbeulich@novell.com>
1252
1253 * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
1254 regardless of address size prefix in effect.
1255 (ptr_reg): Size or address registers does not depend on rex64, but
1256 on the presence of an address size override.
1257 (OP_MMX): Use rex.x only for xmm registers.
1258 (OP_EM): Use rex.z only for xmm registers.
1259
6f14957b
MR		 12602004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
1261
1262 * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
1263 move/branch operations to the bottom so that VR5400 multimedia
1264 instructions take precedence in disassembly.
1265
1586d91e
MR		 12662004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
1267
1268 * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
1269 ISA-specific "break" encoding.
1270
982de27a
NC		 12712004-07-13 Elvis Chiang <elvisfb@gmail.com>
1272
1273 * arm-opc.h: Fix typo in comment.
1274
4300ab10
AS		 12752004-07-11 Andreas Schwab <schwab@suse.de>
1276
1277 * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
1278
8577e690
AS		 12792004-07-09 Andreas Schwab <schwab@suse.de>
1280
1281 * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
1282
1fe1f39c
NC		 12832004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1284
1285 * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
1286 (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
1287 (crx-dis.lo): New target.
1288 (crx-opc.lo): Likewise.
1289 * Makefile.in: Regenerate.
1290 * configure.in: Handle bfd_crx_arch.
1291 * configure: Regenerate.
1292 * crx-dis.c: New file.
1293 * crx-opc.c: New file.
1294 * disassemble.c (ARCH_crx): Define.
1295 (disassembler): Handle ARCH_crx.
1296
7a33b495
JW		 12972004-06-29 James E Wilson <wilson@specifixinc.com>
1298
1299 * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
1300 * ia64-asmtab.c: Regnerate.
1301
98e69875
AM		 13022004-06-28 Alan Modra <amodra@bigpond.net.au>
1303
1304 * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
1305 (extract_fxm): Don't test dialect.
1306 (XFXFXM_MASK): Include the power4 bit.
1307 (XFXM): Add p4 param.
1308 (powerpc_opcodes): Add mfocrf and mtocrf. Adjust mtcr.
1309
a53b85e2
AO		 13102004-06-27 Alexandre Oliva <aoliva@redhat.com>
1311
1312 2003-07-21 Richard Sandiford <rsandifo@redhat.com>
1313 * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
1314
d0618d1c
AM		 13152004-06-26 Alan Modra <amodra@bigpond.net.au>
1316
1317 * ppc-opc.c (BH, XLBH_MASK): Define.
1318 (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
1319
1d9f512f
AM		 13202004-06-24 Alan Modra <amodra@bigpond.net.au>
1321
1322 * i386-dis.c (x_mode): Comment.
1323 (two_source_ops): File scope.
1324 (float_mem): Correct fisttpll and fistpll.
1325 (float_mem_mode): New table.
1326 (dofloat): Use it.
1327 (OP_E): Correct intel mode PTR output.
1328 (ptr_reg): Use open_char and close_char.
1329 (PNI_Fixup): Handle possible suffix on sidt. Use op1out etc. for
1330 operands. Set two_source_ops.
1331
52886d70
AM		 13322004-06-15 Alan Modra <amodra@bigpond.net.au>
1333
1334 * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
1335 instead of _raw_size.
1336
bad9ceea
JJ		 13372004-06-08 Jakub Jelinek <jakub@redhat.com>
1338
1339 * ia64-gen.c (in_iclass): Handle more postinc st
1340 and ld variants.
1341 * ia64-asmtab.c: Rebuilt.
1342
0451f5df
MS		 13432004-06-01 Martin Schwidefsky <schwidefsky@de.ibm.com>
1344
1345 * s390-opc.txt: Correct architecture mask for some opcodes.
1346 lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
1347 in the esa mode as well.
1348
f6f9408f
JR		 13492004-05-28 Andrew Stubbs <andrew.stubbs@superh.com>
1350
1351 * sh-dis.c (target_arch): Make unsigned.
1352 (print_insn_sh): Replace (most of) switch with a call to
1353 sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
1354 * sh-opc.h: Redefine architecture flags values.
1355 Add sh3-nommu architecture.
1356 Reorganise <arch>_up macros so they make more visual sense.
1357 (SH_MERGE_ARCH_SET): Define new macro.
1358 (SH_VALID_BASE_ARCH_SET): Likewise.
1359 (SH_VALID_MMU_ARCH_SET): Likewise.
1360 (SH_VALID_CO_ARCH_SET): Likewise.
1361 (SH_VALID_ARCH_SET): Likewise.
1362 (SH_MERGE_ARCH_SET_VALID): Likewise.
1363 (SH_ARCH_SET_HAS_FPU): Likewise.
1364 (SH_ARCH_SET_HAS_DSP): Likewise.
1365 (SH_ARCH_UNKNOWN_ARCH): Likewise.
1366 (sh_get_arch_from_bfd_mach): Add prototype.
1367 (sh_get_arch_up_from_bfd_mach): Likewise.
1368 (sh_get_bfd_mach_from_arch_set): Likewise.
1369 (sh_merge_bfd_arc): Likewise.
1370
be8c092b
NC		 13712004-05-24 Peter Barada <peter@the-baradas.com>
1372
1373 * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
610ad19b
AM		 1374 into new match_insn_m68k function. Loop over canidate
1375 matches and select first that completely matches.
be8c092b
NC		 1376 * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
1377 * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
610ad19b 1378 to verify addressing for MAC/EMAC.
be8c092b
NC		 1379 * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
1380 reigster halves since 'fpu' and 'spl' look misleading.
1381 * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
1382 * m68k-opc.c: Rearragne mac/emac cases to use longest for
1383 first, tighten up match masks.
1384 * m68k-opc.c: Add 'size' field to struct m68k_opcode. Produce
1385 'size' from special case code in print_insn_m68k to
1386 determine decode size of insns.
1387
a30e9cc4
AM		 13882004-05-19 Alan Modra <amodra@bigpond.net.au>
1389
1390 * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
1391 well as when -mpower4.
1392
9598fbe5
NC		 13932004-05-13 Nick Clifton <nickc@redhat.com>
1394
1395 * po/fr.po: Updated French translation.
1396
6b6e92f4
NC		 13972004-05-05 Peter Barada <peter@the-baradas.com>
1398
1399 * m68k-dis.c(print_insn_m68k): Add new chips, use core
1400 variants in arch_mask. Only set m68881/68851 for 68k chips.
1401 * m68k-op.c: Switch from ColdFire chips to core variants.
1402
a404d431
AM		 14032004-05-05 Alan Modra <amodra@bigpond.net.au>
1404
a30e9cc4 1405 PR 147.
a404d431
AM		 1406 * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
1407
f3806e43
BE		 14082004-04-29 Ben Elliston <bje@au.ibm.com>
1409
520ceea4
BE		 1410 * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
1411 (powerpc_opcodes): Add "dbczl" instruction for PPC970.
f3806e43 1412
1f1799d5
KK		 14132004-04-22 Kaz Kojima <kkojima@rr.iij4u.or.jp>
1414
1415 * sh-dis.c (print_insn_sh): Print the value in constant pool
1416 as a symbol if it looks like a symbol.
1417
fd99574b
NC		 14182004-04-22 Peter Barada <peter@the-baradas.com>
1419
1420 * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
1421 appropriate ColdFire architectures.
1422 (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
1423 mask addressing.
1424 Add EMAC instructions, fix MAC instructions. Remove
1425 macmw/macml/msacmw/msacml instructions since mask addressing now
1426 supported.
1427
b4781d44
JJ		 14282004-04-20 Jakub Jelinek <jakub@redhat.com>
1429
1430 * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
1431 (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
1432 suffix. Use fmov*x macros, create all 3 fpsize variants in one
1433 macro. Adjust all users.
1434
91809fda 14352004-04-15 Anil Paranjpe <anilp1@kpitcummins.com>
610ad19b 1436
91809fda
NC		 1437 * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
1438 separately.
1439
f4453dfa
NC		 14402004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
1441
1442 * m32r-asm.c: Regenerate.
1443
9b0de91a
SS		 14442004-03-29 Stan Shebs <shebs@apple.com>
1445
1446 * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
1447 used.
1448
e20c0b3d
AM		 14492004-03-19 Alan Modra <amodra@bigpond.net.au>
1450
1451 * aclocal.m4: Regenerate.
1452 * config.in: Regenerate.
1453 * configure: Regenerate.
1454 * po/POTFILES.in: Regenerate.
1455 * po/opcodes.pot: Regenerate.
1456
fdd12ef3
AM		 14572004-03-16 Alan Modra <amodra@bigpond.net.au>
1458
1459 * ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
1460 PPC_OPERANDS_GPR_0.
1461 * ppc-opc.c (RA0): Define.
1462 (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
1463 (RAOPT): Rename from RAO. Update all uses.
a9c3619e 1464 (powerpc_opcodes): Use RA0 as appropriate.
fdd12ef3 1465
2dc111b3 14662004-03-15 Aldy Hernandez <aldyh@redhat.com>
fdd12ef3
AM		 1467
1468 * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
2dc111b3 1469
7bfeee7b
AM		 14702004-03-15 Alan Modra <amodra@bigpond.net.au>
1471
1472 * sparc-dis.c (print_insn_sparc): Update getword prototype.
1473
7ffdda93
ML		 14742004-03-12 Michal Ludvig <mludvig@suse.cz>
1475
1476 * i386-dis.c (GRPPLOCK): Delete.
7bfeee7b 1477 (grps): Delete GRPPLOCK entry.
7ffdda93 1478
cc0ec051
AM		 14792004-03-12 Alan Modra <amodra@bigpond.net.au>
1480
1481 * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
1482 (M, Mp): Use OP_M.
1483 (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
1484 (GRPPADLCK): Define.
1485 (dis386): Use NOP_Fixup on "nop".
1486 (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
1487 (twobyte_has_modrm): Set for 0xa7.
1488 (padlock_table): Delete. Move to..
1489 (grps): ..here, using OP_0f07. Use OP_Ofae on lfence, mfence
1490 and clflush.
1491 (print_insn): Revert PADLOCK_SPECIAL code.
1492 (OP_E): Delete sfence, lfence, mfence checks.
1493
4fd61dcb
JJ		 14942004-03-12 Jakub Jelinek <jakub@redhat.com>
1495
1496 * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
1497 (INVLPG_Fixup): New function.
1498 (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
1499
0f10071e
ML		 15002004-03-12 Michal Ludvig <mludvig@suse.cz>
1501
1502 * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
1503 (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
1504 (padlock_table): New struct with PadLock instructions.
1505 (print_insn): Handle PADLOCK_SPECIAL.
1506
c02908d2
AM		 15072004-03-12 Alan Modra <amodra@bigpond.net.au>
1508
1509 * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
1510 (OP_E): Twiddle clflush to sfence here.
1511
d5bb7600
NC		 15122004-03-08 Nick Clifton <nickc@redhat.com>
1513
1514 * po/de.po: Updated German translation.
1515
ae51a426
JR		 15162003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>
1517
1518 * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
1519 nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu.
1520 * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
1521 accordingly.
1522
676a64f4
RS		 15232004-03-01 Richard Sandiford <rsandifo@redhat.com>
1524
1525 * frv-asm.c: Regenerate.
1526 * frv-desc.c: Regenerate.
1527 * frv-desc.h: Regenerate.
1528 * frv-dis.c: Regenerate.
1529 * frv-ibld.c: Regenerate.
1530 * frv-opc.c: Regenerate.
1531 * frv-opc.h: Regenerate.
1532
c7a48b9a
RS		 15332004-03-01 Richard Sandiford <rsandifo@redhat.com>
1534
1535 * frv-desc.c, frv-opc.c: Regenerate.
1536
8ae0baa2
RS		 15372004-03-01 Richard Sandiford <rsandifo@redhat.com>
1538
1539 * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
1540
ce11586c
JR		 15412004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
1542
1543 * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
1544 Also correct mistake in the comment.
1545
6a5709a5
JR		 15462004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
1547
1548 * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
1549 ensure that double registers have even numbers.
1550 Add REG_N_B01 for nn01 (binary 01) nibble to ensure
1551 that reserved instruction 0xfffd does not decode the same
1552 as 0xfdfd (ftrv).
1553 * sh-opc.h: Add REG_N_D nibble type and use it whereever
1554 REG_N refers to a double register.
1555 Add REG_N_B01 nibble type and use it instead of REG_NM
1556 in ftrv.
1557 Adjust the bit patterns in a few comments.
1558
e5d2b64f 15592004-02-25 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 1560
1561 * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
e5d2b64f 1562
1f04b05f
AH		 15632004-02-20 Aldy Hernandez <aldyh@redhat.com>
1564
1565 * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
1566
2f3b8700
AH		 15672004-02-20 Aldy Hernandez <aldyh@redhat.com>
1568
1569 * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
1570
f0b26da6 15712004-02-20 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 1572
1573 * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
1574 mtivor32, mtivor33, mtivor34.
f0b26da6 1575
23d59c56 15762004-02-19 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 1577
1578 * ppc-opc.c (powerpc_opcodes): Add mfmcar.
23d59c56 1579
34920d91
NC		 15802004-02-10 Petko Manolov <petkan@nucleusys.com>
1581
1582 * arm-opc.h Maverick accumulator register opcode fixes.
1583
44d86481
BE		 15842004-02-13 Ben Elliston <bje@wasabisystems.com>
1585
1586 * m32r-dis.c: Regenerate.
1587
17707c23
MS		 15882004-01-27 Michael Snyder <msnyder@redhat.com>
1589
1590 * sh-opc.h (sh_table): "fsrra", not "fssra".
1591
fe3a9bc4
NC		 15922004-01-23 Andrew Over <andrew.over@cs.anu.edu.au>
1593
1594 * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
1595 contraints.
1596
ff24f124
JJ		 15972004-01-19 Andrew Over <andrew.over@cs.anu.edu.au>
1598
1599 * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
1600
a02a862a
AM		 16012004-01-19 Alan Modra <amodra@bigpond.net.au>
1602
1603 * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
1604 1. Don't print scale factor on AT&T mode when index missing.
1605
d164ea7f
AO		 16062004-01-16 Alexandre Oliva <aoliva@redhat.com>
1607
1608 * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
1609 when loaded into XR registers.
1610
cb10e79a
RS		 16112004-01-14 Richard Sandiford <rsandifo@redhat.com>
1612
1613 * frv-desc.h: Regenerate.
1614 * frv-desc.c: Regenerate.
1615 * frv-opc.c: Regenerate.
1616
f532f3fa
MS		 16172004-01-13 Michael Snyder <msnyder@redhat.com>
1618
1619 * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
1620
e45d0630
PB		 16212004-01-09 Paul Brook <paul@codesourcery.com>
1622
1623 * arm-opc.h (arm_opcodes): Move generic mcrr after known
1624 specific opcodes.
1625
3ba7a1aa
DJ		 16262004-01-07 Daniel Jacobowitz <drow@mvista.com>
1627
1628 * Makefile.am (libopcodes_la_DEPENDENCIES)
1629 (libopcodes_la_LIBADD): Revert 2003-05-17 change. Add explanatory
1630 comment about the problem.
1631 * Makefile.in: Regenerate.
1632
ba2d3f07
AO		 16332004-01-06 Alexandre Oliva <aoliva@redhat.com>
1634
1635 2003-12-19 Alexandre Oliva <aoliva@redhat.com>
1636 * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
1637 cut&paste errors in shifting/truncating numerical operands.
1638 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
1639 * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
1640 (parse_uslo16): Likewise.
1641 (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
1642 (parse_d12): Parse gotoff12 and gotofffuncdesc12.
1643 (parse_s12): Likewise.
1644 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
1645 * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
1646 (parse_uslo16): Likewise.
1647 (parse_uhi16): Parse gothi and gotfuncdeschi.
1648 (parse_d12): Parse got12 and gotfuncdesc12.
1649 (parse_s12): Likewise.
1650
3ab48931
NC		 16512004-01-02 Albert Bartoszko <albar@nt.kegel.com.pl>
1652
1653 * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
1654 instruction which looks similar to an 'rla' instruction.
a0bd404e 1655
c9e214e5 1656For older changes see ChangeLog-0203
252b5132
RH		 1657\f
1658Local Variables:
2f6d2f85
NC		 1659mode: change-log
1660left-margin: 8
1661fill-column: 74
252b5132
RH		 1662version-control: never
1663End:
GDB Binutils - Deliverables
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