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More uses of ui_out_emit_tuple
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
a8cc8a54
AM		 12017-04-22 Alexander Fedotov <alfedotov@gmail.com>
2 Alan Modra <amodra@gmail.com>
3
4 * ppc-opc.c (ELEV): Define.
5 (vle_opcodes): Add se_rfgi and e_sc.
6 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
7 for E200Z4.
8
3ab87b68
JM		 92017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
10
11 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
12
792f174f
NC		 132017-04-21 Nick Clifton <nickc@redhat.com>
14
15 PR binutils/21380
16 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
17 LD3R and LD4R.
18
42742084
AM		 192017-04-13 Alan Modra <amodra@gmail.com>
20
21 * epiphany-desc.c: Regenerate.
22 * fr30-desc.c: Regenerate.
23 * frv-desc.c: Regenerate.
24 * ip2k-desc.c: Regenerate.
25 * iq2000-desc.c: Regenerate.
26 * lm32-desc.c: Regenerate.
27 * m32c-desc.c: Regenerate.
28 * m32r-desc.c: Regenerate.
29 * mep-desc.c: Regenerate.
30 * mt-desc.c: Regenerate.
31 * or1k-desc.c: Regenerate.
32 * xc16x-desc.c: Regenerate.
33 * xstormy16-desc.c: Regenerate.
34
9a85b496
AM		 352017-04-11 Alan Modra <amodra@gmail.com>
36
ef85eab0 37 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
c03dc33b
AM		 38 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
39 PPC_OPCODE_TMR for e6500.
9a85b496
AM		 40 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
41 (PPCVEC3): Define as PPC_OPCODE_POWER9.
9570835e
AM		 42 (PPCVSX2): Define as PPC_OPCODE_POWER8.
43 (PPCVSX3): Define as PPC_OPCODE_POWER9.
ef85eab0 44 (PPCHTM): Define as PPC_OPCODE_POWER8.
c03dc33b 45 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
9a85b496 46
62adc510
AM		 472017-04-10 Alan Modra <amodra@gmail.com>
48
49 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
50 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
51 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
52 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
53
aa808707
PC		 542017-04-09 Pip Cet <pipcet@gmail.com>
55
56 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
57 appropriate floating-point precision directly.
58
ac8f0f72
AM		 592017-04-07 Alan Modra <amodra@gmail.com>
60
61 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
62 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
63 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
64 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
65 vector instructions with E6500 not PPCVEC2.
66
62ecb94c
PC		 672017-04-06 Pip Cet <pipcet@gmail.com>
68
69 * Makefile.am: Add wasm32-dis.c.
70 * configure.ac: Add wasm32-dis.c to wasm32 target.
71 * disassemble.c: Add wasm32 disassembler code.
72 * wasm32-dis.c: New file.
73 * Makefile.in: Regenerate.
74 * configure: Regenerate.
75 * po/POTFILES.in: Regenerate.
76 * po/opcodes.pot: Regenerate.
77
f995bbe8
PA		 782017-04-05 Pedro Alves <palves@redhat.com>
79
80 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
81 * arm-dis.c (parse_arm_disassembler_options): Constify.
82 * ppc-dis.c (powerpc_init_dialect): Constify local.
83 * vax-dis.c (parse_disassembler_options): Constify.
84
b5292032
PD		 852017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
86
87 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
88 RISCV_GP_SYMBOL.
89
f96bd6c2
PC		 902017-03-30 Pip Cet <pipcet@gmail.com>
91
92 * configure.ac: Add (empty) bfd_wasm32_arch target.
93 * configure: Regenerate
94 * po/opcodes.pot: Regenerate.
95
f7c514a3
JM		 962017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
97
98 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
99 OSA2015.
100 * opcodes/sparc-opc.c (asi_table): New ASIs.
101
52be03fd
AM		 1022017-03-29 Alan Modra <amodra@gmail.com>
103
104 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
105 "raw" option.
106 (lookup_powerpc): Don't special case -1 dialect. Handle
107 PPC_OPCODE_RAW.
108 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
109 lookup_powerpc call, pass it on second.
110
9b753937
AM		 1112017-03-27 Alan Modra <amodra@gmail.com>
112
113 PR 21303
114 * ppc-dis.c (struct ppc_mopt): Comment.
115 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
116
c0c31e91
RZ		 1172017-03-27 Rinat Zelig <rinat@mellanox.com>
118
119 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
120 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
121 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
122 (insert_nps_misc_imm_offset): New function.
123 (extract_nps_misc imm_offset): New function.
124 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
125 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
126
2253c8f0
AK		 1272017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
128
129 * s390-mkopc.c (main): Remove vx2 check.
130 * s390-opc.txt: Remove vx2 instruction flags.
131
645d3342
RZ		 1322017-03-21 Rinat Zelig <rinat@mellanox.com>
133
134 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
135 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
136 (insert_nps_imm_offset): New function.
137 (extract_nps_imm_offset): New function.
138 (insert_nps_imm_entry): New function.
139 (extract_nps_imm_entry): New function.
140
4b94dd2d
AM		 1412017-03-17 Alan Modra <amodra@gmail.com>
142
143 PR 21248
144 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
145 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
146 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
147
b416fe87
KC		 1482017-03-14 Kito Cheng <kito.cheng@gmail.com>
149
150 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
151 <c.andi>: Likewise.
152 <c.addiw> Likewise.
153
03b039a5
KC		 1542017-03-14 Kito Cheng <kito.cheng@gmail.com>
155
156 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
157
2c232b83
AW		 1582017-03-13 Andrew Waterman <andrew@sifive.com>
159
160 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
161 <srl> Likewise.
162 <srai> Likewise.
163 <sra> Likewise.
164
86fa6981
L		 1652017-03-09 H.J. Lu <hongjiu.lu@intel.com>
166
167 * i386-gen.c (opcode_modifiers): Replace S with Load.
168 * i386-opc.h (S): Removed.
169 (Load): New.
170 (i386_opcode_modifier): Replace s with load.
171 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
172 and {evex}. Replace S with Load.
173 * i386-tbl.h: Regenerated.
174
c1fe188b
L		 1752017-03-09 H.J. Lu <hongjiu.lu@intel.com>
176
177 * i386-opc.tbl: Use CpuCET on rdsspq.
178 * i386-tbl.h: Regenerated.
179
4b8b687e
PB		 1802017-03-08 Peter Bergner <bergner@vnet.ibm.com>
181
182 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
183 <vsx>: Do not use PPC_OPCODE_VSX3;
184
1437d063
PB		 1852017-03-08 Peter Bergner <bergner@vnet.ibm.com>
186
187 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
188
603555e5
L		 1892017-03-06 H.J. Lu <hongjiu.lu@intel.com>
190
191 * i386-dis.c (REG_0F1E_MOD_3): New enum.
192 (MOD_0F1E_PREFIX_1): Likewise.
193 (MOD_0F38F5_PREFIX_2): Likewise.
194 (MOD_0F38F6_PREFIX_0): Likewise.
195 (RM_0F1E_MOD_3_REG_7): Likewise.
196 (PREFIX_MOD_0_0F01_REG_5): Likewise.
197 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
198 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
199 (PREFIX_0F1E): Likewise.
200 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
201 (PREFIX_0F38F5): Likewise.
202 (dis386_twobyte): Use PREFIX_0F1E.
203 (reg_table): Add REG_0F1E_MOD_3.
204 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
205 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
206 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
207 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
208 (three_byte_table): Use PREFIX_0F38F5.
209 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
210 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
211 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
212 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
213 PREFIX_MOD_3_0F01_REG_5_RM_2.
214 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
215 (cpu_flags): Add CpuCET.
216 * i386-opc.h (CpuCET): New enum.
217 (CpuUnused): Commented out.
218 (i386_cpu_flags): Add cpucet.
219 * i386-opc.tbl: Add Intel CET instructions.
220 * i386-init.h: Regenerated.
221 * i386-tbl.h: Likewise.
222
73f07bff
AM		 2232017-03-06 Alan Modra <amodra@gmail.com>
224
225 PR 21124
226 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
227 (extract_raq, extract_ras, extract_rbx): New functions.
228 (powerpc_operands): Use opposite corresponding insert function.
229 (Q_MASK): Define.
230 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
231 register restriction.
232
65b48a81
PB		 2332017-02-28 Peter Bergner <bergner@vnet.ibm.com>
234
235 * disassemble.c Include "safe-ctype.h".
236 (disassemble_init_for_target): Handle s390 init.
237 (remove_whitespace_and_extra_commas): New function.
238 (disassembler_options_cmp): Likewise.
239 * arm-dis.c: Include "libiberty.h".
240 (NUM_ELEM): Delete.
241 (regnames): Use long disassembler style names.
242 Add force-thumb and no-force-thumb options.
243 (NUM_ARM_REGNAMES): Rename from this...
244 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
245 (get_arm_regname_num_options): Delete.
246 (set_arm_regname_option): Likewise.
247 (get_arm_regnames): Likewise.
248 (parse_disassembler_options): Likewise.
249 (parse_arm_disassembler_option): Rename from this...
250 (parse_arm_disassembler_options): ...to this. Make static.
251 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
252 (print_insn): Use parse_arm_disassembler_options.
253 (disassembler_options_arm): New function.
254 (print_arm_disassembler_options): Handle updated regnames.
255 * ppc-dis.c: Include "libiberty.h".
256 (ppc_opts): Add "32" and "64" entries.
257 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
258 (powerpc_init_dialect): Add break to switch statement.
259 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
260 (disassembler_options_powerpc): New function.
261 (print_ppc_disassembler_options): Use ARRAY_SIZE.
262 Remove printing of "32" and "64".
263 * s390-dis.c: Include "libiberty.h".
264 (init_flag): Remove unneeded variable.
265 (struct s390_options_t): New structure type.
266 (options): New structure.
267 (init_disasm): Rename from this...
268 (disassemble_init_s390): ...to this. Add initializations for
269 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
270 (print_insn_s390): Delete call to init_disasm.
271 (disassembler_options_s390): New function.
272 (print_s390_disassembler_options): Print using information from
273 struct 'options'.
274 * po/opcodes.pot: Regenerate.
275
15c7c1d8
JB		 2762017-02-28 Jan Beulich <jbeulich@suse.com>
277
278 * i386-dis.c (PCMPESTR_Fixup): New.
279 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
280 (prefix_table): Use PCMPESTR_Fixup.
281 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
282 PCMPESTR_Fixup.
283 (vex_w_table): Delete VPCMPESTR{I,M} entries.
284 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
285 Split 64-bit and non-64-bit variants.
286 * opcodes/i386-tbl.h: Re-generate.
287
582e12bf
RS		 2882017-02-24 Richard Sandiford <richard.sandiford@arm.com>
289
290 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
291 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
292 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
293 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
294 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
295 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
296 (OP_SVE_V_HSD): New macros.
297 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
298 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
299 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
300 (aarch64_opcode_table): Add new SVE instructions.
301 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
302 for rotation operands. Add new SVE operands.
303 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
304 (ins_sve_quad_index): Likewise.
305 (ins_imm_rotate): Split into...
306 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
307 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
308 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
309 functions.
310 (aarch64_ins_sve_addr_ri_s4): New function.
311 (aarch64_ins_sve_quad_index): Likewise.
312 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
313 * aarch64-asm-2.c: Regenerate.
314 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
315 (ext_sve_quad_index): Likewise.
316 (ext_imm_rotate): Split into...
317 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
318 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
319 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
320 functions.
321 (aarch64_ext_sve_addr_ri_s4): New function.
322 (aarch64_ext_sve_quad_index): Likewise.
323 (aarch64_ext_sve_index): Allow quad indices.
324 (do_misc_decoding): Likewise.
325 * aarch64-dis-2.c: Regenerate.
326 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
327 aarch64_field_kinds.
328 (OPD_F_OD_MASK): Widen by one bit.
329 (OPD_F_NO_ZR): Bump accordingly.
330 (get_operand_field_width): New function.
331 * aarch64-opc.c (fields): Add new SVE fields.
332 (operand_general_constraint_met_p): Handle new SVE operands.
333 (aarch64_print_operand): Likewise.
334 * aarch64-opc-2.c: Regenerate.
335
f482d304
RS		 3362017-02-24 Richard Sandiford <richard.sandiford@arm.com>
337
338 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
339 (aarch64_feature_compnum): ...this.
340 (SIMD_V8_3): Replace with...
341 (COMPNUM): ...this.
342 (CNUM_INSN): New macro.
343 (aarch64_opcode_table): Use it for the complex number instructions.
344
7db2c588
JB		 3452017-02-24 Jan Beulich <jbeulich@suse.com>
346
347 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
348
1e9d41d4
SL		 3492017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
350
351 Add support for associating SPARC ASIs with an architecture level.
352 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
353 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
354 decoding of SPARC ASIs.
355
53c4d625
JB		 3562017-02-23 Jan Beulich <jbeulich@suse.com>
357
358 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
359 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
360
11648de5
JB		 3612017-02-21 Jan Beulich <jbeulich@suse.com>
362
363 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
364 1 (instead of to itself). Correct typo.
365
f98d33be
AW		 3662017-02-14 Andrew Waterman <andrew@sifive.com>
367
368 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
369 pseudoinstructions.
370
773fb663
RS		 3712017-02-15 Richard Sandiford <richard.sandiford@arm.com>
372
373 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
374 (aarch64_sys_reg_supported_p): Handle them.
375
cc07cda6
CZ		 3762017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
377
378 * arc-opc.c (UIMM6_20R): Define.
379 (SIMM12_20): Use above.
380 (SIMM12_20R): Define.
381 (SIMM3_5_S): Use above.
382 (UIMM7_A32_11R_S): Define.
383 (UIMM7_9_S): Use above.
384 (UIMM3_13R_S): Define.
385 (SIMM11_A32_7_S): Use above.
386 (SIMM9_8R): Define.
387 (UIMM10_A32_8_S): Use above.
388 (UIMM8_8R_S): Define.
389 (W6): Use above.
390 (arc_relax_opcodes): Use all above defines.
391
66a5a740
VG		 3922017-02-15 Vineet Gupta <vgupta@synopsys.com>
393
394 * arc-regs.h: Distinguish some of the registers different on
395 ARC700 and HS38 cpus.
396
7e0de605
AM		 3972017-02-14 Alan Modra <amodra@gmail.com>
398
399 PR 21118
400 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
401 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
402
54064fdb
AM		 4032017-02-11 Stafford Horne <shorne@gmail.com>
404 Alan Modra <amodra@gmail.com>
405
406 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
407 Use insn_bytes_value and insn_int_value directly instead. Don't
408 free allocated memory until function exit.
409
dce75bf9
NP		 4102017-02-10 Nicholas Piggin <npiggin@gmail.com>
411
412 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
413
1b7e3d2f
NC		 4142017-02-03 Nick Clifton <nickc@redhat.com>
415
416 PR 21096
417 * aarch64-opc.c (print_register_list): Ensure that the register
418 list index will fir into the tb buffer.
419 (print_register_offset_address): Likewise.
420 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
421
8ec5cf65
AD		 4222017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
423
424 PR 21056
425 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
426 instructions when the previous fetch packet ends with a 32-bit
427 instruction.
428
a1aa5e81
DD		 4292017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
430
431 * pru-opc.c: Remove vague reference to a future GDB port.
432
add3afb2
NC		 4332017-01-20 Nick Clifton <nickc@redhat.com>
434
435 * po/ga.po: Updated Irish translation.
436
c13a63b0
SN		 4372017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
438
439 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
440
9608051a
YQ		 4412017-01-13 Yao Qi <yao.qi@linaro.org>
442
443 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
444 if FETCH_DATA returns 0.
445 (m68k_scan_mask): Likewise.
446 (print_insn_m68k): Update code to handle -1 return value.
447
f622ea96
YQ		 4482017-01-13 Yao Qi <yao.qi@linaro.org>
449
450 * m68k-dis.c (enum print_insn_arg_error): New.
451 (NEXTBYTE): Replace -3 with
452 PRINT_INSN_ARG_MEMORY_ERROR.
453 (NEXTULONG): Likewise.
454 (NEXTSINGLE): Likewise.
455 (NEXTDOUBLE): Likewise.
456 (NEXTDOUBLE): Likewise.
457 (NEXTPACKED): Likewise.
458 (FETCH_ARG): Likewise.
459 (FETCH_DATA): Update comments.
460 (print_insn_arg): Update comments. Replace magic numbers with
461 enum.
462 (match_insn_m68k): Likewise.
463
620214f7
IT		 4642017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
465
466 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
467 * i386-dis-evex.h (evex_table): Updated.
468 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
469 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
470 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
471 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
472 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
473 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
474 * i386-init.h: Regenerate.
475 * i386-tbl.h: Ditto.
476
d95014a2
YQ		 4772017-01-12 Yao Qi <yao.qi@linaro.org>
478
479 * msp430-dis.c (msp430_singleoperand): Return -1 if
480 msp430dis_opcode_signed returns false.
481 (msp430_doubleoperand): Likewise.
482 (msp430_branchinstr): Return -1 if
483 msp430dis_opcode_unsigned returns false.
484 (msp430x_calla_instr): Likewise.
485 (print_insn_msp430): Likewise.
486
0ae60c3e
NC		 4872017-01-05 Nick Clifton <nickc@redhat.com>
488
489 PR 20946
490 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
491 could not be matched.
492 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
493 NULL.
494
d74d4880
SN		 4952017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
496
497 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
498 (aarch64_opcode_table): Use RCPC_INSN.
499
cc917fd9
KC		 5002017-01-03 Kito Cheng <kito.cheng@gmail.com>
501
502 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
503 extension.
504 * riscv-opcodes/all-opcodes: Likewise.
505
b52d3cfc
DP		 5062017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
507
508 * riscv-dis.c (print_insn_args): Add fall through comment.
509
f90c58d5
NC		 5102017-01-03 Nick Clifton <nickc@redhat.com>
511
512 * po/sr.po: New Serbian translation.
513 * configure.ac (ALL_LINGUAS): Add sr.
514 * configure: Regenerate.
515
f47b0d4a
AM		 5162017-01-02 Alan Modra <amodra@gmail.com>
517
518 * epiphany-desc.h: Regenerate.
519 * epiphany-opc.h: Regenerate.
520 * fr30-desc.h: Regenerate.
521 * fr30-opc.h: Regenerate.
522 * frv-desc.h: Regenerate.
523 * frv-opc.h: Regenerate.
524 * ip2k-desc.h: Regenerate.
525 * ip2k-opc.h: Regenerate.
526 * iq2000-desc.h: Regenerate.
527 * iq2000-opc.h: Regenerate.
528 * lm32-desc.h: Regenerate.
529 * lm32-opc.h: Regenerate.
530 * m32c-desc.h: Regenerate.
531 * m32c-opc.h: Regenerate.
532 * m32r-desc.h: Regenerate.
533 * m32r-opc.h: Regenerate.
534 * mep-desc.h: Regenerate.
535 * mep-opc.h: Regenerate.
536 * mt-desc.h: Regenerate.
537 * mt-opc.h: Regenerate.
538 * or1k-desc.h: Regenerate.
539 * or1k-opc.h: Regenerate.
540 * xc16x-desc.h: Regenerate.
541 * xc16x-opc.h: Regenerate.
542 * xstormy16-desc.h: Regenerate.
543 * xstormy16-opc.h: Regenerate.
544
2571583a
AM		 5452017-01-02 Alan Modra <amodra@gmail.com>
546
547 Update year range in copyright notice of all files.
548
5c1ad6b5 549For older changes see ChangeLog-2016
3499769a 550\f
5c1ad6b5 551Copyright (C) 2017 Free Software Foundation, Inc.
3499769a
AM		 552
553Copying and distribution of this file, with or without modification,
554are permitted in any medium without royalty provided the copyright
555notice and this notice are preserved.
556
557Local Variables:
558mode: change-log
559left-margin: 8
560fill-column: 74
561version-control: never
562End:
GDB Binutils - Deliverables
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