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ubsan: csky: left shift cannot be represented in type 'int'
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
d93bba9e
AM		 12019-12-11 Alan Modra <amodra@gmail.com>
2
3 * csky-dis.c (csky_chars_to_number): Rewrite. Avoid signed
4 overflow when collecting bytes of a number.
5
c202f69e
AM		 62019-12-11 Alan Modra <amodra@gmail.com>
7
8 * cris-dis.c (print_with_operands): Avoid signed integer
9 overflow when collecting bytes of a 32-bit integer.
10
0ef562a4
AM		 112019-12-11 Alan Modra <amodra@gmail.com>
12
13 * cr16-dis.c (EXTRACT, SBM): Rewrite.
14 (cr16_match_opcode): Delete duplicate bcond test.
15
2fd2b153
AM		 162019-12-11 Alan Modra <amodra@gmail.com>
17
18 * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
19 (SIGNBIT): New.
20 (MASKBITS, SIGNEXTEND): Rewrite.
21 (fmtconst): Don't use ? expression now that SIGNEXTEND uses
22 unsigned arithmetic, instead assign result of SIGNEXTEND back
23 to x.
24 (fmtconst_val): Use 1u in shift expression.
25
a11db3e9
AM		 262019-12-11 Alan Modra <amodra@gmail.com>
27
28 * arc-dis.c (find_format_from_table): Use ull constant when
29 shifting by up to 32.
30
9d48687b
AM		 312019-12-11 Alan Modra <amodra@gmail.com>
32
33 PR 25270
34 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
35 false when field is zero for sve_size_tsz_bhs.
36
b8e61daa
AM		 372019-12-11 Alan Modra <amodra@gmail.com>
38
39 * epiphany-ibld.c: Regenerate.
40
20135676
AM		 412019-12-10 Alan Modra <amodra@gmail.com>
42
43 PR 24960
44 * disassemble.c (disassemble_free_target): New function.
45
103ebbc3
AM		 462019-12-10 Alan Modra <amodra@gmail.com>
47
48 * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
49 * disassemble.c (disassemble_init_for_target): Likewise.
50 * bpf-dis.c: Regenerate.
51 * epiphany-dis.c: Regenerate.
52 * fr30-dis.c: Regenerate.
53 * frv-dis.c: Regenerate.
54 * ip2k-dis.c: Regenerate.
55 * iq2000-dis.c: Regenerate.
56 * lm32-dis.c: Regenerate.
57 * m32c-dis.c: Regenerate.
58 * m32r-dis.c: Regenerate.
59 * mep-dis.c: Regenerate.
60 * mt-dis.c: Regenerate.
61 * or1k-dis.c: Regenerate.
62 * xc16x-dis.c: Regenerate.
63 * xstormy16-dis.c: Regenerate.
64
6f0e0752
AM		 652019-12-10 Alan Modra <amodra@gmail.com>
66
67 * ppc-dis.c (private): Delete variable.
68 (get_powerpc_dialect): Don't segfault on NULL info->private_data.
69 (powerpc_init_dialect): Don't use global private.
70
e7c22a69
AM		 712019-12-10 Alan Modra <amodra@gmail.com>
72
73 * s12z-opc.c: Formatting.
74
0a6aef6b
AM		 752019-12-08 Alan Modra <amodra@gmail.com>
76
77 * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
78 registers.
79
2dc4b12f
JB		 802019-12-05 Jan Beulich <jbeulich@suse.com>
81
82 * aarch64-tbl.h (aarch64_feature_crypto,
83 aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
84 CRYPTO_V8_2_INSN): Delete.
85
378fd436
AM		 862019-12-05 Alan Modra <amodra@gmail.com>
87
88 PR 25249
89 * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
90 (struct string_buf): New.
91 (strbuf): New function.
92 (get_field): Use strbuf rather than strdup of local temp.
93 (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
94 (get_field_rfsl, get_field_imm15): Likewise.
95 (get_field_rd, get_field_r1, get_field_r2): Update macros.
96 (get_field_special): Likewise. Don't strcpy spr. Formatting.
97 (print_insn_microblaze): Formatting. Init and pass string_buf to
98 get_field functions.
99
0ba59a29
JB		 1002019-12-04 Jan Beulich <jbeulich@suse.com>
101
102 * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
103 * i386-tbl.h: Re-generate.
104
77ad8092
JB		 1052019-12-04 Jan Beulich <jbeulich@suse.com>
106
107 * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
108
3036c899
JB		 1092019-12-04 Jan Beulich <jbeulich@suse.com>
110
111 * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
112 forms.
113 (xbegin): Drop DefaultSize.
114 * i386-tbl.h: Re-generate.
115
8b301fbb
MI		 1162019-11-22 Mihail Ionescu <mihail.ionescu@arm.com>
117
118 * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
119 Change the coproc CRC conditions to use the extension
120 feature set, second word, base on ARM_EXT2_CRC.
121
6aa385b9
JB		 1222019-11-14 Jan Beulich <jbeulich@suse.com>
123
124 * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
125 * i386-tbl.h: Re-generate.
126
0cfa3eb3
JB		 1272019-11-14 Jan Beulich <jbeulich@suse.com>
128
129 * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
130 JumpInterSegment, and JumpAbsolute entries.
131 * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
132 JUMP_ABSOLUTE): Define.
133 (struct i386_opcode_modifier): Extend jump field to 3 bits.
134 Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
135 fields.
136 * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
137 JumpInterSegment): Define.
138 * i386-tbl.h: Re-generate.
139
6f2f06be
JB		 1402019-11-14 Jan Beulich <jbeulich@suse.com>
141
142 * i386-gen.c (operand_type_init): Remove
143 OPERAND_TYPE_JUMPABSOLUTE entry.
144 (opcode_modifiers): Add JumpAbsolute entry.
145 (operand_types): Remove JumpAbsolute entry.
146 * i386-opc.h (JumpAbsolute): Move between enums.
147 (struct i386_opcode_modifier): Add jumpabsolute field.
148 (union i386_operand_type): Remove jumpabsolute field.
149 * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
150 * i386-init.h, i386-tbl.h: Re-generate.
151
601e8564
JB		 1522019-11-14 Jan Beulich <jbeulich@suse.com>
153
154 * i386-gen.c (opcode_modifiers): Add AnySize entry.
155 (operand_types): Remove AnySize entry.
156 * i386-opc.h (AnySize): Move between enums.
157 (struct i386_opcode_modifier): Add anysize field.
158 (OTUnused): Un-comment.
159 (union i386_operand_type): Remove anysize field.
160 * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
161 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
162 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
163 AnySize.
164 * i386-tbl.h: Re-generate.
165
7722d40a
JW		 1662019-11-12 Nelson Chu <nelson.chu@sifive.com>
167
168 * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
169 INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
170 use the floating point register (FPR).
171
ce760a76
MI		 1722019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
173
174 * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
175 cmode 1101.
176 (is_mve_encoding_conflict): Update cmode conflict checks for
177 MVE_VMVN_IMM.
178
51c8edf6
JB		 1792019-11-12 Jan Beulich <jbeulich@suse.com>
180
181 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
182 entry.
183 (operand_types): Remove EsSeg entry.
184 (main): Replace stale use of OTMax.
185 * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
186 (struct i386_opcode_modifier): Expand isstring field to 2 bits.
187 (EsSeg): Delete.
188 (OTUnused): Comment out.
189 (union i386_operand_type): Remove esseg field.
190 * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
191 (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
192 (ins, movs, smov, movsd): Add IsStringEsOpOp1.
193 (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
194 * i386-init.h, i386-tbl.h: Re-generate.
195
474da251
JB		 1962019-11-12 Jan Beulich <jbeulich@suse.com>
197
198 * i386-gen.c (operand_instances): Add RegB entry.
199 * i386-opc.h (enum operand_instance): Add RegB.
200 * i386-opc.tbl (RegC, RegD, RegB): Define.
201 (Acc, ShiftCount, InOutPortReg): Adjust definitions.
202 (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
203 monitorx, mwaitx): Drop ImmExt and convert encodings
204 accordingly.
205 * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
206 (edx, rdx): Add Instance=RegD.
207 (ebx, rbx): Add Instance=RegB.
208 * i386-tbl.h: Re-generate.
209
75e5731b
JB		 2102019-11-12 Jan Beulich <jbeulich@suse.com>
211
212 * i386-gen.c (operand_type_init): Adjust
213 OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
214 OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
215 OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
216 (operand_instances): New.
217 (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
218 (output_operand_type): New parameter "instance". Process it.
219 (process_i386_operand_type): New local variable "instance".
220 (main): Adjust static assertions.
221 * i386-opc.h (INSTANCE_WIDTH): Define.
222 (enum operand_instance): New.
223 (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
224 (union i386_operand_type): Replace acc, inoutportreg, and
225 shiftcount by instance.
226 * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
227 * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
228 Add Instance=.
229 * i386-init.h, i386-tbl.h: Re-generate.
230
91802f3c
JB		 2312019-11-11 Jan Beulich <jbeulich@suse.com>
232
233 * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
234 smaxp/sminp entries' "tied_operand" field to 2.
235
4f5fc85d
JB		 2362019-11-11 Jan Beulich <jbeulich@suse.com>
237
238 * aarch64-opc.c (operand_general_constraint_met_p): Replace
239 "index" local variable by that of the already existing "num".
240
dc2be329
L		 2412019-11-08 H.J. Lu <hongjiu.lu@intel.com>
242
243 PR gas/25167
244 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
245 * i386-tbl.h: Regenerated.
246
f74a6307
JB		 2472019-11-08 Jan Beulich <jbeulich@suse.com>
248
249 * i386-gen.c (operand_type_init): Add Class= to
250 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
251 OPERAND_TYPE_REGBND entry.
252 (operand_classes): Add RegMask and RegBND entries.
253 (operand_types): Drop RegMask and RegBND entry.
254 * i386-opc.h (enum operand_class): Add RegMask and RegBND.
255 (RegMask, RegBND): Delete.
256 (union i386_operand_type): Remove regmask and regbnd fields.
257 * i386-opc.tbl (RegMask, RegBND): Define.
258 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
259 Class=RegBND.
260 * i386-init.h, i386-tbl.h: Re-generate.
261
3528c362
JB		 2622019-11-08 Jan Beulich <jbeulich@suse.com>
263
264 * i386-gen.c (operand_type_init): Add Class= to
265 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
266 OPERAND_TYPE_REGZMM entries.
267 (operand_classes): Add RegMMX and RegSIMD entries.
268 (operand_types): Drop RegMMX and RegSIMD entries.
269 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
270 (RegMMX, RegSIMD): Delete.
271 (union i386_operand_type): Remove regmmx and regsimd fields.
272 * i386-opc.tbl (RegMMX): Define.
273 (RegXMM, RegYMM, RegZMM): Add Class=.
274 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
275 Class=RegSIMD.
276 * i386-init.h, i386-tbl.h: Re-generate.
277
4a5c67ed
JB		 2782019-11-08 Jan Beulich <jbeulich@suse.com>
279
280 * i386-gen.c (operand_type_init): Add Class= to
281 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
282 entries.
283 (operand_classes): Add RegCR, RegDR, and RegTR entries.
284 (operand_types): Drop Control, Debug, and Test entries.
285 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
286 (Control, Debug, Test): Delete.
287 (union i386_operand_type): Remove control, debug, and test
288 fields.
289 * i386-opc.tbl (Control, Debug, Test): Define.
290 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
291 Class=RegDR, and Test by Class=RegTR.
292 * i386-init.h, i386-tbl.h: Re-generate.
293
00cee14f
JB		 2942019-11-08 Jan Beulich <jbeulich@suse.com>
295
296 * i386-gen.c (operand_type_init): Add Class= to
297 OPERAND_TYPE_SREG entry.
298 (operand_classes): Add SReg entry.
299 (operand_types): Drop SReg entry.
300 * i386-opc.h (enum operand_class): Add SReg.
301 (SReg): Delete.
302 (union i386_operand_type): Remove sreg field.
303 * i386-opc.tbl (SReg): Define.
304 * i386-reg.tbl: Replace SReg by Class=SReg.
305 * i386-init.h, i386-tbl.h: Re-generate.
306
bab6aec1
JB		 3072019-11-08 Jan Beulich <jbeulich@suse.com>
308
309 * i386-gen.c (operand_type_init): Add Class=. New
310 OPERAND_TYPE_ANYIMM entry.
311 (operand_classes): New.
312 (operand_types): Drop Reg entry.
313 (output_operand_type): New parameter "class". Process it.
314 (process_i386_operand_type): New local variable "class".
315 (main): Adjust static assertions.
316 * i386-opc.h (CLASS_WIDTH): Define.
317 (enum operand_class): New.
318 (Reg): Replace by Class. Adjust comment.
319 (union i386_operand_type): Replace reg by class.
320 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
321 Class=.
322 * i386-reg.tbl: Replace Reg by Class=Reg.
323 * i386-init.h: Re-generate.
324
1f4cd317
MM		 3252019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
326
327 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
328 (aarch64_opcode_table): Add data gathering hint mnemonic.
329 * opcodes/aarch64-dis-2.c: Account for new instruction.
330
616ce08e
MM		 3312019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
332
333 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
334
335
8382113f
MM		 3362019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
337
338 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
339 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
340 aarch64_feature_f64mm): New feature sets.
341 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
342 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
343 instructions.
344 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
345 macros.
346 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
347 (OP_SVE_QQQ): New qualifier.
348 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
349 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
350 the movprfx constraint.
351 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
352 (aarch64_opcode_table): Define new instructions smmla,
353 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
354 uzip{1/2}, trn{1/2}.
355 * aarch64-opc.c (operand_general_constraint_met_p): Handle
356 AARCH64_OPND_SVE_ADDR_RI_S4x32.
357 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
358 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
359 Account for new instructions.
360 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
361 S4x32 operand.
362 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
363
aab2c27d
MM		 3642019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
3652019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
366
367 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
368 Armv8.6-A.
369 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
370 (neon_opcodes): Add bfloat SIMD instructions.
371 (print_insn_coprocessor): Add new control character %b to print
372 condition code without checking cp_num.
373 (print_insn_neon): Account for BFloat16 instructions that have no
374 special top-byte handling.
375
33593eaf
MM		 3762019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
3772019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
378
379 * arm-dis.c (print_insn_coprocessor,
380 print_insn_generic_coprocessor): Create wrapper functions around
381 the implementation of the print_insn_coprocessor control codes.
382 (print_insn_coprocessor_1): Original print_insn_coprocessor
383 function that now takes which array to look at as an argument.
384 (print_insn_arm): Use both print_insn_coprocessor and
385 print_insn_generic_coprocessor.
386 (print_insn_thumb32): As above.
387
df678013
MM		 3882019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
3892019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
390
391 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
392 in reglane special case.
393 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
394 aarch64_find_next_opcode): Account for new instructions.
395 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
396 in reglane special case.
397 * aarch64-opc.c (struct operand_qualifier_data): Add data for
398 new AARCH64_OPND_QLF_S_2H qualifier.
399 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
400 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
401 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
402 sets.
403 (BFLOAT_SVE, BFLOAT): New feature set macros.
404 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
405 instructions.
406 (aarch64_opcode_table): Define new instructions bfdot,
407 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
408 bfcvtn2, bfcvt.
409
8ae2d3d9
MM		 4102019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
4112019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
412
413 * aarch64-tbl.h (ARMV8_6): New macro.
414
142861df
JB		 4152019-11-07 Jan Beulich <jbeulich@suse.com>
416
417 * i386-dis.c (prefix_table): Add mcommit.
418 (rm_table): Add rdpru.
419 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
420 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
421 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
422 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
423 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
424 * i386-opc.tbl (mcommit, rdpru): New.
425 * i386-init.h, i386-tbl.h: Re-generate.
426
081e283f
JB		 4272019-11-07 Jan Beulich <jbeulich@suse.com>
428
429 * i386-dis.c (OP_Mwait): Drop local variable "names", use
430 "names32" instead.
431 (OP_Monitor): Drop local variable "op1_names", re-purpose
432 "names" for it instead, and replace former "names" uses by
433 "names32" ones.
434
c050c89a
JB		 4352019-11-07 Jan Beulich <jbeulich@suse.com>
436
437 PR/gas 25167
438 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
439 operand-less forms.
440 * opcodes/i386-tbl.h: Re-generate.
441
7abb8d81
JB		 4422019-11-05 Jan Beulich <jbeulich@suse.com>
443
444 * i386-dis.c (OP_Mwaitx): Delete.
445 (prefix_table): Use OP_Mwait for mwaitx entry.
446 (OP_Mwait): Also handle mwaitx.
447
267b8516
JB		 4482019-11-05 Jan Beulich <jbeulich@suse.com>
449
450 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
451 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
452 (prefix_table): Add respective entries.
453 (rm_table): Link to those entries.
454
f8687e93
JB		 4552019-11-05 Jan Beulich <jbeulich@suse.com>
456
457 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
458 (REG_0F1C_P_0_MOD_0): ... this.
459 (REG_0F1E_MOD_3): Rename to ...
460 (REG_0F1E_P_1_MOD_3): ... this.
461 (RM_0F01_REG_5): Rename to ...
462 (RM_0F01_REG_5_MOD_3): ... this.
463 (RM_0F01_REG_7): Rename to ...
464 (RM_0F01_REG_7_MOD_3): ... this.
465 (RM_0F1E_MOD_3_REG_7): Rename to ...
466 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
467 (RM_0FAE_REG_6): Rename to ...
468 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
469 (RM_0FAE_REG_7): Rename to ...
470 (RM_0FAE_REG_7_MOD_3): ... this.
471 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
472 (PREFIX_0F01_REG_5_MOD_0): ... this.
473 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
474 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
475 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
476 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
477 (PREFIX_0FAE_REG_0): Rename to ...
478 (PREFIX_0FAE_REG_0_MOD_3): ... this.
479 (PREFIX_0FAE_REG_1): Rename to ...
480 (PREFIX_0FAE_REG_1_MOD_3): ... this.
481 (PREFIX_0FAE_REG_2): Rename to ...
482 (PREFIX_0FAE_REG_2_MOD_3): ... this.
483 (PREFIX_0FAE_REG_3): Rename to ...
484 (PREFIX_0FAE_REG_3_MOD_3): ... this.
485 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
486 (PREFIX_0FAE_REG_4_MOD_0): ... this.
487 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
488 (PREFIX_0FAE_REG_4_MOD_3): ... this.
489 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
490 (PREFIX_0FAE_REG_5_MOD_0): ... this.
491 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
492 (PREFIX_0FAE_REG_5_MOD_3): ... this.
493 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
494 (PREFIX_0FAE_REG_6_MOD_0): ... this.
495 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
496 (PREFIX_0FAE_REG_6_MOD_3): ... this.
497 (PREFIX_0FAE_REG_7): Rename to ...
498 (PREFIX_0FAE_REG_7_MOD_0): ... this.
499 (PREFIX_MOD_0_0FC3): Rename to ...
500 (PREFIX_0FC3_MOD_0): ... this.
501 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
502 (PREFIX_0FC7_REG_6_MOD_0): ... this.
503 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
504 (PREFIX_0FC7_REG_6_MOD_3): ... this.
505 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
506 (PREFIX_0FC7_REG_7_MOD_3): ... this.
507 (reg_table, prefix_table, mod_table, rm_table): Adjust
508 accordingly.
509
5103274f
NC		 5102019-11-04 Nick Clifton <nickc@redhat.com>
511
512 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
513 of a v850 system register. Move the v850_sreg_names array into
514 this function.
515 (get_v850_reg_name): Likewise for ordinary register names.
516 (get_v850_vreg_name): Likewise for vector register names.
517 (get_v850_cc_name): Likewise for condition codes.
518 * get_v850_float_cc_name): Likewise for floating point condition
519 codes.
520 (get_v850_cacheop_name): Likewise for cache-ops.
521 (get_v850_prefop_name): Likewise for pref-ops.
522 (disassemble): Use the new accessor functions.
523
1820262b
DB		 5242019-10-30 Delia Burduv <delia.burduv@arm.com>
525
526 * aarch64-opc.c (print_immediate_offset_address): Don't print the
527 immediate for the writeback form of ldraa/ldrab if it is 0.
528 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
529 * aarch64-opc-2.c: Regenerated.
530
3cc17af5
JB		 5312019-10-30 Jan Beulich <jbeulich@suse.com>
532
533 * i386-gen.c (operand_type_shorthands): Delete.
534 (operand_type_init): Expand previous shorthands.
535 (set_bitfield_from_shorthand): Rename back to ...
536 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
537 of operand_type_init[].
538 (set_bitfield): Adjust call to the above function.
539 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
540 RegXMM, RegYMM, RegZMM): Define.
541 * i386-reg.tbl: Expand prior shorthands.
542
a2cebd03
JB		 5432019-10-30 Jan Beulich <jbeulich@suse.com>
544
545 * i386-gen.c (output_i386_opcode): Change order of fields
546 emitted to output.
547 * i386-opc.h (struct insn_template): Move operands field.
548 Convert extension_opcode field to unsigned short.
549 * i386-tbl.h: Re-generate.
550
507916b8
JB		 5512019-10-30 Jan Beulich <jbeulich@suse.com>
552
553 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
554 of W.
555 * i386-opc.h (W): Extend comment.
556 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
557 general purpose variants not allowing for byte operands.
558 * i386-tbl.h: Re-generate.
559
efea62b4
NC		 5602019-10-29 Nick Clifton <nickc@redhat.com>
561
562 * tic30-dis.c (print_branch): Correct size of operand array.
563
9adb2591
NC		 5642019-10-29 Nick Clifton <nickc@redhat.com>
565
566 * d30v-dis.c (print_insn): Check that operand index is valid
567 before attempting to access the operands array.
568
993a00a9
NC		 5692019-10-29 Nick Clifton <nickc@redhat.com>
570
571 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
572 locating the bit to be tested.
573
66a66a17
NC		 5742019-10-29 Nick Clifton <nickc@redhat.com>
575
576 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
577 values.
578 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
579 (print_insn_s12z): Check for illegal size values.
580
1ee3542c
NC		 5812019-10-28 Nick Clifton <nickc@redhat.com>
582
583 * csky-dis.c (csky_chars_to_number): Check for a negative
584 count. Use an unsigned integer to construct the return value.
585
bbf9a0b5
NC		 5862019-10-28 Nick Clifton <nickc@redhat.com>
587
588 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
589 operand buffer. Set value to 15 not 13.
590 (get_register_operand): Use OPERAND_BUFFER_LEN.
591 (get_indirect_operand): Likewise.
592 (print_two_operand): Likewise.
593 (print_three_operand): Likewise.
594 (print_oar_insn): Likewise.
595
d1e304bc
NC		 5962019-10-28 Nick Clifton <nickc@redhat.com>
597
598 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
599 (bit_extract_simple): Likewise.
600 (bit_copy): Likewise.
601 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
602 index_offset array are not accessed.
603
dee33451
NC		 6042019-10-28 Nick Clifton <nickc@redhat.com>
605
606 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
607 operand.
608
27cee81d
NC		 6092019-10-25 Nick Clifton <nickc@redhat.com>
610
611 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
612 access to opcodes.op array element.
613
de6d8dc2
NC		 6142019-10-23 Nick Clifton <nickc@redhat.com>
615
616 * rx-dis.c (get_register_name): Fix spelling typo in error
617 message.
618 (get_condition_name, get_flag_name, get_double_register_name)
619 (get_double_register_high_name, get_double_register_low_name)
620 (get_double_control_register_name, get_double_condition_name)
621 (get_opsize_name, get_size_name): Likewise.
622
6207ed28
NC		 6232019-10-22 Nick Clifton <nickc@redhat.com>
624
625 * rx-dis.c (get_size_name): New function. Provides safe
626 access to name array.
627 (get_opsize_name): Likewise.
628 (print_insn_rx): Use the accessor functions.
629
12234dfd
NC		 6302019-10-16 Nick Clifton <nickc@redhat.com>
631
632 * rx-dis.c (get_register_name): New function. Provides safe
633 access to name array.
634 (get_condition_name, get_flag_name, get_double_register_name)
635 (get_double_register_high_name, get_double_register_low_name)
636 (get_double_control_register_name, get_double_condition_name):
637 Likewise.
638 (print_insn_rx): Use the accessor functions.
639
1d378749
NC		 6402019-10-09 Nick Clifton <nickc@redhat.com>
641
642 PR 25041
643 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
644 instructions.
645
d241b910
JB		 6462019-10-07 Jan Beulich <jbeulich@suse.com>
647
648 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
649 (cmpsd): Likewise. Move EsSeg to other operand.
650 * opcodes/i386-tbl.h: Re-generate.
651
f5c5b7c1
AM		 6522019-09-23 Alan Modra <amodra@gmail.com>
653
654 * m68k-dis.c: Include cpu-m68k.h
655
7beeaeb8
AM		 6562019-09-23 Alan Modra <amodra@gmail.com>
657
658 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
659 "elf/mips.h" earlier.
660
3f9aad11
JB		 6612018-09-20 Jan Beulich <jbeulich@suse.com>
662
663 PR gas/25012
664 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
665 with SReg operand.
666 * i386-tbl.h: Re-generate.
667
fd361982
AM		 6682019-09-18 Alan Modra <amodra@gmail.com>
669
670 * arc-ext.c: Update throughout for bfd section macro changes.
671
e0b2a78c
SM		 6722019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
673
674 * Makefile.in: Re-generate.
675 * configure: Re-generate.
676
7e9ad3a3
JW		 6772019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
678
679 * riscv-opc.c (riscv_opcodes): Change subset field
680 to insn_class field for all instructions.
681 (riscv_insn_types): Likewise.
682
bb695960
PB		 6832019-09-16 Phil Blundell <pb@pbcl.net>
684
685 * configure: Regenerated.
686
8063ab7e
MV		 6872019-09-10 Miod Vallat <miod@online.fr>
688
689 PR 24982
690 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
691
60391a25
PB		 6922019-09-09 Phil Blundell <pb@pbcl.net>
693
694 binutils 2.33 branch created.
695
f44b758d
NC		 6962019-09-03 Nick Clifton <nickc@redhat.com>
697
698 PR 24961
699 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
700 greater than zero before indexing via (bufcnt -1).
701
1e4b5e7d
NC		 7022019-09-03 Nick Clifton <nickc@redhat.com>
703
704 PR 24958
705 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
706 (MAX_SPEC_REG_NAME_LEN): Define.
707 (struct mmix_dis_info): Use defined constants for array lengths.
708 (get_reg_name): New function.
709 (get_sprec_reg_name): New function.
710 (print_insn_mmix): Use new functions.
711
c4a23bf8
SP		 7122019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
713
714 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
715 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
716 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
717
a051e2f3
KT		 7182019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
719
720 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
721 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
722 (aarch64_sys_reg_supported_p): Update checks for the above.
723
08132bdd
SP		 7242019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
725
726 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
727 cases MVE_SQRSHRL and MVE_UQRSHLL.
728 (print_insn_mve): Add case for specifier 'k' to check
729 specific bit of the instruction.
730
d88bdcb4
PA		 7312019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
732
733 PR 24854
734 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
735 encountering an unknown machine type.
736 (print_insn_arc): Handle arc_insn_length returning 0. In error
737 cases return -1 rather than calling abort.
738
bc750500
JB		 7392019-08-07 Jan Beulich <jbeulich@suse.com>
740
741 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
742 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
743 IgnoreSize.
744 * i386-tbl.h: Re-generate.
745
23d188c7
BW		 7462019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
747
748 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
749 instructions.
750
c0d6f62f
JW		 7512019-07-30 Mel Chen <mel.chen@sifive.com>
752
753 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
754 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
755
756 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
757 fscsr.
758
0f3f7167
CZ		 7592019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
760
761 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
762 and MPY class instructions.
763 (parse_option): Add nps400 option.
764 (print_arc_disassembler_options): Add nps400 info.
765
7e126ba3
CZ		 7662019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
767
768 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
769 (bspop): Likewise.
770 (modapp): Likewise.
771 * arc-opc.c (RAD_CHK): Add.
772 * arc-tbl.h: Regenerate.
773
a028026d
KT		 7742019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
775
776 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
777 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
778
ac79ff9e
NC		 7792019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
780
781 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
782 instructions as UNPREDICTABLE.
783
231097b0
JM		 7842019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
785
786 * bpf-desc.c: Regenerated.
787
1d942ae9
JB		 7882019-07-17 Jan Beulich <jbeulich@suse.com>
789
790 * i386-gen.c (static_assert): Define.
791 (main): Use it.
792 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
793 (Opcode_Modifier_Num): ... this.
794 (Mem): Delete.
795
dfd69174
JB		 7962019-07-16 Jan Beulich <jbeulich@suse.com>
797
798 * i386-gen.c (operand_types): Move RegMem ...
799 (opcode_modifiers): ... here.
800 * i386-opc.h (RegMem): Move to opcode modifer enum.
801 (union i386_operand_type): Move regmem field ...
802 (struct i386_opcode_modifier): ... here.
803 * i386-opc.tbl (RegMem): Define.
804 (mov, movq): Move RegMem on segment, control, debug, and test
805 register flavors.
806 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
807 to non-SSE2AVX flavor.
808 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
809 Move RegMem on register only flavors. Drop IgnoreSize from
810 legacy encoding flavors.
811 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
812 flavors.
813 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
814 register only flavors.
815 (vmovd): Move RegMem and drop IgnoreSize on register only
816 flavor. Change opcode and operand order to store form.
817 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
818
21df382b
JB		 8192019-07-16 Jan Beulich <jbeulich@suse.com>
820
821 * i386-gen.c (operand_type_init, operand_types): Replace SReg
822 entries.
823 * i386-opc.h (SReg2, SReg3): Replace by ...
824 (SReg): ... this.
825 (union i386_operand_type): Replace sreg fields.
826 * i386-opc.tbl (mov, ): Use SReg.
827 (push, pop): Likewies. Drop i386 and x86-64 specific segment
828 register flavors.
829 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
830 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
831
3719fd55
JM		 8322019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
833
834 * bpf-desc.c: Regenerate.
835 * bpf-opc.c: Likewise.
836 * bpf-opc.h: Likewise.
837
92434a14
JM		 8382019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
839
840 * bpf-desc.c: Regenerate.
841 * bpf-opc.c: Likewise.
842
43dd7626
HPN		 8432019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
844
845 * arm-dis.c (print_insn_coprocessor): Rename index to
846 index_operand.
847
98602811
JW		 8482019-07-05 Kito Cheng <kito.cheng@sifive.com>
849
850 * riscv-opc.c (riscv_insn_types): Add r4 type.
851
852 * riscv-opc.c (riscv_insn_types): Add b and j type.
853
854 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
855 format for sb type and correct s type.
856
01c1ee4a
RS		 8572019-07-02 Richard Sandiford <richard.sandiford@arm.com>
858
859 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
860 SVE FMOV alias of FCPY.
861
83adff69
RS		 8622019-07-02 Richard Sandiford <richard.sandiford@arm.com>
863
864 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
865 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
866
89418844
RS		 8672019-07-02 Richard Sandiford <richard.sandiford@arm.com>
868
869 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
870 registers in an instruction prefixed by MOVPRFX.
871
41be57ca
MM		 8722019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
873
874 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
875 sve_size_13 icode to account for variant behaviour of
876 pmull{t,b}.
877 * aarch64-dis-2.c: Regenerate.
878 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
879 sve_size_13 icode to account for variant behaviour of
880 pmull{t,b}.
881 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
882 (OP_SVE_VVV_Q_D): Add new qualifier.
883 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
884 (struct aarch64_opcode): Split pmull{t,b} into those requiring
885 AES and those not.
886
9d3bf266
JB		 8872019-07-01 Jan Beulich <jbeulich@suse.com>
888
889 * opcodes/i386-gen.c (operand_type_init): Remove
890 OPERAND_TYPE_VEC_IMM4 entry.
891 (operand_types): Remove Vec_Imm4.
892 * opcodes/i386-opc.h (Vec_Imm4): Delete.
893 (union i386_operand_type): Remove vec_imm4.
894 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
895 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
896
c3949f43
JB		 8972019-07-01 Jan Beulich <jbeulich@suse.com>
898
899 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
900 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
901 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
902 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
903 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
904 monitorx, mwaitx): Drop ImmExt from operand-less forms.
905 * i386-tbl.h: Re-generate.
906
5641ec01
JB		 9072019-07-01 Jan Beulich <jbeulich@suse.com>
908
909 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
910 register operands.
911 * i386-tbl.h: Re-generate.
912
79dec6b7
JB		 9132019-07-01 Jan Beulich <jbeulich@suse.com>
914
915 * i386-opc.tbl (C): New.
916 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
917 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
918 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
919 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
920 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
921 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
922 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
923 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
924 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
925 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
926 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
927 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
928 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
929 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
930 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
931 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
932 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
933 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
934 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
935 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
936 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
937 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
938 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
939 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
940 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
941 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
942 flavors.
943 * i386-tbl.h: Re-generate.
944
a0a1771e
JB		 9452019-07-01 Jan Beulich <jbeulich@suse.com>
946
947 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
948 register operands.
949 * i386-tbl.h: Re-generate.
950
cd546e7b
JB		 9512019-07-01 Jan Beulich <jbeulich@suse.com>
952
953 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
954 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
955 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
956 * i386-tbl.h: Re-generate.
957
e3bba3fc
JB		 9582019-07-01 Jan Beulich <jbeulich@suse.com>
959
960 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
961 Disp8MemShift from register only templates.
962 * i386-tbl.h: Re-generate.
963
36cc073e
JB		 9642019-07-01 Jan Beulich <jbeulich@suse.com>
965
966 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
967 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
968 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
969 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
970 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
971 EVEX_W_0F11_P_3_M_1): Delete.
972 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
973 EVEX_W_0F11_P_3): New.
974 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
975 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
976 MOD_EVEX_0F11_PREFIX_3 table entries.
977 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
978 PREFIX_EVEX_0F11 table entries.
979 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
980 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
981 EVEX_W_0F11_P_3_M_{0,1} table entries.
982
219920a7
JB		 9832019-07-01 Jan Beulich <jbeulich@suse.com>
984
985 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
986 Delete.
987
e395f487
L		 9882019-06-27 H.J. Lu <hongjiu.lu@intel.com>
989
990 PR binutils/24719
991 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
992 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
993 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
994 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
995 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
996 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
997 EVEX_LEN_0F38C7_R_6_P_2_W_1.
998 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
999 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
1000 PREFIX_EVEX_0F38C6_REG_6 entries.
1001 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
1002 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
1003 EVEX_W_0F38C7_R_6_P_2 entries.
1004 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1005 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1006 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1007 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1008 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1009 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1010 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
1011
2b7bcc87
JB		 10122019-06-27 Jan Beulich <jbeulich@suse.com>
1013
1014 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1015 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1016 VEX_LEN_0F2D_P_3): Delete.
1017 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1018 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1019 (prefix_table): ... here.
1020
c1dc7af5
JB		 10212019-06-27 Jan Beulich <jbeulich@suse.com>
1022
1023 * i386-dis.c (Iq): Delete.
1024 (Id): New.
1025 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1026 TBM insns.
1027 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1028 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1029 (OP_E_memory): Also honor needindex when deciding whether an
1030 address size prefix needs printing.
1031 (OP_I): Remove handling of q_mode. Add handling of d_mode.
1032
d7560e2d
JW		 10332019-06-26 Jim Wilson <jimw@sifive.com>
1034
1035 PR binutils/24739
1036 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1037 Set info->display_endian to info->endian_code.
1038
2c703856
JB		 10392019-06-25 Jan Beulich <jbeulich@suse.com>
1040
1041 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1042 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1043 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1044 OPERAND_TYPE_ACC64 entries.
1045 * i386-init.h: Re-generate.
1046
54fbadc0
JB		 10472019-06-25 Jan Beulich <jbeulich@suse.com>
1048
1049 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1050 Delete.
1051 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1052 of dqa_mode.
1053 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1054 entries here.
1055 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1056 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1057
a280ab8e
JB		 10582019-06-25 Jan Beulich <jbeulich@suse.com>
1059
1060 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1061 variables.
1062
e1a1babd
JB		 10632019-06-25 Jan Beulich <jbeulich@suse.com>
1064
1065 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1066 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1067 movnti.
d7560e2d 1068 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 1069 * i386-tbl.h: Re-generate.
1070
b8364fa7
JB		 10712019-06-25 Jan Beulich <jbeulich@suse.com>
1072
1073 * i386-opc.tbl (and): Mark Imm8S form for optimization.
1074 * i386-tbl.h: Re-generate.
1075
ad692897
L		 10762019-06-21 H.J. Lu <hongjiu.lu@intel.com>
1077
1078 * i386-dis-evex.h: Break into ...
1079 * i386-dis-evex-len.h: New file.
1080 * i386-dis-evex-mod.h: Likewise.
1081 * i386-dis-evex-prefix.h: Likewise.
1082 * i386-dis-evex-reg.h: Likewise.
1083 * i386-dis-evex-w.h: Likewise.
1084 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1085 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1086 i386-dis-evex-mod.h.
1087
f0a6222e
L		 10882019-06-19 H.J. Lu <hongjiu.lu@intel.com>
1089
1090 PR binutils/24700
1091 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1092 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1093 EVEX_W_0F385B_P_2.
1094 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1095 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1096 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1097 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1098 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1099 EVEX_LEN_0F385B_P_2_W_1.
1100 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1101 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1102 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1103 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1104 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1105 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1106 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1107 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1108 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1109 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1110
6e1c90b7
L		 11112019-06-17 H.J. Lu <hongjiu.lu@intel.com>
1112
1113 PR binutils/24691
1114 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1115 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1116 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1117 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1118 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1119 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1120 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1121 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1122 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1123 EVEX_LEN_0F3A43_P_2_W_1.
1124 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1125 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1126 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1127 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1128 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1129 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1130 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1131 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1132 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1133 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1134 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1135 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1136
bcc5a6eb
NC		 11372019-06-14 Nick Clifton <nickc@redhat.com>
1138
1139 * po/fr.po; Updated French translation.
1140
e4c4ac46
SH		 11412019-06-13 Stafford Horne <shorne@gmail.com>
1142
1143 * or1k-asm.c: Regenerated.
1144 * or1k-desc.c: Regenerated.
1145 * or1k-desc.h: Regenerated.
1146 * or1k-dis.c: Regenerated.
1147 * or1k-ibld.c: Regenerated.
1148 * or1k-opc.c: Regenerated.
1149 * or1k-opc.h: Regenerated.
1150 * or1k-opinst.c: Regenerated.
1151
a0e44ef5
PB		 11522019-06-12 Peter Bergner <bergner@linux.ibm.com>
1153
1154 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1155
12efd68d
L		 11562019-06-05 H.J. Lu <hongjiu.lu@intel.com>
1157
1158 PR binutils/24633
1159 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1160 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1161 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1162 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1163 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1164 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1165 EVEX_LEN_0F3A1B_P_2_W_1.
1166 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1167 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1168 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1169 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1170 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1171 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1172 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1173 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1174
63c6fc6c
L		 11752019-06-04 H.J. Lu <hongjiu.lu@intel.com>
1176
1177 PR binutils/24626
1178 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1179 EVEX.vvvv when disassembling VEX and EVEX instructions.
1180 (OP_VEX): Set vex.register_specifier to 0 after readding
1181 vex.register_specifier.
1182 (OP_Vex_2src_1): Likewise.
1183 (OP_Vex_2src_2): Likewise.
1184 (OP_LWP_E): Likewise.
1185 (OP_EX_Vex): Don't check vex.register_specifier.
1186 (OP_XMM_Vex): Likewise.
1187
9186c494
L		 11882019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1189 Lili Cui <lili.cui@intel.com>
1190
1191 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1192 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1193 instructions.
1194 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1195 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1196 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1197 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1198 (i386_cpu_flags): Add cpuavx512_vp2intersect.
1199 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1200 * i386-init.h: Regenerated.
1201 * i386-tbl.h: Likewise.
1202
5d79adc4
L		 12032019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
1204 Lili Cui <lili.cui@intel.com>
1205
1206 * doc/c-i386.texi: Document enqcmd.
1207 * testsuite/gas/i386/enqcmd-intel.d: New file.
1208 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1209 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1210 * testsuite/gas/i386/enqcmd.d: Likewise.
1211 * testsuite/gas/i386/enqcmd.s: Likewise.
1212 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1213 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1214 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1215 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1216 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1217 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1218 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1219 and x86-64-enqcmd.
1220
a9d96ab9
AH		 12212019-06-04 Alan Hayward <alan.hayward@arm.com>
1222
1223 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1224
4f6d070a
AM		 12252019-06-03 Alan Modra <amodra@gmail.com>
1226
1227 * ppc-dis.c (prefix_opcd_indices): Correct size.
1228
a2f4b66c
L		 12292019-05-28 H.J. Lu <hongjiu.lu@intel.com>
1230
1231 PR gas/24625
1232 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1233 Disp8ShiftVL.
1234 * i386-tbl.h: Regenerated.
1235
405b5bd8
AM		 12362019-05-24 Alan Modra <amodra@gmail.com>
1237
1238 * po/POTFILES.in: Regenerate.
1239
8acf1435
PB		 12402019-05-24 Peter Bergner <bergner@linux.ibm.com>
1241 Alan Modra <amodra@gmail.com>
1242
1243 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1244 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1245 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1246 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1247 XTOP>): Define and add entries.
1248 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1249 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1250 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1251 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1252
dd7efa79
PB		 12532019-05-24 Peter Bergner <bergner@linux.ibm.com>
1254 Alan Modra <amodra@gmail.com>
1255
1256 * ppc-dis.c (ppc_opts): Add "future" entry.
1257 (PREFIX_OPCD_SEGS): Define.
1258 (prefix_opcd_indices): New array.
1259 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1260 (lookup_prefix): New function.
1261 (print_insn_powerpc): Handle 64-bit prefix instructions.
1262 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1263 (PMRR, POWERXX): Define.
1264 (prefix_opcodes): New instruction table.
1265 (prefix_num_opcodes): New constant.
1266
79472b45
JM		 12672019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
1268
1269 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1270 * configure: Regenerated.
1271 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1272 and cpu/bpf.opc.
1273 (HFILES): Add bpf-desc.h and bpf-opc.h.
1274 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1275 bpf-ibld.c and bpf-opc.c.
1276 (BPF_DEPS): Define.
1277 * Makefile.in: Regenerated.
1278 * disassemble.c (ARCH_bpf): Define.
1279 (disassembler): Add case for bfd_arch_bpf.
1280 (disassemble_init_for_target): Likewise.
1281 (enum epbf_isa_attr): Define.
1282 * disassemble.h: extern print_insn_bpf.
1283 * bpf-asm.c: Generated.
1284 * bpf-opc.h: Likewise.
1285 * bpf-opc.c: Likewise.
1286 * bpf-ibld.c: Likewise.
1287 * bpf-dis.c: Likewise.
1288 * bpf-desc.h: Likewise.
1289 * bpf-desc.c: Likewise.
1290
ba6cd17f
SD		 12912019-05-21 Sudakshina Das <sudi.das@arm.com>
1292
1293 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1294 and VMSR with the new operands.
1295
e39c1607
SD		 12962019-05-21 Sudakshina Das <sudi.das@arm.com>
1297
1298 * arm-dis.c (enum mve_instructions): New enum
1299 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1300 and cneg.
1301 (mve_opcodes): New instructions as above.
1302 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1303 csneg and csel.
1304 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1305
23d00a41
SD		 13062019-05-21 Sudakshina Das <sudi.das@arm.com>
1307
1308 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1309 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1310 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1311 uqshl, urshrl and urshr.
1312 (is_mve_okay_in_it): Add new instructions to TRUE list.
1313 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1314 (print_insn_mve): Updated to accept new %j,
1315 %<bitfield>m and %<bitfield>n patterns.
1316
cd4797ee
FS		 13172019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1318
1319 * mips-opc.c (mips_builtin_opcodes): Change source register
1320 constraint for DAUI.
1321
999b073b
NC		 13222019-05-20 Nick Clifton <nickc@redhat.com>
1323
1324 * po/fr.po: Updated French translation.
1325
14b456f2
AV		 13262019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1327 Michael Collison <michael.collison@arm.com>
1328
1329 * arm-dis.c (thumb32_opcodes): Add new instructions.
1330 (enum mve_instructions): Likewise.
1331 (enum mve_undefined): Add new reasons.
1332 (is_mve_encoding_conflict): Handle new instructions.
1333 (is_mve_undefined): Likewise.
1334 (is_mve_unpredictable): Likewise.
1335 (print_mve_undefined): Likewise.
1336 (print_mve_size): Likewise.
1337
f49bb598
AV		 13382019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1339 Michael Collison <michael.collison@arm.com>
1340
1341 * arm-dis.c (thumb32_opcodes): Add new instructions.
1342 (enum mve_instructions): Likewise.
1343 (is_mve_encoding_conflict): Handle new instructions.
1344 (is_mve_undefined): Likewise.
1345 (is_mve_unpredictable): Likewise.
1346 (print_mve_size): Likewise.
1347
56858bea
AV		 13482019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1349 Michael Collison <michael.collison@arm.com>
1350
1351 * arm-dis.c (thumb32_opcodes): Add new instructions.
1352 (enum mve_instructions): Likewise.
1353 (is_mve_encoding_conflict): Likewise.
1354 (is_mve_unpredictable): Likewise.
1355 (print_mve_size): Likewise.
1356
e523f101
AV		 13572019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1358 Michael Collison <michael.collison@arm.com>
1359
1360 * arm-dis.c (thumb32_opcodes): Add new instructions.
1361 (enum mve_instructions): Likewise.
1362 (is_mve_encoding_conflict): Handle new instructions.
1363 (is_mve_undefined): Likewise.
1364 (is_mve_unpredictable): Likewise.
1365 (print_mve_size): Likewise.
1366
66dcaa5d
AV		 13672019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1368 Michael Collison <michael.collison@arm.com>
1369
1370 * arm-dis.c (thumb32_opcodes): Add new instructions.
1371 (enum mve_instructions): Likewise.
1372 (is_mve_encoding_conflict): Handle new instructions.
1373 (is_mve_undefined): Likewise.
1374 (is_mve_unpredictable): Likewise.
1375 (print_mve_size): Likewise.
1376 (print_insn_mve): Likewise.
1377
d052b9b7
AV		 13782019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1379 Michael Collison <michael.collison@arm.com>
1380
1381 * arm-dis.c (thumb32_opcodes): Add new instructions.
1382 (print_insn_thumb32): Handle new instructions.
1383
ed63aa17
AV		 13842019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1385 Michael Collison <michael.collison@arm.com>
1386
1387 * arm-dis.c (enum mve_instructions): Add new instructions.
1388 (enum mve_undefined): Add new reasons.
1389 (is_mve_encoding_conflict): Handle new instructions.
1390 (is_mve_undefined): Likewise.
1391 (is_mve_unpredictable): Likewise.
1392 (print_mve_undefined): Likewise.
1393 (print_mve_size): Likewise.
1394 (print_mve_shift_n): Likewise.
1395 (print_insn_mve): Likewise.
1396
897b9bbc
AV		 13972019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1398 Michael Collison <michael.collison@arm.com>
1399
1400 * arm-dis.c (enum mve_instructions): Add new instructions.
1401 (is_mve_encoding_conflict): Handle new instructions.
1402 (is_mve_unpredictable): Likewise.
1403 (print_mve_rotate): Likewise.
1404 (print_mve_size): Likewise.
1405 (print_insn_mve): Likewise.
1406
1c8f2df8
AV		 14072019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1408 Michael Collison <michael.collison@arm.com>
1409
1410 * arm-dis.c (enum mve_instructions): Add new instructions.
1411 (is_mve_encoding_conflict): Handle new instructions.
1412 (is_mve_unpredictable): Likewise.
1413 (print_mve_size): Likewise.
1414 (print_insn_mve): Likewise.
1415
d3b63143
AV		 14162019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1417 Michael Collison <michael.collison@arm.com>
1418
1419 * arm-dis.c (enum mve_instructions): Add new instructions.
1420 (enum mve_undefined): Add new reasons.
1421 (is_mve_encoding_conflict): Handle new instructions.
1422 (is_mve_undefined): Likewise.
1423 (is_mve_unpredictable): Likewise.
1424 (print_mve_undefined): Likewise.
1425 (print_mve_size): Likewise.
1426 (print_insn_mve): Likewise.
1427
14925797
AV		 14282019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1429 Michael Collison <michael.collison@arm.com>
1430
1431 * arm-dis.c (enum mve_instructions): Add new instructions.
1432 (is_mve_encoding_conflict): Handle new instructions.
1433 (is_mve_undefined): Likewise.
1434 (is_mve_unpredictable): Likewise.
1435 (print_mve_size): Likewise.
1436 (print_insn_mve): Likewise.
1437
c507f10b
AV		 14382019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1439 Michael Collison <michael.collison@arm.com>
1440
1441 * arm-dis.c (enum mve_instructions): Add new instructions.
1442 (enum mve_unpredictable): Add new reasons.
1443 (enum mve_undefined): Likewise.
1444 (is_mve_okay_in_it): Handle new isntructions.
1445 (is_mve_encoding_conflict): Likewise.
1446 (is_mve_undefined): Likewise.
1447 (is_mve_unpredictable): Likewise.
1448 (print_mve_vmov_index): Likewise.
1449 (print_simd_imm8): Likewise.
1450 (print_mve_undefined): Likewise.
1451 (print_mve_unpredictable): Likewise.
1452 (print_mve_size): Likewise.
1453 (print_insn_mve): Likewise.
1454
bf0b396d
AV		 14552019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1456 Michael Collison <michael.collison@arm.com>
1457
1458 * arm-dis.c (enum mve_instructions): Add new instructions.
1459 (enum mve_unpredictable): Add new reasons.
1460 (enum mve_undefined): Likewise.
1461 (is_mve_encoding_conflict): Handle new instructions.
1462 (is_mve_undefined): Likewise.
1463 (is_mve_unpredictable): Likewise.
1464 (print_mve_undefined): Likewise.
1465 (print_mve_unpredictable): Likewise.
1466 (print_mve_rounding_mode): Likewise.
1467 (print_mve_vcvt_size): Likewise.
1468 (print_mve_size): Likewise.
1469 (print_insn_mve): Likewise.
1470
ef1576a1
AV		 14712019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1472 Michael Collison <michael.collison@arm.com>
1473
1474 * arm-dis.c (enum mve_instructions): Add new instructions.
1475 (enum mve_unpredictable): Add new reasons.
1476 (enum mve_undefined): Likewise.
1477 (is_mve_undefined): Handle new instructions.
1478 (is_mve_unpredictable): Likewise.
1479 (print_mve_undefined): Likewise.
1480 (print_mve_unpredictable): Likewise.
1481 (print_mve_size): Likewise.
1482 (print_insn_mve): Likewise.
1483
aef6d006
AV		 14842019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1485 Michael Collison <michael.collison@arm.com>
1486
1487 * arm-dis.c (enum mve_instructions): Add new instructions.
1488 (enum mve_undefined): Add new reasons.
1489 (insns): Add new instructions.
1490 (is_mve_encoding_conflict):
1491 (print_mve_vld_str_addr): New print function.
1492 (is_mve_undefined): Handle new instructions.
1493 (is_mve_unpredictable): Likewise.
1494 (print_mve_undefined): Likewise.
1495 (print_mve_size): Likewise.
1496 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1497 (print_insn_mve): Handle new operands.
1498
04d54ace
AV		 14992019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1500 Michael Collison <michael.collison@arm.com>
1501
1502 * arm-dis.c (enum mve_instructions): Add new instructions.
1503 (enum mve_unpredictable): Add new reasons.
1504 (is_mve_encoding_conflict): Handle new instructions.
1505 (is_mve_unpredictable): Likewise.
1506 (mve_opcodes): Add new instructions.
1507 (print_mve_unpredictable): Handle new reasons.
1508 (print_mve_register_blocks): New print function.
1509 (print_mve_size): Handle new instructions.
1510 (print_insn_mve): Likewise.
1511
9743db03
AV		 15122019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1513 Michael Collison <michael.collison@arm.com>
1514
1515 * arm-dis.c (enum mve_instructions): Add new instructions.
1516 (enum mve_unpredictable): Add new reasons.
1517 (enum mve_undefined): Likewise.
1518 (is_mve_encoding_conflict): Handle new instructions.
1519 (is_mve_undefined): Likewise.
1520 (is_mve_unpredictable): Likewise.
1521 (coprocessor_opcodes): Move NEON VDUP from here...
1522 (neon_opcodes): ... to here.
1523 (mve_opcodes): Add new instructions.
1524 (print_mve_undefined): Handle new reasons.
1525 (print_mve_unpredictable): Likewise.
1526 (print_mve_size): Handle new instructions.
1527 (print_insn_neon): Handle vdup.
1528 (print_insn_mve): Handle new operands.
1529
143275ea
AV		 15302019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1531 Michael Collison <michael.collison@arm.com>
1532
1533 * arm-dis.c (enum mve_instructions): Add new instructions.
1534 (enum mve_unpredictable): Add new values.
1535 (mve_opcodes): Add new instructions.
1536 (vec_condnames): New array with vector conditions.
1537 (mve_predicatenames): New array with predicate suffixes.
1538 (mve_vec_sizename): New array with vector sizes.
1539 (enum vpt_pred_state): New enum with vector predication states.
1540 (struct vpt_block): New struct type for vpt blocks.
1541 (vpt_block_state): Global struct to keep track of state.
1542 (mve_extract_pred_mask): New helper function.
1543 (num_instructions_vpt_block): Likewise.
1544 (mark_outside_vpt_block): Likewise.
1545 (mark_inside_vpt_block): Likewise.
1546 (invert_next_predicate_state): Likewise.
1547 (update_next_predicate_state): Likewise.
1548 (update_vpt_block_state): Likewise.
1549 (is_vpt_instruction): Likewise.
1550 (is_mve_encoding_conflict): Add entries for new instructions.
1551 (is_mve_unpredictable): Likewise.
1552 (print_mve_unpredictable): Handle new cases.
1553 (print_instruction_predicate): Likewise.
1554 (print_mve_size): New function.
1555 (print_vec_condition): New function.
1556 (print_insn_mve): Handle vpt blocks and new print operands.
1557
f08d8ce3
AV		 15582019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1559
1560 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1561 8, 14 and 15 for Armv8.1-M Mainline.
1562
73cd51e5
AV		 15632019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1564 Michael Collison <michael.collison@arm.com>
1565
1566 * arm-dis.c (enum mve_instructions): New enum.
1567 (enum mve_unpredictable): Likewise.
1568 (enum mve_undefined): Likewise.
1569 (struct mopcode32): New struct.
1570 (is_mve_okay_in_it): New function.
1571 (is_mve_architecture): Likewise.
1572 (arm_decode_field): Likewise.
1573 (arm_decode_field_multiple): Likewise.
1574 (is_mve_encoding_conflict): Likewise.
1575 (is_mve_undefined): Likewise.
1576 (is_mve_unpredictable): Likewise.
1577 (print_mve_undefined): Likewise.
1578 (print_mve_unpredictable): Likewise.
1579 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1580 (print_insn_mve): New function.
1581 (print_insn_thumb32): Handle MVE architecture.
1582 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1583
3076e594
NC		 15842019-05-10 Nick Clifton <nickc@redhat.com>
1585
1586 PR 24538
1587 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1588 end of the table prematurely.
1589
387e7624
FS		 15902019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1591
1592 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1593 macros for R6.
1594
0067be51
AM		 15952019-05-11 Alan Modra <amodra@gmail.com>
1596
1597 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1598 when -Mraw is in effect.
1599
42e6288f
MM		 16002019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1601
1602 * aarch64-dis-2.c: Regenerate.
1603 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1604 (OP_SVE_BBB): New variant set.
1605 (OP_SVE_DDDD): New variant set.
1606 (OP_SVE_HHH): New variant set.
1607 (OP_SVE_HHHU): New variant set.
1608 (OP_SVE_SSS): New variant set.
1609 (OP_SVE_SSSU): New variant set.
1610 (OP_SVE_SHH): New variant set.
1611 (OP_SVE_SBBU): New variant set.
1612 (OP_SVE_DSS): New variant set.
1613 (OP_SVE_DHHU): New variant set.
1614 (OP_SVE_VMV_HSD_BHS): New variant set.
1615 (OP_SVE_VVU_HSD_BHS): New variant set.
1616 (OP_SVE_VVVU_SD_BH): New variant set.
1617 (OP_SVE_VVVU_BHSD): New variant set.
1618 (OP_SVE_VVV_QHD_DBS): New variant set.
1619 (OP_SVE_VVV_HSD_BHS): New variant set.
1620 (OP_SVE_VVV_HSD_BHS2): New variant set.
1621 (OP_SVE_VVV_BHS_HSD): New variant set.
1622 (OP_SVE_VV_BHS_HSD): New variant set.
1623 (OP_SVE_VVV_SD): New variant set.
1624 (OP_SVE_VVU_BHS_HSD): New variant set.
1625 (OP_SVE_VZVV_SD): New variant set.
1626 (OP_SVE_VZVV_BH): New variant set.
1627 (OP_SVE_VZV_SD): New variant set.
1628 (aarch64_opcode_table): Add sve2 instructions.
1629
28ed815a
MM		 16302019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1631
1632 * aarch64-asm-2.c: Regenerated.
1633 * aarch64-dis-2.c: Regenerated.
1634 * aarch64-opc-2.c: Regenerated.
1635 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1636 for SVE_SHLIMM_UNPRED_22.
1637 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1638 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1639 operand.
1640
fd1dc4a0
MM		 16412019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1642
1643 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1644 sve_size_tsz_bhs iclass encode.
1645 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1646 sve_size_tsz_bhs iclass decode.
1647
31e36ab3
MM		 16482019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1649
1650 * aarch64-asm-2.c: Regenerated.
1651 * aarch64-dis-2.c: Regenerated.
1652 * aarch64-opc-2.c: Regenerated.
1653 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1654 for SVE_Zm4_11_INDEX.
1655 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1656 (fields): Handle SVE_i2h field.
1657 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1658 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1659
1be5f94f
MM		 16602019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1661
1662 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1663 sve_shift_tsz_bhsd iclass encode.
1664 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1665 sve_shift_tsz_bhsd iclass decode.
1666
3c17238b
MM		 16672019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1668
1669 * aarch64-asm-2.c: Regenerated.
1670 * aarch64-dis-2.c: Regenerated.
1671 * aarch64-opc-2.c: Regenerated.
1672 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1673 (aarch64_encode_variant_using_iclass): Handle
1674 sve_shift_tsz_hsd iclass encode.
1675 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1676 sve_shift_tsz_hsd iclass decode.
1677 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1678 for SVE_SHRIMM_UNPRED_22.
1679 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1680 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1681 operand.
1682
cd50a87a
MM		 16832019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1684
1685 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1686 sve_size_013 iclass encode.
1687 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1688 sve_size_013 iclass decode.
1689
3c705960
MM		 16902019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1691
1692 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1693 sve_size_bh iclass encode.
1694 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1695 sve_size_bh iclass decode.
1696
0a57e14f
MM		 16972019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1698
1699 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1700 sve_size_sd2 iclass encode.
1701 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1702 sve_size_sd2 iclass decode.
1703 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1704 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1705
c469c864
MM		 17062019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1707
1708 * aarch64-asm-2.c: Regenerated.
1709 * aarch64-dis-2.c: Regenerated.
1710 * aarch64-opc-2.c: Regenerated.
1711 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1712 for SVE_ADDR_ZX.
1713 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1714 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1715
116adc27
MM		 17162019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1717
1718 * aarch64-asm-2.c: Regenerated.
1719 * aarch64-dis-2.c: Regenerated.
1720 * aarch64-opc-2.c: Regenerated.
1721 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1722 for SVE_Zm3_11_INDEX.
1723 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1724 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1725 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1726 fields.
1727 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1728
3bd82c86
MM		 17292019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1730
1731 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1732 sve_size_hsd2 iclass encode.
1733 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1734 sve_size_hsd2 iclass decode.
1735 * aarch64-opc.c (fields): Handle SVE_size field.
1736 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1737
adccc507
MM		 17382019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1739
1740 * aarch64-asm-2.c: Regenerated.
1741 * aarch64-dis-2.c: Regenerated.
1742 * aarch64-opc-2.c: Regenerated.
1743 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1744 for SVE_IMM_ROT3.
1745 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1746 (fields): Handle SVE_rot3 field.
1747 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1748 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1749
5cd99750
MM		 17502019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1751
1752 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1753 instructions.
1754
7ce2460a
MM		 17552019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1756
1757 * aarch64-tbl.h
1758 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1759 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1760 aarch64_feature_sve2bitperm): New feature sets.
1761 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1762 for feature set addresses.
1763 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1764 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1765
41cee089
FS		 17662019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1767 Faraz Shahbazker <fshahbazker@wavecomp.com>
1768
1769 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1770 argument and set ASE_EVA_R6 appropriately.
1771 (set_default_mips_dis_options): Pass ISA to above.
1772 (parse_mips_dis_option): Likewise.
1773 * mips-opc.c (EVAR6): New macro.
1774 (mips_builtin_opcodes): Add llwpe, scwpe.
1775
b83b4b13
SD		 17762019-05-01 Sudakshina Das <sudi.das@arm.com>
1777
1778 * aarch64-asm-2.c: Regenerated.
1779 * aarch64-dis-2.c: Regenerated.
1780 * aarch64-opc-2.c: Regenerated.
1781 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1782 AARCH64_OPND_TME_UIMM16.
1783 (aarch64_print_operand): Likewise.
1784 * aarch64-tbl.h (QL_IMM_NIL): New.
1785 (TME): New.
1786 (_TME_INSN): New.
1787 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1788
4a90ce95
JD		 17892019-04-29 John Darrington <john@darrington.wattle.id.au>
1790
1791 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1792
a45328b9
AB		 17932019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1794 Faraz Shahbazker <fshahbazker@wavecomp.com>
1795
1796 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1797
d10be0cb
JD		 17982019-04-24 John Darrington <john@darrington.wattle.id.au>
1799
1800 * s12z-opc.h: Add extern "C" bracketing to help
1801 users who wish to use this interface in c++ code.
1802
a679f24e
JD		 18032019-04-24 John Darrington <john@darrington.wattle.id.au>
1804
1805 * s12z-opc.c (bm_decode): Handle bit map operations with the
1806 "reserved0" mode.
1807
32c36c3c
AV		 18082019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1809
1810 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1811 specifier. Add entries for VLDR and VSTR of system registers.
1812 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1813 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1814 of %J and %K format specifier.
1815
efd6b359
AV		 18162019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1817
1818 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1819 Add new entries for VSCCLRM instruction.
1820 (print_insn_coprocessor): Handle new %C format control code.
1821
6b0dd094
AV		 18222019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1823
1824 * arm-dis.c (enum isa): New enum.
1825 (struct sopcode32): New structure.
1826 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1827 set isa field of all current entries to ANY.
1828 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1829 Only match an entry if its isa field allows the current mode.
1830
4b5a202f
AV		 18312019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1832
1833 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1834 CLRM.
1835 (print_insn_thumb32): Add logic to print %n CLRM register list.
1836
60f993ce
AV		 18372019-04-15 Sudakshina Das <sudi.das@arm.com>
1838
1839 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1840 and %Q patterns.
1841
f6b2b12d
AV		 18422019-04-15 Sudakshina Das <sudi.das@arm.com>
1843
1844 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1845 (print_insn_thumb32): Edit the switch case for %Z.
1846
1889da70
AV		 18472019-04-15 Sudakshina Das <sudi.das@arm.com>
1848
1849 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1850
65d1bc05
AV		 18512019-04-15 Sudakshina Das <sudi.das@arm.com>
1852
1853 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1854
1caf72a5
AV		 18552019-04-15 Sudakshina Das <sudi.das@arm.com>
1856
1857 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1858
f1c7f421
AV		 18592019-04-15 Sudakshina Das <sudi.das@arm.com>
1860
1861 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1862 Arm register with r13 and r15 unpredictable.
1863 (thumb32_opcodes): New instructions for bfx and bflx.
1864
4389b29a
AV		 18652019-04-15 Sudakshina Das <sudi.das@arm.com>
1866
1867 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1868
e5d6e09e
AV		 18692019-04-15 Sudakshina Das <sudi.das@arm.com>
1870
1871 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1872
e12437dc
AV		 18732019-04-15 Sudakshina Das <sudi.das@arm.com>
1874
1875 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1876
031254f2
AV		 18772019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1878
1879 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1880
e5a557ac
JD		 18812019-04-12 John Darrington <john@darrington.wattle.id.au>
1882
1883 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1884 "optr". ("operator" is a reserved word in c++).
1885
bd7ceb8d
SD		 18862019-04-11 Sudakshina Das <sudi.das@arm.com>
1887
1888 * aarch64-opc.c (aarch64_print_operand): Add case for
1889 AARCH64_OPND_Rt_SP.
1890 (verify_constraints): Likewise.
1891 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1892 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1893 to accept Rt|SP as first operand.
1894 (AARCH64_OPERANDS): Add new Rt_SP.
1895 * aarch64-asm-2.c: Regenerated.
1896 * aarch64-dis-2.c: Regenerated.
1897 * aarch64-opc-2.c: Regenerated.
1898
e54010f1
SD		 18992019-04-11 Sudakshina Das <sudi.das@arm.com>
1900
1901 * aarch64-asm-2.c: Regenerated.
1902 * aarch64-dis-2.c: Likewise.
1903 * aarch64-opc-2.c: Likewise.
1904 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1905
7e96e219
RS		 19062019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1907
1908 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1909
6f2791d5
L		 19102019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1911
1912 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1913 * i386-init.h: Regenerated.
1914
e392bad3
AM		 19152019-04-07 Alan Modra <amodra@gmail.com>
1916
1917 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1918 op_separator to control printing of spaces, comma and parens
1919 rather than need_comma, need_paren and spaces vars.
1920
dffaa15c
AM		 19212019-04-07 Alan Modra <amodra@gmail.com>
1922
1923 PR 24421
1924 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1925 (print_insn_neon, print_insn_arm): Likewise.
1926
d6aab7a1
XG		 19272019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1928
1929 * i386-dis-evex.h (evex_table): Updated to support BF16
1930 instructions.
1931 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1932 and EVEX_W_0F3872_P_3.
1933 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1934 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1935 * i386-opc.h (enum): Add CpuAVX512_BF16.
1936 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1937 * i386-opc.tbl: Add AVX512 BF16 instructions.
1938 * i386-init.h: Regenerated.
1939 * i386-tbl.h: Likewise.
1940
66e85460
AM		 19412019-04-05 Alan Modra <amodra@gmail.com>
1942
1943 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1944 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1945 to favour printing of "-" branch hint when using the "y" bit.
1946 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1947
c2b1c275
AM		 19482019-04-05 Alan Modra <amodra@gmail.com>
1949
1950 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1951 opcode until first operand is output.
1952
aae9718e
PB		 19532019-04-04 Peter Bergner <bergner@linux.ibm.com>
1954
1955 PR gas/24349
1956 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1957 (valid_bo_post_v2): Add support for 'at' branch hints.
1958 (insert_bo): Only error on branch on ctr.
1959 (get_bo_hint_mask): New function.
1960 (insert_boe): Add new 'branch_taken' formal argument. Add support
1961 for inserting 'at' branch hints.
1962 (extract_boe): Add new 'branch_taken' formal argument. Add support
1963 for extracting 'at' branch hints.
1964 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1965 (BOE): Delete operand.
1966 (BOM, BOP): New operands.
1967 (RM): Update value.
1968 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1969 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1970 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1971 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1972 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1973 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1974 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1975 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1976 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1977 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1978 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1979 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1980 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1981 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1982 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1983 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1984 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1985 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1986 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1987 bttarl+>: New extended mnemonics.
1988
96a86c01
AM		 19892019-03-28 Alan Modra <amodra@gmail.com>
1990
1991 PR 24390
1992 * ppc-opc.c (BTF): Define.
1993 (powerpc_opcodes): Use for mtfsb*.
1994 * ppc-dis.c (print_insn_powerpc): Print fields with both
1995 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1996
796d6298
TC		 19972019-03-25 Tamar Christina <tamar.christina@arm.com>
1998
1999 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
2000 (mapping_symbol_for_insn): Implement new algorithm.
2001 (print_insn): Remove duplicate code.
2002
60df3720
TC		 20032019-03-25 Tamar Christina <tamar.christina@arm.com>
2004
2005 * aarch64-dis.c (print_insn_aarch64):
2006 Implement override.
2007
51457761
TC		 20082019-03-25 Tamar Christina <tamar.christina@arm.com>
2009
2010 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
2011 order.
2012
53b2f36b
TC		 20132019-03-25 Tamar Christina <tamar.christina@arm.com>
2014
2015 * aarch64-dis.c (last_stop_offset): New.
2016 (print_insn_aarch64): Use stop_offset.
2017
89199bb5
L		 20182019-03-19 H.J. Lu <hongjiu.lu@intel.com>
2019
2020 PR gas/24359
2021 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2022 CPU_ANY_AVX2_FLAGS.
2023 * i386-init.h: Regenerated.
2024
97ed31ae
L		 20252019-03-18 H.J. Lu <hongjiu.lu@intel.com>
2026
2027 PR gas/24348
2028 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2029 vmovdqu16, vmovdqu32 and vmovdqu64.
2030 * i386-tbl.h: Regenerated.
2031
0919bfe9
AK		 20322019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2033
2034 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
2035 from vstrszb, vstrszh, and vstrszf.
2036
20372019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2038
2039 * s390-opc.txt: Add instruction descriptions.
2040
21820ebe
JW		 20412019-02-08 Jim Wilson <jimw@sifive.com>
2042
2043 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2044 <bne>: Likewise.
2045
f7dd2fb2
TC		 20462019-02-07 Tamar Christina <tamar.christina@arm.com>
2047
2048 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2049
6456d318
TC		 20502019-02-07 Tamar Christina <tamar.christina@arm.com>
2051
2052 PR binutils/23212
2053 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2054 * aarch64-opc.c (verify_elem_sd): New.
2055 (fields): Add FLD_sz entr.
2056 * aarch64-tbl.h (_SIMD_INSN): New.
2057 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2058 fmulx scalar and vector by element isns.
2059
4a83b610
NC		 20602019-02-07 Nick Clifton <nickc@redhat.com>
2061
2062 * po/sv.po: Updated Swedish translation.
2063
fc60b8c8
AK		 20642019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
2065
2066 * s390-mkopc.c (main): Accept arch13 as cpu string.
2067 * s390-opc.c: Add new instruction formats and instruction opcode
2068 masks.
2069 * s390-opc.txt: Add new arch13 instructions.
2070
e10620d3
TC		 20712019-01-25 Sudakshina Das <sudi.das@arm.com>
2072
2073 * aarch64-tbl.h (QL_LDST_AT): Update macro.
2074 (aarch64_opcode): Change encoding for stg, stzg
2075 st2g and st2zg.
2076 * aarch64-asm-2.c: Regenerated.
2077 * aarch64-dis-2.c: Regenerated.
2078 * aarch64-opc-2.c: Regenerated.
2079
20a4ca55
SD		 20802019-01-25 Sudakshina Das <sudi.das@arm.com>
2081
2082 * aarch64-asm-2.c: Regenerated.
2083 * aarch64-dis-2.c: Likewise.
2084 * aarch64-opc-2.c: Likewise.
2085 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2086
550fd7bf
SD		 20872019-01-25 Sudakshina Das <sudi.das@arm.com>
2088 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
2089
2090 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2091 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2092 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2093 * aarch64-dis.h (ext_addr_simple_2): Likewise.
2094 * aarch64-opc.c (operand_general_constraint_met_p): Remove
2095 case for ldstgv_indexed.
2096 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2097 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2098 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2099 * aarch64-asm-2.c: Regenerated.
2100 * aarch64-dis-2.c: Regenerated.
2101 * aarch64-opc-2.c: Regenerated.
2102
d9938630
NC		 21032019-01-23 Nick Clifton <nickc@redhat.com>
2104
2105 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2106
375cd423
NC		 21072019-01-21 Nick Clifton <nickc@redhat.com>
2108
2109 * po/de.po: Updated German translation.
2110 * po/uk.po: Updated Ukranian translation.
2111
57299f48
CX		 21122019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
2113 * mips-dis.c (mips_arch_choices): Fix typo in
2114 gs464, gs464e and gs264e descriptors.
2115
f48dfe41
NC		 21162019-01-19 Nick Clifton <nickc@redhat.com>
2117
2118 * configure: Regenerate.
2119 * po/opcodes.pot: Regenerate.
2120
f974f26c
NC		 21212018-06-24 Nick Clifton <nickc@redhat.com>
2122
2123 2.32 branch created.
2124
39f286cd
JD		 21252019-01-09 John Darrington <john@darrington.wattle.id.au>
2126
448b8ca8
JD		 2127 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
2128 if it is null.
2129 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 2130 zero.
2131
3107326d
AP		 21322019-01-09 Andrew Paprocki <andrew@ishiboo.com>
2133
2134 * configure: Regenerate.
2135
7e9ca91e
AM		 21362019-01-07 Alan Modra <amodra@gmail.com>
2137
2138 * configure: Regenerate.
2139 * po/POTFILES.in: Regenerate.
2140
ef1ad42b
JD		 21412019-01-03 John Darrington <john@darrington.wattle.id.au>
2142
2143 * s12z-opc.c: New file.
2144 * s12z-opc.h: New file.
2145 * s12z-dis.c: Removed all code not directly related to display
2146 of instructions. Used the interface provided by the new files
2147 instead.
2148 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 2149 * Makefile.in: Regenerate.
ef1ad42b 2150 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 2151 * configure: Regenerate.
ef1ad42b 2152
82704155
AM		 21532019-01-01 Alan Modra <amodra@gmail.com>
2154
2155 Update year range in copyright notice of all files.
2156
d5c04e1b 2157For older changes see ChangeLog-2018
3499769a 2158\f
d5c04e1b 2159Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 2160
2161Copying and distribution of this file, with or without modification,
2162are permitted in any medium without royalty provided the copyright
2163notice and this notice are preserved.
2164
2165Local Variables:
2166mode: change-log
2167left-margin: 8
2168fill-column: 74
2169version-control: never
2170End:
GDB Binutils - Deliverables
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