Commit | Line | Data |
---|---|---|
aa2aa4c6 RS |
1 | 2016-09-21 Richard Sandiford <richard.sandiford@arm.com> |
2 | ||
3 | * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm | |
4 | for FPIMM. | |
5 | * aarch64-asm.h (ins_fpimm): New inserter. | |
6 | * aarch64-asm.c (aarch64_ins_fpimm): New function. | |
7 | * aarch64-asm-2.c: Regenerate. | |
8 | * aarch64-dis.h (ext_fpimm): New extractor. | |
9 | * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test. | |
10 | (aarch64_ext_fpimm): New function. | |
11 | * aarch64-dis-2.c: Regenerate. | |
12 | ||
b5464a68 RS |
13 | 2016-09-21 Richard Sandiford <richard.sandiford@arm.com> |
14 | ||
15 | * aarch64-asm.c: Include libiberty.h. | |
16 | (insert_fields): New function. | |
17 | (aarch64_ins_imm): Use it. | |
18 | * aarch64-dis.c (extract_fields): New function. | |
19 | (aarch64_ext_imm): Use it. | |
20 | ||
42408347 RS |
21 | 2016-09-21 Richard Sandiford <richard.sandiford@arm.com> |
22 | ||
23 | * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32 | |
24 | with an esize parameter. | |
25 | (operand_general_constraint_met_p): Update accordingly. | |
26 | Fix misindented code. | |
27 | * aarch64-asm.c (aarch64_ins_limm): Update call to | |
28 | aarch64_logical_immediate_p. | |
29 | ||
4989adac RS |
30 | 2016-09-21 Richard Sandiford <richard.sandiford@arm.com> |
31 | ||
32 | * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT. | |
33 | ||
bd11d5d8 RS |
34 | 2016-09-21 Richard Sandiford <richard.sandiford@arm.com> |
35 | ||
36 | * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit. | |
37 | ||
f807f43d CZ |
38 | 2016-09-15 Claudiu Zissulescu <claziss@synopsys.com> |
39 | ||
40 | * arc-dis.c (find_format): Walk the linked list pointed by einsn. | |
41 | ||
fd486b63 PB |
42 | 2016-09-14 Peter Bergner <bergner@vnet.ibm.com> |
43 | ||
44 | * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic. | |
45 | <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool, | |
46 | xor3>: Delete mnemonics. | |
47 | <cp_abort>: Rename mnemonic from ... | |
48 | <cpabort>: ...to this. | |
49 | <setb>: Change to a X form instruction. | |
50 | <sync>: Change to 1 operand form. | |
51 | <copy>: Delete mnemonic. | |
52 | <copy_first>: Rename mnemonic from ... | |
53 | <copy>: ...to this. | |
54 | <paste, paste.>: Delete mnemonics. | |
55 | <paste_last>: Rename mnemonic from ... | |
56 | <paste.>: ...to this. | |
57 | ||
dce08442 AK |
58 | 2016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com> |
59 | ||
60 | * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully. | |
61 | ||
952c3f51 AK |
62 | 2016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com> |
63 | ||
64 | * s390-mkopc.c (main): Support alternate arch strings. | |
65 | ||
8b71537b PS |
66 | 2016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com> |
67 | ||
68 | * s390-opc.txt: Fix kmctr instruction type. | |
69 | ||
5b64d091 L |
70 | 2016-09-07 H.J. Lu <hongjiu.lu@intel.com> |
71 | ||
72 | * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS. | |
73 | * i386-init.h: Regenerated. | |
74 | ||
7763838e CM |
75 | 2016-08-30 Cupertino Miranda <cmiranda@synopsys.com> |
76 | ||
77 | * opcodes/arc-dis.c (print_insn_arc): Changed. | |
78 | ||
1b8b6532 JM |
79 | 2016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com> |
80 | ||
81 | * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi -> | |
82 | camellia_fl. | |
83 | ||
1a336194 TP |
84 | 2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com> |
85 | ||
86 | * arm-dis.c (psr_name): Use hex as case labels. Add detection for | |
87 | MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS, | |
88 | FAULTMASK_NS, CONTROL_NS and SP_NS special registers. | |
89 | ||
6b40c462 L |
90 | 2016-08-24 H.J. Lu <hongjiu.lu@intel.com> |
91 | ||
92 | * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New. | |
93 | (PREFIX_MOD_3_0FAE_REG_4): Likewise. | |
94 | (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and | |
95 | PREFIX_MOD_3_0FAE_REG_4. | |
96 | (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and | |
97 | PREFIX_MOD_3_0FAE_REG_4. | |
98 | * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS. | |
99 | (cpu_flags): Add CpuPTWRITE. | |
100 | * i386-opc.h (CpuPTWRITE): New. | |
101 | (i386_cpu_flags): Add cpuptwrite. | |
102 | * i386-opc.tbl: Add ptwrite instruction. | |
103 | * i386-init.h: Regenerated. | |
104 | * i386-tbl.h: Likewise. | |
105 | ||
ab548d2d AK |
106 | 2016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com> |
107 | ||
108 | * arc-dis.h: Wrap around in extern "C". | |
109 | ||
344bde0a RS |
110 | 2016-08-23 Richard Sandiford <richard.sandiford@arm.com> |
111 | ||
112 | * aarch64-tbl.h (V8_2_INSN): New macro. | |
113 | (aarch64_opcode_table): Use it. | |
114 | ||
5ce912d8 RS |
115 | 2016-08-23 Richard Sandiford <richard.sandiford@arm.com> |
116 | ||
117 | * aarch64-tbl.h (aarch64_opcode_table): Make more use of | |
118 | CORE_INSN, __FP_INSN and SIMD_INSN. | |
119 | ||
9d30b0bd RS |
120 | 2016-08-23 Richard Sandiford <richard.sandiford@arm.com> |
121 | ||
122 | * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter. | |
123 | (aarch64_opcode_table): Update uses accordingly. | |
124 | ||
dfdaec14 AJ |
125 | 2016-07-25 Andrew Jenner <andrew@codesourcery.com> |
126 | Kwok Cheung Yeung <kcy@codesourcery.com> | |
127 | ||
128 | opcodes/ | |
129 | * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and | |
130 | 'e_cmplwi' to 'e_cmpli' instead. | |
131 | (OPVUPRT, OPVUPRT_MASK): Define. | |
132 | (powerpc_opcodes): Add E200Z4 insns. | |
133 | (vle_opcodes): Add context save/restore insns. | |
134 | ||
7bd374a4 MR |
135 | 2016-07-27 Maciej W. Rozycki <macro@imgtec.com> |
136 | ||
137 | * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b", | |
138 | "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to | |
139 | "j". | |
140 | ||
db18dbab GM |
141 | 2016-07-27 Graham Markall <graham.markall@embecosm.com> |
142 | ||
143 | * arc-nps400-tbl.h: Change block comments to GNU format. | |
144 | * arc-dis.c: Add new globals addrtypenames, | |
145 | addrtypenames_max, and addtypeunknown. | |
146 | (get_addrtype): New function. | |
147 | (print_insn_arc): Print colons and address types when | |
148 | required. | |
149 | * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to | |
150 | define insert and extract functions for all address types. | |
151 | (arc_operands): Add operands for colon and all address | |
152 | types. | |
153 | * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table. | |
154 | * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands, | |
155 | insert_nps_bd_num_buff and extract_nps_bd_num_buff functions. | |
156 | * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table. | |
157 | * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands, | |
158 | insert_nps_pmu_num_job and extract_nps_pmu_num_job functions. | |
159 | ||
fecd57f9 L |
160 | 2016-07-21 H.J. Lu <hongjiu.lu@intel.com> |
161 | ||
162 | * configure: Regenerated. | |
163 | ||
37fd5ef3 CZ |
164 | 2016-07-20 Claudiu Zissulescu <claziss@synopsys.com> |
165 | ||
166 | * arc-dis.c (skipclass): New structure. | |
167 | (decodelist): New variable. | |
168 | (is_compatible_p): New function. | |
169 | (new_element): Likewise. | |
170 | (skip_class_p): Likewise. | |
171 | (find_format_from_table): Use skip_class_p function. | |
172 | (find_format): Decode first the extension instructions. | |
173 | (print_insn_arc): Select either ARCEM or ARCHS based on elf | |
174 | e_flags. | |
175 | (parse_option): New function. | |
176 | (parse_disassembler_options): Likewise. | |
177 | (print_arc_disassembler_options): Likewise. | |
178 | (print_insn_arc): Use parse_disassembler_options function. Proper | |
179 | select ARCv2 cpu variant. | |
180 | * disassemble.c (disassembler_usage): Add ARC disassembler | |
181 | options. | |
182 | ||
92281a5b MR |
183 | 2016-07-13 Maciej W. Rozycki <macro@imgtec.com> |
184 | ||
185 | * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS | |
186 | annotation from the "nal" entry and reorder it beyond "bltzal". | |
187 | ||
6e7ced37 JM |
188 | 2016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com> |
189 | ||
190 | * sparc-opc.c (ldtxa): New macro. | |
191 | (sparc_opcodes): Use the macro defined above to add entries for | |
192 | the LDTXA instructions. | |
193 | (asi_table): Add the ASI_TWINX_* asis used in the LDTXA | |
194 | instruction. | |
195 | ||
2f831b9a | 196 | 2016-07-07 James Bowman <james.bowman@ftdichip.com> |
197 | ||
198 | * ft32-opc.c (ft32_opc_info): Correct mask for "callc" | |
199 | and "jmpc". | |
200 | ||
c07315e0 JB |
201 | 2016-07-01 Jan Beulich <jbeulich@suse.com> |
202 | ||
203 | * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove. | |
204 | (movzb): Adjust to cover all permitted suffixes. | |
205 | (movzw): New. | |
206 | * i386-tbl.h: Re-generate. | |
207 | ||
9243100a JB |
208 | 2016-07-01 Jan Beulich <jbeulich@suse.com> |
209 | ||
210 | * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant. | |
211 | (lgdt): Remove Tbyte from non-64-bit variant. | |
212 | (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64, | |
213 | xsaves64, xsavec64): Remove Disp16. | |
214 | (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd): | |
215 | Remove Disp32S from non-64-bit variants. Remove Disp16 from | |
216 | 64-bit variants. | |
217 | (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd, | |
218 | vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi, | |
219 | vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from | |
220 | 64-bit variants. | |
221 | * i386-tbl.h: Re-generate. | |
222 | ||
8325cc63 JB |
223 | 2016-07-01 Jan Beulich <jbeulich@suse.com> |
224 | ||
225 | * i386-opc.tbl (xlat): Remove RepPrefixOk. | |
226 | * i386-tbl.h: Re-generate. | |
227 | ||
838441e4 YQ |
228 | 2016-06-30 Yao Qi <yao.qi@linaro.org> |
229 | ||
230 | * arm-dis.c (print_insn): Fix typo in comment. | |
231 | ||
dab26bf4 RS |
232 | 2016-06-28 Richard Sandiford <richard.sandiford@arm.com> |
233 | ||
234 | * aarch64-opc.c (operand_general_constraint_met_p): Check the | |
235 | range of ldst_elemlist operands. | |
236 | (print_register_list): Use PRIi64 to print the index. | |
237 | (aarch64_print_operand): Likewise. | |
238 | ||
5703197e TS |
239 | 2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> |
240 | ||
241 | * mcore-opc.h: Remove sentinal. | |
242 | * mcore-dis.c (print_insn_mcore): Adjust. | |
243 | ||
ce440d63 GM |
244 | 2016-06-23 Graham Markall <graham.markall@embecosm.com> |
245 | ||
246 | * arc-opc.c: Correct description of availability of NPS400 | |
247 | features. | |
248 | ||
6fd3a02d PB |
249 | 2016-06-22 Peter Bergner <bergner@vnet.ibm.com> |
250 | ||
251 | * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines. | |
252 | (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni, | |
253 | mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool, | |
254 | xor3>: New mnemonics. | |
255 | <setb>: Change to a VX form instruction. | |
256 | (insert_sh6): Add support for rldixor. | |
257 | (extract_sh6): Likewise. | |
258 | ||
6b477896 TS |
259 | 2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> |
260 | ||
261 | * arc-ext.h: Wrap in extern C. | |
262 | ||
bdd582db GM |
263 | 2016-06-21 Graham Markall <graham.markall@embecosm.com> |
264 | ||
265 | * arc-dis.c (arc_insn_length): Add comment on instruction length. | |
266 | Use same method for determining instruction length on ARC700 and | |
267 | NPS-400. | |
268 | (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400. | |
269 | * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions | |
270 | with the NPS400 subclass. | |
271 | * arc-opc.c: Likewise. | |
272 | ||
96074adc JM |
273 | 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com> |
274 | ||
275 | * sparc-opc.c (rdasr): New macro. | |
276 | (wrasr): Likewise. | |
277 | (rdpr): Likewise. | |
278 | (wrpr): Likewise. | |
279 | (rdhpr): Likewise. | |
280 | (wrhpr): Likewise. | |
281 | (sparc_opcodes): Use the macros above to fix and expand the | |
282 | definition of read/write instructions from/to | |
283 | asr/privileged/hyperprivileged instructions. | |
284 | * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and | |
285 | %hva_mask_nz. Prefer softint_set and softint_clear over | |
286 | set_softint and clear_softint. | |
287 | (print_insn_sparc): Support %ver in Rd. | |
288 | ||
7a10c22f JM |
289 | 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com> |
290 | ||
291 | * sparc-opc.c (sparc_opcodes): Adjust instructions opcode | |
292 | architecture according to the hardware capabilities they require. | |
293 | ||
4f26fb3a JM |
294 | 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com> |
295 | ||
296 | * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}. | |
297 | (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and | |
298 | bfd_mach_sparc_v9{c,d,e,v,m}. | |
299 | * sparc-opc.c (MASK_V9C): Define. | |
300 | (MASK_V9D): Likewise. | |
301 | (MASK_V9E): Likewise. | |
302 | (MASK_V9V): Likewise. | |
303 | (MASK_V9M): Likewise. | |
304 | (v6): Add MASK_V9{C,D,E,V,M}. | |
305 | (v6notlet): Likewise. | |
306 | (v7): Likewise. | |
307 | (v8): Likewise. | |
308 | (v9): Likewise. | |
309 | (v9andleon): Likewise. | |
310 | (v9a): Likewise. | |
311 | (v9b): Likewise. | |
312 | (v9c): Define. | |
313 | (v9d): Likewise. | |
314 | (v9e): Likewise. | |
315 | (v9v): Likewise. | |
316 | (v9m): Likewise. | |
317 | (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}. | |
318 | ||
3ee6e4fb NC |
319 | 2016-06-15 Nick Clifton <nickc@redhat.com> |
320 | ||
321 | * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer | |
322 | constants to match expected behaviour. | |
323 | (nds32_parse_opcode): Likewise. Also for whitespace. | |
324 | ||
02f3be19 AB |
325 | 2016-06-15 Andrew Burgess <andrew.burgess@embecosm.com> |
326 | ||
327 | * arc-opc.c (extract_rhv1): Extract value from insn. | |
328 | ||
6f9f37ed | 329 | 2016-06-14 Graham Markall <graham.markall@embecosm.com> |
28215275 GM |
330 | |
331 | * arc-nps400-tbl.h: Add ldbit instruction. | |
332 | * arc-opc.c: Add flag classes required for ldbit. | |
333 | ||
6f9f37ed | 334 | 2016-06-14 Graham Markall <graham.markall@embecosm.com> |
9ba75c88 GM |
335 | |
336 | * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf | |
337 | * arc-opc.c: Add flag classes, insert/extract functions, and operands to | |
338 | support the above instructions. | |
339 | ||
6f9f37ed | 340 | 2016-06-14 Graham Markall <graham.markall@embecosm.com> |
14053c19 GM |
341 | |
342 | * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb, | |
343 | imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms, | |
344 | csma, cbba, zncv, and hofs. | |
345 | * arc-opc.c: Add flag classes, insert/extract functions, and operands to | |
346 | support the above instructions. | |
347 | ||
348 | 2016-06-06 Graham Markall <graham.markall@embecosm.com> | |
349 | ||
350 | * arc-nps400-tbl.h: Add andab and orab instructions. | |
351 | ||
352 | 2016-06-06 Graham Markall <graham.markall@embecosm.com> | |
353 | ||
354 | * arc-nps400-tbl.h: Add addl-like instructions. | |
355 | ||
356 | 2016-06-06 Graham Markall <graham.markall@embecosm.com> | |
357 | ||
358 | * arc-nps400-tbl.h: Add mxb and imxb instructions. | |
359 | ||
360 | 2016-06-06 Graham Markall <graham.markall@embecosm.com> | |
361 | ||
362 | * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey | |
363 | instructions. | |
364 | ||
b2cc3f6f AK |
365 | 2016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com> |
366 | ||
367 | * s390-dis.c (option_use_insn_len_bits_p): New file scope | |
368 | variable. | |
369 | (init_disasm): Handle new command line option "insnlength". | |
370 | (print_s390_disassembler_options): Mention new option in help | |
371 | output. | |
372 | (print_insn_s390): Use the encoded insn length when dumping | |
373 | unknown instructions. | |
374 | ||
1857fe72 DC |
375 | 2016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com> |
376 | ||
377 | * avr-dis.c (avr_operand): Add default data address space origin (0x800000) | |
378 | to the address and set as symbol address for LDS/ STS immediate operands. | |
379 | ||
14b57c7c AM |
380 | 2016-06-07 Alan Modra <amodra@gmail.com> |
381 | ||
382 | * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default | |
383 | cpu for "vle" to e500. | |
384 | * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE. | |
385 | (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise. | |
386 | (PPCNONE): Delete, substitute throughout. | |
387 | (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated" | |
388 | except for major opcode 4 and 31. | |
389 | (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags. | |
390 | ||
4d1464f2 MW |
391 | 2016-06-07 Matthew Wahab <matthew.wahab@arm.com> |
392 | ||
393 | * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with | |
394 | ARM_EXT_RAS in relevant entries. | |
395 | ||
026122a6 PB |
396 | 2016-06-03 Peter Bergner <bergner@vnet.ibm.com> |
397 | ||
398 | PR binutils/20196 | |
399 | * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable | |
400 | opcodes for E6500. | |
401 | ||
07f5af7d L |
402 | 2016-06-03 H.J. Lu <hongjiu.lu@intel.com> |
403 | ||
404 | PR binutis/18386 | |
405 | * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode. | |
406 | (indir_v_mode): New. | |
407 | Add comments for '&'. | |
408 | (reg_table): Replace "{T|}" with "{&|}" on call and jmp. | |
409 | (putop): Handle '&'. | |
410 | (intel_operand_size): Handle indir_v_mode. | |
411 | (OP_E_register): Likewise. | |
412 | * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add | |
413 | 64-bit indirect call/jmp for AMD64. | |
414 | * i386-tbl.h: Regenerated | |
415 | ||
4eb6f892 AB |
416 | 2016-06-02 Andrew Burgess <andrew.burgess@embecosm.com> |
417 | ||
418 | * arc-dis.c (struct arc_operand_iterator): New structure. | |
419 | (find_format_from_table): All the old content from find_format, | |
420 | with some minor adjustments, and parameter renaming. | |
421 | (find_format_long_instructions): New function. | |
422 | (find_format): Rewritten. | |
423 | (arc_insn_length): Add LSB parameter. | |
424 | (extract_operand_value): New function. | |
425 | (operand_iterator_next): New function. | |
426 | (print_insn_arc): Use new functions to find opcode, and iterator | |
427 | over operands. | |
428 | * arc-opc.c (insert_nps_3bit_dst_short): New function. | |
429 | (extract_nps_3bit_dst_short): New function. | |
430 | (insert_nps_3bit_src2_short): New function. | |
431 | (extract_nps_3bit_src2_short): New function. | |
432 | (insert_nps_bitop1_size): New function. | |
433 | (extract_nps_bitop1_size): New function. | |
434 | (insert_nps_bitop2_size): New function. | |
435 | (extract_nps_bitop2_size): New function. | |
436 | (insert_nps_bitop_mod4_msb): New function. | |
437 | (extract_nps_bitop_mod4_msb): New function. | |
438 | (insert_nps_bitop_mod4_lsb): New function. | |
439 | (extract_nps_bitop_mod4_lsb): New function. | |
440 | (insert_nps_bitop_dst_pos3_pos4): New function. | |
441 | (extract_nps_bitop_dst_pos3_pos4): New function. | |
442 | (insert_nps_bitop_ins_ext): New function. | |
443 | (extract_nps_bitop_ins_ext): New function. | |
444 | (arc_operands): Add new operands. | |
445 | (arc_long_opcodes): New global array. | |
446 | (arc_num_long_opcodes): New global. | |
447 | * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes. | |
448 | ||
1fe0971e TS |
449 | 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> |
450 | ||
451 | * nds32-asm.h: Add extern "C". | |
452 | * sh-opc.h: Likewise. | |
453 | ||
315f180f GM |
454 | 2016-06-01 Graham Markall <graham.markall@embecosm.com> |
455 | ||
456 | * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and | |
457 | 0,b,limm to the rflt instruction. | |
458 | ||
a2b5fccc TS |
459 | 2016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> |
460 | ||
461 | * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned | |
462 | constant. | |
463 | ||
0cbd0046 L |
464 | 2016-05-29 H.J. Lu <hongjiu.lu@intel.com> |
465 | ||
466 | PR gas/20145 | |
467 | * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS, | |
468 | CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS, | |
469 | CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS, | |
470 | CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS, | |
471 | CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS. | |
472 | * i386-init.h: Regenerated. | |
473 | ||
1848e567 L |
474 | 2016-05-27 H.J. Lu <hongjiu.lu@intel.com> |
475 | ||
476 | PR gas/20145 | |
477 | * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove | |
478 | CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from | |
479 | CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS. | |
480 | Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and | |
481 | CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from | |
482 | CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS, | |
483 | CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS. | |
484 | Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS, | |
485 | CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS, | |
486 | CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS, | |
487 | CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX | |
488 | for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable | |
489 | CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and | |
490 | CpuRegMask for AVX512. | |
491 | (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM | |
492 | and CpuRegMask. | |
493 | (set_bitfield_from_cpu_flag_init): New function. | |
494 | (set_bitfield): Remove const on f. Call | |
495 | set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS. | |
496 | * i386-opc.h (CpuRegMMX): New. | |
497 | (CpuRegXMM): Likewise. | |
498 | (CpuRegYMM): Likewise. | |
499 | (CpuRegZMM): Likewise. | |
500 | (CpuRegMask): Likewise. | |
501 | (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm | |
502 | and cpuregmask. | |
503 | * i386-init.h: Regenerated. | |
504 | * i386-tbl.h: Likewise. | |
505 | ||
e92bae62 L |
506 | 2016-05-27 H.J. Lu <hongjiu.lu@intel.com> |
507 | ||
508 | PR gas/20154 | |
509 | * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64. | |
510 | (opcode_modifiers): Add AMD64 and Intel64. | |
511 | (main): Properly verify CpuMax. | |
512 | * i386-opc.h (CpuAMD64): Removed. | |
513 | (CpuIntel64): Likewise. | |
514 | (CpuMax): Set to CpuNo64. | |
515 | (i386_cpu_flags): Remove cpuamd64 and cpuintel64. | |
516 | (AMD64): New. | |
517 | (Intel64): Likewise. | |
518 | (i386_opcode_modifier): Add amd64 and intel64. | |
519 | (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64 | |
520 | on call and jmp. | |
521 | * i386-init.h: Regenerated. | |
522 | * i386-tbl.h: Likewise. | |
523 | ||
e89c5eaa L |
524 | 2016-05-27 H.J. Lu <hongjiu.lu@intel.com> |
525 | ||
526 | PR gas/20154 | |
527 | * i386-gen.c (main): Fail if CpuMax is incorrect. | |
528 | * i386-opc.h (CpuMax): Set to CpuIntel64. | |
529 | * i386-tbl.h: Regenerated. | |
530 | ||
77d66e7b NC |
531 | 2016-05-27 Nick Clifton <nickc@redhat.com> |
532 | ||
533 | PR target/20150 | |
534 | * msp430-dis.c (msp430dis_read_two_bytes): New function. | |
535 | (msp430dis_opcode_unsigned): New function. | |
536 | (msp430dis_opcode_signed): New function. | |
537 | (msp430_singleoperand): Use the new opcode reading functions. | |
538 | Only disassenmble bytes if they were successfully read. | |
539 | (msp430_doubleoperand): Likewise. | |
540 | (msp430_branchinstr): Likewise. | |
541 | (msp430x_callx_instr): Likewise. | |
542 | (print_insn_msp430): Check that it is safe to read bytes before | |
543 | attempting disassembly. Use the new opcode reading functions. | |
544 | ||
19dfcc89 PB |
545 | 2016-05-26 Peter Bergner <bergner@vnet.ibm.com> |
546 | ||
547 | * ppc-opc.c (CY): New define. Document it. | |
548 | (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics. | |
549 | ||
f3ad7637 L |
550 | 2016-05-25 H.J. Lu <hongjiu.lu@intel.com> |
551 | ||
552 | * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS, | |
553 | CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS | |
554 | and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW, | |
555 | CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to | |
556 | CPU_ANY_AVX_FLAGS. | |
557 | * i386-init.h: Regenerated. | |
558 | ||
f1360d58 L |
559 | 2016-05-25 H.J. Lu <hongjiu.lu@intel.com> |
560 | ||
561 | PR gas/20141 | |
562 | * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS, | |
563 | CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. | |
564 | * i386-init.h: Regenerated. | |
565 | ||
293f5f65 L |
566 | 2016-05-25 H.J. Lu <hongjiu.lu@intel.com> |
567 | ||
568 | * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to | |
569 | CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS. | |
570 | * i386-init.h: Regenerated. | |
571 | ||
d9eca1df CZ |
572 | 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com> |
573 | ||
574 | * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type | |
575 | information. | |
576 | (print_insn_arc): Set insn_type information. | |
577 | * arc-opc.c (C_CC): Add F_CLASS_COND. | |
578 | * arc-tbl.h (bbit0, bbit1): Update subclass to COND. | |
579 | (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise. | |
580 | (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise. | |
581 | (breq, breq_s, brge, brhs, brlo, brlt): Likewise. | |
582 | (brne, brne_s, jeq_s, jne_s): Likewise. | |
583 | ||
87789e08 CZ |
584 | 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com> |
585 | ||
586 | * arc-tbl.h (neg): New instruction variant. | |
587 | ||
c810e0b8 CZ |
588 | 2016-05-23 Cupertino Miranda <cmiranda@synopsys.com> |
589 | ||
590 | * arc-dis.c (find_format, find_format, get_auxreg) | |
591 | (print_insn_arc): Changed. | |
592 | * arc-ext.h (INSERT_XOP): Likewise. | |
593 | ||
3d207518 TS |
594 | 2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> |
595 | ||
596 | * tic54x-dis.c (sprint_mmr): Adjust. | |
597 | * tic54x-opc.c: Likewise. | |
598 | ||
514e58b7 AM |
599 | 2016-05-19 Alan Modra <amodra@gmail.com> |
600 | ||
601 | * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi. | |
602 | ||
e43de63c AM |
603 | 2016-05-19 Alan Modra <amodra@gmail.com> |
604 | ||
605 | * ppc-opc.c: Formatting. | |
606 | (NSISIGNOPT): Define. | |
607 | (powerpc_opcodes <subis>): Use NSISIGNOPT. | |
608 | ||
1401d2fe MR |
609 | 2016-05-18 Maciej W. Rozycki <macro@imgtec.com> |
610 | ||
611 | * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand, | |
612 | replacing references to `micromips_ase' throughout. | |
613 | (_print_insn_mips): Don't use file-level microMIPS annotation to | |
614 | determine the disassembly mode with the symbol table. | |
615 | ||
1178da44 PB |
616 | 2016-05-13 Peter Bergner <bergner@vnet.ibm.com> |
617 | ||
618 | * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT. | |
619 | ||
8f4f9071 MF |
620 | 2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com> |
621 | ||
622 | * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and | |
623 | mips64r6. | |
624 | * mips-opc.c (D34): New macro. | |
625 | (mips_builtin_opcodes): Define bposge32c for DSPr3. | |
626 | ||
8bc52696 AF |
627 | 2016-05-10 Alexander Fomin <alexander.fomin@intel.com> |
628 | ||
629 | * i386-dis.c (prefix_table): Add RDPID instruction. | |
630 | * i386-gen.c (cpu_flag_init): Add RDPID flag. | |
631 | (cpu_flags): Add RDPID bitfield. | |
632 | * i386-opc.h (enum): Add RDPID element. | |
633 | (i386_cpu_flags): Add RDPID field. | |
634 | * i386-opc.tbl: Add RDPID instruction. | |
635 | * i386-init.h: Regenerate. | |
636 | * i386-tbl.h: Regenerate. | |
637 | ||
39d911fc TP |
638 | 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com> |
639 | ||
640 | * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get | |
641 | branch type of a symbol. | |
642 | (print_insn): Likewise. | |
643 | ||
16a1fa25 TP |
644 | 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com> |
645 | ||
646 | * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M | |
647 | Mainline Security Extensions instructions. | |
648 | (thumb_opcodes): Add entries for narrow ARMv8-M Security | |
649 | Extensions instructions. | |
650 | (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions | |
651 | instructions. | |
652 | (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions | |
653 | special registers. | |
654 | ||
d751b79e JM |
655 | 2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com> |
656 | ||
657 | * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai. | |
658 | ||
945e0f82 CZ |
659 | 2016-05-03 Claudiu Zissulescu <claziss@synopsys.com> |
660 | ||
661 | * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP. | |
662 | (arcExtMap_genOpcode): Likewise. | |
663 | * arc-opc.c (arg_32bit_rc): Define new variable. | |
664 | (arg_32bit_u6): Likewise. | |
665 | (arg_32bit_limm): Likewise. | |
666 | ||
20f55f38 SN |
667 | 2016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com> |
668 | ||
669 | * aarch64-gen.c (VERIFIER): Define. | |
670 | * aarch64-opc.c (VERIFIER): Define. | |
671 | (verify_ldpsw): Use static linkage. | |
672 | * aarch64-opc.h (verify_ldpsw): Remove. | |
673 | * aarch64-tbl.h: Use VERIFIER for verifiers. | |
674 | ||
4bd13cde NC |
675 | 2016-04-28 Nick Clifton <nickc@redhat.com> |
676 | ||
677 | PR target/19722 | |
678 | * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present. | |
679 | * aarch64-opc.c (verify_ldpsw): New function. | |
680 | * aarch64-opc.h (verify_ldpsw): New prototype. | |
681 | * aarch64-tbl.h: Add initialiser for verifier field. | |
682 | (LDPSW): Set verifier to verify_ldpsw. | |
683 | ||
c0f92bf9 L |
684 | 2016-04-23 H.J. Lu <hongjiu.lu@intel.com> |
685 | ||
686 | PR binutils/19983 | |
687 | PR binutils/19984 | |
688 | * i386-dis.c (print_insn): Return -1 if size of bfd_vma is | |
689 | smaller than address size. | |
690 | ||
e6c7cdec TS |
691 | 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> |
692 | ||
693 | * alpha-dis.c: Regenerate. | |
694 | * crx-dis.c: Likewise. | |
695 | * disassemble.c: Likewise. | |
696 | * epiphany-opc.c: Likewise. | |
697 | * fr30-opc.c: Likewise. | |
698 | * frv-opc.c: Likewise. | |
699 | * ip2k-opc.c: Likewise. | |
700 | * iq2000-opc.c: Likewise. | |
701 | * lm32-opc.c: Likewise. | |
702 | * lm32-opinst.c: Likewise. | |
703 | * m32c-opc.c: Likewise. | |
704 | * m32r-opc.c: Likewise. | |
705 | * m32r-opinst.c: Likewise. | |
706 | * mep-opc.c: Likewise. | |
707 | * mt-opc.c: Likewise. | |
708 | * or1k-opc.c: Likewise. | |
709 | * or1k-opinst.c: Likewise. | |
710 | * tic80-opc.c: Likewise. | |
711 | * xc16x-opc.c: Likewise. | |
712 | * xstormy16-opc.c: Likewise. | |
713 | ||
537aefaf AB |
714 | 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com> |
715 | ||
716 | * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb, | |
717 | fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp, | |
718 | calcsd, and calcxd instructions. | |
719 | * arc-opc.c (insert_nps_bitop_size): Delete. | |
720 | (extract_nps_bitop_size): Delete. | |
721 | (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use. | |
722 | (extract_nps_qcmp_m3): Define. | |
723 | (extract_nps_qcmp_m2): Define. | |
724 | (extract_nps_qcmp_m1): Define. | |
725 | (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL. | |
726 | (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL | |
727 | (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE, | |
728 | NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST, | |
729 | NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and | |
730 | NPS_QCMP_M3. | |
731 | ||
c8f785f2 AB |
732 | 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com> |
733 | ||
734 | * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions. | |
735 | ||
6fd8e7c2 L |
736 | 2016-04-15 H.J. Lu <hongjiu.lu@intel.com> |
737 | ||
738 | * Makefile.in: Regenerated with automake 1.11.6. | |
739 | * aclocal.m4: Likewise. | |
740 | ||
4b0c052e AB |
741 | 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com> |
742 | ||
743 | * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst | |
744 | instructions. | |
745 | * arc-opc.c (insert_nps_cmem_uimm16): New function. | |
746 | (extract_nps_cmem_uimm16): New function. | |
747 | (arc_operands): Add NPS_XLDST_UIMM16 operand. | |
748 | ||
cb040366 AB |
749 | 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com> |
750 | ||
751 | * arc-dis.c (arc_insn_length): New function. | |
752 | (print_insn_arc): Use arc_insn_length, change insnLen to unsigned. | |
753 | (find_format): Change insnLen parameter to unsigned. | |
754 | ||
accc0180 NC |
755 | 2016-04-13 Nick Clifton <nickc@redhat.com> |
756 | ||
757 | PR target/19937 | |
758 | * v850-opc.c (v850_opcodes): Correct masks for long versions of | |
759 | the LD.B and LD.BU instructions. | |
760 | ||
f36e33da CZ |
761 | 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com> |
762 | ||
763 | * arc-dis.c (find_format): Check for extension flags. | |
764 | (print_flags): New function. | |
765 | (print_insn_arc): Update for .extCondCode, .extCoreRegister and | |
766 | .extAuxRegister. | |
767 | * arc-ext.c (arcExtMap_coreRegName): Use | |
768 | LAST_EXTENSION_CORE_REGISTER. | |
769 | (arcExtMap_coreReadWrite): Likewise. | |
770 | (dump_ARC_extmap): Update printing. | |
771 | * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag. | |
772 | (arc_aux_regs): Add cpu field. | |
773 | * arc-regs.h: Add cpu field, lower case name aux registers. | |
774 | ||
1c2e355e CZ |
775 | 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com> |
776 | ||
777 | * arc-tbl.h: Add rtsc, sleep with no arguments. | |
778 | ||
b99747ae CZ |
779 | 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com> |
780 | ||
781 | * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf): | |
782 | Initialize. | |
783 | (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc) | |
784 | (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6) | |
785 | (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm) | |
786 | (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm) | |
787 | (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12) | |
788 | (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc) | |
789 | (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm) | |
790 | (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6) | |
791 | (arg_32bit_limms12, arg_32bit_limmlimm): Likewise. | |
792 | (arc_opcode arc_opcodes): Null terminate the array. | |
793 | (arc_num_opcodes): Remove. | |
794 | * arc-ext.h (INSERT_XOP): Define. | |
795 | (extInstruction_t): Likewise. | |
796 | (arcExtMap_instName): Delete. | |
797 | (arcExtMap_insn): New function. | |
798 | (arcExtMap_genOpcode): Likewise. | |
799 | * arc-ext.c (ExtInstruction): Remove. | |
800 | (create_map): Zero initialize instruction fields. | |
801 | (arcExtMap_instName): Remove. | |
802 | (arcExtMap_insn): New function. | |
803 | (dump_ARC_extmap): More info while debuging. | |
804 | (arcExtMap_genOpcode): New function. | |
805 | * arc-dis.c (find_format): New function. | |
806 | (print_insn_arc): Use find_format. | |
807 | (arc_get_disassembler): Enable dump_ARC_extmap only when | |
808 | debugging. | |
809 | ||
92708cec MR |
810 | 2016-04-11 Maciej W. Rozycki <macro@imgtec.com> |
811 | ||
812 | * mips-dis.c (print_mips16_insn_arg): Mask unused extended | |
813 | instruction bits out. | |
814 | ||
a42a4f84 AB |
815 | 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com> |
816 | ||
817 | * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions. | |
818 | * arc-opc.c (arc_flag_operands): Add new flags. | |
819 | (arc_flag_classes): Add new classes. | |
820 | ||
1328504b AB |
821 | 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com> |
822 | ||
823 | * arc-opc.c (arc_opcodes): Extend comment to discus table layout. | |
824 | ||
820f03ff AB |
825 | 2016-04-05 Andrew Burgess <andrew.burgess@embecosm.com> |
826 | ||
827 | * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0, | |
828 | encode1, rflt, crc16, and crc32 instructions. | |
829 | * arc-opc.c (arc_flag_operands): Add F_NPS_R. | |
830 | (arc_flag_classes): Add C_NPS_R. | |
831 | (insert_nps_bitop_size_2b): New function. | |
832 | (extract_nps_bitop_size_2b): Likewise. | |
833 | (insert_nps_bitop_uimm8): Likewise. | |
834 | (extract_nps_bitop_uimm8): Likewise. | |
835 | (arc_operands): Add new operand entries. | |
836 | ||
8ddf6b2a CZ |
837 | 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com> |
838 | ||
b99747ae CZ |
839 | * arc-regs.h: Add a new subclass field. Add double assist |
840 | accumulator register values. | |
841 | * arc-tbl.h: Use DPA subclass to mark the double assist | |
842 | instructions. Use DPX/SPX subclas to mark the FPX instructions. | |
843 | * arc-opc.c (RSP): Define instead of SP. | |
844 | (arc_aux_regs): Add the subclass field. | |
8ddf6b2a | 845 | |
589a7d88 JW |
846 | 2016-04-05 Jiong Wang <jiong.wang@arm.com> |
847 | ||
848 | * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar). | |
849 | ||
0a191de9 | 850 | 2016-03-31 Andrew Burgess <andrew.burgess@embecosm.com> |
2cce10e7 AB |
851 | |
852 | * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and | |
853 | NPS_R_SRC1. | |
854 | ||
0a106562 AB |
855 | 2016-03-30 Andrew Burgess <andrew.burgess@embecosm.com> |
856 | ||
857 | * arc-nps400-tbl.h: Add a header comment, and fix some whitespace | |
858 | issues. No functional changes. | |
859 | ||
bd05ac5f CZ |
860 | 2016-03-30 Claudiu Zissulescu <claziss@synopsys.com> |
861 | ||
b99747ae CZ |
862 | * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0) |
863 | (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1) | |
864 | (RTT): Remove duplicate. | |
865 | (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*) | |
866 | (PCT_CONFIG*): Remove. | |
867 | (D1L, D1H, D2H, D2L): Define. | |
bd05ac5f | 868 | |
9885948f CZ |
869 | 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com> |
870 | ||
b99747ae | 871 | * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo. |
9885948f | 872 | |
f2dd8838 CZ |
873 | 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com> |
874 | ||
b99747ae CZ |
875 | * arc-tbl.h (invld07): Remove. |
876 | * arc-ext-tbl.h: New file. | |
877 | * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove. | |
878 | * arc-opc.c (arc_opcodes): Add ext-tbl include. | |
f2dd8838 | 879 | |
0d2f91fe JK |
880 | 2016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com> |
881 | ||
882 | Fix -Wstack-usage warnings. | |
883 | * aarch64-dis.c (print_operands): Substitute size. | |
884 | * aarch64-opc.c (print_register_offset_address): Substitute tblen. | |
885 | ||
a6b71f42 JM |
886 | 2016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com> |
887 | ||
888 | * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order | |
889 | to get a proper diagnostic when an invalid ASR register is used. | |
890 | ||
9780e045 NC |
891 | 2016-03-22 Nick Clifton <nickc@redhat.com> |
892 | ||
893 | * configure: Regenerate. | |
894 | ||
e23e8ebe AB |
895 | 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com> |
896 | ||
897 | * arc-nps400-tbl.h: New file. | |
898 | * arc-opc.c: Add top level comment. | |
899 | (insert_nps_3bit_dst): New function. | |
900 | (extract_nps_3bit_dst): New function. | |
901 | (insert_nps_3bit_src2): New function. | |
902 | (extract_nps_3bit_src2): New function. | |
903 | (insert_nps_bitop_size): New function. | |
904 | (extract_nps_bitop_size): New function. | |
905 | (arc_flag_operands): Add nps400 entries. | |
906 | (arc_flag_classes): Add nps400 entries. | |
907 | (arc_operands): Add nps400 entries. | |
908 | (arc_opcodes): Add nps400 include. | |
909 | ||
1ae8ab47 AB |
910 | 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com> |
911 | ||
912 | * arc-opc.c (arc_flag_classes): Convert all flag classes to use | |
913 | the new class enum values. | |
914 | ||
8699fc3e AB |
915 | 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com> |
916 | ||
917 | * arc-dis.c (print_insn_arc): Handle nps400. | |
918 | ||
24740d83 AB |
919 | 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com> |
920 | ||
921 | * arc-opc.c (BASE): Delete. | |
922 | ||
8678914f NC |
923 | 2016-03-18 Nick Clifton <nickc@redhat.com> |
924 | ||
925 | PR target/19721 | |
926 | * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand | |
927 | of MOV insn that aliases an ORR insn. | |
928 | ||
cc933301 JW |
929 | 2016-03-16 Jiong Wang <jiong.wang@arm.com> |
930 | ||
931 | * arm-dis.c (neon_opcodes): Support new FP16 instructions. | |
932 | ||
f86f5863 TS |
933 | 2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> |
934 | ||
935 | * mcore-opc.h: Add const qualifiers. | |
936 | * microblaze-opc.h (struct op_code_struct): Likewise. | |
937 | * sh-opc.h: Likewise. | |
938 | * tic4x-dis.c (tic4x_print_indirect): Likewise. | |
939 | (tic4x_print_op): Likewise. | |
940 | ||
62de1c63 AM |
941 | 2016-03-02 Alan Modra <amodra@gmail.com> |
942 | ||
d11698cd | 943 | * or1k-desc.h: Regenerate. |
62de1c63 | 944 | * fr30-ibld.c: Regenerate. |
c697cf0b | 945 | * rl78-decode.c: Regenerate. |
62de1c63 | 946 | |
020efce5 NC |
947 | 2016-03-01 Nick Clifton <nickc@redhat.com> |
948 | ||
949 | PR target/19747 | |
950 | * rl78-dis.c (print_insn_rl78_common): Fix typo. | |
951 | ||
b0c11777 RL |
952 | 2016-02-24 Renlin Li <renlin.li@arm.com> |
953 | ||
954 | * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries. | |
955 | (print_insn_coprocessor): Support fp16 instructions. | |
956 | ||
3e309328 RL |
957 | 2016-02-24 Renlin Li <renlin.li@arm.com> |
958 | ||
959 | * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm, | |
960 | vminnm, vrint(mpna). | |
961 | ||
8afc7bea RL |
962 | 2016-02-24 Renlin Li <renlin.li@arm.com> |
963 | ||
964 | * arm-dis.c (print_insn_coprocessor): Check co-processor number for | |
965 | cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2. | |
966 | ||
4fd7268a L |
967 | 2016-02-15 H.J. Lu <hongjiu.lu@intel.com> |
968 | ||
969 | * i386-dis.c (print_insn): Parenthesize expression to prevent | |
970 | truncated addresses. | |
971 | (OP_J): Likewise. | |
972 | ||
4670103e CZ |
973 | 2016-02-10 Claudiu Zissulescu <claziss@synopsys.com> |
974 | Janek van Oirschot <jvanoirs@synopsys.com> | |
975 | ||
b99747ae CZ |
976 | * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New |
977 | variable. | |
4670103e | 978 | |
c1d9289f NC |
979 | 2016-02-04 Nick Clifton <nickc@redhat.com> |
980 | ||
981 | PR target/19561 | |
982 | * msp430-dis.c (print_insn_msp430): Add a special case for | |
983 | decoding an RRC instruction with the ZC bit set in the extension | |
984 | word. | |
985 | ||
a143b004 AB |
986 | 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com> |
987 | ||
988 | * cgen-ibld.in (insert_normal): Rework calculation of shift. | |
989 | * epiphany-ibld.c: Regenerate. | |
990 | * fr30-ibld.c: Regenerate. | |
991 | * frv-ibld.c: Regenerate. | |
992 | * ip2k-ibld.c: Regenerate. | |
993 | * iq2000-ibld.c: Regenerate. | |
994 | * lm32-ibld.c: Regenerate. | |
995 | * m32c-ibld.c: Regenerate. | |
996 | * m32r-ibld.c: Regenerate. | |
997 | * mep-ibld.c: Regenerate. | |
998 | * mt-ibld.c: Regenerate. | |
999 | * or1k-ibld.c: Regenerate. | |
1000 | * xc16x-ibld.c: Regenerate. | |
1001 | * xstormy16-ibld.c: Regenerate. | |
1002 | ||
b89807c6 AB |
1003 | 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com> |
1004 | ||
1005 | * epiphany-dis.c: Regenerated from latest cpu files. | |
1006 | ||
d8c823c8 MM |
1007 | 2016-02-01 Michael McConville <mmcco@mykolab.com> |
1008 | ||
1009 | * cgen-dis.c (count_decodable_bits): Use unsigned value for mask | |
1010 | test bit. | |
1011 | ||
5bc5ae88 RL |
1012 | 2016-01-25 Renlin Li <renlin.li@arm.com> |
1013 | ||
1014 | * arm-dis.c (mapping_symbol_for_insn): New function. | |
1015 | (find_ifthen_state): Call mapping_symbol_for_insn(). | |
1016 | ||
0bff6e2d MW |
1017 | 2016-01-20 Matthew Wahab <matthew.wahab@arm.com> |
1018 | ||
1019 | * aarch64-opc.c (operand_general_constraint_met_p): Check validity | |
1020 | of MSR UAO immediate operand. | |
1021 | ||
100b4f2e MR |
1022 | 2016-01-18 Maciej W. Rozycki <macro@imgtec.com> |
1023 | ||
1024 | * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS | |
1025 | instruction support. | |
1026 | ||
5c14705f AM |
1027 | 2016-01-17 Alan Modra <amodra@gmail.com> |
1028 | ||
1029 | * configure: Regenerate. | |
1030 | ||
4d82fe66 NC |
1031 | 2016-01-14 Nick Clifton <nickc@redhat.com> |
1032 | ||
1033 | * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw | |
1034 | instructions that can support stack pointer operations. | |
1035 | * rl78-decode.c: Regenerate. | |
1036 | * rl78-dis.c: Fix display of stack pointer in MOVW based | |
1037 | instructions. | |
1038 | ||
651657fa MW |
1039 | 2016-01-14 Matthew Wahab <matthew.wahab@arm.com> |
1040 | ||
1041 | * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals | |
1042 | testing for RAS support. Add checks for erxfr_el1, erxctlr_el1, | |
1043 | erxtatus_el1 and erxaddr_el1. | |
1044 | ||
105bde57 MW |
1045 | 2016-01-12 Matthew Wahab <matthew.wahab@arm.com> |
1046 | ||
1047 | * arm-dis.c (arm_opcodes): Add "esb". | |
1048 | (thumb_opcodes): Likewise. | |
1049 | ||
afa8d405 PB |
1050 | 2016-01-11 Peter Bergner <bergner@vnet.ibm.com> |
1051 | ||
1052 | * ppc-opc.c <xscmpnedp>: Delete. | |
1053 | <xvcmpnedp>: Likewise. | |
1054 | <xvcmpnedp.>: Likewise. | |
1055 | <xvcmpnesp>: Likewise. | |
1056 | <xvcmpnesp.>: Likewise. | |
1057 | ||
83c3256e AS |
1058 | 2016-01-08 Andreas Schwab <schwab@linux-m68k.org> |
1059 | ||
1060 | PR gas/13050 | |
1061 | * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in | |
1062 | addition to ISA_A. | |
1063 | ||
6f2750fe AM |
1064 | 2016-01-01 Alan Modra <amodra@gmail.com> |
1065 | ||
1066 | Update year range in copyright notice of all files. | |
1067 | ||
3499769a AM |
1068 | For older changes see ChangeLog-2015 |
1069 | \f | |
1070 | Copyright (C) 2016 Free Software Foundation, Inc. | |
1071 | ||
1072 | Copying and distribution of this file, with or without modification, | |
1073 | are permitted in any medium without royalty provided the copyright | |
1074 | notice and this notice are preserved. | |
1075 | ||
1076 | Local Variables: | |
1077 | mode: change-log | |
1078 | left-margin: 8 | |
1079 | fill-column: 74 | |
1080 | version-control: never | |
1081 | End: |