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Check invalid mask registers
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
9889cbb1
L		 12016-10-20 H.J. Lu <hongjiu.lu@intel.com>
2
3 PR binutis/20705
4 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
5 the highest bit in VEX.vvvv for the 3-byte VEX prefix in
6 32-bit mode. Don't check vex.register_specifier in 32-bit
7 mode.
8 (OP_VEX): Check for invalid mask registers.
9
28596323
L		 102016-10-18 H.J. Lu <hongjiu.lu@intel.com>
11
12 PR binutis/20699
13 * i386-dis.c (OP_E_memory): Check addr32flag in stead of
14 sizeflag.
15
da8d7d66
L		 162016-10-18 H.J. Lu <hongjiu.lu@intel.com>
17
18 PR binutis/20704
19 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
20
eaf02703
MR		 212016-10-18 Maciej W. Rozycki <macro@imgtec.com>
22
23 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
24 local variable to `index_regno'.
25
decf5bd1
CM		 262016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
27
28 * arc-tbl.h: Removed any "inv.+" instructions from the table.
29
e5b06ef0
CZ		 302016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
31
32 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
33 usage on ISA basis.
34
93562a34
JW		 352016-10-11 Jiong Wang <jiong.wang@arm.com>
36
37 PR target/20666
38 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
39
362c0c4d
JW		 402016-10-07 Jiong Wang <jiong.wang@arm.com>
41
42 PR target/20667
43 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
44 available.
45
1047201f
AM		 462016-10-07 Alan Modra <amodra@gmail.com>
47
48 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
49
1a0670f3
AM		 502016-10-06 Alan Modra <amodra@gmail.com>
51
52 * aarch64-opc.c: Spell fall through comments consistently.
53 * i386-dis.c: Likewise.
54 * aarch64-dis.c: Add missing fall through comments.
55 * aarch64-opc.c: Likewise.
56 * arc-dis.c: Likewise.
57 * arm-dis.c: Likewise.
58 * i386-dis.c: Likewise.
59 * m68k-dis.c: Likewise.
60 * mep-asm.c: Likewise.
61 * ns32k-dis.c: Likewise.
62 * sh-dis.c: Likewise.
63 * tic4x-dis.c: Likewise.
64 * tic6x-dis.c: Likewise.
65 * vax-dis.c: Likewise.
66
2b804145
AM		 672016-10-06 Alan Modra <amodra@gmail.com>
68
69 * arc-ext.c (create_map): Add missing break.
70 * msp430-decode.opc (encode_as): Likewise.
71 * msp430-decode.c: Regenerate.
72
616ec358
AM		 732016-10-06 Alan Modra <amodra@gmail.com>
74
75 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
76 * crx-dis.c (print_insn_crx): Likewise.
77
72da393d
L		 782016-09-30 H.J. Lu <hongjiu.lu@intel.com>
79
80 PR binutils/20657
81 * i386-dis.c (putop): Don't assign alt twice.
82
744ce302
JW		 832016-09-29 Jiong Wang <jiong.wang@arm.com>
84
85 PR target/20553
86 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
87
a5721ba2
AM		 882016-09-29 Alan Modra <amodra@gmail.com>
89
90 * ppc-opc.c (L): Make compulsory.
91 (LOPT): New, optional form of L.
92 (HTM_R): Define as LOPT.
93 (L0, L1): Delete.
94 (L32OPT): New, optional for 32-bit L.
95 (L2OPT): New, 2-bit L for dcbf.
96 (SVC_LEC): Update.
97 (L2): Define.
98 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
99 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
100 <dcbf>: Use L2OPT.
101 <tlbiel, tlbie>: Use LOPT.
102 <wclr, wclrall>: Use L2.
103
c5da1932
VZ		 1042016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
105
106 * Makefile.in: Regenerate.
107 * configure: Likewise.
108
2b848ebd
CZ		 1092016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
110
111 * arc-ext-tbl.h (EXTINSN2OPF): Define.
112 (EXTINSN2OP): Use EXTINSN2OPF.
113 (bspeekm, bspop, modapp): New extension instructions.
114 * arc-opc.c (F_DNZ_ND): Define.
115 (F_DNZ_D): Likewise.
116 (F_SIZEB1): Changed.
117 (C_DNZ_D): Define.
118 (C_HARD): Changed.
119 * arc-tbl.h (dbnz): New instruction.
120 (prealloc): Allow it for ARC EM.
121 (xbfu): Likewise.
122
ad43e107
RS		 1232016-09-21 Richard Sandiford <richard.sandiford@arm.com>
124
125 * aarch64-opc.c (print_immediate_offset_address): Print spaces
126 after commas in addresses.
127 (aarch64_print_operand): Likewise.
128
ab3b8fcf
RS		 1292016-09-21 Richard Sandiford <richard.sandiford@arm.com>
130
131 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
132 rather than "should be" or "expected to be" in error messages.
133
bb7eff52
RS		 1342016-09-21 Richard Sandiford <richard.sandiford@arm.com>
135
136 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
137 (print_mnemonic_name): ...here.
138 (print_comment): New function.
139 (print_aarch64_insn): Call it.
140 * aarch64-opc.c (aarch64_conds): Add SVE names.
141 (aarch64_print_operand): Print alternative condition names in
142 a comment.
143
c0890d26
RS		 1442016-09-21 Richard Sandiford <richard.sandiford@arm.com>
145
146 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
147 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
148 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
149 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
150 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
151 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
152 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
153 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
154 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
155 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
156 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
157 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
158 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
159 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
160 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
161 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
162 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
163 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
164 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
165 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
166 (OP_SVE_XWU, OP_SVE_XXU): New macros.
167 (aarch64_feature_sve): New variable.
168 (SVE): New macro.
169 (_SVE_INSN): Likewise.
170 (aarch64_opcode_table): Add SVE instructions.
171 * aarch64-opc.h (extract_fields): Declare.
172 * aarch64-opc-2.c: Regenerate.
173 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
174 * aarch64-asm-2.c: Regenerate.
175 * aarch64-dis.c (extract_fields): Make global.
176 (do_misc_decoding): Handle the new SVE aarch64_ops.
177 * aarch64-dis-2.c: Regenerate.
178
116b6019
RS		 1792016-09-21 Richard Sandiford <richard.sandiford@arm.com>
180
181 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
182 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
183 aarch64_field_kinds.
184 * aarch64-opc.c (fields): Add corresponding entries.
185 * aarch64-asm.c (aarch64_get_variant): New function.
186 (aarch64_encode_variant_using_iclass): Likewise.
187 (aarch64_opcode_encode): Call it.
188 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
189 (aarch64_opcode_decode): Call it.
190
047cd301
RS		 1912016-09-21 Richard Sandiford <richard.sandiford@arm.com>
192
193 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
194 and FP register operands.
195 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
196 (FLD_SVE_Vn): New aarch64_field_kinds.
197 * aarch64-opc.c (fields): Add corresponding entries.
198 (aarch64_print_operand): Handle the new SVE core and FP register
199 operands.
200 * aarch64-opc-2.c: Regenerate.
201 * aarch64-asm-2.c: Likewise.
202 * aarch64-dis-2.c: Likewise.
203
165d4950
RS		 2042016-09-21 Richard Sandiford <richard.sandiford@arm.com>
205
206 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
207 immediate operands.
208 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
209 * aarch64-opc.c (fields): Add corresponding entry.
210 (operand_general_constraint_met_p): Handle the new SVE FP immediate
211 operands.
212 (aarch64_print_operand): Likewise.
213 * aarch64-opc-2.c: Regenerate.
214 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
215 (ins_sve_float_zero_one): New inserters.
216 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
217 (aarch64_ins_sve_float_half_two): Likewise.
218 (aarch64_ins_sve_float_zero_one): Likewise.
219 * aarch64-asm-2.c: Regenerate.
220 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
221 (ext_sve_float_zero_one): New extractors.
222 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
223 (aarch64_ext_sve_float_half_two): Likewise.
224 (aarch64_ext_sve_float_zero_one): Likewise.
225 * aarch64-dis-2.c: Regenerate.
226
e950b345
RS		 2272016-09-21 Richard Sandiford <richard.sandiford@arm.com>
228
229 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
230 integer immediate operands.
231 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
232 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
233 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
234 * aarch64-opc.c (fields): Add corresponding entries.
235 (operand_general_constraint_met_p): Handle the new SVE integer
236 immediate operands.
237 (aarch64_print_operand): Likewise.
238 (aarch64_sve_dupm_mov_immediate_p): New function.
239 * aarch64-opc-2.c: Regenerate.
240 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
241 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
242 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
243 (aarch64_ins_limm): ...here.
244 (aarch64_ins_inv_limm): New function.
245 (aarch64_ins_sve_aimm): Likewise.
246 (aarch64_ins_sve_asimm): Likewise.
247 (aarch64_ins_sve_limm_mov): Likewise.
248 (aarch64_ins_sve_shlimm): Likewise.
249 (aarch64_ins_sve_shrimm): Likewise.
250 * aarch64-asm-2.c: Regenerate.
251 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
252 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
253 * aarch64-dis.c (decode_limm): New function, split out from...
254 (aarch64_ext_limm): ...here.
255 (aarch64_ext_inv_limm): New function.
256 (decode_sve_aimm): Likewise.
257 (aarch64_ext_sve_aimm): Likewise.
258 (aarch64_ext_sve_asimm): Likewise.
259 (aarch64_ext_sve_limm_mov): Likewise.
260 (aarch64_top_bit): Likewise.
261 (aarch64_ext_sve_shlimm): Likewise.
262 (aarch64_ext_sve_shrimm): Likewise.
263 * aarch64-dis-2.c: Regenerate.
264
98907a70
RS		 2652016-09-21 Richard Sandiford <richard.sandiford@arm.com>
266
267 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
268 operands.
269 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
270 the AARCH64_MOD_MUL_VL entry.
271 (value_aligned_p): Cope with non-power-of-two alignments.
272 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
273 (print_immediate_offset_address): Likewise.
274 (aarch64_print_operand): Likewise.
275 * aarch64-opc-2.c: Regenerate.
276 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
277 (ins_sve_addr_ri_s9xvl): New inserters.
278 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
279 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
280 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
281 * aarch64-asm-2.c: Regenerate.
282 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
283 (ext_sve_addr_ri_s9xvl): New extractors.
284 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
285 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
286 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
287 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
288 * aarch64-dis-2.c: Regenerate.
289
4df068de
RS		 2902016-09-21 Richard Sandiford <richard.sandiford@arm.com>
291
292 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
293 address operands.
294 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
295 (FLD_SVE_xs_22): New aarch64_field_kinds.
296 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
297 (get_operand_specific_data): New function.
298 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
299 FLD_SVE_xs_14 and FLD_SVE_xs_22.
300 (operand_general_constraint_met_p): Handle the new SVE address
301 operands.
302 (sve_reg): New array.
303 (get_addr_sve_reg_name): New function.
304 (aarch64_print_operand): Handle the new SVE address operands.
305 * aarch64-opc-2.c: Regenerate.
306 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
307 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
308 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
309 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
310 (aarch64_ins_sve_addr_rr_lsl): Likewise.
311 (aarch64_ins_sve_addr_rz_xtw): Likewise.
312 (aarch64_ins_sve_addr_zi_u5): Likewise.
313 (aarch64_ins_sve_addr_zz): Likewise.
314 (aarch64_ins_sve_addr_zz_lsl): Likewise.
315 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
316 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
317 * aarch64-asm-2.c: Regenerate.
318 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
319 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
320 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
321 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
322 (aarch64_ext_sve_addr_ri_u6): Likewise.
323 (aarch64_ext_sve_addr_rr_lsl): Likewise.
324 (aarch64_ext_sve_addr_rz_xtw): Likewise.
325 (aarch64_ext_sve_addr_zi_u5): Likewise.
326 (aarch64_ext_sve_addr_zz): Likewise.
327 (aarch64_ext_sve_addr_zz_lsl): Likewise.
328 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
329 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
330 * aarch64-dis-2.c: Regenerate.
331
2442d846
RS		 3322016-09-21 Richard Sandiford <richard.sandiford@arm.com>
333
334 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
335 AARCH64_OPND_SVE_PATTERN_SCALED.
336 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
337 * aarch64-opc.c (fields): Add a corresponding entry.
338 (set_multiplier_out_of_range_error): New function.
339 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
340 (operand_general_constraint_met_p): Handle
341 AARCH64_OPND_SVE_PATTERN_SCALED.
342 (print_register_offset_address): Use PRIi64 to print the
343 shift amount.
344 (aarch64_print_operand): Likewise. Handle
345 AARCH64_OPND_SVE_PATTERN_SCALED.
346 * aarch64-opc-2.c: Regenerate.
347 * aarch64-asm.h (ins_sve_scale): New inserter.
348 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
349 * aarch64-asm-2.c: Regenerate.
350 * aarch64-dis.h (ext_sve_scale): New inserter.
351 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
352 * aarch64-dis-2.c: Regenerate.
353
245d2e3f
RS		 3542016-09-21 Richard Sandiford <richard.sandiford@arm.com>
355
356 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
357 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
358 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
359 (FLD_SVE_prfop): Likewise.
360 * aarch64-opc.c: Include libiberty.h.
361 (aarch64_sve_pattern_array): New variable.
362 (aarch64_sve_prfop_array): Likewise.
363 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
364 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
365 AARCH64_OPND_SVE_PRFOP.
366 * aarch64-asm-2.c: Regenerate.
367 * aarch64-dis-2.c: Likewise.
368 * aarch64-opc-2.c: Likewise.
369
d50c751e
RS		 3702016-09-21 Richard Sandiford <richard.sandiford@arm.com>
371
372 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
373 AARCH64_OPND_QLF_P_[ZM].
374 (aarch64_print_operand): Print /z and /m where appropriate.
375
f11ad6bc
RS		 3762016-09-21 Richard Sandiford <richard.sandiford@arm.com>
377
378 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
379 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
380 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
381 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
382 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
383 * aarch64-opc.c (fields): Add corresponding entries here.
384 (operand_general_constraint_met_p): Check that SVE register lists
385 have the correct length. Check the ranges of SVE index registers.
386 Check for cases where p8-p15 are used in 3-bit predicate fields.
387 (aarch64_print_operand): Handle the new SVE operands.
388 * aarch64-opc-2.c: Regenerate.
389 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
390 * aarch64-asm.c (aarch64_ins_sve_index): New function.
391 (aarch64_ins_sve_reglist): Likewise.
392 * aarch64-asm-2.c: Regenerate.
393 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
394 * aarch64-dis.c (aarch64_ext_sve_index): New function.
395 (aarch64_ext_sve_reglist): Likewise.
396 * aarch64-dis-2.c: Regenerate.
397
0c608d6b
RS		 3982016-09-21 Richard Sandiford <richard.sandiford@arm.com>
399
400 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
401 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
402 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
403 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
404 tied operands.
405
01dbfe4c
RS		 4062016-09-21 Richard Sandiford <richard.sandiford@arm.com>
407
408 * aarch64-opc.c (get_offset_int_reg_name): New function.
409 (print_immediate_offset_address): Likewise.
410 (print_register_offset_address): Take the base and offset
411 registers as parameters.
412 (aarch64_print_operand): Update caller accordingly. Use
413 print_immediate_offset_address.
414
72e9f319
RS		 4152016-09-21 Richard Sandiford <richard.sandiford@arm.com>
416
417 * aarch64-opc.c (BANK): New macro.
418 (R32, R64): Take a register number as argument
419 (int_reg): Use BANK.
420
8a7f0c1b
RS		 4212016-09-21 Richard Sandiford <richard.sandiford@arm.com>
422
423 * aarch64-opc.c (print_register_list): Add a prefix parameter.
424 (aarch64_print_operand): Update accordingly.
425
aa2aa4c6
RS		 4262016-09-21 Richard Sandiford <richard.sandiford@arm.com>
427
428 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
429 for FPIMM.
430 * aarch64-asm.h (ins_fpimm): New inserter.
431 * aarch64-asm.c (aarch64_ins_fpimm): New function.
432 * aarch64-asm-2.c: Regenerate.
433 * aarch64-dis.h (ext_fpimm): New extractor.
434 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
435 (aarch64_ext_fpimm): New function.
436 * aarch64-dis-2.c: Regenerate.
437
b5464a68
RS		 4382016-09-21 Richard Sandiford <richard.sandiford@arm.com>
439
440 * aarch64-asm.c: Include libiberty.h.
441 (insert_fields): New function.
442 (aarch64_ins_imm): Use it.
443 * aarch64-dis.c (extract_fields): New function.
444 (aarch64_ext_imm): Use it.
445
42408347
RS		 4462016-09-21 Richard Sandiford <richard.sandiford@arm.com>
447
448 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
449 with an esize parameter.
450 (operand_general_constraint_met_p): Update accordingly.
451 Fix misindented code.
452 * aarch64-asm.c (aarch64_ins_limm): Update call to
453 aarch64_logical_immediate_p.
454
4989adac
RS		 4552016-09-21 Richard Sandiford <richard.sandiford@arm.com>
456
457 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
458
bd11d5d8
RS		 4592016-09-21 Richard Sandiford <richard.sandiford@arm.com>
460
461 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
462
f807f43d
CZ		 4632016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
464
465 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
466
fd486b63
PB		 4672016-09-14 Peter Bergner <bergner@vnet.ibm.com>
468
469 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
470 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
471 xor3>: Delete mnemonics.
472 <cp_abort>: Rename mnemonic from ...
473 <cpabort>: ...to this.
474 <setb>: Change to a X form instruction.
475 <sync>: Change to 1 operand form.
476 <copy>: Delete mnemonic.
477 <copy_first>: Rename mnemonic from ...
478 <copy>: ...to this.
479 <paste, paste.>: Delete mnemonics.
480 <paste_last>: Rename mnemonic from ...
481 <paste.>: ...to this.
482
dce08442
AK		 4832016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
484
485 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
486
952c3f51
AK		 4872016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
488
489 * s390-mkopc.c (main): Support alternate arch strings.
490
8b71537b
PS		 4912016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
492
493 * s390-opc.txt: Fix kmctr instruction type.
494
5b64d091
L		 4952016-09-07 H.J. Lu <hongjiu.lu@intel.com>
496
497 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
498 * i386-init.h: Regenerated.
499
7763838e
CM		 5002016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
501
502 * opcodes/arc-dis.c (print_insn_arc): Changed.
503
1b8b6532
JM		 5042016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
505
506 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
507 camellia_fl.
508
1a336194
TP		 5092016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
510
511 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
512 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
513 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
514
6b40c462
L		 5152016-08-24 H.J. Lu <hongjiu.lu@intel.com>
516
517 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
518 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
519 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
520 PREFIX_MOD_3_0FAE_REG_4.
521 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
522 PREFIX_MOD_3_0FAE_REG_4.
523 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
524 (cpu_flags): Add CpuPTWRITE.
525 * i386-opc.h (CpuPTWRITE): New.
526 (i386_cpu_flags): Add cpuptwrite.
527 * i386-opc.tbl: Add ptwrite instruction.
528 * i386-init.h: Regenerated.
529 * i386-tbl.h: Likewise.
530
ab548d2d
AK		 5312016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
532
533 * arc-dis.h: Wrap around in extern "C".
534
344bde0a
RS		 5352016-08-23 Richard Sandiford <richard.sandiford@arm.com>
536
537 * aarch64-tbl.h (V8_2_INSN): New macro.
538 (aarch64_opcode_table): Use it.
539
5ce912d8
RS		 5402016-08-23 Richard Sandiford <richard.sandiford@arm.com>
541
542 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
543 CORE_INSN, __FP_INSN and SIMD_INSN.
544
9d30b0bd
RS		 5452016-08-23 Richard Sandiford <richard.sandiford@arm.com>
546
547 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
548 (aarch64_opcode_table): Update uses accordingly.
549
dfdaec14
AJ		 5502016-07-25 Andrew Jenner <andrew@codesourcery.com>
551 Kwok Cheung Yeung <kcy@codesourcery.com>
552
553 opcodes/
554 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
555 'e_cmplwi' to 'e_cmpli' instead.
556 (OPVUPRT, OPVUPRT_MASK): Define.
557 (powerpc_opcodes): Add E200Z4 insns.
558 (vle_opcodes): Add context save/restore insns.
559
7bd374a4
MR		 5602016-07-27 Maciej W. Rozycki <macro@imgtec.com>
561
562 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
563 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
564 "j".
565
db18dbab
GM		 5662016-07-27 Graham Markall <graham.markall@embecosm.com>
567
568 * arc-nps400-tbl.h: Change block comments to GNU format.
569 * arc-dis.c: Add new globals addrtypenames,
570 addrtypenames_max, and addtypeunknown.
571 (get_addrtype): New function.
572 (print_insn_arc): Print colons and address types when
573 required.
574 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
575 define insert and extract functions for all address types.
576 (arc_operands): Add operands for colon and all address
577 types.
578 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
579 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
580 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
581 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
582 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
583 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
584
fecd57f9
L		 5852016-07-21 H.J. Lu <hongjiu.lu@intel.com>
586
587 * configure: Regenerated.
588
37fd5ef3
CZ		 5892016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
590
591 * arc-dis.c (skipclass): New structure.
592 (decodelist): New variable.
593 (is_compatible_p): New function.
594 (new_element): Likewise.
595 (skip_class_p): Likewise.
596 (find_format_from_table): Use skip_class_p function.
597 (find_format): Decode first the extension instructions.
598 (print_insn_arc): Select either ARCEM or ARCHS based on elf
599 e_flags.
600 (parse_option): New function.
601 (parse_disassembler_options): Likewise.
602 (print_arc_disassembler_options): Likewise.
603 (print_insn_arc): Use parse_disassembler_options function. Proper
604 select ARCv2 cpu variant.
605 * disassemble.c (disassembler_usage): Add ARC disassembler
606 options.
607
92281a5b
MR		 6082016-07-13 Maciej W. Rozycki <macro@imgtec.com>
609
610 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
611 annotation from the "nal" entry and reorder it beyond "bltzal".
612
6e7ced37
JM		 6132016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
614
615 * sparc-opc.c (ldtxa): New macro.
616 (sparc_opcodes): Use the macro defined above to add entries for
617 the LDTXA instructions.
618 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
619 instruction.
620
2f831b9a 6212016-07-07 James Bowman <james.bowman@ftdichip.com>
622
623 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
624 and "jmpc".
625
c07315e0
JB		 6262016-07-01 Jan Beulich <jbeulich@suse.com>
627
628 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
629 (movzb): Adjust to cover all permitted suffixes.
630 (movzw): New.
631 * i386-tbl.h: Re-generate.
632
9243100a
JB		 6332016-07-01 Jan Beulich <jbeulich@suse.com>
634
635 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
636 (lgdt): Remove Tbyte from non-64-bit variant.
637 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
638 xsaves64, xsavec64): Remove Disp16.
639 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
640 Remove Disp32S from non-64-bit variants. Remove Disp16 from
641 64-bit variants.
642 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
643 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
644 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
645 64-bit variants.
646 * i386-tbl.h: Re-generate.
647
8325cc63
JB		 6482016-07-01 Jan Beulich <jbeulich@suse.com>
649
650 * i386-opc.tbl (xlat): Remove RepPrefixOk.
651 * i386-tbl.h: Re-generate.
652
838441e4
YQ		 6532016-06-30 Yao Qi <yao.qi@linaro.org>
654
655 * arm-dis.c (print_insn): Fix typo in comment.
656
dab26bf4
RS		 6572016-06-28 Richard Sandiford <richard.sandiford@arm.com>
658
659 * aarch64-opc.c (operand_general_constraint_met_p): Check the
660 range of ldst_elemlist operands.
661 (print_register_list): Use PRIi64 to print the index.
662 (aarch64_print_operand): Likewise.
663
5703197e
TS		 6642016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
665
666 * mcore-opc.h: Remove sentinal.
667 * mcore-dis.c (print_insn_mcore): Adjust.
668
ce440d63
GM		 6692016-06-23 Graham Markall <graham.markall@embecosm.com>
670
671 * arc-opc.c: Correct description of availability of NPS400
672 features.
673
6fd3a02d
PB		 6742016-06-22 Peter Bergner <bergner@vnet.ibm.com>
675
676 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
677 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
678 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
679 xor3>: New mnemonics.
680 <setb>: Change to a VX form instruction.
681 (insert_sh6): Add support for rldixor.
682 (extract_sh6): Likewise.
683
6b477896
TS		 6842016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
685
686 * arc-ext.h: Wrap in extern C.
687
bdd582db
GM		 6882016-06-21 Graham Markall <graham.markall@embecosm.com>
689
690 * arc-dis.c (arc_insn_length): Add comment on instruction length.
691 Use same method for determining instruction length on ARC700 and
692 NPS-400.
693 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
694 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
695 with the NPS400 subclass.
696 * arc-opc.c: Likewise.
697
96074adc
JM		 6982016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
699
700 * sparc-opc.c (rdasr): New macro.
701 (wrasr): Likewise.
702 (rdpr): Likewise.
703 (wrpr): Likewise.
704 (rdhpr): Likewise.
705 (wrhpr): Likewise.
706 (sparc_opcodes): Use the macros above to fix and expand the
707 definition of read/write instructions from/to
708 asr/privileged/hyperprivileged instructions.
709 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
710 %hva_mask_nz. Prefer softint_set and softint_clear over
711 set_softint and clear_softint.
712 (print_insn_sparc): Support %ver in Rd.
713
7a10c22f
JM		 7142016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
715
716 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
717 architecture according to the hardware capabilities they require.
718
4f26fb3a
JM		 7192016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
720
721 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
722 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
723 bfd_mach_sparc_v9{c,d,e,v,m}.
724 * sparc-opc.c (MASK_V9C): Define.
725 (MASK_V9D): Likewise.
726 (MASK_V9E): Likewise.
727 (MASK_V9V): Likewise.
728 (MASK_V9M): Likewise.
729 (v6): Add MASK_V9{C,D,E,V,M}.
730 (v6notlet): Likewise.
731 (v7): Likewise.
732 (v8): Likewise.
733 (v9): Likewise.
734 (v9andleon): Likewise.
735 (v9a): Likewise.
736 (v9b): Likewise.
737 (v9c): Define.
738 (v9d): Likewise.
739 (v9e): Likewise.
740 (v9v): Likewise.
741 (v9m): Likewise.
742 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
743
3ee6e4fb
NC		 7442016-06-15 Nick Clifton <nickc@redhat.com>
745
746 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
747 constants to match expected behaviour.
748 (nds32_parse_opcode): Likewise. Also for whitespace.
749
02f3be19
AB		 7502016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
751
752 * arc-opc.c (extract_rhv1): Extract value from insn.
753
6f9f37ed 7542016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM		 755
756 * arc-nps400-tbl.h: Add ldbit instruction.
757 * arc-opc.c: Add flag classes required for ldbit.
758
6f9f37ed 7592016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM		 760
761 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
762 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
763 support the above instructions.
764
6f9f37ed 7652016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM		 766
767 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
768 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
769 csma, cbba, zncv, and hofs.
770 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
771 support the above instructions.
772
7732016-06-06 Graham Markall <graham.markall@embecosm.com>
774
775 * arc-nps400-tbl.h: Add andab and orab instructions.
776
7772016-06-06 Graham Markall <graham.markall@embecosm.com>
778
779 * arc-nps400-tbl.h: Add addl-like instructions.
780
7812016-06-06 Graham Markall <graham.markall@embecosm.com>
782
783 * arc-nps400-tbl.h: Add mxb and imxb instructions.
784
7852016-06-06 Graham Markall <graham.markall@embecosm.com>
786
787 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
788 instructions.
789
b2cc3f6f
AK		 7902016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
791
792 * s390-dis.c (option_use_insn_len_bits_p): New file scope
793 variable.
794 (init_disasm): Handle new command line option "insnlength".
795 (print_s390_disassembler_options): Mention new option in help
796 output.
797 (print_insn_s390): Use the encoded insn length when dumping
798 unknown instructions.
799
1857fe72
DC		 8002016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
801
802 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
803 to the address and set as symbol address for LDS/ STS immediate operands.
804
14b57c7c
AM		 8052016-06-07 Alan Modra <amodra@gmail.com>
806
807 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
808 cpu for "vle" to e500.
809 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
810 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
811 (PPCNONE): Delete, substitute throughout.
812 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
813 except for major opcode 4 and 31.
814 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
815
4d1464f2
MW		 8162016-06-07 Matthew Wahab <matthew.wahab@arm.com>
817
818 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
819 ARM_EXT_RAS in relevant entries.
820
026122a6
PB		 8212016-06-03 Peter Bergner <bergner@vnet.ibm.com>
822
823 PR binutils/20196
824 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
825 opcodes for E6500.
826
07f5af7d
L		 8272016-06-03 H.J. Lu <hongjiu.lu@intel.com>
828
829 PR binutis/18386
830 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
831 (indir_v_mode): New.
832 Add comments for '&'.
833 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
834 (putop): Handle '&'.
835 (intel_operand_size): Handle indir_v_mode.
836 (OP_E_register): Likewise.
837 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
838 64-bit indirect call/jmp for AMD64.
839 * i386-tbl.h: Regenerated
840
4eb6f892
AB		 8412016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
842
843 * arc-dis.c (struct arc_operand_iterator): New structure.
844 (find_format_from_table): All the old content from find_format,
845 with some minor adjustments, and parameter renaming.
846 (find_format_long_instructions): New function.
847 (find_format): Rewritten.
848 (arc_insn_length): Add LSB parameter.
849 (extract_operand_value): New function.
850 (operand_iterator_next): New function.
851 (print_insn_arc): Use new functions to find opcode, and iterator
852 over operands.
853 * arc-opc.c (insert_nps_3bit_dst_short): New function.
854 (extract_nps_3bit_dst_short): New function.
855 (insert_nps_3bit_src2_short): New function.
856 (extract_nps_3bit_src2_short): New function.
857 (insert_nps_bitop1_size): New function.
858 (extract_nps_bitop1_size): New function.
859 (insert_nps_bitop2_size): New function.
860 (extract_nps_bitop2_size): New function.
861 (insert_nps_bitop_mod4_msb): New function.
862 (extract_nps_bitop_mod4_msb): New function.
863 (insert_nps_bitop_mod4_lsb): New function.
864 (extract_nps_bitop_mod4_lsb): New function.
865 (insert_nps_bitop_dst_pos3_pos4): New function.
866 (extract_nps_bitop_dst_pos3_pos4): New function.
867 (insert_nps_bitop_ins_ext): New function.
868 (extract_nps_bitop_ins_ext): New function.
869 (arc_operands): Add new operands.
870 (arc_long_opcodes): New global array.
871 (arc_num_long_opcodes): New global.
872 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
873
1fe0971e
TS		 8742016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
875
876 * nds32-asm.h: Add extern "C".
877 * sh-opc.h: Likewise.
878
315f180f
GM		 8792016-06-01 Graham Markall <graham.markall@embecosm.com>
880
881 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
882 0,b,limm to the rflt instruction.
883
a2b5fccc
TS		 8842016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
885
886 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
887 constant.
888
0cbd0046
L		 8892016-05-29 H.J. Lu <hongjiu.lu@intel.com>
890
891 PR gas/20145
892 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
893 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
894 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
895 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
896 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
897 * i386-init.h: Regenerated.
898
1848e567
L		 8992016-05-27 H.J. Lu <hongjiu.lu@intel.com>
900
901 PR gas/20145
902 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
903 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
904 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
905 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
906 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
907 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
908 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
909 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
910 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
911 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
912 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
913 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
914 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
915 CpuRegMask for AVX512.
916 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
917 and CpuRegMask.
918 (set_bitfield_from_cpu_flag_init): New function.
919 (set_bitfield): Remove const on f. Call
920 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
921 * i386-opc.h (CpuRegMMX): New.
922 (CpuRegXMM): Likewise.
923 (CpuRegYMM): Likewise.
924 (CpuRegZMM): Likewise.
925 (CpuRegMask): Likewise.
926 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
927 and cpuregmask.
928 * i386-init.h: Regenerated.
929 * i386-tbl.h: Likewise.
930
e92bae62
L		 9312016-05-27 H.J. Lu <hongjiu.lu@intel.com>
932
933 PR gas/20154
934 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
935 (opcode_modifiers): Add AMD64 and Intel64.
936 (main): Properly verify CpuMax.
937 * i386-opc.h (CpuAMD64): Removed.
938 (CpuIntel64): Likewise.
939 (CpuMax): Set to CpuNo64.
940 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
941 (AMD64): New.
942 (Intel64): Likewise.
943 (i386_opcode_modifier): Add amd64 and intel64.
944 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
945 on call and jmp.
946 * i386-init.h: Regenerated.
947 * i386-tbl.h: Likewise.
948
e89c5eaa
L		 9492016-05-27 H.J. Lu <hongjiu.lu@intel.com>
950
951 PR gas/20154
952 * i386-gen.c (main): Fail if CpuMax is incorrect.
953 * i386-opc.h (CpuMax): Set to CpuIntel64.
954 * i386-tbl.h: Regenerated.
955
77d66e7b
NC		 9562016-05-27 Nick Clifton <nickc@redhat.com>
957
958 PR target/20150
959 * msp430-dis.c (msp430dis_read_two_bytes): New function.
960 (msp430dis_opcode_unsigned): New function.
961 (msp430dis_opcode_signed): New function.
962 (msp430_singleoperand): Use the new opcode reading functions.
963 Only disassenmble bytes if they were successfully read.
964 (msp430_doubleoperand): Likewise.
965 (msp430_branchinstr): Likewise.
966 (msp430x_callx_instr): Likewise.
967 (print_insn_msp430): Check that it is safe to read bytes before
968 attempting disassembly. Use the new opcode reading functions.
969
19dfcc89
PB		 9702016-05-26 Peter Bergner <bergner@vnet.ibm.com>
971
972 * ppc-opc.c (CY): New define. Document it.
973 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
974
f3ad7637
L		 9752016-05-25 H.J. Lu <hongjiu.lu@intel.com>
976
977 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
978 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
979 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
980 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
981 CPU_ANY_AVX_FLAGS.
982 * i386-init.h: Regenerated.
983
f1360d58
L		 9842016-05-25 H.J. Lu <hongjiu.lu@intel.com>
985
986 PR gas/20141
987 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
988 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
989 * i386-init.h: Regenerated.
990
293f5f65
L		 9912016-05-25 H.J. Lu <hongjiu.lu@intel.com>
992
993 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
994 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
995 * i386-init.h: Regenerated.
996
d9eca1df
CZ		 9972016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
998
999 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1000 information.
1001 (print_insn_arc): Set insn_type information.
1002 * arc-opc.c (C_CC): Add F_CLASS_COND.
1003 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1004 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1005 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1006 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1007 (brne, brne_s, jeq_s, jne_s): Likewise.
1008
87789e08
CZ		 10092016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1010
1011 * arc-tbl.h (neg): New instruction variant.
1012
c810e0b8
CZ		 10132016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
1014
1015 * arc-dis.c (find_format, find_format, get_auxreg)
1016 (print_insn_arc): Changed.
1017 * arc-ext.h (INSERT_XOP): Likewise.
1018
3d207518
TS		 10192016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1020
1021 * tic54x-dis.c (sprint_mmr): Adjust.
1022 * tic54x-opc.c: Likewise.
1023
514e58b7
AM		 10242016-05-19 Alan Modra <amodra@gmail.com>
1025
1026 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1027
e43de63c
AM		 10282016-05-19 Alan Modra <amodra@gmail.com>
1029
1030 * ppc-opc.c: Formatting.
1031 (NSISIGNOPT): Define.
1032 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1033
1401d2fe
MR		 10342016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1035
1036 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1037 replacing references to `micromips_ase' throughout.
1038 (_print_insn_mips): Don't use file-level microMIPS annotation to
1039 determine the disassembly mode with the symbol table.
1040
1178da44
PB		 10412016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1042
1043 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1044
8f4f9071
MF		 10452016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1046
1047 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1048 mips64r6.
1049 * mips-opc.c (D34): New macro.
1050 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1051
8bc52696
AF		 10522016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1053
1054 * i386-dis.c (prefix_table): Add RDPID instruction.
1055 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1056 (cpu_flags): Add RDPID bitfield.
1057 * i386-opc.h (enum): Add RDPID element.
1058 (i386_cpu_flags): Add RDPID field.
1059 * i386-opc.tbl: Add RDPID instruction.
1060 * i386-init.h: Regenerate.
1061 * i386-tbl.h: Regenerate.
1062
39d911fc
TP		 10632016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1064
1065 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1066 branch type of a symbol.
1067 (print_insn): Likewise.
1068
16a1fa25
TP		 10692016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1070
1071 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1072 Mainline Security Extensions instructions.
1073 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1074 Extensions instructions.
1075 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1076 instructions.
1077 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1078 special registers.
1079
d751b79e
JM		 10802016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1081
1082 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1083
945e0f82
CZ		 10842016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1085
1086 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1087 (arcExtMap_genOpcode): Likewise.
1088 * arc-opc.c (arg_32bit_rc): Define new variable.
1089 (arg_32bit_u6): Likewise.
1090 (arg_32bit_limm): Likewise.
1091
20f55f38
SN		 10922016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1093
1094 * aarch64-gen.c (VERIFIER): Define.
1095 * aarch64-opc.c (VERIFIER): Define.
1096 (verify_ldpsw): Use static linkage.
1097 * aarch64-opc.h (verify_ldpsw): Remove.
1098 * aarch64-tbl.h: Use VERIFIER for verifiers.
1099
4bd13cde
NC		 11002016-04-28 Nick Clifton <nickc@redhat.com>
1101
1102 PR target/19722
1103 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1104 * aarch64-opc.c (verify_ldpsw): New function.
1105 * aarch64-opc.h (verify_ldpsw): New prototype.
1106 * aarch64-tbl.h: Add initialiser for verifier field.
1107 (LDPSW): Set verifier to verify_ldpsw.
1108
c0f92bf9
L		 11092016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1110
1111 PR binutils/19983
1112 PR binutils/19984
1113 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1114 smaller than address size.
1115
e6c7cdec
TS		 11162016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1117
1118 * alpha-dis.c: Regenerate.
1119 * crx-dis.c: Likewise.
1120 * disassemble.c: Likewise.
1121 * epiphany-opc.c: Likewise.
1122 * fr30-opc.c: Likewise.
1123 * frv-opc.c: Likewise.
1124 * ip2k-opc.c: Likewise.
1125 * iq2000-opc.c: Likewise.
1126 * lm32-opc.c: Likewise.
1127 * lm32-opinst.c: Likewise.
1128 * m32c-opc.c: Likewise.
1129 * m32r-opc.c: Likewise.
1130 * m32r-opinst.c: Likewise.
1131 * mep-opc.c: Likewise.
1132 * mt-opc.c: Likewise.
1133 * or1k-opc.c: Likewise.
1134 * or1k-opinst.c: Likewise.
1135 * tic80-opc.c: Likewise.
1136 * xc16x-opc.c: Likewise.
1137 * xstormy16-opc.c: Likewise.
1138
537aefaf
AB		 11392016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1140
1141 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1142 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1143 calcsd, and calcxd instructions.
1144 * arc-opc.c (insert_nps_bitop_size): Delete.
1145 (extract_nps_bitop_size): Delete.
1146 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1147 (extract_nps_qcmp_m3): Define.
1148 (extract_nps_qcmp_m2): Define.
1149 (extract_nps_qcmp_m1): Define.
1150 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1151 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1152 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1153 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1154 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1155 NPS_QCMP_M3.
1156
c8f785f2
AB		 11572016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1158
1159 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1160
6fd8e7c2
L		 11612016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1162
1163 * Makefile.in: Regenerated with automake 1.11.6.
1164 * aclocal.m4: Likewise.
1165
4b0c052e
AB		 11662016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1167
1168 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1169 instructions.
1170 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1171 (extract_nps_cmem_uimm16): New function.
1172 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1173
cb040366
AB		 11742016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1175
1176 * arc-dis.c (arc_insn_length): New function.
1177 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1178 (find_format): Change insnLen parameter to unsigned.
1179
accc0180
NC		 11802016-04-13 Nick Clifton <nickc@redhat.com>
1181
1182 PR target/19937
1183 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1184 the LD.B and LD.BU instructions.
1185
f36e33da
CZ		 11862016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1187
1188 * arc-dis.c (find_format): Check for extension flags.
1189 (print_flags): New function.
1190 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1191 .extAuxRegister.
1192 * arc-ext.c (arcExtMap_coreRegName): Use
1193 LAST_EXTENSION_CORE_REGISTER.
1194 (arcExtMap_coreReadWrite): Likewise.
1195 (dump_ARC_extmap): Update printing.
1196 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1197 (arc_aux_regs): Add cpu field.
1198 * arc-regs.h: Add cpu field, lower case name aux registers.
1199
1c2e355e
CZ		 12002016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1201
1202 * arc-tbl.h: Add rtsc, sleep with no arguments.
1203
b99747ae
CZ		 12042016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1205
1206 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1207 Initialize.
1208 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1209 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1210 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1211 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1212 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1213 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1214 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1215 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1216 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1217 (arc_opcode arc_opcodes): Null terminate the array.
1218 (arc_num_opcodes): Remove.
1219 * arc-ext.h (INSERT_XOP): Define.
1220 (extInstruction_t): Likewise.
1221 (arcExtMap_instName): Delete.
1222 (arcExtMap_insn): New function.
1223 (arcExtMap_genOpcode): Likewise.
1224 * arc-ext.c (ExtInstruction): Remove.
1225 (create_map): Zero initialize instruction fields.
1226 (arcExtMap_instName): Remove.
1227 (arcExtMap_insn): New function.
1228 (dump_ARC_extmap): More info while debuging.
1229 (arcExtMap_genOpcode): New function.
1230 * arc-dis.c (find_format): New function.
1231 (print_insn_arc): Use find_format.
1232 (arc_get_disassembler): Enable dump_ARC_extmap only when
1233 debugging.
1234
92708cec
MR		 12352016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1236
1237 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1238 instruction bits out.
1239
a42a4f84
AB		 12402016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1241
1242 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1243 * arc-opc.c (arc_flag_operands): Add new flags.
1244 (arc_flag_classes): Add new classes.
1245
1328504b
AB		 12462016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1247
1248 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1249
820f03ff
AB		 12502016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1251
1252 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1253 encode1, rflt, crc16, and crc32 instructions.
1254 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1255 (arc_flag_classes): Add C_NPS_R.
1256 (insert_nps_bitop_size_2b): New function.
1257 (extract_nps_bitop_size_2b): Likewise.
1258 (insert_nps_bitop_uimm8): Likewise.
1259 (extract_nps_bitop_uimm8): Likewise.
1260 (arc_operands): Add new operand entries.
1261
8ddf6b2a
CZ		 12622016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1263
b99747ae
CZ		 1264 * arc-regs.h: Add a new subclass field. Add double assist
1265 accumulator register values.
1266 * arc-tbl.h: Use DPA subclass to mark the double assist
1267 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1268 * arc-opc.c (RSP): Define instead of SP.
1269 (arc_aux_regs): Add the subclass field.
8ddf6b2a 1270
589a7d88
JW		 12712016-04-05 Jiong Wang <jiong.wang@arm.com>
1272
1273 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1274
0a191de9 12752016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 1276
1277 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1278 NPS_R_SRC1.
1279
0a106562
AB		 12802016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1281
1282 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1283 issues. No functional changes.
1284
bd05ac5f
CZ		 12852016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1286
b99747ae
CZ		 1287 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1288 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1289 (RTT): Remove duplicate.
1290 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1291 (PCT_CONFIG*): Remove.
1292 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 1293
9885948f
CZ		 12942016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1295
b99747ae 1296 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 1297
f2dd8838
CZ		 12982016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1299
b99747ae
CZ		 1300 * arc-tbl.h (invld07): Remove.
1301 * arc-ext-tbl.h: New file.
1302 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1303 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 1304
0d2f91fe
JK		 13052016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1306
1307 Fix -Wstack-usage warnings.
1308 * aarch64-dis.c (print_operands): Substitute size.
1309 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1310
a6b71f42
JM		 13112016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1312
1313 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1314 to get a proper diagnostic when an invalid ASR register is used.
1315
9780e045
NC		 13162016-03-22 Nick Clifton <nickc@redhat.com>
1317
1318 * configure: Regenerate.
1319
e23e8ebe
AB		 13202016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1321
1322 * arc-nps400-tbl.h: New file.
1323 * arc-opc.c: Add top level comment.
1324 (insert_nps_3bit_dst): New function.
1325 (extract_nps_3bit_dst): New function.
1326 (insert_nps_3bit_src2): New function.
1327 (extract_nps_3bit_src2): New function.
1328 (insert_nps_bitop_size): New function.
1329 (extract_nps_bitop_size): New function.
1330 (arc_flag_operands): Add nps400 entries.
1331 (arc_flag_classes): Add nps400 entries.
1332 (arc_operands): Add nps400 entries.
1333 (arc_opcodes): Add nps400 include.
1334
1ae8ab47
AB		 13352016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1336
1337 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1338 the new class enum values.
1339
8699fc3e
AB		 13402016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1341
1342 * arc-dis.c (print_insn_arc): Handle nps400.
1343
24740d83
AB		 13442016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1345
1346 * arc-opc.c (BASE): Delete.
1347
8678914f
NC		 13482016-03-18 Nick Clifton <nickc@redhat.com>
1349
1350 PR target/19721
1351 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1352 of MOV insn that aliases an ORR insn.
1353
cc933301
JW		 13542016-03-16 Jiong Wang <jiong.wang@arm.com>
1355
1356 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1357
f86f5863
TS		 13582016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1359
1360 * mcore-opc.h: Add const qualifiers.
1361 * microblaze-opc.h (struct op_code_struct): Likewise.
1362 * sh-opc.h: Likewise.
1363 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1364 (tic4x_print_op): Likewise.
1365
62de1c63
AM		 13662016-03-02 Alan Modra <amodra@gmail.com>
1367
d11698cd 1368 * or1k-desc.h: Regenerate.
62de1c63 1369 * fr30-ibld.c: Regenerate.
c697cf0b 1370 * rl78-decode.c: Regenerate.
62de1c63 1371
020efce5
NC		 13722016-03-01 Nick Clifton <nickc@redhat.com>
1373
1374 PR target/19747
1375 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1376
b0c11777
RL		 13772016-02-24 Renlin Li <renlin.li@arm.com>
1378
1379 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1380 (print_insn_coprocessor): Support fp16 instructions.
1381
3e309328
RL		 13822016-02-24 Renlin Li <renlin.li@arm.com>
1383
1384 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1385 vminnm, vrint(mpna).
1386
8afc7bea
RL		 13872016-02-24 Renlin Li <renlin.li@arm.com>
1388
1389 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1390 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1391
4fd7268a
L		 13922016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1393
1394 * i386-dis.c (print_insn): Parenthesize expression to prevent
1395 truncated addresses.
1396 (OP_J): Likewise.
1397
4670103e
CZ		 13982016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1399 Janek van Oirschot <jvanoirs@synopsys.com>
1400
b99747ae
CZ		 1401 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1402 variable.
4670103e 1403
c1d9289f
NC		 14042016-02-04 Nick Clifton <nickc@redhat.com>
1405
1406 PR target/19561
1407 * msp430-dis.c (print_insn_msp430): Add a special case for
1408 decoding an RRC instruction with the ZC bit set in the extension
1409 word.
1410
a143b004
AB		 14112016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1412
1413 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1414 * epiphany-ibld.c: Regenerate.
1415 * fr30-ibld.c: Regenerate.
1416 * frv-ibld.c: Regenerate.
1417 * ip2k-ibld.c: Regenerate.
1418 * iq2000-ibld.c: Regenerate.
1419 * lm32-ibld.c: Regenerate.
1420 * m32c-ibld.c: Regenerate.
1421 * m32r-ibld.c: Regenerate.
1422 * mep-ibld.c: Regenerate.
1423 * mt-ibld.c: Regenerate.
1424 * or1k-ibld.c: Regenerate.
1425 * xc16x-ibld.c: Regenerate.
1426 * xstormy16-ibld.c: Regenerate.
1427
b89807c6
AB		 14282016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1429
1430 * epiphany-dis.c: Regenerated from latest cpu files.
1431
d8c823c8
MM		 14322016-02-01 Michael McConville <mmcco@mykolab.com>
1433
1434 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1435 test bit.
1436
5bc5ae88
RL		 14372016-01-25 Renlin Li <renlin.li@arm.com>
1438
1439 * arm-dis.c (mapping_symbol_for_insn): New function.
1440 (find_ifthen_state): Call mapping_symbol_for_insn().
1441
0bff6e2d
MW		 14422016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1443
1444 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1445 of MSR UAO immediate operand.
1446
100b4f2e
MR		 14472016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1448
1449 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1450 instruction support.
1451
5c14705f
AM		 14522016-01-17 Alan Modra <amodra@gmail.com>
1453
1454 * configure: Regenerate.
1455
4d82fe66
NC		 14562016-01-14 Nick Clifton <nickc@redhat.com>
1457
1458 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1459 instructions that can support stack pointer operations.
1460 * rl78-decode.c: Regenerate.
1461 * rl78-dis.c: Fix display of stack pointer in MOVW based
1462 instructions.
1463
651657fa
MW		 14642016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1465
1466 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1467 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1468 erxtatus_el1 and erxaddr_el1.
1469
105bde57
MW		 14702016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1471
1472 * arm-dis.c (arm_opcodes): Add "esb".
1473 (thumb_opcodes): Likewise.
1474
afa8d405
PB		 14752016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1476
1477 * ppc-opc.c <xscmpnedp>: Delete.
1478 <xvcmpnedp>: Likewise.
1479 <xvcmpnedp.>: Likewise.
1480 <xvcmpnesp>: Likewise.
1481 <xvcmpnesp.>: Likewise.
1482
83c3256e
AS		 14832016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1484
1485 PR gas/13050
1486 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1487 addition to ISA_A.
1488
6f2750fe
AM		 14892016-01-01 Alan Modra <amodra@gmail.com>
1490
1491 Update year range in copyright notice of all files.
1492
3499769a
AM		 1493For older changes see ChangeLog-2015
1494\f
1495Copyright (C) 2016 Free Software Foundation, Inc.
1496
1497Copying and distribution of this file, with or without modification,
1498are permitted in any medium without royalty provided the copyright
1499notice and this notice are preserved.
1500
1501Local Variables:
1502mode: change-log
1503left-margin: 8
1504fill-column: 74
1505version-control: never
1506End:
GDB Binutils - Deliverables
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