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* object.cc (Sized_relobj_file::do_layout): Remove unused local
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
9bf29d72
DM		 12011-09-08 Mark Fortescue <mark@mtfhpc.demon.co.uk>
2
3 The changes below bring 'mov' and 'ticc' instructions into line
4 with the V8 SPARC Architecture Manual.
5 * sparc-opc.c (sparc_opcodes): Add entry for 'ticc imm + regrs1'.
6 * sparc-opc.c (sparc_opcodes): Add alias entries for
7 'mov regrs2,%asrX'; 'mov regrs2,%y'; 'mov regrs2,%prs';
8 'mov regrs2,%wim' and 'mov regrs2,%tbr'.
9 * sparc-opc.c (sparc_opcodes): Move/Change entries for
10 'mov imm,%asrX'; 'mov imm,%y'; 'mov imm,%prs'; 'mov imm,%wim'
11 and 'mov imm,%tbr'.
12 * sparc-opc.c (sparc_opcodes): Add wr alias entries to match above
13 mov aliases.
14
8dbb9eb3
DM		 15 * sparc-opc.c (sparc_opcodes): Add entry for 'save simm13,regrs1,regrd'
16 This has been reported as being accepted by the Sun assmebler.
17
cdf49201
DM		 182011-09-08 David S. Miller <davem@davemloft.net>
19
20 * sparc-opc.c (pdistn): Destination is integer not float register.
21
96e67898
AS		 222011-09-07 Andreas Schwab <schwab@linux-m68k.org>
23
b2ea1829 24 PR gas/13145
96e67898
AS		 25 * m68k-opc.c: Use "y" in moveml pattern for mcfisa_a.
26
7cf80422
NC		 272011-08-26 Nick Clifton <nickc@redhat.com>
28
29 * po/es.po: Updated Spanish translation.
30
dc15e575
NC		 312011-08-22 Nick Clifton <nickc@redhat.com>
32
33 * Makefile.am (CPUDIR): Redfine to point to top level cpu
34 directory.
35 (stamp-frv): Use CPUDIR.
36 (stamp-iq2000): Likewise.
37 (stamp-lm32): Likewise.
38 (stamp-m32c): Likewise.
39 (stamp-mt): Likewise.
40 (stamp-xc16x): Likewise.
41 * Makefile.in: Regenerate.
42
dec0624d
MR		 432011-08-09 Chao-ying Fu <fu@mips.com>
44 Maciej W. Rozycki <macro@codesourcery.com>
45
46 * mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2"
47 and "mips64r2".
48 (print_insn_args, print_insn_micromips): Handle MCU.
49 * micromips-opc.c (MC): New macro.
50 (micromips_opcodes): Add "aclr", "aset" and "iret".
51 * mips-opc.c (MC): New macro.
52 (mips_builtin_opcodes): Add "aclr", "aset" and "iret".
53
2b0c8b40
MR		 542011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
55
56 * micromips-opc.c (MOD_mb, MOD_mc, MOD_md): Remove macros.
57 (MOD_me, MOD_mf, MOD_mg, MOD_mhi, MOD_mj, MOD_ml): Likewise.
58 (MOD_mm, MOD_mn, MOD_mp, MOD_mq, MOD_sp): Likewise.
59 (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf): New macros.
60 (RD_mg, WR_mhi, RD_mj, WR_mj, RD_ml, RD_mmn): Likewise.
61 (RD_mp, WR_mp, RD_mq, RD_sp, WR_sp): Likewise.
62 (WR_s): Update macro.
63 (micromips_opcodes): Update register use flags of: "addiu",
64 "addiupc", "addiur1sp", "addiur2", "addius5", "addiusp", "addu",
65 "and", "andi", "beq", "beqz", "bne", "bnez", "di", "ei", "j",
66 "jalr", "jalrs", "jr", "jraddiusp", "jrc", "lbu", "lhu", "li",
67 "lui", "lw", "lwm", "mfhi", "mflo", "move", "movep", "not",
68 "nor", "or", "ori", "sb", "sh", "sll", "srl", "subu", "sw",
69 "swm" and "xor" instructions.
70
ea783ef3
DM		 712011-08-05 David S. Miller <davem@davemloft.net>
72
73 * sparc-dis.c (v9a_ast_reg_names): Add "cps".
74 (X_RS3): New macro.
75 (print_insn_sparc): Handle '4', '5', and '(' format codes.
76 Accept %asr numbers below 28.
77 * sparc-opc.c (sparc_opcodes): Add entries for HPC and VIS3
78 instructions.
79
3929df09
QN		 802011-08-02 Quentin Neill <quentin.neill@amd.com>
81
82 * i386-dis.c (xop_table): Remove spurious bextr insn.
83
d7921315
L		 842011-08-01 H.J. Lu <hongjiu.lu@intel.com>
85
86 PR ld/13048
87 * i386-dis.c (print_insn): Optimize info->mach check.
88
00f51a41
L		 892011-08-01 H.J. Lu <hongjiu.lu@intel.com>
90
91 PR gas/13046
92 * i386-opc.tbl: Add Disp32S to 64bit call.
93 * i386-tbl.h: Regenerated.
94
df58fc94
RS		 952011-07-24 Chao-ying Fu <fu@mips.com>
96 Maciej W. Rozycki <macro@codesourcery.com>
97
98 * micromips-opc.c: New file.
99 * mips-dis.c (micromips_to_32_reg_b_map): New array.
100 (micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise.
101 (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise.
102 (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise.
103 (micromips_to_32_reg_q_map): Likewise.
104 (micromips_imm_b_map, micromips_imm_c_map): Likewise.
105 (micromips_ase): New variable.
106 (is_micromips): New function.
107 (set_default_mips_dis_options): Handle microMIPS ASE.
108 (print_insn_micromips): New function.
109 (is_compressed_mode_p): Likewise.
110 (_print_insn_mips): Handle microMIPS instructions.
111 * Makefile.am (CFILES): Add micromips-opc.c.
112 * configure.in (bfd_mips_arch): Add micromips-opc.lo.
113 * Makefile.in: Regenerate.
114 * configure: Regenerate.
115
116 * mips-dis.c (micromips_to_32_reg_h_map): New variable.
117 (micromips_to_32_reg_i_map): Likewise.
118 (micromips_to_32_reg_m_map): Likewise.
119 (micromips_to_32_reg_n_map): New macro.
120
bcd530a7
RS		 1212011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
122
123 * mips-opc.c (NODS): New macro.
124 (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
125 (DSP_VOLA): Likewise.
126 (mips_builtin_opcodes): Add NODS annotation to "deret" and
127 "eret". Replace INSN_SYNC with NODS throughout. Use NODS in
128 place of TRAP for "wait", "waiti" and "yield".
129 * mips16-opc.c (NODS): New macro.
130 (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
131 (mips16_opcodes): Use NODS in place of TRAP for "jalrc", "jrc",
132 "restore" and "save".
133
7a9068fe
L		 1342011-07-22 H.J. Lu <hongjiu.lu@intel.com>
135
136 * configure.in: Handle bfd_k1om_arch.
137 * configure: Regenerated.
138
139 * disassemble.c (disassembler): Handle bfd_k1om_arch.
140
141 * i386-dis.c (print_insn): Handle bfd_mach_k1om and
142 bfd_mach_k1om_intel_syntax.
143
144 * i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to
145 ~(CpuL1OM|CpuK1OM). Add CPU_K1OM_FLAGS.
146 (cpu_flags): Add CpuK1OM.
147
148 * i386-opc.h (CpuK1OM): New.
149 (i386_cpu_flags): Add cpuk1om.
150
151 * i386-init.h: Regenerated.
152 * i386-tbl.h: Likewise.
153
1b93226d
NC		 1542011-07-12 Nick Clifton <nickc@redhat.com>
155
156 * arm-dis.c (print_insn_arm): Revert previous, undocumented,
157 accidental change.
158
5d73b1f1
NC		 1592011-07-01 Nick Clifton <nickc@redhat.com>
160
161 PR binutils/12329
162 * avr-dis.c (avr_operand): Fix disassembly of ELPM, LPM and SPM
163 insns using post-increment addressing.
164
182ae480
L		 1652011-06-30 H.J. Lu <hongjiu.lu@intel.com>
166
167 * i386-dis.c (vex_len_table): Update rorxS.
168
4cb0953d
L		 1692011-06-30 H.J. Lu <hongjiu.lu@intel.com>
170
171 AVX Programming Reference (June, 2011)
172 * i386-dis.c (vex_len_table): Correct rorxS.
173
174 * i386-opc.tbl: Correct rorx.
175 * i386-tbl.h: Regenerated.
176
906efcbc
L		 1772011-06-29 H.J. Lu <hongjiu.lu@intel.com>
178
179 * tilegx-opc.c (find_opcode): Replace "index" with "i".
180 * tilepro-opc.c (find_opcode): Likewise.
181
ceb94aa5
RS		 1822011-06-29 Richard Sandiford <rdsandiford@googlemail.com>
183
184 * mips16-opc.c (jalrc, jrc): Move earlier in file.
185
f7002f42
L		 1862011-06-21 H.J. Lu <hongjiu.lu@intel.com>
187
188 * i386-dis.c (prefix_table): Re-indent PREFIX_VEX_0F388C and
189 PREFIX_VEX_0F388E.
190
56300268
AS		 1912011-06-17 Andreas Schwab <schwab@redhat.com>
192
193 * Makefile.am (MAINTAINERCLEANFILES): Move s390-opc.tab ...
194 (MOSTLYCLEANFILES): ... here.
195 * Makefile.in: Regenerate.
196
bcf2cf9f
AM		 1972011-06-14 Alan Modra <amodra@gmail.com>
198
199 * Makefile.in: Regenerate.
200
aa137e4d
NC		 2012011-06-13 Walter Lee <walt@tilera.com>
202
203 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c,
204 tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c.
205 * Makefile.in: Regenerate.
206 * configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch.
207 * configure: Regenerate.
208 * disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro.
209 * po/POTFILES.in: Regenerate.
210 * tilegx-dis.c: New file.
211 * tilegx-opc.c: New file.
212 * tilepro-dis.c: New file.
213 * tilepro-opc.c: New file.
214
6c30d220
L		 2152011-06-10 H.J. Lu <hongjiu.lu@intel.com>
216
217 AVX Programming Reference (June, 2011)
218 * i386-dis.c (XMGatherQ): New.
219 * i386-dis.c (EXxmm_mb): New.
220 (EXxmm_mb): Likewise.
221 (EXxmm_mw): Likewise.
222 (EXxmm_md): Likewise.
223 (EXxmm_mq): Likewise.
224 (EXxmmdw): Likewise.
225 (EXxmmqd): Likewise.
226 (VexGatherQ): Likewise.
227 (MVexVSIBDWpX): Likewise.
228 (MVexVSIBQWpX): Likewise.
229 (xmm_mb_mode): Likewise.
230 (xmm_mw_mode): Likewise.
231 (xmm_md_mode): Likewise.
232 (xmm_mq_mode): Likewise.
233 (xmmdw_mode): Likewise.
234 (xmmqd_mode): Likewise.
235 (ymmxmm_mode): Likewise.
236 (vex_vsib_d_w_dq_mode): Likewise.
237 (vex_vsib_q_w_dq_mode): Likewise.
238 (MOD_VEX_0F385A_PREFIX_2): Likewise.
239 (MOD_VEX_0F388C_PREFIX_2): Likewise.
240 (MOD_VEX_0F388E_PREFIX_2): Likewise.
241 (PREFIX_0F3882): Likewise.
242 (PREFIX_VEX_0F3816): Likewise.
243 (PREFIX_VEX_0F3836): Likewise.
244 (PREFIX_VEX_0F3845): Likewise.
245 (PREFIX_VEX_0F3846): Likewise.
246 (PREFIX_VEX_0F3847): Likewise.
247 (PREFIX_VEX_0F3858): Likewise.
248 (PREFIX_VEX_0F3859): Likewise.
249 (PREFIX_VEX_0F385A): Likewise.
250 (PREFIX_VEX_0F3878): Likewise.
251 (PREFIX_VEX_0F3879): Likewise.
252 (PREFIX_VEX_0F388C): Likewise.
253 (PREFIX_VEX_0F388E): Likewise.
254 (PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise.
255 (PREFIX_VEX_0F38F5): Likewise.
256 (PREFIX_VEX_0F38F6): Likewise.
257 (PREFIX_VEX_0F3A00): Likewise.
258 (PREFIX_VEX_0F3A01): Likewise.
259 (PREFIX_VEX_0F3A02): Likewise.
260 (PREFIX_VEX_0F3A38): Likewise.
261 (PREFIX_VEX_0F3A39): Likewise.
262 (PREFIX_VEX_0F3A46): Likewise.
263 (PREFIX_VEX_0F3AF0): Likewise.
264 (VEX_LEN_0F3816_P_2): Likewise.
265 (VEX_LEN_0F3819_P_2): Likewise.
266 (VEX_LEN_0F3836_P_2): Likewise.
267 (VEX_LEN_0F385A_P_2_M_0): Likewise.
268 (VEX_LEN_0F38F5_P_0): Likewise.
269 (VEX_LEN_0F38F5_P_1): Likewise.
270 (VEX_LEN_0F38F5_P_3): Likewise.
271 (VEX_LEN_0F38F6_P_3): Likewise.
272 (VEX_LEN_0F38F7_P_1): Likewise.
273 (VEX_LEN_0F38F7_P_2): Likewise.
274 (VEX_LEN_0F38F7_P_3): Likewise.
275 (VEX_LEN_0F3A00_P_2): Likewise.
276 (VEX_LEN_0F3A01_P_2): Likewise.
277 (VEX_LEN_0F3A38_P_2): Likewise.
278 (VEX_LEN_0F3A39_P_2): Likewise.
279 (VEX_LEN_0F3A46_P_2): Likewise.
280 (VEX_LEN_0F3AF0_P_3): Likewise.
281 (VEX_W_0F3816_P_2): Likewise.
282 (VEX_W_0F3818_P_2): Likewise.
283 (VEX_W_0F3819_P_2): Likewise.
284 (VEX_W_0F3836_P_2): Likewise.
285 (VEX_W_0F3846_P_2): Likewise.
286 (VEX_W_0F3858_P_2): Likewise.
287 (VEX_W_0F3859_P_2): Likewise.
288 (VEX_W_0F385A_P_2_M_0): Likewise.
289 (VEX_W_0F3878_P_2): Likewise.
290 (VEX_W_0F3879_P_2): Likewise.
291 (VEX_W_0F3A00_P_2): Likewise.
292 (VEX_W_0F3A01_P_2): Likewise.
293 (VEX_W_0F3A02_P_2): Likewise.
294 (VEX_W_0F3A38_P_2): Likewise.
295 (VEX_W_0F3A39_P_2): Likewise.
296 (VEX_W_0F3A46_P_2): Likewise.
297 (MOD_VEX_0F3818_PREFIX_2): Removed.
298 (MOD_VEX_0F3819_PREFIX_2): Likewise.
299 (VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise.
300 (VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise.
301 (VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise.
302 (VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise.
303 (VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise.
304 (VEX_LEN_0F3A0E_P_2): Likewise.
305 (VEX_LEN_0F3A0F_P_2): Likewise.
306 (VEX_LEN_0F3A42_P_2): Likewise.
307 (VEX_LEN_0F3A4C_P_2): Likewise.
308 (VEX_W_0F3818_P_2_M_0): Likewise.
309 (VEX_W_0F3819_P_2_M_0): Likewise.
310 (prefix_table): Updated.
311 (three_byte_table): Likewise.
312 (vex_table): Likewise.
313 (vex_len_table): Likewise.
314 (vex_w_table): Likewise.
315 (mod_table): Likewise.
316 (putop): Handle "LW".
317 (intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode,
318 xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode,
319 vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode.
320 (OP_EX): Likewise.
321 (OP_E_memory): Handle vex_vsib_d_w_dq_mode and
322 vex_vsib_q_w_dq_mode.
323 (OP_XMM): Handle vex_vsib_q_w_dq_mode.
324 (OP_VEX): Likewise.
325
326 * i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS
327 and CPU_ANY_AVX_FLAGS. Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS,
328 CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS.
329 (cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID.
330 (opcode_modifiers): Add VecSIB.
331
332 * i386-opc.h (CpuAVX2): New.
333 (CpuBMI2): Likewise.
334 (CpuLZCNT): Likewise.
335 (CpuINVPCID): Likewise.
336 (VecSIB128): Likewise.
337 (VecSIB256): Likewise.
338 (VecSIB): Likewise.
339 (i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid.
340 (i386_opcode_modifier): Add vecsib.
341
342 * i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions.
343 * i386-init.h: Regenerated.
344 * i386-tbl.h: Likewise.
345
d535accd
QN		 3462011-06-03 Quentin Neill <quentin.neill@amd.com>
347
348 * i386-gen.c (cpu_flag_init): Add CpuF16C to CPU_BDVER2_FLAGS.
349 * i386-init.h: Regenerated.
350
f8b960bc
NC		 3512011-06-03 Nick Clifton <nickc@redhat.com>
352
353 PR binutils/12752
354 * arm-dis.c (print_insn_coprocessor): Use bfd_vma type for
355 computing address offsets.
356 (print_arm_address): Likewise.
357 (print_insn_arm): Likewise.
358 (print_insn_thumb16): Likewise.
359 (print_insn_thumb32): Likewise.
360
26d97720
NS		 3612011-06-02 Jie Zhang <jie@codesourcery.com>
362 Nathan Sidwell <nathan@codesourcery.com>
363 Maciej Rozycki <macro@codesourcery.com>
364
365 * arm-dis.c (print_insn_coprocessor): Explicitly print #-0
366 as address offset.
367 (print_arm_address): Likewise. Elide positive #0 appropriately.
368 (print_insn_arm): Likewise.
369
f8b960bc
NC		 3702011-06-02 Nick Clifton <nickc@redhat.com>
371
372 PR gas/12752
373 * arm-dis.c (print_insn_thumb32): Do not sign extend addresses
374 passed to print_address_func.
375
cc643b88
NC		 3762011-06-02 Nick Clifton <nickc@redhat.com>
377
378 * arm-dis.c: Fix spelling mistakes.
379 * op/opcodes.pot: Regenerate.
380
c8fa16ed
AK		 3812011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
382
383 * s390-opc.c: Replace S390_OPERAND_REG_EVEN with
384 S390_OPERAND_REG_PAIR. Fix INSTR_RRF_0UFEF instruction type.
385 * s390-opc.txt: Fix cxr instruction type.
386
5e4b319c
AK		 3872011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
388
389 * s390-opc.c: Add new instruction types marking register pair
390 operands.
391 * s390-opc.txt: Match instructions having register pair operands
392 to the new instruction types.
393
fda544a2
NC		 3942011-05-19 Nick Clifton <nickc@redhat.com>
395
396 * v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2
397 operands.
398
4cab4add
QN		 3992011-05-10 Quentin Neill <quentin.neill@amd.com>
400
401 * i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS.
402 * i386-init.h: Regenerated.
403
b4e7b885
NC		 4042011-04-27 Nick Clifton <nickc@redhat.com>
405
406 * po/da.po: Updated Danish translation.
407
2f7f7710
AM		 4082011-04-26 Anton Blanchard <anton@samba.org>
409
410 * ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7.
411
9887672f
DD		 4122011-04-21 DJ Delorie <dj@redhat.com>
413
414 * rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs.
415 * rx-decode.c: Regenerate.
416
3251b375
L		 4172011-04-20 H.J. Lu <hongjiu.lu@intel.com>
418
419 * i386-init.h: Regenerated.
420
b13a3ca6
QN		 4212011-04-19 Quentin Neill <quentin.neill@amd.com>
422
423 * i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits
424 from bdver1 flags.
425
7d063384
NC		 4262011-04-13 Nick Clifton <nickc@redhat.com>
427
428 * v850-dis.c (disassemble): Always print a closing square brace if
429 an opening square brace was printed.
430
32a94698
NC		 4312011-04-12 Nick Clifton <nickc@redhat.com>
432
433 PR binutils/12534
434 * arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn
435 patterns.
436 (print_insn_thumb32): Handle %L.
437
d2cd1205
JB		 4382011-04-11 Julian Brown <julian@codesourcery.com>
439
440 * arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
441 (print_insn_thumb32): Add APSR bitmask support.
442
1fbaefec
PB		 4432011-04-07 Paul Carroll<pcarroll@codesourcery.com>
444
445 * arm-dis.c (print_insn): init vars moved into private_data structure.
446
67171547
MF		 4472011-03-24 Mike Frysinger <vapier@gentoo.org>
448
449 * bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic.
450
8cc66334
EW		 4512011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
452
453 * avr-dis.c (avr_operand): Add opcode_str parameter. Check for
454 post-increment to support LPM Z+ instruction. Add support for 'E'
455 constraint for DES instruction.
456 (print_insn_avr): Adjust calls to avr_operand. Rename variable.
457
34e77a92
RS		 4582011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
459
460 * arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
461
35fc36a8
RS		 4622011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
463
464 * arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
465 Use branch types instead.
466 (print_insn): Likewise.
467
0067d8fc
MR		 4682011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
469
470 * mips-opc.c (mips_builtin_opcodes): Correct register use
471 annotation of "alnv.ps".
472
3eebd5eb
MR		 4732011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
474
475 * mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
476
500cccad
MF		 4772011-02-22 Mike Frysinger <vapier@gentoo.org>
478
479 * bfin-dis.c (OUTS): Remove p NULL check and txt NUL check.
480
f5caf9f4
MF		 4812011-02-22 Mike Frysinger <vapier@gentoo.org>
482
483 * bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS.
484
e5bc4265
MF		 4852011-02-19 Mike Frysinger <vapier@gentoo.org>
486
487 * bfin-dis.c (saved_state): Mark static. Change a[01]x to ax[] and
488 a[01]w to aw[]. Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1,
489 av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts,
490 exception, end_of_registers, msize, memory, bfd_mach.
491 (CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG,
492 LB0REG, LC1REG, LT1REG, LB1REG): Delete
493 (AXREG, AWREG, LCREG, LTREG, LBREG): Define.
494 (get_allreg): Change to new defines. Fallback to abort().
495
602427c4
MF		 4962011-02-14 Mike Frysinger <vapier@gentoo.org>
497
498 * bfin-dis.c: Add whitespace/parenthesis where needed.
499
298c1ec2
MF		 5002011-02-14 Mike Frysinger <vapier@gentoo.org>
501
502 * bfin-dis.c (decode_LoopSetup_0): Return when reg is greater
503 than 7.
504
822ce8ee
RW		 5052011-02-13 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
506
507 * configure: Regenerate.
508
13c02f06
MF		 5092011-02-13 Mike Frysinger <vapier@gentoo.org>
510
511 * bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg.
512
4db66394
MF		 5132011-02-13 Mike Frysinger <vapier@gentoo.org>
514
515 * bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1. Output
516 dregs only when P is set, and dregs_lo otherwise.
517
36f44611
MF		 5182011-02-13 Mike Frysinger <vapier@gentoo.org>
519
520 * bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code.
521
9805c0a5
MF		 5222011-02-12 Mike Frysinger <vapier@gentoo.org>
523
524 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT.
525
43a6aa65
MF		 5262011-02-12 Mike Frysinger <vapier@gentoo.org>
527
528 * bfin-dis.c (machine_registers): Delete REG_GP.
529 (reg_names): Delete "GP".
530 (decode_allregs): Change REG_GP to REG_LASTREG.
531
26bb3ddd
MF		 5322011-02-12 Mike Frysinger <vapier@gentoo.org>
533
89c0d58c
MR		 534 * bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2,
535 M_IH, M_IU): Delete.
26bb3ddd 536
69b8ea4a
MF		 5372011-02-11 Mike Frysinger <vapier@gentoo.org>
538
539 * bfin-dis.c (reg_names): Add const.
540 (decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte,
541 decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs,
542 decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits,
543 decode_counters, decode_allregs): Likewise.
544
42d5f9c6
MS		 5452011-02-09 Michael Snyder <msnyder@vmware.com>
546
56300268 547 * i386-dis.c (OP_J): Parenthesize expression to prevent
42d5f9c6
MS		 548 truncated addresses.
549 (print_insn): Fix indentation off-by-one.
550
4be0c941
NC		 5512011-02-01 Nick Clifton <nickc@redhat.com>
552
553 * po/da.po: Updated Danish translation.
554
6b069ee7
AM		 5552011-01-21 Dave Murphy <davem@devkitpro.org>
556
557 * ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.
558
e3949f17
L		 5592011-01-18 H.J. Lu <hongjiu.lu@intel.com>
560
561 * i386-dis.c (sIbT): New.
562 (b_T_mode): Likewise.
563 (dis386): Replace sIb with sIbT on "pushT".
564 (x86_64_table): Replace sIb with Ib on "aam" and "aad".
565 (OP_sI): Handle b_T_mode. Properly sign-extend byte.
566
752573b2
JK		 5672011-01-18 Jan Kratochvil <jan.kratochvil@redhat.com>
568
569 * i386-init.h: Regenerated.
570 * i386-tbl.h: Regenerated
571
2a2a0f38
QN		 5722011-01-17 Quentin Neill <quentin.neill@amd.com>
573
574 * i386-dis.c (REG_XOP_TBM_01): New.
575 (REG_XOP_TBM_02): New.
576 (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
577 (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
578 entries, and add bextr instruction.
579
580 * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
581 (cpu_flags): Add CpuTBM.
582
583 * i386-opc.h (CpuTBM) New.
584 (i386_cpu_flags): Add bit cputbm.
585
586 * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
587 blcs, blsfill, blsic, t1mskc, and tzmsk.
588
90d6ff62
DD		 5892011-01-12 DJ Delorie <dj@redhat.com>
590
591 * rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.
592
c95354ed
MX		 5932011-01-11 Mingjie Xing <mingjie.xing@gmail.com>
594
595 * mips-dis.c (print_insn_args): Adjust the value to print the real
596 offset for "+c" argument.
597
f7465604
NC		 5982011-01-10 Nick Clifton <nickc@redhat.com>
599
600 * po/da.po: Updated Danish translation.
601
639e30d2
NS		 6022011-01-05 Nathan Sidwell <nathan@codesourcery.com>
603
604 * arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
605
f12dc422
L		 6062011-01-04 H.J. Lu <hongjiu.lu@intel.com>
607
608 * i386-dis.c (REG_VEX_38F3): New.
609 (PREFIX_0FBC): Likewise.
610 (PREFIX_VEX_38F2): Likewise.
611 (PREFIX_VEX_38F3_REG_1): Likewise.
612 (PREFIX_VEX_38F3_REG_2): Likewise.
613 (PREFIX_VEX_38F3_REG_3): Likewise.
614 (PREFIX_VEX_38F7): Likewise.
615 (VEX_LEN_38F2_P_0): Likewise.
616 (VEX_LEN_38F3_R_1_P_0): Likewise.
617 (VEX_LEN_38F3_R_2_P_0): Likewise.
618 (VEX_LEN_38F3_R_3_P_0): Likewise.
619 (VEX_LEN_38F7_P_0): Likewise.
620 (dis386_twobyte): Use PREFIX_0FBC.
621 (reg_table): Add REG_VEX_38F3.
622 (prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2,
623 PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2,
624 PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7.
625 (vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and
626 PREFIX_VEX_38F7.
627 (vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0,
628 VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and
629 VEX_LEN_38F7_P_0.
630
631 * i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS.
632 (cpu_flags): Add CpuBMI.
633
634 * i386-opc.h (CpuBMI): New.
635 (i386_cpu_flags): Add cpubmi.
636
637 * i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt.
638 * i386-init.h: Regenerated.
639 * i386-tbl.h: Likewise.
640
cb21baef
L		 6412011-01-04 H.J. Lu <hongjiu.lu@intel.com>
642
643 * i386-dis.c (VexGdq): New.
644 (OP_VEX): Handle dq_mode.
645
0db46eb4
L		 6462011-01-01 H.J. Lu <hongjiu.lu@intel.com>
647
648 * i386-gen.c (process_copyright): Update copyright to 2011.
649
9e9e0820 650For older changes see ChangeLog-2010
252b5132
RH		 651\f
652Local Variables:
2f6d2f85
NC		 653mode: change-log
654left-margin: 8
655fill-column: 74
252b5132
RH		 656version-control: never
657End:
GDB Binutils - Deliverables
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