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[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
1de34e0a
AM		 12010-11-25 Alan Modra <amodra@gmail.com>
2
3 * po/es.po: Update.
4 * po/fr.po: Update.
5 * po/nl.po: Update.
6 * po/zh_CN.po: Update.
7
fd503541
NC		 82010-11-11 Mingming Sun <mingm.sun@gmail.com>
9
10 * mips-dis.c (mips_arch_choices): Add loongson3a.
11 * mips-opc.c (IL3A): Defined as INSN_LOONGSON_3A.
12 (mips_builtin_opcodes): Modify some instructions' membership from
1de34e0a 13 IL2F to IL2F|IL3A.
fd503541 14
8e295ce0
NC		 152010-11-10 Nick Clifton <nickc@redhat.com>
16
17 * po/fi.po: Updated Finnish translation.
18
2ee0aedf
TG		 192010-11-05 Tristan Gingold <gingold@adacore.com>
20
21 * po/opcodes.pot: Regenerate
22
af478898
MR		 232010-10-28 Maciej W. Rozycki <macro@codesourcery.com>
24
25 * mips-opc.c (mips_builtin_opcodes): Fix formatting of "ld".
26
be7a250d
AK		 272010-10-28 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
28
29 * s390-opc.txt: cfxr, cfdr and cfer z900 -> g5.
30
d958d1a3
CF		 312010-10-25 Chao-ying Fu <fu@mips.com>
32
33 * mips-opc.c (madd, maddu, msub, msubu, mult, multu): Change D33 to D32.
34
c0621d88
NS		 352010-10-25 Nathan Sidwell <nathan@codesourcery.com>
36
37 * tic6x-dis.c: Add attribution.
38
a43817df
AM		 392010-10-22 Alan Modra <amodra@gmail.com>
40
41 * Makefile.am (CLEANFILES): Add stamp-lm32. Sort.
42 * Makefile.in: Regenerate.
43
704897fb
MR		 442010-10-18 Maciej W. Rozycki <macro@linux-mips.org>
45
46 * mips-opc.c (mips_builtin_opcodes): Move M_LD_OB and M_SD_OB
47 macros before their corresponding MIPS III hardware instructions.
48
da98bb4c
L		 492010-10-16 H.J. Lu <hongjiu.lu@intel.com>
50
51 * i386-gen.c (cpu_flag_init): Add CpuNop to CPU_GENERIC64_FLAGS.
52
53 * i386-init.h: Regenerated.
54
e1791cb8
MF		 552010-10-15 Mike Frysinger <vapier@gentoo.org>
56
57 * bfin-dis.c (decode_dsp32alu_0): Call imm5d() for BYTEOP2M.
58
553d0a74
L		 592010-10-14 H.J. Lu <hongjiu.lu@intel.com>
60
61 * i386-opc.tbl: Remove CheckRegSize from movq.
62 * i386-tbl.h: Regenerated.
63
cfc08d49
L		 642010-10-14 H.J. Lu <hongjiu.lu@intel.com>
65
66 * i386-opc.tbl: Remove CheckRegSize from instructions with
67 0, 1 or fixed operands.
68 * i386-tbl.h: Regenerated.
69
56ffb741
L		 702010-10-14 H.J. Lu <hongjiu.lu@intel.com>
71
72 * i386-gen.c (opcode_modifiers): Add CheckRegSize.
73
74 * i386-opc.h (CheckRegSize): New.
75 (i386_opcode_modifier): Add checkregsize.
76
77 * i386-opc.tbl: Add CheckRegSize to instructions which
78 require register size check.
79 * i386-tbl.h: Regenerated.
80
1a2dab1f
AS		 812010-10-12 Andreas Schwab <schwab@linux-m68k.org>
82
83 * m68k-opc.c (m68k_opcodes): Move fnop before fbf.
84
a3ec2691
AK		 852010-10-11 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
86
87 * s390-opc.c: Make the instruction masks for the load/store on
88 condition instructions to cover the condition code mask as well.
89 * s390-opc.txt: lgoc -> locg and stgoc -> stocg.
90
d92fa646
JK		 912010-10-11 Jan Kratochvil <jan.kratochvil@redhat.com>
92 Jiang Jilin <freephp@gmail.com>
93
94 * Makefile.am (libopcodes_a_SOURCES): New as empty.
95 * Makefile.in: Regenerate.
96
4469d2be
AM		 972010-10-09 Matt Rice <ratmice@gmail.com>
98
99 * fr30-desc.h: Regenerate.
100 * frv-desc.h: Regenerate.
101 * ip2k-desc.h: Regenerate.
102 * iq2000-desc.h: Regenerate.
103 * lm32-desc.h: Regenerate.
104 * m32c-desc.h: Regenerate.
105 * m32r-desc.h: Regenerate.
106 * mep-desc.h: Regenerate.
107 * mep-opc.c: Regenerate.
108 * mt-desc.h: Regenerate.
109 * openrisc-desc.h: Regenerate.
110 * xc16x-desc.h: Regenerate.
111 * xstormy16-desc.h: Regenerate.
112
9ccb8af9
AM		 1132010-10-08 Pierre Muller <muller@ics.u-strasbg.fr>
114
115 Fix build with -DDEBUG=7
116 * frv-opc.c: Regenerate.
117 * or32-dis.c (DEBUG): Don't redefine.
118 (find_bytes_big, or32_extract, or32_opcode_match, or32_print_register):
119 Adapt DEBUG code to some type changes throughout.
120 * or32-opc.c (or32_extract): Likewise.
121
5d4c71e1
BS		 1222010-10-07 Bernd Schmidt <bernds@codesourcery.com>
123
124 * tic6x-dis.c (print_insn_tic6x): Correct decoding of fstg field
125 in SPKERNEL instructions.
126
9ce00134
L		 1272010-10-02 H.J. Lu <hongjiu.lu@intel.com>
128
129 PR binutils/12076
130 * i386-dis.c (RMAL): Remove duplicate.
131
e7390eec
PM		 1322010-09-30 Pierre Muller <muller@ics.u-strasbg.fr>
133
134 * s390-mkopc.c (main): Exit with error 1 if sscanf fails
135 to parse all 6 parameters.
136
d2ae9c84
PM		 1372010-09-28 Pierre Muller <muller@ics.u-strasbg.fr>
138
139 * s390-mkopc.c (main): Change description array size to 80.
140 Add maximum length of 79 to description parsing.
141
3cac54d2
RW		 1422010-09-27 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
143
144 * configure: Regenerate.
145
d9aee5d7
AK		 1462010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
147
148 * s390-mkopc.c (enum s390_opcde_cpu_val): Add S390_OPCODE_Z196.
149 (main): Recognize the new CPU string.
150 * s390-opc.c: Add new instruction formats and masks.
151 * s390-opc.txt: Add new z196 instructions.
152
02cbf767
AK		 1532010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
154
155 * s390-dis.c (print_insn_s390): Pick instruction with most
156 specific mask.
157 * s390-opc.c: Add unused bits to the insn mask.
158 * s390-opc.txt: Reorder some instructions to prefer more recent
159 versions.
160
6844b2c2
MGD		 1612010-09-27 Tejas Belagod <tejas.belagod@arm.com>
162
163 * arm_dis.c (print_insn_coprocessor): Apply off-by-alignment
164 correction to unaligned PCs while printing comment.
165
90ec0d68
MGD		 1662010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
167
168 * arm-dis.c (arm_opcodes): Add Virtualiztion Extensions support.
169 (thumb32_opcodes): Likewise.
170 (banked_regname): New function.
171 (print_insn_arm): Add Virtualization Extensions support.
172 (print_insn_thumb32): Likewise.
173
eea54501
MGD		 1742010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
175
176 * arm-dis.c (arm_opcodes): Support disassembly of UDIV and SDIV in
177 ARM state.
178
f4c65163
MGD		 1792010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
180
181 * arm-dis.c (arm_opcodes): SMC implies Security Extensions.
182 (thumb32_opcodes): Likewise.
183
60e5ef9f
MGD		 1842010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
185
186 * arm-dis.c (arm_opcodes): Add support for pldw.
187 (thumb32_opcodes): Likewise.
188
7a360e83
MF		 1892010-09-22 Robin Getz <robin.getz@analog.com>
190
191 * bfin-dis.c (fmtconst): Cast address to 32bits.
192
35fc57f3
MF		 1932010-09-22 Mike Frysinger <vapier@gentoo.org>
194
195 * bfin-dis.c (decode_REGMV_0): Rewrite valid combo checks.
196
219b747a
MF		 1972010-09-22 Robin Getz <robin.getz@analog.com>
198
199 * bfin-dis.c (decode_ProgCtrl_0): Check for parallel insns.
200 Reject P6/P7 to TESTSET.
201 (decode_PushPopReg_0): Check for parallel insns. Reject pushing
202 SP onto the stack.
203 (decode_PushPopMultiple_0): Check for parallel insns. Make sure
204 P/D fields match all the time.
205 (decode_CCflag_0): Check for parallel insns. Verify x/y fields
206 are 0 for accumulator compares.
207 (decode_CC2stat_0): Check for parallel insns. Reject CC<op>CC.
208 (decode_CaCTRL_0, decode_ccMV_0, decode_CC2dreg_0, decode_BRCC_0,
209 decode_UJUMP_0, decode_LOGI2op_0, decode_COMPI2opD_0,
210 decode_COMPI2opP_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
211 decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
212 decode_pseudoOChar_0, decode_pseudodbg_assert_0): Check for parallel
213 insns.
214 (decode_dagMODim_0): Verify br field for IREG ops.
215 (decode_LDST_0): Reject preg load into same preg.
216 (_print_insn_bfin): Handle returns for ILLEGAL decodes.
217 (print_insn_bfin): Likewise.
218
775f1cf0
MF		 2192010-09-22 Mike Frysinger <vapier@gentoo.org>
220
221 * bfin-dis.c (decode_PushPopMultiple_0): Return 0 when pr > 5.
222
0b7691fd
MF		 2232010-09-22 Robin Getz <robin.getz@analog.com>
224
225 * bfin-dis.c (decode_dsp32shiftimm_0): Add missing "S" flag.
226
b2459327
MF		 2272010-09-22 Mike Frysinger <vapier@gentoo.org>
228
229 * bfin-dis.c (decode_CC2stat_0): Decode all ASTAT bits.
230
50e2162a
MF		 2312010-09-22 Robin Getz <robin.getz@analog.com>
232
233 * bfin-dis.c (IS_DREG, IS_PREG, IS_GENREG, IS_DAGREG): Reject
234 register values greater than 8.
235 (IS_RESERVEDREG, allreg, mostreg): New helpers.
236 (decode_ProgCtrl_0): Call IS_DREG/IS_PREG as appropriate.
237 (decode_PushPopReg_0): Call mostreg/allreg as appropriate.
238 (decode_CC2dreg_0): Check valid CC register number.
239
a01eda85
MF		 2402010-09-22 Robin Getz <robin.getz@analog.com>
241
242 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after DBG.
243
22215ae0
MF		 2442010-09-22 Robin Getz <robin.getz@analog.com>
245
246 * bfin-dis.c (machine_registers): Add AC0_COPY, V_COPY, and RND_MOD.
247 (reg_names): Likewise.
248 (decode_statbits): Likewise; while reformatting to make manageable.
249
73a63ccf
MF		 2502010-09-22 Mike Frysinger <vapier@gentoo.org>
251
252 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after OUTC.
253 (decode_pseudoOChar_0): New function.
254 (_print_insn_bfin): Remove #if 0 and call new decode_pseudoOChar_0.
255
59a82d23
MF		 2562010-09-22 Robin Getz <robin.getz@analog.com>
257
258 * bfin-dis.c (decode_dsp32shift_0): Decode sub opcodes 2/2 as
259 LSHIFT instead of SHIFT.
260
528c6277
MF		 2612010-09-22 Mike Frysinger <vapier@gentoo.org>
262
263 * bfin-dis.c (constant_formats): Constify the whole structure.
264 (fmtconst): Add const to return value.
265 (reg_names): Mark const.
266 (decode_multfunc): Mark s0/s1 as const.
267 (decode_macfunc): Mark a/sop as const.
268
db472d6f
MGD		 2692010-09-17 Tejas Belagod <tejas.belagod@arm.com>
270
271 * arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv.
272
f6690563
MR		 2732010-09-14 Maciej W. Rozycki <macro@codesourcery.com>
274
275 * mips-opc.c (mips_builtin_opcodes): Add "sync_acquire",
276 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb".
277
8901a3cd
PM		 2782010-09-10 Pierre Muller <muller@ics.u-strasbg.fr>
279
280 * src/opcodes/dlx-dis.c (print_insn_dlx): Use dlx_insn type for
281 dlx_insn_type array.
282
d9e3625e
L		 2832010-08-31 H.J. Lu <hongjiu.lu@intel.com>
284
285 PR binutils/11960
286 * i386-dis.c (sIv): New.
287 (dis386): Replace Iq with sIv on "pushT".
288 (reg_table): Replace T with {T|} on callT, JcallT, jmpT and JjmpT.
4469d2be 289 (x86_64_table): Replace {T|}/{P|} with P.
d9e3625e
L		 290 (putop): Add 'w' to 'T'/'P' if needed for Intel syntax.
291 (OP_sI): Update v_mode. Remove w_mode.
292
f383de66
NF		 2932010-08-27 Nathan Froyd <froydnj@codesourcery.com>
294
295 * ppc-opc.c (powerpc_opcodes) [lswx,lswi,stswx,stswi]: Deprecate
296 on E500 and E500MC.
297
1ab03f4b
L		 2982010-08-17 H.J. Lu <hongjiu.lu@intel.com>
299
300 * i386-dis.c (reg_table): Replace Eb with Mb on prefetch and
301 prefetchw.
302
22109423
L		 3032010-08-06 Quentin Neill <quentin.neill@amd.com>
304
305 * i386-gen.c (cpu_flag_init): Define CpuNop extension flag, add
306 to processor flags for PENTIUMPRO processors and later.
307 * i386-opc.h (enum): Add CpuNop.
308 (i386_cpu_flags): Add cpunop bit.
309 * i386-opc.tbl: Change nop cpu_flags.
310 * i386-init.h: Regenerated.
311 * i386-tbl.h: Likewise.
312
b49dfb4a
L		 3132010-08-06 Quentin Neill <quentin.neill@amd.com>
314
315 * i386-opc.h (enum): Fix typos in comments.
316
6ca4eb77
AM		 3172010-08-06 Alan Modra <amodra@gmail.com>
318
319 * disassemble.c: Formatting.
320 (disassemble_init_for_target <ARCH_m32c>): Comment on endian.
321
92d4d42e
L		 3222010-08-05 H.J. Lu <hongjiu.lu@intel.com>
323
324 * i386-opc.tbl: Add Cpu186 to ud1/ud2/ud2a/ud2b.
325 * i386-tbl.h: Regenerated.
326
b414985b
L		 3272010-08-05 H.J. Lu <hongjiu.lu@intel.com>
328
329 * i386-dis.c (dis386_twobyte): Replace ud2a/ud2b with ud2/ud1.
330
331 * i386-opc.tbl: Add ud1. Remove Cpu686 from ud2/ud2a/ud2b.
332 * i386-tbl.h: Regenerated.
333
f9c7014e
DD		 3342010-07-29 DJ Delorie <dj@redhat.com>
335
336 * rx-decode.opc (SRR): New.
337 (rx_decode_opcode): Use it for movbi and movbir. Decode NOP2 (mov
338 r0,r0) and NOP3 (max r0,r0) special cases.
339 * rx-decode.c: Regenerate.
6ca4eb77 340
592a252b
L		 3412010-07-28 H.J. Lu <hongjiu.lu@intel.com>
342
343 * i386-dis.c: Add 0F to VEX opcode enums.
344
3cf79a01
DD		 3452010-07-27 DJ Delorie <dj@redhat.com>
346
347 * rx-decode.opc (store_flags): Remove, replace with F_* macros.
348 (rx_decode_opcode): Likewise.
349 * rx-decode.c: Regenerate.
350
1cd986c5
NC		 3512010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
352 Ina Pandit <ina.pandit@kpitcummins.com>
353
354 * v850-dis.c (v850_sreg_names): Updated structure for system
355 registers.
356 (float_cc_names): new structure for condition codes.
357 (print_value): Update the function that prints value.
358 (get_operand_value): New function to get the operand value.
359 (disassemble): Updated to handle the disassembly of instructions.
360 (print_insn_v850): Updated function to print instruction for different
361 families.
362 * opcodes/v850-opc.c (v850_msg_is_out_of_range, insert_i5div1,
363 extract_i5div1, insert_i5div2, extract_i5div2, insert_i5div3,
364 extract_i5div3, insert_d5_4, extract_d5_4, extract_d8_6,
365 insert_d8_7, extract_d8_7, insert_v8, extract_v8, insert_u16_loop,
366 extract_u16_loop, insert_d16_15, extract_d16_15, insert_d16_16,
367 extract_d16_16, nsert_d17_16, extract_d17_16, insert_d22,
368 extract_d22, insert_d23, extract_d23, insert_i9, extract_i9,
369 insert_u9, extract_u9, extract_spe, insert_r4, extract_r4): New.
370 (insert_d8_7, insert_d5_4, insert_i5div): Remove.
371 (v850_operands): Update with the relocation name. Also update
372 the instructions with specific set of processors.
373
52e7f43d
RE		 3742010-07-08 Tejas Belagod <tejas.belagod@arm.com>
375
376 * arm-dis.c (print_insn_arm): Add cases for printing more
377 symbolic operands.
378 (print_insn_thumb32): Likewise.
379
c680e7f6
MR		 3802010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
381
382 * mips-dis.c (print_insn_mips): Correct branch instruction type
383 determination.
384
9a2c7088
MR		 3852010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
386
387 * mips-dis.c (print_mips16_insn_arg): Remove branch instruction
388 type and delay slot determination.
389 (print_insn_mips16): Extend branch instruction type and delay
390 slot determination to cover all instructions.
391 * mips16-opc.c (BR): Remove macro.
392 (UBR, CBR): New macros.
393 (mips16_opcodes): Update branch annotation for "b", "beqz",
394 "bnez", "bteqz" and "btnez". Add branch annotation for "jalrc"
395 and "jrc".
396
d7d9a9f8
L		 3972010-07-05 H.J. Lu <hongjiu.lu@intel.com>
398
399 AVX Programming Reference (June, 2010)
400 * i386-dis.c (mod_table): Replace rdrnd with rdrand.
401 * i386-opc.tbl: Likewise.
402 * i386-tbl.h: Regenerated.
403
77321f53
L		 4042010-07-05 H.J. Lu <hongjiu.lu@intel.com>
405
406 * i386-opc.h (CpuFSGSBase): Fix a typo in comments.
407
7102e95e
AS		 4082010-07-03 Andreas Schwab <schwab@linux-m68k.org>
409
410 * ppc-dis.c (powerpc_init_dialect): Cast PPC_OPCODE_xxx to
411 ppc_cpu_t before inverting.
3a5530ea
AS		 412 (ppc_parse_cpu): Likewise.
413 (print_insn_powerpc): Likewise.
7102e95e 414
bdc70b4a
AM		 4152010-07-03 Alan Modra <amodra@gmail.com>
416
417 * ppc-dis.c (ppc_opts, powerpc_init_dialect): Remove old opcode flags.
418 * ppc-opc.c (PPC32, POWER32, COM32, CLASSIC): Delete.
419 (PPC64, MFDEC2): Update.
420 (NON32, NO371): Define.
421 (powerpc_opcode): Update to not use old opcode flags, and avoid
422 -m601 duplicates.
423
21375995
DD		 4242010-07-03 DJ Delorie <dj@delorie.com>
425
426 * m32c-ibld.c: Regenerate.
427
81a0b7e2
AM		 4282010-07-03 Alan Modra <amodra@gmail.com>
429
430 * ppc-opc.c (PWR2COM): Define.
431 (PPCPWR2): Add PPC_OPCODE_COMMON.
432 (powerpc_opcodes): Add "subc", "subco", "subco.", "fcir", "fcir.",
433 "fcirz", "fcirz." to -mcom opcodes. Remove "mfsri", "dclst",
434 "rac" from -mcom.
435
c7b8aa3a
L		 4362010-07-01 H.J. Lu <hongjiu.lu@intel.com>
437
438 AVX Programming Reference (June, 2010)
439 * i386-dis.c (PREFIX_0FAE_REG_0): New.
440 (PREFIX_0FAE_REG_1): Likewise.
441 (PREFIX_0FAE_REG_2): Likewise.
442 (PREFIX_0FAE_REG_3): Likewise.
443 (PREFIX_VEX_3813): Likewise.
444 (PREFIX_VEX_3A1D): Likewise.
445 (prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
446 PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and
447 PREFIX_VEX_3A1D.
448 (vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D.
449 (mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
450 PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd.
451
452 * i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS,
453 CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS.
454 (cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C.
455
456 * i386-opc.h (CpuXsaveopt): New.
77321f53 457 (CpuFSGSBase): Likewise.
c7b8aa3a
L		 458 (CpuRdRnd): Likewise.
459 (CpuF16C): Likewise.
460 (i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and
461 cpuf16c.
462
463 * i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd,
464 wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph.
a00eb5e8
L		 465 * i386-init.h: Regenerated.
466 * i386-tbl.h: Likewise.
c7b8aa3a 467
09a8ad8d
AM		 4682010-07-01 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
469
470 * ppc-opc.c (powerpc_opcodes): Revert deprecation of mfocrf, mtcrf
471 and mtocrf on EFS.
472
360cfc9c
AM		 4732010-06-29 Alan Modra <amodra@gmail.com>
474
475 * maxq-dis.c: Delete file.
476 * Makefile.am: Remove references to maxq.
477 * configure.in: Likewise.
478 * disassemble.c: Likewise.
479 * Makefile.in: Regenerate.
480 * configure: Regenerate.
481 * po/POTFILES.in: Regenerate.
482
dc898d5e
AM		 4832010-06-29 Alan Modra <amodra@gmail.com>
484
485 * mep-dis.c: Regenerate.
486
8e560766
MGD		 4872010-06-28 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
488
489 * arm-disc.c (parse_insn_neon): Fix Neon alignment syntax.
490
c7e2358a
AM		 4912010-06-27 Alan Modra <amodra@gmail.com>
492
493 * arc-dis.c (arc_sprintf): Delete set but unused variables.
494 (decodeInstr): Likewise.
495 * dlx-dis.c (print_insn_dlx): Likewise.
496 * h8300-dis.c (bfd_h8_disassemble_init): Likewise.
497 * maxq-dis.c (check_move, print_insn): Likewise.
498 * mep-dis.c (mep_examine_ivc2_insns): Likewise.
499 * msp430-dis.c (msp430_branchinstr): Likewise.
500 * bfin-dis.c (_print_insn_bfin): Avoid set but unused warning.
501 * cgen-asm.in (parse_insn_normal, _cgen_assemble_insn): Likewise.
502 * sparc-dis.c (print_insn_sparc): Likewise.
503 * fr30-asm.c: Regenerate.
504 * frv-asm.c: Regenerate.
505 * ip2k-asm.c: Regenerate.
506 * iq2000-asm.c: Regenerate.
507 * lm32-asm.c: Regenerate.
508 * m32c-asm.c: Regenerate.
509 * m32r-asm.c: Regenerate.
510 * mep-asm.c: Regenerate.
511 * mt-asm.c: Regenerate.
512 * openrisc-asm.c: Regenerate.
513 * xc16x-asm.c: Regenerate.
514 * xstormy16-asm.c: Regenerate.
515
6ffe3d99
NC		 5162010-06-16 Vincent Rivière <vincent.riviere@freesbee.fr>
517
518 PR gas/11673
519 * m68k-opc.c (m68k_opcodes): Remove move.l for isab and later.
520
09ec0d17
NC		 5212010-06-16 Vincent Rivière <vincent.riviere@freesbee.fr>
522
523 PR binutils/11676
524 * m68k-dis.c (print_insn_arg): Prefix float constants with #0e.
525
e01d869a
AM		 5262010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
527
528 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_E500MC from e500 and
529 e500x2. Add PPC_OPCODE_E500 to e500 and e500x2
530 * ppc-opc.c (powerpc_opcodes): Deprecate all opcodes on EFS which
531 touch floating point regs and are enabled by COM, PPC or PPCCOM.
532 Treat sync as msync on e500. Treat eieio as mbar 1 on e500.
533 Treat lwsync as msync on e500.
534
1f4e4950
MGD		 5352010-06-07 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
536
537 * arm-dis.c (thumb-opcodes): Add disassembly for movs.
538
9d82ec38
MGD		 5392010-05-28 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
540
e01d869a 541 * arm-dis.c (print_insn_neon): Ensure disassembly of Neon
9d82ec38
MGD		 542 constants is the same on 32-bit and 64-bit hosts.
543
c3a6ea62 5442010-05-27 Jason Duerstock <jason.duerstock+binutils@gmail.com>
d8b24b95
NC		 545
546 * m68k-dis.c (print_insn_m68k): Emit undefined instructions as
547 .short directives so that they can be reassembled.
548
9db8dccb
CM		 5492010-05-26 Catherine Moore <clm@codesourcery.com>
550 David Ung <davidu@mips.com>
551
552 * mips-opc.c: Change membership to I1 for instructions ssnop and
553 ehb.
554
dfc8cf43
L		 5552010-05-26 H.J. Lu <hongjiu.lu@intel.com>
556
557 * i386-dis.c (sib): New.
558 (get_sib): Likewise.
559 (print_insn): Call get_sib.
560 OP_E_memory): Use sib.
561
f79e2745
CM		 5622010-05-26 Catherine Moore <clm@codesoourcery.com>
563
564 * mips-dis.c (mips_arch): Remove INSN_MIPS16.
565 * mips-opc.c (I16): Remove.
566 (mips_builtin_op): Reclassify jalx.
567
51b5d4a8
AM		 5682010-05-19 Alan Modra <amodra@gmail.com>
569
570 * ppc-opc.c (powerpc_opcodes): Enable divdeu, devweu, divde,
571 divwe, divdeuo, divweuo, divdeo, divweo for A2. Add icswepx.
572
85d4ac0b
AM		 5732010-05-13 Alan Modra <amodra@gmail.com>
574
575 * ppc-opc.c (powerpc_opcodes): Correct wclr encoding.
576
4547cb56
NC		 5772010-05-11 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
578
579 * arm-dis.c (thumb_opcodes): Update ldmia entry to use new %W
580 format.
581 (print_insn_thumb16): Add support for new %W format.
582
6540b386
TG		 5832010-05-07 Tristan Gingold <gingold@adacore.com>
584
585 * Makefile.in: Regenerate with automake 1.11.1.
586 * aclocal.m4: Ditto.
587
3e01a7fd
NC		 5882010-05-05 Nick Clifton <nickc@redhat.com>
589
590 * po/es.po: Updated Spanish translation.
591
9c9c98a5
NC		 5922010-04-22 Nick Clifton <nickc@redhat.com>
593
594 * po/opcodes.pot: Updated by the Translation project.
595 * po/vi.po: Updated Vietnamese translation.
596
f07af43e
L		 5972010-04-16 H.J. Lu <hongjiu.lu@intel.com>
598
599 * i386-dis.c (get_valid_dis386): Return bad_opcode on unknown
600 bits in opcode.
601
3d540e93
NC		 6022010-04-09 Nick Clifton <nickc@redhat.com>
603
604 * i386-dis.c (print_insn): Remove unused variable op.
605 (OP_sI): Remove unused variable mask.
606
397841b5
AM		 6072010-04-07 Alan Modra <amodra@gmail.com>
608
609 * configure: Regenerate.
610
cee62821
PB		 6112010-04-06 Peter Bergner <bergner@vnet.ibm.com>
612
613 * ppc-opc.c (RBOPT): New define.
614 ("dccci"): Enable for PPCA2. Make operands optional.
615 ("iccci"): Likewise. Do not deprecate for PPC476.
616
accf4463
NC		 6172010-04-02 Masaki Muranaka <monaka@monami-software.com>
618
619 * cr16-opc.c (cr16_instruction): Fix typo in comment.
620
40b36596
JM		 6212010-03-25 Joseph Myers <joseph@codesourcery.com>
622
623 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tic6x-dis.c.
624 * Makefile.in: Regenerate.
625 * configure.in (bfd_tic6x_arch): New.
626 * configure: Regenerate.
627 * disassemble.c (ARCH_tic6x): Define if ARCH_all.
628 (disassembler): Handle TI C6X.
629 * tic6x-dis.c: New.
630
1985c81c
MF		 6312010-03-24 Mike Frysinger <vapier@gentoo.org>
632
633 * bfin-dis.c (decode_regs_hi): Change REG_LH2 typo to REG_MH2.
634
f66187fd
JM		 6352010-03-23 Joseph Myers <joseph@codesourcery.com>
636
637 * dis-buf.c (buffer_read_memory): Give error for reading just
638 before the start of memory.
639
ce7d077e
SP		 6402010-03-22 Sebastian Pop <sebastian.pop@amd.com>
641 Quentin Neill <quentin.neill@amd.com>
642
643 * i386-dis.c (OP_LWP_I): Removed.
644 (reg_table): Do not use OP_LWP_I, use Iq.
645 (OP_LWPCB_E): Remove use of names16.
646 (OP_LWP_E): Same.
647 * i386-opc.tbl: Removed 16bit LWP insns. 32bit LWP insns
648 should not set the Vex.length bit.
649 * i386-tbl.h: Regenerated.
650
63d0fa4e
AM		 6512010-02-25 Edmar Wienskoski <edmar@freescale.com>
652
653 * ppc-dis.c (ppc_opts): Add PPC_OPCODE_E500MC for "e500mc64".
654
c060226a
NC		 6552010-02-24 Nick Clifton <nickc@redhat.com>
656
657 PR binutils/6773
658 * arm-dis.c (arm_opcodes): Replace <prefix>addsubx with
659 <prefix>asx. Replace <prefix>subaddx with <prefix>sax.
660 (thumb32_opcodes): Likewise.
661
ab7875de
NC		 6622010-02-15 Nick Clifton <nickc@redhat.com>
663
664 * po/vi.po: Updated Vietnamese translation.
665
fee1d3e8
DE		 6662010-02-12 Doug Evans <dje@sebabeach.org>
667
668 * lm32-opinst.c: Regenerate.
669
37ec9240
DE		 6702010-02-11 Doug Evans <dje@sebabeach.org>
671
9468ae89
DE		 672 * cgen-dis.in (print_normal): Delete CGEN_PRINT_NORMAL.
673 (print_address): Delete CGEN_PRINT_ADDRESS.
674 * fr30-dis.c, * frv-dis.c, * ip2k-dis.c, * iq2000-dis.c,
675 * lm32-dis.c, * m32c-dis.c, * m32r-desc.c, * m32r-desc.h,
676 * m32r-dis.c, * mep-dis.c, * mt-dis.c, * openrisc-dis.c,
677 * xc16x-dis.c, * xstormy16-dis.c: Regenerate.
678
37ec9240
DE		 679 * fr30-desc.c, * fr30-desc.h, * fr30-opc.c,
680 * frv-desc.c, * frv-desc.h, * frv-opc.c,
681 * ip2k-desc.c, * ip2k-desc.h, * ip2k-opc.c,
682 * iq2000-desc.c, * iq2000-desc.h, * iq2000-opc.c,
683 * lm32-desc.c, * lm32-desc.h, * lm32-opc.c, * lm32-opinst.c,
684 * m32c-desc.c, * m32c-desc.h, * m32c-opc.c,
685 * m32r-desc.c, * m32r-desc.h, * m32r-opc.c, * m32r-opinst.c,
686 * mep-desc.c, * mep-desc.h, * mep-opc.c,
687 * mt-desc.c, * mt-desc.h, * mt-opc.c,
688 * openrisc-desc.c, * openrisc-desc.h, * openrisc-opc.c,
689 * xc16x-desc.c, * xc16x-desc.h, * xc16x-opc.c,
690 * xstormy16-desc.c, * xstormy16-desc.h, * xstormy16-opc.c: Regenerate.
691
c75ef631
L		 6922010-02-11 H.J. Lu <hongjiu.lu@intel.com>
693
694 * i386-dis.c: Update copyright.
695 * i386-gen.c: Likewise.
696 * i386-opc.h: Likewise.
697 * i386-opc.tbl: Likewise.
698
a683cc34
SP		 6992010-02-10 Quentin Neill <quentin.neill@amd.com>
700 Sebastian Pop <sebastian.pop@amd.com>
701
702 * i386-dis.c (OP_EX_VexImmW): Reintroduced
703 function to handle 5th imm8 operand.
704 (PREFIX_VEX_3A48): Added.
705 (PREFIX_VEX_3A49): Added.
706 (VEX_W_3A48_P_2): Added.
707 (VEX_W_3A49_P_2): Added.
708 (prefix table): Added entries for PREFIX_VEX_3A48
709 and PREFIX_VEX_3A49.
710 (vex table): Added entries for VEX_W_3A48_P_2 and
711 and VEX_W_3A49_P_2.
712 * i386-gen.c (operand_type_init): Added OPERAND_TYPE_VEC_IMM4
713 for Vec_Imm4 operands.
714 * i386-opc.h (enum): Added Vec_Imm4.
715 (i386_operand_type): Added vec_imm4.
716 * i386-opc.tbl: Add entries for vpermilp[ds].
717 * i386-init.h: Regenerated.
718 * i386-tbl.h: Regenerated.
719
cdc51b07
RS		 7202010-02-10 Richard Sandiford <r.sandiford@uk.ibm.com>
721
722 * ppc-dis.c (ppc_opts): Add "pwr4", "pwr5", "pwr5x", "pwr6"
723 and "pwr7". Move "a2" into alphabetical order.
724
ce3d2015
AM		 7252010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
726
727 * ppc-dis.c (ppc_opts): Add titan entry.
728 * ppc-opc.c (TITAN, MULHW): Define.
729 (powerpc_opcodes): Support AppliedMicro Titan core (APM83xxx).
730
68339fdf
SP		 7312010-02-03 Quentin Neill <quentin.neill@amd.com>
732
733 * i386-gen.c (cpu_flag_init): Rename CPU_AMDFAM15_FLAGS
734 to CPU_BDVER1_FLAGS
735 * i386-init.h: Regenerated.
736
f3d55a94
AG		 7372010-02-03 Anthony Green <green@moxielogic.com>
738
739 * moxie-opc.c (moxie_form1_opc_info): Move "nop" from 0x00 to
740 0x0f, and make 0x00 an illegal instruction.
741
b0e28b39
DJ		 7422010-01-29 Daniel Jacobowitz <dan@codesourcery.com>
743
744 * opcodes/arm-dis.c (struct arm_private_data): New.
745 (print_insn_coprocessor, print_insn_arm): Update to use struct
746 arm_private_data.
747 (is_mapping_symbol, get_map_sym_type): New functions.
748 (get_sym_code_type): Check the symbol's section. Do not check
749 mapping symbols.
750 (print_insn): Default to disassembling ARM mode code. Check
751 for mapping symbols separately from other symbols. Use
752 struct arm_private_data.
753
1c480963
L		 7542010-01-28 H.J. Lu <hongjiu.lu@intel.com>
755
756 * i386-dis.c (EXVexWdqScalar): New.
757 (vex_scalar_w_dq_mode): Likewise.
758 (prefix_table): Update entries for PREFIX_VEX_3899,
759 PREFIX_VEX_389B, PREFIX_VEX_389D, PREFIX_VEX_389F,
760 PREFIX_VEX_38A9, PREFIX_VEX_38AB, PREFIX_VEX_38AD,
761 PREFIX_VEX_38AF, PREFIX_VEX_38B9, PREFIX_VEX_38BB,
762 PREFIX_VEX_38BD and PREFIX_VEX_38BF.
763 (intel_operand_size): Handle vex_scalar_w_dq_mode.
764 (OP_EX): Likewise.
765
539f890d
L		 7662010-01-27 H.J. Lu <hongjiu.lu@intel.com>
767
768 * i386-dis.c (XMScalar): New.
769 (EXdScalar): Likewise.
770 (EXqScalar): Likewise.
771 (EXqScalarS): Likewise.
772 (VexScalar): Likewise.
773 (EXdVexScalarS): Likewise.
774 (EXqVexScalarS): Likewise.
775 (XMVexScalar): Likewise.
776 (scalar_mode): Likewise.
777 (d_scalar_mode): Likewise.
778 (d_scalar_swap_mode): Likewise.
779 (q_scalar_mode): Likewise.
780 (q_scalar_swap_mode): Likewise.
781 (vex_scalar_mode): Likewise.
782 (vex_len_table): Duplcate entries for VEX_LEN_10_P_1,
783 VEX_LEN_10_P_3, VEX_LEN_11_P_1, VEX_LEN_11_P_3, VEX_LEN_2A_P_1,
784 VEX_LEN_2A_P_3, VEX_LEN_2C_P_3, VEX_LEN_2D_P_1, VEX_LEN_2E_P_0,
785 VEX_LEN_2E_P_2, VEX_LEN_2F_P_2, VEX_LEN_51_P_1, VEX_LEN_51_P_3,
786 VEX_LEN_52_P_1, VEX_LEN_53_P_1, VEX_LEN_58_P_1, VEX_LEN_58_P_3,
787 VEX_LEN_59_P_1, VEX_LEN_5A_P_1, VEX_LEN_5A_P_3, VEX_LEN_5C_P_1,
788 VEX_LEN_5C_P_3, VEX_LEN_5D_P_1, VEX_LEN_5D_P_3, VEX_LEN_5E_P_1,
789 VEX_LEN_5E_P_3, VEX_LEN_5F_P_1, VEX_LEN_5F_P_3, VEX_LEN_6E_P_2,
790 VEX_LEN_7E_P_1, VEX_LEN_7E_P_2, VEX_LEN_D6_P_2, VEX_LEN_C2_P_1,
791 VEX_LEN_C2_P_3, VEX_LEN_3A0A_P_2 and VEX_LEN_3A0B_P_2.
792 (vex_w_table): Update entries for VEX_W_10_P_1, VEX_W_10_P_3,
793 VEX_W_11_P_1, VEX_W_11_P_3, VEX_W_2E_P_0, VEX_W_2E_P_2,
794 VEX_W_2F_P_0, VEX_W_2F_P_2, VEX_W_51_P_1, VEX_W_51_P_3,
795 VEX_W_52_P_1, VEX_W_53_P_1, VEX_W_58_P_1, VEX_W_58_P_3,
796 VEX_W_59_P_1, VEX_W_59_P_3, VEX_W_5A_P_1, VEX_W_5A_P_3,
797 VEX_W_5C_P_1, VEX_W_5C_P_3, VEX_W_5D_P_1, VEX_W_5D_P_3,
798 VEX_W_5E_P_1, VEX_W_5E_P_3, VEX_W_5F_P_1, VEX_W_5F_P_3,
799 VEX_W_7E_P_1, VEX_W_D6_P_2 VEX_W_C2_P_1, VEX_W_C2_P_3,
800 VEX_W_3A0A_P_2 and VEX_W_3A0B_P_2.
801 (intel_operand_size): Handle d_scalar_mode, d_scalar_swap_mode,
802 q_scalar_mode, q_scalar_swap_mode.
803 (OP_XMM): Handle scalar_mode.
804 (OP_EX): Handle d_scalar_mode, d_scalar_swap_mode, q_scalar_mode
805 and q_scalar_swap_mode.
806 (OP_VEX): Handle vex_scalar_mode.
807
208b4d78
L		 8082010-01-24 H.J. Lu <hongjiu.lu@intel.com>
809
810 * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
811
448b213a
L		 8122010-01-24 H.J. Lu <hongjiu.lu@intel.com>
813
814 * i386-dis.c (vex_len_table): Remove trailing { Bad_Opcode }.
815
47cf8fa0
L		 8162010-01-24 H.J. Lu <hongjiu.lu@intel.com>
817
818 * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
819
592d1631
L		 8202010-01-24 H.J. Lu <hongjiu.lu@intel.com>
821
822 * i386-dis.c (Bad_Opcode): New.
823 (bad_opcode): Likewise.
824 (dis386): Replace { "(bad)", { XX } } with { Bad_Opcode }.
825 (dis386_twobyte): Likewise.
826 (reg_table): Likewise.
827 (prefix_table): Likewise.
828 (x86_64_table): Likewise.
829 (vex_len_table): Likewise.
830 (vex_w_table): Likewise.
831 (mod_table): Likewise.
832 (rm_table): Likewise.
833 (float_reg): Likewise.
834 (reg_table): Remove trailing "(bad)" entries.
835 (prefix_table): Likewise.
836 (x86_64_table): Likewise.
837 (vex_len_table): Likewise.
838 (vex_w_table): Likewise.
839 (mod_table): Likewise.
840 (rm_table): Likewise.
841 (get_valid_dis386): Handle bytemode 0.
842
712366da
L		 8432010-01-23 H.J. Lu <hongjiu.lu@intel.com>
844
845 * i386-opc.h (VEXScalar): New.
846
847 * i386-opc.tbl: Replace "Vex" with "Vex=3" on AVX scalar
848 instructions.
849 * i386-tbl.h: Regenerated.
850
706e8205 8512010-01-21 H.J. Lu <hongjiu.lu@intel.com>
73bb6729
L		 852
853 * i386-dis.c (mod_table): Use FXSAVE on xsave and xrstor.
854
855 * i386-opc.tbl: Add xsave64 and xrstor64.
856 * i386-tbl.h: Regenerated.
857
99ea83aa
NC		 8582010-01-20 Nick Clifton <nickc@redhat.com>
859
860 PR 11170
861 * arm-dis.c (print_arm_address): Do not ignore negative bit in PC
862 based post-indexed addressing.
863
a6461c02
SP		 8642010-01-15 Sebastian Pop <sebastian.pop@amd.com>
865
866 * i386-opc.tbl: Support all the possible aliases for VPCOM* insns.
867 * i386-tbl.h: Regenerated.
868
a2a7d12c
L		 8692010-01-14 H.J. Lu <hongjiu.lu@intel.com>
870
871 * i386-opc.h (VexVVVV): Replace VEX.DNS with VEX.NDS in
872 comments.
873
b9733481
L		 8742010-01-14 H.J. Lu <hongjiu.lu@intel.com>
875
876 * i386-dis.c (names_mm): New.
877 (intel_names_mm): Likewise.
878 (att_names_mm): Likewise.
879 (names_xmm): Likewise.
880 (intel_names_xmm): Likewise.
881 (att_names_xmm): Likewise.
882 (names_ymm): Likewise.
883 (intel_names_ymm): Likewise.
884 (att_names_ymm): Likewise.
885 (print_insn): Set names_mm, names_xmm and names_ymm.
886 (OP_MMX): Use names_mm, names_xmm and names_ymm.
887 (OP_XMM): Likewise.
888 (OP_EM): Likewise.
889 (OP_EMC): Likewise.
890 (OP_MXC): Likewise.
891 (OP_EX): Likewise.
892 (XMM_Fixup): Likewise.
893 (OP_VEX): Likewise.
894 (OP_EX_VexReg): Likewise.
895 (OP_Vex_2src): Likewise.
896 (OP_Vex_2src_1): Likewise.
897 (OP_Vex_2src_2): Likewise.
898 (OP_REG_VexI4): Likewise.
899
5e6718e4
L		 9002010-01-13 H.J. Lu <hongjiu.lu@intel.com>
901
902 * i386-dis.c (print_insn): Update comments.
903
d869730d
L		 9042010-01-12 H.J. Lu <hongjiu.lu@intel.com>
905
906 * i386-dis.c (rex_original): Removed.
907 (ckprefix): Remove rex_original.
908 (print_insn): Update comments.
909
3725885a
RW		 9102010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
911
912 * Makefile.in: Regenerate.
913 * configure: Regenerate.
914
b7cd1872
DE		 9152010-01-07 Doug Evans <dje@sebabeach.org>
916
917 * cgen-ibld.in (insert_normal, extract_normal): Minor cleanup.
918 * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
919 * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
920 * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
921 * xstormy16-ibld.c: Regenerate.
922
69dd9865
SP		 9232010-01-06 Quentin Neill <quentin.neill@amd.com>
924
925 * i386-gen.c (cpu_flag_init): Add new CPU_AMDFAM15_FLAGS.
926 * i386-init.h: Regenerated.
927
e3e535bc
NC		 9282010-01-06 Daniel Gutson <dgutson@codesourcery.com>
929
930 * arm-dis.c (print_insn): Fixed search for next symbol and data
931 dumping condition, and the initial mapping symbol state.
932
fe8afbc4
DE		 9332010-01-05 Doug Evans <dje@sebabeach.org>
934
935 * cgen-ibld.in: #include "cgen/basic-modes.h".
936 * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
937 * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
938 * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
939 * xstormy16-ibld.c: Regenerate.
940
2edcd244
NC		 9412010-01-04 Nick Clifton <nickc@redhat.com>
942
943 PR 11123
944 * arm-dis.c (print_insn_coprocessor): Initialise value.
945
0dc93057
AM		 9462010-01-04 Edmar Wienskoski <edmar@freescale.com>
947
948 * ppc-dis.c (ppc_opts): Add entry for "e500mc64".
949
05994f45
DE		 9502010-01-02 Doug Evans <dje@sebabeach.org>
951
952 * cgen-asm.in: Update copyright year.
953 * cgen-dis.in: Update copyright year.
954 * cgen-ibld.in: Update copyright year.
955 * fr30-asm.c, * fr30-desc.c, * fr30-desc.h, * fr30-dis.c,
956 * fr30-ibld.c, * fr30-opc.c, * fr30-opc.h, * frv-asm.c, * frv-desc.c,
957 * frv-desc.h, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * frv-opc.h,
958 * ip2k-asm.c, * ip2k-desc.c, * ip2k-desc.h, * ip2k-dis.c,
959 * ip2k-ibld.c, * ip2k-opc.c, * ip2k-opc.h, * iq2000-asm.c,
960 * iq2000-desc.c, * iq2000-desc.h, * iq2000-dis.c, * iq2000-ibld.c,
961 * iq2000-opc.c, * iq2000-opc.h, * lm32-asm.c, * lm32-desc.c,
962 * lm32-desc.h, * lm32-dis.c, * lm32-ibld.c, * lm32-opc.c, * lm32-opc.h,
963 * lm32-opinst.c, * m32c-asm.c, * m32c-desc.c, * m32c-desc.h,
964 * m32c-dis.c, * m32c-ibld.c, * m32c-opc.c, * m32c-opc.h, * m32r-asm.c,
965 * m32r-desc.c, * m32r-desc.h, * m32r-dis.c, * m32r-ibld.c,
966 * m32r-opc.c, * m32r-opc.h, * m32r-opinst.c, * mep-asm.c, * mep-desc.c,
967 * mep-desc.h, * mep-dis.c, * mep-ibld.c, * mep-opc.c, * mep-opc.h,
968 * mt-asm.c, * mt-desc.c, * mt-desc.h, * mt-dis.c, * mt-ibld.c,
969 * mt-opc.c, * mt-opc.h, * openrisc-asm.c, * openrisc-desc.c,
970 * openrisc-desc.h, * openrisc-dis.c, * openrisc-ibld.c,
971 * openrisc-opc.c, * openrisc-opc.h, * xc16x-asm.c, * xc16x-desc.c,
972 * xc16x-desc.h, * xc16x-dis.c, * xc16x-ibld.c, * xc16x-opc.c,
973 * xc16x-opc.h, * xstormy16-asm.c, * xstormy16-desc.c,
974 * xstormy16-desc.h, * xstormy16-dis.c, * xstormy16-ibld.c,
975 * xstormy16-opc.c, * xstormy16-opc.h: Regenerate.
2426c15f 976
43ecc30f 977For older changes see ChangeLog-2009
252b5132
RH		 978\f
979Local Variables:
2f6d2f85
NC		 980mode: change-log
981left-margin: 8
982fill-column: 74
252b5132
RH		 983version-control: never
984End:
GDB Binutils - Deliverables
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