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Workaround a FreeBSD kernel bug resulting in spurious SIGTRAP events.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
2d5d5a8f
AM		 12018-12-18 Alan Modra <amodra@gmail.com>
2
3 * arm-dis.c: Include bfd.h.
4 * aarch64-opc.c: Include bfd_stdint.h rather than stdint.h.
5 * csky-dis.c: Likewise.
6 * nds32-asm.c: Likewise.
7 * riscv-dis.c: Likewise.
8 * s12z-dis.c: Likewise.
9 * wasm32-dis.c: Likewise.
10
f50fabe4
JW		 112018-12-07 Jim Wilson <jimw@sifive.com>
12
13 PR gas/23956
14 * riscv-opc.c (riscv_opcodes) <"add">: Use 1 not 0 for fourth arg.
15
7fb45a68
AB		 162018-12-06 Andrew Burgess <andrew.burgess@embecosm.com>
17
18 * configure.ac (enable-cgen-maint): Support passing path to cgen
19 source tree.
20 * configure: Regenerate.
21
884b49e3
AB		 222018-12-06 Andrew Burgess <andrew.burgess@embecosm.com>
23
24 * disassembler.c (disassemble_init_for_target): Add RISC-V
25 initialisation.
26 * riscv-dis.c (riscv_symbol_is_valid): New function.
27
1080bf78
JW		 282018-12-03 Kito Cheng <kito@andestech.com>
29
30 * riscv-opc.c: Change the type of xlen, because type of
31 xlen_requirement changed.
32
57b64c41
EB		 332018-12-03 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
34
35 PR 23193
36 PR 19721
37 * aarch64-tbl.h (aarch64_opcode_table): Only disassemble an ORR
38 encoding as MOV if the shift operation is a left shift of zero.
39
12951a2f
JW		 402018-11-29 Jim Wilson <jimw@sifive.com>
41
42 * riscv-opc.c (unimp): Mark compressed unimp as INSN_ALIAS.
43 (c.unimp): New.
44
4765cd61
JW		 452018-11-27 Jim Wilson <jimw@sifive.com>
46
47 * riscv-opc.c (ciw): Fix whitespace to align columns.
48 (ca): New.
49
27f42a4d
JD		 502018-11-21 John Darrington <john@darrington.wattle.id.au>
51
52 * s12z-dis.c (print_insn_shift) [SB_REG_REG_N]: Enter special case
53 if the postbyte matches the appropriate pattern.
54
97b3f392
FT		 552018-11-13 Francois H. Theron <francois.theron@netronome.com>
56
57 * nfp-dis.c: Fix crc[] disassembly if operands are swapped.
58
3a0f69be
SD		 592018-11-12 Sudakshina Das <sudi.das@arm.com>
60
61 * aarch64-opc.c (aarch64_sys_regs_dc): New entries for
62 IGVAC, IGSW, CGSW, CIGSW, CGVAC, CGVAP, CGVADP, CIGVAC, GVA,
63 IGDVAC, IGDSW, CGDSW, CIGDSW, CGDVAC, CGDVAP, CGDVADP,
64 CIGDVAC and GZVA.
65 (aarch64_sys_ins_reg_supported_p): New check for above.
66
70f3d23a
SD		 672018-11-12 Sudakshina Das <sudi.das@arm.com>
68
69 * aarch64-opc.c (aarch64_sys_regs): New entries for TCO,
70 TFSRE0_SL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, TFSR_EL12,
71 RGSR_EL1 and GCR_EL1.
72 (aarch64_sys_reg_supported_p): New check for above.
73 (aarch64_pstatefields): New entry for TCO.
74 (aarch64_pstatefield_supported_p): New check for above.
75
503ba600
SD		 762018-11-12 Sudakshina Das <sudi.das@arm.com>
77
78 * aarch64-asm.c (aarch64_ins_addr_simple_2): New.
79 * aarch64-asm.h (ins_addr_simple_2): Declare the above.
80 * aarch64-dis.c (aarch64_ext_addr_simple_2): New.
81 * aarch64-dis.h (ext_addr_simple_2): Declare the above.
82 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
83 AARCH64_OPND_ADDR_SIMPLE_2 and ldstgv_indexed.
84 (aarch64_print_operand): Add case for AARCH64_OPND_ADDR_SIMPLE_2.
85 * aarch64-tbl.h (aarch64_opcode_table): Add stgv and ldgv.
86 (AARCH64_OPERANDS): Define ADDR_SIMPLE_2.
87 * aarch64-asm-2.c: Regenerated.
88 * aarch64-dis-2.c: Regenerated.
89 * aarch64-opc-2.c: Regenerated.
90
e6025b54
SD		 912018-11-12 Sudakshina Das <sudi.das@arm.com>
92
93 * aarch64-tbl.h (QL_LDG): New.
94 (aarch64_opcode_table): Add ldg.
95 * aarch64-asm-2.c: Regenerated.
96 * aarch64-dis-2.c: Regenerated.
97 * aarch64-opc-2.c: Regenerated.
98
fb3265b3
SD		 992018-11-12 Sudakshina Das <sudi.das@arm.com>
100
101 * aarch64-opc.c (aarch64_opnd_qualifiers): Add new data
102 for AARCH64_OPND_QLF_imm_tag.
103 (operand_general_constraint_met_p): Add case for
104 AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
105 (aarch64_print_operand): Likewise.
106 * aarch64-tbl.h (QL_LDST_AT, QL_STGP): New.
107 (aarch64_opcode_table): Add stg, stzg, st2g, stz2g and stgp
108 for both offset and pre/post indexed versions.
109 (AARCH64_OPERANDS): Define ADDR_SIMM11 and ADDR_SIMM13.
110 * aarch64-asm-2.c: Regenerated.
111 * aarch64-dis-2.c: Regenerated.
112 * aarch64-opc-2.c: Regenerated.
113
b731bc3b
SD		 1142018-11-12 Sudakshina Das <sudi.das@arm.com>
115
116 * aarch64-tbl.h (aarch64_opcode_table): Add subp, subps and cmpp.
117 * aarch64-asm-2.c: Regenerated.
118 * aarch64-dis-2.c: Regenerated.
119 * aarch64-opc-2.c: Regenerated.
120
193614f2
SD		 1212018-11-12 Sudakshina Das <sudi.das@arm.com>
122
123 * aarch64-opc.h (aarch64_field_kind): New FLD_imm4_3.
124 (OPD_F_SHIFT_BY_4, operand_need_shift_by_four): New.
125 * aarch64-opc.c (fields): Add entry for imm4_3.
126 (operand_general_constraint_met_p): Add cases for
127 AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10.
128 (aarch64_print_operand): Likewise.
129 * aarch64-tbl.h (QL_ADDG): New.
130 (aarch64_opcode_table): Add addg, subg, irg and gmi.
131 (AARCH64_OPERANDS): Define UIMM4_ADDG and UIMM10.
132 * aarch64-asm.c (aarch64_ins_imm): Add case for
133 operand_need_shift_by_four.
134 * aarch64-asm-2.c: Regenerated.
135 * aarch64-dis-2.c: Regenerated.
136 * aarch64-opc-2.c: Regenerated.
137
73b605ec
SD		 1382018-11-12 Sudakshina Das <sudi.das@arm.com>
139
140 * aarch64-tbl.h (aarch64_feature_memtag): New.
141 (MEMTAG, MEMTAG_INSN): New.
142
0632eeea
SD		 1432018-11-06 Sudakshina Das <sudi.das@arm.com>
144
145 * arm-dis.c (select_arm_features): Update bfd_mach_arm_8
146 with Armv8.5-A. Remove reduntant ARM_EXT2_FP16_FML.
147
71553718
AM		 1482018-11-06 Alan Modra <amodra@gmail.com>
149
150 * ppc-opc.c (insert_arx, insert_ary, insert_rx, insert_ry, insert_ls),
151 (insert_evuimm1_ex0, insert_evuimm2_ex0, insert_evuimm4_ex0),
152 (insert_evuimm8_ex0, insert_evuimm_lt8, insert_evuimm_lt16),
153 (insert_rD_rS_even, insert_off_lsp, insert_off_spe2, insert_Ddd):
154 Don't return zero on error, insert mask bits instead.
155 (insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w): Delete.
156 (insert_sh6, extract_sh6): Delete dead code.
157 (insert_sprbat, insert_sprg): Use unsigned comparisions.
158 (powerpc_operands <OIMM>): Set shift count rather than using
159 PPC_OPSHIFT_INV.
160 <SE_SDH, SE_SDW>: Likewise. Don't use insert/extract functions.
161
4dd4e639
JB		 1622018-11-06 Jan Beulich <jbeulich@suse.com>
163
164 * i386-dis-evex.h (evex_table): Use K suffix instead of %LW for
165 vpbroadcast{d,q} with GPR operand.
166
9819647a
JB		 1672018-11-06 Jan Beulich <jbeulich@suse.com>
168
169 * i386-dis.c (EVEX_W_0F6E_P_2, EVEX_W_0F7E_P_2): Delete.
170 * i386-dis-evex.h (evex_table): Move vmov[dq} with GPR operand
171 cases up one level in the hierarchy.
172
58a211d2
JB		 1732018-11-06 Jan Beulich <jbeulich@suse.com>
174
175 * i386-dis.c (MOD_VEX_W_0_0F92_P_3_LEN_0,
176 MOD_VEX_W_1_0F92_P_3_LEN_0): Fold into MOD_VEX_0F92_P_3_LEN_0.
177 (MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0): Fold
178 into MOD_VEX_0F93_P_3_LEN_0.
179 (vex_len_table, vex_w_table, mod_table): Move kmov[dq} with GPR
180 operand cases up one level in the hierarchy.
181
b50c9f31
JB		 1822018-11-06 Jan Beulich <jbeulich@suse.com>
183
184 * i386-dis.c (VEX_W_0FC4_P_2, VEX_W_0FC5_P_2, VEX_W_0F3A14_P_2,
185 VEX_W_0F3A15_P_2, VEX_W_0F3A20_P_2, EVEX_W_0F3A16_P_2,
186 EVEX_W_0F3A22_P_2): Delete.
187 (vex_len_table, vex_w_table): Move vpextr{b,w} and vpinsr{b,w}
188 entries up one level in the hierarchy.
189 (OP_E_memory): Handle dq_mode when determining Disp8 shift
190 value.
191 * i386-dis-evex.h (evex_table): Move vpextr{d,q} and vpinsr{d,q}
192 entries up one level in the hierarchy.
193 * i386-opc.tbl (vpextrb, vpextrw, vpinsrb, vpinsrw): Change to
194 VexWIG for AVX flavors.
195 * i386-tbl.h: Re-generate.
196
931d03b7
JB		 1972018-11-06 Jan Beulich <jbeulich@suse.com>
198
199 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vmovd, vpcmpestri,
200 vpcmpestrm, vpextrd, vpinsrd, vpbroadcastd, vcvtusi2sd,
201 vcvtusi2ss, kmovd): Drop VexW=1.
202 * i386-tbl.h: Re-generate.
203
fd71a375
JB		 2042018-11-06 Jan Beulich <jbeulich@suse.com>
205
206 * i386-opc.tbl (Vex128, Vex256, VexLIG, EVex128, EVex256,
207 EVex512, EVexLIG, EVexDYN): New.
208 (ldmxcsr, stmxcsr, vldmxcsr, vstmxcsr, all BMI, BMI2, and TBM
209 insns): Use Vex128 instead of Vex=3 (aka VexLIG).
210 (vextractps, vinsertps, vpextr*, vpinsr*): Use EVex128 instead
211 of EVex=4 (aka EVexLIG).
212 * i386-tbl.h: Re-generate.
213
563c7eef
JB		 2142018-11-06 Jan Beulich <jbeulich@suse.com>
215
216 * i386-opc.tbl (pextrw, vpextrw): Add Load to 0F C5 forms.
217 (vpmaxub): Re-order attributes on AVX512BW flavor.
218 * i386-tbl.h: Re-generate.
219
0aaca1d9
JB		 2202018-11-06 Jan Beulich <jbeulich@suse.com>
221
222 * i386-opc.tbl (vandnp*, vandp*, vcmp*, vcvtss2sd, vorp*,
223 vpmaxub, vmovntdqa, vmpsadbw, vphsub*): Use VexWIG instead of
224 Vex=1 on AVX / AVX2 flavors.
225 (vpmaxub): Re-order attributes on AVX512BW flavor.
226 * i386-tbl.h: Re-generate.
227
bbae6b11
JB		 2282018-11-06 Jan Beulich <jbeulich@suse.com>
229
230 * i386-opc.tbl (VexW0, VexW1): New.
231 (vphadd*, vphsub*): Use VexW0 on XOP variants.
232 * i386-tbl.h: Re-generate.
233
192c2bfb
JD		 2342018-10-22 John Darrington <john@darrington.wattle.id.au>
235
236 * s12z-dis.c (decode_possible_symbol): Add fallback case.
237 (rel_15_7): Likewise.
238
0b347048
TC		 2392018-10-19 Tamar Christina <tamar.christina@arm.com>
240
241 * arm-dis.c (UNKNOWN_INSTRUCTION_32BIT): Format specifier for arm mode.
242 (UNKNOWN_INSTRUCTION_16BIT): Format specifier for thumb mode.
243 (print_insn_arm, print_insn_thumb16, print_insn_thumb32): Use them.
244
66e6f0b7
MM		 2452018-10-16 Matthew Malcomson <matthew.malcomson@arm.com>
246
247 * aarch64-opc.c (struct operand_qualifier_data): Change qualifier data
248 corresponding to AARCH64_OPND_QLF_S_4B qualifier.
249
673fe0f0
JB		 2502018-10-10 Jan Beulich <jbeulich@suse.com>
251
252 * i386-gen.c (opcode_modifiers): Drop Size16, Size32, and
253 Size64. Add Size.
254 * i386-opc.h (Size16, Size32, Size64): Delete.
255 (Size): New.
256 (SIZE16, SIZE32, SIZE64): Define.
257 (struct i386_opcode_modifier): Drop size16, size32, and size64.
258 Add size.
259 * i386-opc.tbl (Size16, Size32, Size64): Define.
260 * i386-tbl.h: Re-generate.
261
104fefee
SD		 2622018-10-09 Sudakshina Das <sudi.das@arm.com>
263
264 * aarch64-opc.c (operand_general_constraint_met_p): Add
265 SSBS in the check for one-bit immediate.
266 (aarch64_sys_regs): New entry for SSBS.
267 (aarch64_sys_reg_supported_p): New check for above.
268 (aarch64_pstatefields): New entry for SSBS.
269 (aarch64_pstatefield_supported_p): New check for above.
270
a97330e7
SD		 2712018-10-09 Sudakshina Das <sudi.das@arm.com>
272
273 * aarch64-opc.c (aarch64_sys_regs): New entries for
274 scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
275 (aarch64_sys_reg_supported_p): New checks for above.
276
ff605452
SD		 2772018-10-09 Sudakshina Das <sudi.das@arm.com>
278
279 * aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.
280 (HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag
281 with the hint immediate.
282 * aarch64-opc.c (aarch64_hint_options): New entries for
283 c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI.
284 (aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET
285 while checking for HINT_OPD_F_NOPRINT flag.
286 * aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to
287 extract value.
288 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New.
289 (aarch64_opcode_table): Add entry for BTI.
290 (AARCH64_OPERANDS): Add new description for BTI targets.
291 * aarch64-asm-2.c: Regenerate.
292 * aarch64-dis-2.c: Regenerate.
293 * aarch64-opc-2.c: Regenerate.
294
af4bcb4c
SD		 2952018-10-09 Sudakshina Das <sudi.das@arm.com>
296
297 * aarch64-opc.c (aarch64_sys_regs): New entries for
298 rndr and rndrrs.
299 (aarch64_sys_reg_supported_p): New check for above.
300
3fd229a4
SD		 3012018-10-09 Sudakshina Das <sudi.das@arm.com>
302
303 * aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp.
304 (aarch64_sys_ins_reg_supported_p): New check for above.
305
2ac435d4
SD		 3062018-10-09 Sudakshina Das <sudi.das@arm.com>
307
308 * aarch64-dis.c (aarch64_ext_sysins_op): Add case for
309 AARCH64_OPND_SYSREG_SR.
310 * aarch64-opc.c (aarch64_print_operand): Likewise.
311 (aarch64_sys_regs_sr): Define table.
312 (aarch64_sys_ins_reg_supported_p): Check for RCTX with
313 AARCH64_FEATURE_PREDRES.
314 * aarch64-tbl.h (aarch64_feature_predres): New.
315 (PREDRES, PREDRES_INSN): New.
316 (aarch64_opcode_table): Add entries for cfp, dvp and cpp.
317 (AARCH64_OPERANDS): Add new description for SYSREG_SR.
318 * aarch64-asm-2.c: Regenerate.
319 * aarch64-dis-2.c: Regenerate.
320 * aarch64-opc-2.c: Regenerate.
321
68dfbb92
SD		 3222018-10-09 Sudakshina Das <sudi.das@arm.com>
323
324 * aarch64-tbl.h (aarch64_feature_sb): New.
325 (SB, SB_INSN): New.
326 (aarch64_opcode_table): Add entry for sb.
327 * aarch64-asm-2.c: Regenerate.
328 * aarch64-dis-2.c: Regenerate.
329 * aarch64-opc-2.c: Regenerate.
330
13c60ad7
SD		 3312018-10-09 Sudakshina Das <sudi.das@arm.com>
332
333 * aarch64-tbl.h (aarch64_feature_flagmanip): New.
334 (aarch64_feature_frintts): New.
335 (FLAGMANIP, FRINTTS): New.
336 (aarch64_opcode_table): Add entries for xaflag, axflag
337 and frint[32,64][x,z] instructions.
338 * aarch64-asm-2.c: Regenerate.
339 * aarch64-dis-2.c: Regenerate.
340 * aarch64-opc-2.c: Regenerate.
341
70d56181
SD		 3422018-10-09 Sudakshina Das <sudi.das@arm.com>
343
344 * aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New.
345 (ARMV8_5, V8_5_INSN): New.
346
780f601c
TC		 3472018-10-08 Tamar Christina <tamar.christina@arm.com>
348
349 * aarch64-opc.c (verify_constraints): Use memset instead of {0}.
350
a4e78aa5
L		 3512018-10-05 H.J. Lu <hongjiu.lu@intel.com>
352
353 * i386-dis.c (rm_table): Add enclv.
354 * i386-opc.tbl: Add enclv.
355 * i386-tbl.h: Regenerated.
356
7fadb25d
SD		 3572018-10-05 Sudakshina Das <sudi.das@arm.com>
358
359 * arm-dis.c (arm_opcodes): Add sb.
360 (thumb32_opcodes): Likewise.
361
07f5f4c6
RH		 3622018-10-05 Richard Henderson <rth@twiddle.net>
363 Stafford Horne <shorne@gmail.com>
364
365 * or1k-desc.c: Regenerate.
366 * or1k-desc.h: Regenerate.
367 * or1k-opc.c: Regenerate.
368 * or1k-opc.h: Regenerate.
369 * or1k-opinst.c: Regenerate.
370
c8e98e36
SH		 3712018-10-05 Richard Henderson <rth@twiddle.net>
372
373 * or1k-asm.c: Regenerated.
374 * or1k-desc.c: Regenerated.
375 * or1k-desc.h: Regenerated.
376 * or1k-dis.c: Regenerated.
377 * or1k-ibld.c: Regenerated.
378 * or1k-opc.c: Regenerated.
379 * or1k-opc.h: Regenerated.
380 * or1k-opinst.c: Regenerated.
381
1c4f3780
RH		 3822018-10-05 Richard Henderson <rth@twiddle.net>
383
384 * or1k-asm.c: Regenerate.
385
bde90be2
TC		 3862018-10-03 Tamar Christina <tamar.christina@arm.com>
387
388 * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
389 * aarch64-dis.c (print_operands): Refactor to take notes.
390 (print_verifier_notes): New.
391 (print_aarch64_insn): Apply constraint verifier.
392 (print_insn_aarch64_word): Update call to print_aarch64_insn.
393 * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
394
a68f4cd2
TC		 3952018-10-03 Tamar Christina <tamar.christina@arm.com>
396
397 * aarch64-opc.c (init_insn_block): New.
398 (verify_constraints, aarch64_is_destructive_by_operands): New.
399 * aarch64-opc.h (verify_constraints): New.
400
755b748f
TC		 4012018-10-03 Tamar Christina <tamar.christina@arm.com>
402
403 * aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
404 * aarch64-opc.c (verify_ldpsw): Update arguments.
405
1d482394
TC		 4062018-10-03 Tamar Christina <tamar.christina@arm.com>
407
408 * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
409 (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
410
7e84b55d
TC		 4112018-10-03 Tamar Christina <tamar.christina@arm.com>
412
413 * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
414 * aarch64-dis.c (insn_sequence): New.
415
eae424ae
TC		 4162018-10-03 Tamar Christina <tamar.christina@arm.com>
417
418 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
419 _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
420 _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
421 V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
422 constraints.
423 (_SVE_INSNC): New.
424 (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
425 constraints.
426 (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
427 F_SCAN flags.
428 (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
429 sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
430 sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
431 sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
432 uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
433 uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
434 C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
435
64a336ac
PD		 4362018-10-02 Palmer Dabbelt <palmer@sifive.com>
437
438 * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
439
6031ac35
SL		 4402018-09-23 Sandra Loosemore <sandra@codesourcery.com>
441
442 * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
443 are used when extracting signed fields and converting them to
444 potentially 64-bit types.
445
f24ff6e9
SM		 4462018-09-21 Simon Marchi <simon.marchi@ericsson.com>
447
448 * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
449 * Makefile.in: Re-generate.
450 * aclocal.m4: Re-generate.
451 * configure: Re-generate.
452 * configure.ac: Remove check for -Wno-missing-field-initializers.
453 * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
454 (csky_v2_opcodes): Likewise.
455
53b6d6f5
MR		 4562018-09-20 Maciej W. Rozycki <macro@linux-mips.org>
457
458 * arc-nps400-tbl.h: Append `ull' to large constants throughout.
459
fbaf61ad
NC		 4602018-09-20 Nelson Chu <nelson.chu1990@gmail.com>
461
462 * nds32-asm.c (operand_fields): Remove the unused fields.
463 (nds32_opcodes): Remove the unused instructions.
464 * nds32-dis.c (nds32_ex9_info): Removed.
465 (nds32_parse_opcode): Updated.
466 (print_insn_nds32): Likewise.
467 * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
468 (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
469 (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
470 build_opcode_hash_table): New functions.
471 (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
472 nds32_opcode_table): New.
473 (hw_ktabs): Declare it to a pointer rather than an array.
474 (build_hash_table): Removed.
475 * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
476 SYN_ROPT and upadte HW_GPR and HW_INT.
477 * nds32-dis.c (keywords): Remove const.
478 (match_field): New function.
479 (nds32_parse_opcode): Updated.
480 * disassemble.c (disassemble_init_for_target):
481 Add disassemble_init_nds32.
482 * nds32-dis.c (eum map_type): New.
483 (nds32_private_data): Likewise.
484 (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
485 nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
486 (print_insn_nds32): Updated.
487 * nds32-asm.c (parse_aext_reg): Add new parameter.
488 (parse_re, parse_re2, parse_aext_reg): Only reduced registers
489 are allowed to use.
490 All callers changed.
491 * nds32-asm.c (keyword_usr, keyword_sr): Updated.
492 (operand_fields): Add new fields.
493 (nds32_opcodes): Add new instructions.
494 (keyword_aridxi_mx): New keyword.
495 * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
496 and NASM_ATTR_ZOL.
497 (ALU2_1, ALU2_2, ALU2_3): New macros.
498 * nds32-dis.c (nds32_filter_unknown_insn): Updated.
499
4e2b1898
JW		 5002018-09-17 Kito Cheng <kito@andestech.com>
501
502 * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
503
04e2a182
L		 5042018-09-17 H.J. Lu <hongjiu.lu@intel.com>
505
506 PR gas/23670
507 * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
508 EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
509 (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
510 (EVEX_LEN_0F7E_P_1): Likewise.
511 (EVEX_LEN_0F7E_P_2): Likewise.
512 (EVEX_LEN_0FD6_P_2): Likewise.
513 * i386-dis.c (USE_EVEX_LEN_TABLE): New.
514 (EVEX_LEN_TABLE): Likewise.
515 (EVEX_LEN_0F6E_P_2): New enum.
516 (EVEX_LEN_0F7E_P_1): Likewise.
517 (EVEX_LEN_0F7E_P_2): Likewise.
518 (EVEX_LEN_0FD6_P_2): Likewise.
519 (evex_len_table): New.
520 (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
521 * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
522 * i386-tbl.h: Regenerated.
523
d5f787c2
L		 5242018-09-17 H.J. Lu <hongjiu.lu@intel.com>
525
526 PR gas/23665
527 * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
528 VEX_LEN_0F7E_P_2 entries.
529 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
530 * i386-tbl.h: Regenerated.
531
ec6f095a
L		 5322018-09-17 H.J. Lu <hongjiu.lu@intel.com>
533
534 * i386-dis.c (VZERO_Fixup): Removed.
535 (VZERO): Likewise.
536 (VEX_LEN_0F10_P_1): Likewise.
537 (VEX_LEN_0F10_P_3): Likewise.
538 (VEX_LEN_0F11_P_1): Likewise.
539 (VEX_LEN_0F11_P_3): Likewise.
540 (VEX_LEN_0F2E_P_0): Likewise.
541 (VEX_LEN_0F2E_P_2): Likewise.
542 (VEX_LEN_0F2F_P_0): Likewise.
543 (VEX_LEN_0F2F_P_2): Likewise.
544 (VEX_LEN_0F51_P_1): Likewise.
545 (VEX_LEN_0F51_P_3): Likewise.
546 (VEX_LEN_0F52_P_1): Likewise.
547 (VEX_LEN_0F53_P_1): Likewise.
548 (VEX_LEN_0F58_P_1): Likewise.
549 (VEX_LEN_0F58_P_3): Likewise.
550 (VEX_LEN_0F59_P_1): Likewise.
551 (VEX_LEN_0F59_P_3): Likewise.
552 (VEX_LEN_0F5A_P_1): Likewise.
553 (VEX_LEN_0F5A_P_3): Likewise.
554 (VEX_LEN_0F5C_P_1): Likewise.
555 (VEX_LEN_0F5C_P_3): Likewise.
556 (VEX_LEN_0F5D_P_1): Likewise.
557 (VEX_LEN_0F5D_P_3): Likewise.
558 (VEX_LEN_0F5E_P_1): Likewise.
559 (VEX_LEN_0F5E_P_3): Likewise.
560 (VEX_LEN_0F5F_P_1): Likewise.
561 (VEX_LEN_0F5F_P_3): Likewise.
562 (VEX_LEN_0FC2_P_1): Likewise.
563 (VEX_LEN_0FC2_P_3): Likewise.
564 (VEX_LEN_0F3A0A_P_2): Likewise.
565 (VEX_LEN_0F3A0B_P_2): Likewise.
566 (VEX_W_0F10_P_0): Likewise.
567 (VEX_W_0F10_P_1): Likewise.
568 (VEX_W_0F10_P_2): Likewise.
569 (VEX_W_0F10_P_3): Likewise.
570 (VEX_W_0F11_P_0): Likewise.
571 (VEX_W_0F11_P_1): Likewise.
572 (VEX_W_0F11_P_2): Likewise.
573 (VEX_W_0F11_P_3): Likewise.
574 (VEX_W_0F12_P_0_M_0): Likewise.
575 (VEX_W_0F12_P_0_M_1): Likewise.
576 (VEX_W_0F12_P_1): Likewise.
577 (VEX_W_0F12_P_2): Likewise.
578 (VEX_W_0F12_P_3): Likewise.
579 (VEX_W_0F13_M_0): Likewise.
580 (VEX_W_0F14): Likewise.
581 (VEX_W_0F15): Likewise.
582 (VEX_W_0F16_P_0_M_0): Likewise.
583 (VEX_W_0F16_P_0_M_1): Likewise.
584 (VEX_W_0F16_P_1): Likewise.
585 (VEX_W_0F16_P_2): Likewise.
586 (VEX_W_0F17_M_0): Likewise.
587 (VEX_W_0F28): Likewise.
588 (VEX_W_0F29): Likewise.
589 (VEX_W_0F2B_M_0): Likewise.
590 (VEX_W_0F2E_P_0): Likewise.
591 (VEX_W_0F2E_P_2): Likewise.
592 (VEX_W_0F2F_P_0): Likewise.
593 (VEX_W_0F2F_P_2): Likewise.
594 (VEX_W_0F50_M_0): Likewise.
595 (VEX_W_0F51_P_0): Likewise.
596 (VEX_W_0F51_P_1): Likewise.
597 (VEX_W_0F51_P_2): Likewise.
598 (VEX_W_0F51_P_3): Likewise.
599 (VEX_W_0F52_P_0): Likewise.
600 (VEX_W_0F52_P_1): Likewise.
601 (VEX_W_0F53_P_0): Likewise.
602 (VEX_W_0F53_P_1): Likewise.
603 (VEX_W_0F58_P_0): Likewise.
604 (VEX_W_0F58_P_1): Likewise.
605 (VEX_W_0F58_P_2): Likewise.
606 (VEX_W_0F58_P_3): Likewise.
607 (VEX_W_0F59_P_0): Likewise.
608 (VEX_W_0F59_P_1): Likewise.
609 (VEX_W_0F59_P_2): Likewise.
610 (VEX_W_0F59_P_3): Likewise.
611 (VEX_W_0F5A_P_0): Likewise.
612 (VEX_W_0F5A_P_1): Likewise.
613 (VEX_W_0F5A_P_3): Likewise.
614 (VEX_W_0F5B_P_0): Likewise.
615 (VEX_W_0F5B_P_1): Likewise.
616 (VEX_W_0F5B_P_2): Likewise.
617 (VEX_W_0F5C_P_0): Likewise.
618 (VEX_W_0F5C_P_1): Likewise.
619 (VEX_W_0F5C_P_2): Likewise.
620 (VEX_W_0F5C_P_3): Likewise.
621 (VEX_W_0F5D_P_0): Likewise.
622 (VEX_W_0F5D_P_1): Likewise.
623 (VEX_W_0F5D_P_2): Likewise.
624 (VEX_W_0F5D_P_3): Likewise.
625 (VEX_W_0F5E_P_0): Likewise.
626 (VEX_W_0F5E_P_1): Likewise.
627 (VEX_W_0F5E_P_2): Likewise.
628 (VEX_W_0F5E_P_3): Likewise.
629 (VEX_W_0F5F_P_0): Likewise.
630 (VEX_W_0F5F_P_1): Likewise.
631 (VEX_W_0F5F_P_2): Likewise.
632 (VEX_W_0F5F_P_3): Likewise.
633 (VEX_W_0F60_P_2): Likewise.
634 (VEX_W_0F61_P_2): Likewise.
635 (VEX_W_0F62_P_2): Likewise.
636 (VEX_W_0F63_P_2): Likewise.
637 (VEX_W_0F64_P_2): Likewise.
638 (VEX_W_0F65_P_2): Likewise.
639 (VEX_W_0F66_P_2): Likewise.
640 (VEX_W_0F67_P_2): Likewise.
641 (VEX_W_0F68_P_2): Likewise.
642 (VEX_W_0F69_P_2): Likewise.
643 (VEX_W_0F6A_P_2): Likewise.
644 (VEX_W_0F6B_P_2): Likewise.
645 (VEX_W_0F6C_P_2): Likewise.
646 (VEX_W_0F6D_P_2): Likewise.
647 (VEX_W_0F6F_P_1): Likewise.
648 (VEX_W_0F6F_P_2): Likewise.
649 (VEX_W_0F70_P_1): Likewise.
650 (VEX_W_0F70_P_2): Likewise.
651 (VEX_W_0F70_P_3): Likewise.
652 (VEX_W_0F71_R_2_P_2): Likewise.
653 (VEX_W_0F71_R_4_P_2): Likewise.
654 (VEX_W_0F71_R_6_P_2): Likewise.
655 (VEX_W_0F72_R_2_P_2): Likewise.
656 (VEX_W_0F72_R_4_P_2): Likewise.
657 (VEX_W_0F72_R_6_P_2): Likewise.
658 (VEX_W_0F73_R_2_P_2): Likewise.
659 (VEX_W_0F73_R_3_P_2): Likewise.
660 (VEX_W_0F73_R_6_P_2): Likewise.
661 (VEX_W_0F73_R_7_P_2): Likewise.
662 (VEX_W_0F74_P_2): Likewise.
663 (VEX_W_0F75_P_2): Likewise.
664 (VEX_W_0F76_P_2): Likewise.
665 (VEX_W_0F77_P_0): Likewise.
666 (VEX_W_0F7C_P_2): Likewise.
667 (VEX_W_0F7C_P_3): Likewise.
668 (VEX_W_0F7D_P_2): Likewise.
669 (VEX_W_0F7D_P_3): Likewise.
670 (VEX_W_0F7E_P_1): Likewise.
671 (VEX_W_0F7F_P_1): Likewise.
672 (VEX_W_0F7F_P_2): Likewise.
673 (VEX_W_0FAE_R_2_M_0): Likewise.
674 (VEX_W_0FAE_R_3_M_0): Likewise.
675 (VEX_W_0FC2_P_0): Likewise.
676 (VEX_W_0FC2_P_1): Likewise.
677 (VEX_W_0FC2_P_2): Likewise.
678 (VEX_W_0FC2_P_3): Likewise.
679 (VEX_W_0FD0_P_2): Likewise.
680 (VEX_W_0FD0_P_3): Likewise.
681 (VEX_W_0FD1_P_2): Likewise.
682 (VEX_W_0FD2_P_2): Likewise.
683 (VEX_W_0FD3_P_2): Likewise.
684 (VEX_W_0FD4_P_2): Likewise.
685 (VEX_W_0FD5_P_2): Likewise.
686 (VEX_W_0FD6_P_2): Likewise.
687 (VEX_W_0FD7_P_2_M_1): Likewise.
688 (VEX_W_0FD8_P_2): Likewise.
689 (VEX_W_0FD9_P_2): Likewise.
690 (VEX_W_0FDA_P_2): Likewise.
691 (VEX_W_0FDB_P_2): Likewise.
692 (VEX_W_0FDC_P_2): Likewise.
693 (VEX_W_0FDD_P_2): Likewise.
694 (VEX_W_0FDE_P_2): Likewise.
695 (VEX_W_0FDF_P_2): Likewise.
696 (VEX_W_0FE0_P_2): Likewise.
697 (VEX_W_0FE1_P_2): Likewise.
698 (VEX_W_0FE2_P_2): Likewise.
699 (VEX_W_0FE3_P_2): Likewise.
700 (VEX_W_0FE4_P_2): Likewise.
701 (VEX_W_0FE5_P_2): Likewise.
702 (VEX_W_0FE6_P_1): Likewise.
703 (VEX_W_0FE6_P_2): Likewise.
704 (VEX_W_0FE6_P_3): Likewise.
705 (VEX_W_0FE7_P_2_M_0): Likewise.
706 (VEX_W_0FE8_P_2): Likewise.
707 (VEX_W_0FE9_P_2): Likewise.
708 (VEX_W_0FEA_P_2): Likewise.
709 (VEX_W_0FEB_P_2): Likewise.
710 (VEX_W_0FEC_P_2): Likewise.
711 (VEX_W_0FED_P_2): Likewise.
712 (VEX_W_0FEE_P_2): Likewise.
713 (VEX_W_0FEF_P_2): Likewise.
714 (VEX_W_0FF0_P_3_M_0): Likewise.
715 (VEX_W_0FF1_P_2): Likewise.
716 (VEX_W_0FF2_P_2): Likewise.
717 (VEX_W_0FF3_P_2): Likewise.
718 (VEX_W_0FF4_P_2): Likewise.
719 (VEX_W_0FF5_P_2): Likewise.
720 (VEX_W_0FF6_P_2): Likewise.
721 (VEX_W_0FF7_P_2): Likewise.
722 (VEX_W_0FF8_P_2): Likewise.
723 (VEX_W_0FF9_P_2): Likewise.
724 (VEX_W_0FFA_P_2): Likewise.
725 (VEX_W_0FFB_P_2): Likewise.
726 (VEX_W_0FFC_P_2): Likewise.
727 (VEX_W_0FFD_P_2): Likewise.
728 (VEX_W_0FFE_P_2): Likewise.
729 (VEX_W_0F3800_P_2): Likewise.
730 (VEX_W_0F3801_P_2): Likewise.
731 (VEX_W_0F3802_P_2): Likewise.
732 (VEX_W_0F3803_P_2): Likewise.
733 (VEX_W_0F3804_P_2): Likewise.
734 (VEX_W_0F3805_P_2): Likewise.
735 (VEX_W_0F3806_P_2): Likewise.
736 (VEX_W_0F3807_P_2): Likewise.
737 (VEX_W_0F3808_P_2): Likewise.
738 (VEX_W_0F3809_P_2): Likewise.
739 (VEX_W_0F380A_P_2): Likewise.
740 (VEX_W_0F380B_P_2): Likewise.
741 (VEX_W_0F3817_P_2): Likewise.
742 (VEX_W_0F381C_P_2): Likewise.
743 (VEX_W_0F381D_P_2): Likewise.
744 (VEX_W_0F381E_P_2): Likewise.
745 (VEX_W_0F3820_P_2): Likewise.
746 (VEX_W_0F3821_P_2): Likewise.
747 (VEX_W_0F3822_P_2): Likewise.
748 (VEX_W_0F3823_P_2): Likewise.
749 (VEX_W_0F3824_P_2): Likewise.
750 (VEX_W_0F3825_P_2): Likewise.
751 (VEX_W_0F3828_P_2): Likewise.
752 (VEX_W_0F3829_P_2): Likewise.
753 (VEX_W_0F382A_P_2_M_0): Likewise.
754 (VEX_W_0F382B_P_2): Likewise.
755 (VEX_W_0F3830_P_2): Likewise.
756 (VEX_W_0F3831_P_2): Likewise.
757 (VEX_W_0F3832_P_2): Likewise.
758 (VEX_W_0F3833_P_2): Likewise.
759 (VEX_W_0F3834_P_2): Likewise.
760 (VEX_W_0F3835_P_2): Likewise.
761 (VEX_W_0F3837_P_2): Likewise.
762 (VEX_W_0F3838_P_2): Likewise.
763 (VEX_W_0F3839_P_2): Likewise.
764 (VEX_W_0F383A_P_2): Likewise.
765 (VEX_W_0F383B_P_2): Likewise.
766 (VEX_W_0F383C_P_2): Likewise.
767 (VEX_W_0F383D_P_2): Likewise.
768 (VEX_W_0F383E_P_2): Likewise.
769 (VEX_W_0F383F_P_2): Likewise.
770 (VEX_W_0F3840_P_2): Likewise.
771 (VEX_W_0F3841_P_2): Likewise.
772 (VEX_W_0F38DB_P_2): Likewise.
773 (VEX_W_0F3A08_P_2): Likewise.
774 (VEX_W_0F3A09_P_2): Likewise.
775 (VEX_W_0F3A0A_P_2): Likewise.
776 (VEX_W_0F3A0B_P_2): Likewise.
777 (VEX_W_0F3A0C_P_2): Likewise.
778 (VEX_W_0F3A0D_P_2): Likewise.
779 (VEX_W_0F3A0E_P_2): Likewise.
780 (VEX_W_0F3A0F_P_2): Likewise.
781 (VEX_W_0F3A21_P_2): Likewise.
782 (VEX_W_0F3A40_P_2): Likewise.
783 (VEX_W_0F3A41_P_2): Likewise.
784 (VEX_W_0F3A42_P_2): Likewise.
785 (VEX_W_0F3A62_P_2): Likewise.
786 (VEX_W_0F3A63_P_2): Likewise.
787 (VEX_W_0F3ADF_P_2): Likewise.
788 (VEX_LEN_0F77_P_0): New.
789 (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
790 PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
791 PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
792 PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
793 PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
794 PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
795 PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
796 PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
797 PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
798 PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
799 PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
800 PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
801 PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
802 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
803 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
804 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
805 PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
806 PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
807 PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
808 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
809 PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
810 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
811 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
812 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
813 PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
814 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
815 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
816 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
817 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
818 PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
819 PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
820 PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
821 PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
822 PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
823 PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
824 PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
825 PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
826 PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
827 PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
828 PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
829 PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
830 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
831 PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
832 PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
833 PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
834 PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
835 PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
836 PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
837 PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
838 (vex_table): Update VEX 0F28 and 0F29 entries.
839 (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
840 VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
841 VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
842 VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
843 VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
844 VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
845 VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
846 VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
847 VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
848 VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
849 VEX_LEN_0F3A0B_P_2 entries.
850 (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
851 VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
852 VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
853 VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
854 VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
855 VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
856 VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
857 VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
858 VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
859 VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
860 VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
861 VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
862 VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
863 VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
864 VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
865 VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
866 VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
867 VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
868 VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
869 VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
870 VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
871 VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
872 VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
873 VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
874 VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
875 VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
876 VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
877 VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
878 VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
879 VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
880 VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
881 VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
882 VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
883 VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
884 VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
885 VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
886 VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
887 VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
888 VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
889 VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
890 VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
891 VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
892 VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
893 VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
894 VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
895 VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
896 VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
897 VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
898 VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
899 VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
900 VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
901 VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
902 VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
903 VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
904 VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
905 VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
906 VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
907 VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
908 VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
909 VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
910 VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
911 VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
912 VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
913 VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
914 VEX_W_0F3ADF_P_2 entries.
915 (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
916 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
917 MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
918
6fa52824
L		 9192018-09-17 H.J. Lu <hongjiu.lu@intel.com>
920
921 * i386-opc.tbl (VexWIG): New.
922 Replace VexW=3 with VexWIG.
923
db4cc665
L		 9242018-09-15 H.J. Lu <hongjiu.lu@intel.com>
925
926 * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
927 * i386-tbl.h: Regenerated.
928
3c374143
L		 9292018-09-15 H.J. Lu <hongjiu.lu@intel.com>
930
931 PR gas/23665
932 * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
933 VEX_LEN_0FD6_P_2 entries.
934 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
935 * i386-tbl.h: Regenerated.
936
6865c043
L		 9372018-09-14 H.J. Lu <hongjiu.lu@intel.com>
938
939 PR gas/23642
940 * i386-opc.h (VEXWIG): New.
941 * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
942 * i386-tbl.h: Regenerated.
943
70df6fc9
L		 9442018-09-14 H.J. Lu <hongjiu.lu@intel.com>
945
946 PR binutils/23655
947 * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
948 vcvtsi2sd%LQ and vcvtusi2sd%LQ.
949 * i386-dis.c (EXxEVexR64): New.
950 (evex_rounding_64_mode): Likewise.
951 (OP_Rounding): Handle evex_rounding_64_mode.
952
d20dee9e
L		 9532018-09-14 H.J. Lu <hongjiu.lu@intel.com>
954
955 PR binutils/23655
956 * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
957 vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
958 * i386-dis.c (Edqa): New.
959 (dqa_mode): Likewise.
960 (intel_operand_size): Handle dqa_mode as m_mode.
961 (OP_E_register): Handle dqa_mode as dq_mode.
962 (OP_E_memory): Set shift for dqa_mode based on address_mode.
963
5074ad8a
L		 9642018-09-14 H.J. Lu <hongjiu.lu@intel.com>
965
966 * i386-dis.c (OP_E_memory): Reformat.
967
556059dd
JB		 9682018-09-14 Jan Beulich <jbeulich@suse.com>
969
970 * i386-opc.tbl (crc32): Fold byte and word forms.
971 * i386-tbl.h: Re-generate.
972
41d1ab6a
L		 9732018-09-13 H.J. Lu <hongjiu.lu@intel.com>
974
975 * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
976 pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
977 Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
978 vpinsrq. Remove VexW=1 from WIG VEX movq and vmovq.
979 * i386-tbl.h: Regenerated.
980
57f6375e
JB		 9812018-09-13 Jan Beulich <jbeulich@suse.com>
982
983 * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
984 meaningless.
985 (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
986 xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
987 rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
988 * i386-tbl.h: Re-generate.
989
2589a7e5
JB		 9902018-09-13 Jan Beulich <jbeulich@suse.com>
991
992 * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
993 AVX512_4VNNIW insns.
994 * i386-tbl.h: Re-generate.
995
a760eb41
JB		 9962018-09-13 Jan Beulich <jbeulich@suse.com>
997
998 * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
999 meaningless.
1000 * i386-tbl.h: Re-generate.
1001
e9042658
JB		 10022018-09-13 Jan Beulich <jbeulich@suse.com>
1003
1004 * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
1005 meaningless.
1006 * i386-tbl.h: Re-generate.
1007
9caa306f
JB		 10082018-09-13 Jan Beulich <jbeulich@suse.com>
1009
1010 * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
1011 meaningless.
1012 * i386-tbl.h: Re-generate.
1013
fb6ce599
JB		 10142018-09-13 Jan Beulich <jbeulich@suse.com>
1015
1016 * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
1017 meaningless.
1018 * i386-tbl.h: Re-generate.
1019
6a8da886
JB		 10202018-09-13 Jan Beulich <jbeulich@suse.com>
1021
1022 * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
1023 meaningless.
1024 * i386-tbl.h: Re-generate.
1025
c7f27919
JB		 10262018-09-13 Jan Beulich <jbeulich@suse.com>
1027
1028 * i386-opc.tbl: Drop IgnoreSize from SHA insns.
1029 * i386-tbl.h: Re-generate.
1030
0f407ee9
JB		 10312018-09-13 Jan Beulich <jbeulich@suse.com>
1032
1033 * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
1034 * i386-tbl.h: Re-generate.
1035
2fbbbee5
JB		 10362018-09-13 Jan Beulich <jbeulich@suse.com>
1037
1038 * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
1039 meaningless.
1040 * i386-tbl.h: Re-generate.
1041
2b02b9a2
JB		 10422018-09-13 Jan Beulich <jbeulich@suse.com>
1043
1044 * i386-opc.tbl: Drop IgnoreSize from AVX insns where
1045 meaningless.
1046 * i386-tbl.h: Re-generate.
1047
963c68aa
JB		 10482018-09-13 Jan Beulich <jbeulich@suse.com>
1049
1050 * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
1051 * i386-tbl.h: Re-generate.
1052
64e025c3
JB		 10532018-09-13 Jan Beulich <jbeulich@suse.com>
1054
1055 * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
1056 * i386-tbl.h: Re-generate.
1057
47603f88
JB		 10582018-09-13 Jan Beulich <jbeulich@suse.com>
1059
1060 * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
1061 * i386-tbl.h: Re-generate.
1062
0001cfd0
JB		 10632018-09-13 Jan Beulich <jbeulich@suse.com>
1064
1065 * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
1066 meaningless.
1067 * i386-tbl.h: Re-generate.
1068
be4b452e
JB		 10692018-09-13 Jan Beulich <jbeulich@suse.com>
1070
1071 * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
1072 meaningless.
1073 * i386-tbl.h: Re-generate.
1074
d09a1394
JB		 10752018-09-13 Jan Beulich <jbeulich@suse.com>
1076
1077 * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
1078 meaningless.
1079 * i386-tbl.h: Re-generate.
1080
07599e13
JB		 10812018-09-13 Jan Beulich <jbeulich@suse.com>
1082
1083 * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
1084 * i386-tbl.h: Re-generate.
1085
1ee3e487
JB		 10862018-09-13 Jan Beulich <jbeulich@suse.com>
1087
1088 * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
1089 * i386-tbl.h: Re-generate.
1090
a5f580e5
JB		 10912018-09-13 Jan Beulich <jbeulich@suse.com>
1092
1093 * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
1094 * i386-tbl.h: Re-generate.
1095
49d5d12d
JB		 10962018-09-13 Jan Beulich <jbeulich@suse.com>
1097
1098 * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
1099 (vpbroadcastw, rdpid): Drop NoRex64.
1100 * i386-tbl.h: Re-generate.
1101
f5eb1d70
JB		 11022018-09-13 Jan Beulich <jbeulich@suse.com>
1103
1104 * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
1105 store templates, adding D.
1106 * i386-tbl.h: Re-generate.
1107
dbbc8b7e
JB		 11082018-09-13 Jan Beulich <jbeulich@suse.com>
1109
1110 * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
1111 movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
1112 movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
1113 vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
1114 vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
1115 Fold load and store templates where possible, adding D. Drop
1116 IgnoreSize where it was pointlessly present. Drop redundant
1117 *word.
1118 * i386-tbl.h: Re-generate.
1119
d276ec69
JB		 11202018-09-13 Jan Beulich <jbeulich@suse.com>
1121
1122 * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
1123 (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
1124 (intel_operand_size): Handle v_bndmk_mode.
1125 (OP_E_memory): Likewise. Produce (bad) when also riprel.
1126
9da4dfd6
JD		 11272018-09-08 John Darrington <john@darrington.wattle.id.au>
1128
1129 * disassemble.c (ARCH_s12z): Define if ARCH_all.
1130
be192bc2
JW		 11312018-08-31 Kito Cheng <kito@andestech.com>
1132
1133 * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
1134 compressed floating point instructions.
1135
43135d3b
JW		 11362018-08-30 Kito Cheng <kito@andestech.com>
1137
1138 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
1139 riscv_opcode.xlen_requirement.
1140 * riscv-opc.c (riscv_opcodes): Update for struct change.
1141
df28970f
MA		 11422018-08-29 Martin Aberg <maberg@gaisler.com>
1143
1144 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
1145 psr (PWRPSR) instruction.
1146
9108bc33
CX		 11472018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1148
1149 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
1150
bd782c07
CX		 11512018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1152
1153 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
1154
ac8cb70f
CX		 11552018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1156
1157 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
1158 loongson3a as an alias of gs464 for compatibility.
1159 * mips-opc.c (mips_opcodes): Change Comments.
1160
a693765e
CX		 11612018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1162
1163 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
1164 option.
1165 (print_mips_disassembler_options): Document -M loongson-ext.
1166 * mips-opc.c (LEXT2): New macro.
1167 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
1168
bdc6c06e
CX		 11692018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1170
1171 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
1172 descriptors.
1173 (parse_mips_ase_option): Handle -M loongson-ext option.
1174 (print_mips_disassembler_options): Document -M loongson-ext.
1175 * mips-opc.c (IL3A): Delete.
1176 * mips-opc.c (LEXT): New macro.
1177 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
1178 instructions.
1179
716c08de
CX		 11802018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1181
1182 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
1183 descriptors.
1184 (parse_mips_ase_option): Handle -M loongson-cam option.
1185 (print_mips_disassembler_options): Document -M loongson-cam.
1186 * mips-opc.c (LCAM): New macro.
1187 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
1188 instructions.
1189
9cf7e568
AM		 11902018-08-21 Alan Modra <amodra@gmail.com>
1191
1192 * ppc-dis.c (operand_value_powerpc): Init "invalid".
1193 (skip_optional_operands): Count optional operands, and update
1194 ppc_optional_operand_value call.
1195 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
1196 (extract_vlensi): Likewise.
1197 (extract_fxm): Return default value for missing optional operand.
1198 (extract_ls, extract_raq, extract_tbr): Likewise.
1199 (insert_sxl, extract_sxl): New functions.
1200 (insert_esync, extract_esync): Remove Power9 handling and simplify.
1201 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
1202 flag and extra entry.
1203 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
1204 extract_sxl.
1205
d203b41a 12062018-08-20 Alan Modra <amodra@gmail.com>
f4107842 1207
d203b41a 1208 * sh-opc.h (MASK): Simplify.
f4107842 1209
08a8fe2f 12102018-08-18 John Darrington <john@darrington.wattle.id.au>
7ba3ba91 1211
d203b41a
AM		 1212 * s12z-dis.c (bm_decode): Deal with cases where the mode is
1213 BM_RESERVED0 or BM_RESERVED1
08a8fe2f 1214 (bm_rel_decode, bm_n_bytes): Ditto.
d203b41a 1215
08a8fe2f 12162018-08-18 John Darrington <john@darrington.wattle.id.au>
d203b41a
AM		 1217
1218 * s12z.h: Delete.
7ba3ba91 1219
1bc60e56
L		 12202018-08-14 H.J. Lu <hongjiu.lu@intel.com>
1221
1222 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
1223 address with the addr32 prefix and without base nor index
1224 registers.
1225
d871f3f4
L		 12262018-08-11 H.J. Lu <hongjiu.lu@intel.com>
1227
1228 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
1229 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
1230 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
1231 (cpu_flags): Add CpuCMOV and CpuFXSR.
1232 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
1233 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
1234 * i386-init.h: Regenerated.
1235 * i386-tbl.h: Likewise.
1236
b6523c37 12372018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
1238
1239 * arc-regs.h: Update auxiliary registers.
1240
e968fc9b
JB		 12412018-08-06 Jan Beulich <jbeulich@suse.com>
1242
1243 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
1244 (RegIP, RegIZ): Define.
1245 * i386-reg.tbl: Adjust comments.
1246 (rip): Use Qword instead of BaseIndex. Use RegIP.
1247 (eip): Use Dword instead of BaseIndex. Use RegIP.
1248 (riz): Add Qword. Use RegIZ.
1249 (eiz): Add Dword. Use RegIZ.
1250 * i386-tbl.h: Re-generate.
1251
dbf8be89
JB		 12522018-08-03 Jan Beulich <jbeulich@suse.com>
1253
1254 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
1255 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
1256 vpmovzxdq, vpmovzxwd): Remove NoRex64.
1257 * i386-tbl.h: Re-generate.
1258
c48dadc9
JB		 12592018-08-03 Jan Beulich <jbeulich@suse.com>
1260
1261 * i386-gen.c (operand_types): Remove Mem field.
1262 * i386-opc.h (union i386_operand_type): Remove mem field.
1263 * i386-init.h, i386-tbl.h: Re-generate.
1264
cb86a42a
AM		 12652018-08-01 Alan Modra <amodra@gmail.com>
1266
1267 * po/POTFILES.in: Regenerate.
1268
07cc0450
NC		 12692018-07-31 Nick Clifton <nickc@redhat.com>
1270
1271 * po/sv.po: Updated Swedish translation.
1272
1424ad86
JB		 12732018-07-31 Jan Beulich <jbeulich@suse.com>
1274
1275 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
1276 * i386-init.h, i386-tbl.h: Re-generate.
1277
ae2387fe
JB		 12782018-07-31 Jan Beulich <jbeulich@suse.com>
1279
1280 * i386-opc.h (ZEROING_MASKING) Rename to ...
1281 (DYNAMIC_MASKING): ... this. Adjust comment.
1282 * i386-opc.tbl (MaskingMorZ): Define.
1283 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
1284 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
1285 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
1286 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
1287 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
1288 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
1289 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
1290 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
1291 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
1292
6ff00b5e
JB		 12932018-07-31 Jan Beulich <jbeulich@suse.com>
1294
1295 * i386-opc.tbl: Use element rather than vector size for AVX512*
1296 scatter/gather insns.
1297 * i386-tbl.h: Re-generate.
1298
e951d5ca
JB		 12992018-07-31 Jan Beulich <jbeulich@suse.com>
1300
1301 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
1302 (cpu_flags): Drop CpuVREX.
1303 * i386-opc.h (CpuVREX): Delete.
1304 (union i386_cpu_flags): Remove cpuvrex.
1305 * i386-init.h, i386-tbl.h: Re-generate.
1306
eb41b248
JW		 13072018-07-30 Jim Wilson <jimw@sifive.com>
1308
1309 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
1310 fields.
1311 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
1312
b8891f8d
AJ		 13132018-07-30 Andrew Jenner <andrew@codesourcery.com>
1314
1315 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
1316 * Makefile.in: Regenerated.
1317 * configure.ac: Add C-SKY.
1318 * configure: Regenerated.
1319 * csky-dis.c: New file.
1320 * csky-opc.h: New file.
1321 * disassemble.c (ARCH_csky): Define.
1322 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
1323 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
1324
16065af1
AM		 13252018-07-27 Alan Modra <amodra@gmail.com>
1326
1327 * ppc-opc.c (insert_sprbat): Correct function parameter and
1328 return type.
1329 (extract_sprbat): Likewise, variable too.
1330
fa758a70
AC		 13312018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
1332 Alan Modra <amodra@gmail.com>
1333
1334 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
1335 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
1336 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
1337 support disjointed BAT.
1338 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
1339 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
1340 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
1341
4a1b91ea
L		 13422018-07-25 H.J. Lu <hongjiu.lu@intel.com>
1343 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1344
1345 * i386-gen.c (adjust_broadcast_modifier): New function.
1346 (process_i386_opcode_modifier): Add an argument for operands.
1347 Adjust the Broadcast value based on operands.
1348 (output_i386_opcode): Pass operand_types to
1349 process_i386_opcode_modifier.
1350 (process_i386_opcodes): Pass NULL as operands to
1351 process_i386_opcode_modifier.
1352 * i386-opc.h (BYTE_BROADCAST): New.
1353 (WORD_BROADCAST): Likewise.
1354 (DWORD_BROADCAST): Likewise.
1355 (QWORD_BROADCAST): Likewise.
1356 (i386_opcode_modifier): Expand broadcast to 3 bits.
1357 * i386-tbl.h: Regenerated.
1358
67ce483b
AM		 13592018-07-24 Alan Modra <amodra@gmail.com>
1360
1361 PR 23430
1362 * or1k-desc.h: Regenerate.
1363
4174bfff
JB		 13642018-07-24 Jan Beulich <jbeulich@suse.com>
1365
1366 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
1367 vcvtusi2ss, and vcvtusi2sd.
1368 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
1369 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
1370 * i386-tbl.h: Re-generate.
1371
04e65276
CZ		 13722018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
1373
1374 * arc-opc.c (extract_w6): Fix extending the sign.
1375
47e6f81c
CZ		 13762018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
1377
1378 * arc-tbl.h (vewt): Allow it for ARC EM family.
1379
bb71536f
AM		 13802018-07-23 Alan Modra <amodra@gmail.com>
1381
1382 PR 23419
1383 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
1384 opcode variants for mtspr/mfspr encodings.
1385
8095d2f7
CX		 13862018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
1387 Maciej W. Rozycki <macro@mips.com>
1388
1389 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
1390 loongson3a descriptors.
1391 (parse_mips_ase_option): Handle -M loongson-mmi option.
1392 (print_mips_disassembler_options): Document -M loongson-mmi.
1393 * mips-opc.c (LMMI): New macro.
1394 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
1395 instructions.
1396
5f32791e
JB		 13972018-07-19 Jan Beulich <jbeulich@suse.com>
1398
1399 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1400 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
1401 IgnoreSize and [XYZ]MMword where applicable.
1402 * i386-tbl.h: Re-generate.
1403
625cbd7a
JB		 14042018-07-19 Jan Beulich <jbeulich@suse.com>
1405
1406 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
1407 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
1408 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
1409 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
1410 * i386-tbl.h: Re-generate.
1411
86b15c32
JB		 14122018-07-19 Jan Beulich <jbeulich@suse.com>
1413
1414 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
1415 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
1416 VPCLMULQDQ templates into their respective AVX512VL counterparts
1417 where possible, using Disp8ShiftVL and CheckRegSize instead of
1418 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
1419 * i386-tbl.h: Re-generate.
1420
cf769ed5
JB		 14212018-07-19 Jan Beulich <jbeulich@suse.com>
1422
1423 * i386-opc.tbl: Fold AVX512DQ templates into their respective
1424 AVX512VL counterparts where possible, using Disp8ShiftVL and
1425 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1426 IgnoreSize) as appropriate.
1427 * i386-tbl.h: Re-generate.
1428
8282b7ad
JB		 14292018-07-19 Jan Beulich <jbeulich@suse.com>
1430
1431 * i386-opc.tbl: Fold AVX512BW templates into their respective
1432 AVX512VL counterparts where possible, using Disp8ShiftVL and
1433 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1434 IgnoreSize) as appropriate.
1435 * i386-tbl.h: Re-generate.
1436
755908cc
JB		 14372018-07-19 Jan Beulich <jbeulich@suse.com>
1438
1439 * i386-opc.tbl: Fold AVX512CD templates into their respective
1440 AVX512VL counterparts where possible, using Disp8ShiftVL and
1441 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1442 IgnoreSize) as appropriate.
1443 * i386-tbl.h: Re-generate.
1444
7091c612
JB		 14452018-07-19 Jan Beulich <jbeulich@suse.com>
1446
1447 * i386-opc.h (DISP8_SHIFT_VL): New.
1448 * i386-opc.tbl (Disp8ShiftVL): Define.
1449 (various): Fold AVX512VL templates into their respective
1450 AVX512F counterparts where possible, using Disp8ShiftVL and
1451 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1452 IgnoreSize) as appropriate.
1453 * i386-tbl.h: Re-generate.
1454
c30be56e
JB		 14552018-07-19 Jan Beulich <jbeulich@suse.com>
1456
1457 * Makefile.am: Change dependencies and rule for
1458 $(srcdir)/i386-init.h.
1459 * Makefile.in: Re-generate.
1460 * i386-gen.c (process_i386_opcodes): New local variable
1461 "marker". Drop opening of input file. Recognize marker and line
1462 number directives.
1463 * i386-opc.tbl (OPCODE_I386_H): Define.
1464 (i386-opc.h): Include it.
1465 (None): Undefine.
1466
11a322db
L		 14672018-07-18 H.J. Lu <hongjiu.lu@intel.com>
1468
1469 PR gas/23418
1470 * i386-opc.h (Byte): Update comments.
1471 (Word): Likewise.
1472 (Dword): Likewise.
1473 (Fword): Likewise.
1474 (Qword): Likewise.
1475 (Tbyte): Likewise.
1476 (Xmmword): Likewise.
1477 (Ymmword): Likewise.
1478 (Zmmword): Likewise.
1479 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1480 vcvttps2uqq.
1481 * i386-tbl.h: Regenerated.
1482
cde3679e
NC		 14832018-07-12 Sudakshina Das <sudi.das@arm.com>
1484
1485 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1486 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1487 * aarch64-asm-2.c: Regenerate.
1488 * aarch64-dis-2.c: Regenerate.
1489 * aarch64-opc-2.c: Regenerate.
1490
45a28947
TC		 14912018-07-12 Tamar Christina <tamar.christina@arm.com>
1492
1493 PR binutils/23192
1494 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1495 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1496 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1497 sqdmulh, sqrdmulh): Use Em16.
1498
c597cc3d
SD		 14992018-07-11 Sudakshina Das <sudi.das@arm.com>
1500
1501 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1502 csdb together with them.
1503 (thumb32_opcodes): Likewise.
1504
a79eaed6
JB		 15052018-07-11 Jan Beulich <jbeulich@suse.com>
1506
1507 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1508 requiring 32-bit registers as operands 2 and 3. Improve
1509 comments.
1510 (mwait, mwaitx): Fold templates. Improve comments.
1511 OPERAND_TYPE_INOUTPORTREG.
1512 * i386-tbl.h: Re-generate.
1513
2fb5be8d
JB		 15142018-07-11 Jan Beulich <jbeulich@suse.com>
1515
1516 * i386-gen.c (operand_type_init): Remove
1517 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1518 OPERAND_TYPE_INOUTPORTREG.
1519 * i386-init.h: Re-generate.
1520
7f5cad30
JB		 15212018-07-11 Jan Beulich <jbeulich@suse.com>
1522
1523 * i386-opc.tbl (wrssd, wrussd): Add Dword.
1524 (wrssq, wrussq): Add Qword.
1525 * i386-tbl.h: Re-generate.
1526
f0a85b07
JB		 15272018-07-11 Jan Beulich <jbeulich@suse.com>
1528
1529 * i386-opc.h: Rename OTMax to OTNum.
1530 (OTNumOfUints): Adjust calculation.
1531 (OTUnused): Directly alias to OTNum.
1532
9dcb0ba4
MR		 15332018-07-09 Maciej W. Rozycki <macro@mips.com>
1534
1535 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1536 `reg_xys'.
1537 (lea_reg_xys): Likewise.
1538 (print_insn_loop_primitive): Rename `reg' local variable to
1539 `reg_dxy'.
1540
f311ba7e
TC		 15412018-07-06 Tamar Christina <tamar.christina@arm.com>
1542
1543 PR binutils/23242
1544 * aarch64-tbl.h (ldarh): Fix disassembly mask.
1545
cba05feb
TC		 15462018-07-06 Tamar Christina <tamar.christina@arm.com>
1547
1548 PR binutils/23369
1549 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1550 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1551
471b9d15
MR		 15522018-07-02 Maciej W. Rozycki <macro@mips.com>
1553
1554 PR tdep/8282
1555 * mips-dis.c (mips_option_arg_t): New enumeration.
1556 (mips_options): New variable.
1557 (disassembler_options_mips): New function.
1558 (print_mips_disassembler_options): Reimplement in terms of
1559 `disassembler_options_mips'.
1560 * arm-dis.c (disassembler_options_arm): Adapt to using the
1561 `disasm_options_and_args_t' structure.
1562 * ppc-dis.c (disassembler_options_powerpc): Likewise.
1563 * s390-dis.c (disassembler_options_s390): Likewise.
1564
c0c468d5
TP		 15652018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
1566
1567 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1568 expected result.
1569 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1570 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1571 * testsuite/ld-arm/tls-longplt.d: Likewise.
1572
369c9167
TC		 15732018-06-29 Tamar Christina <tamar.christina@arm.com>
1574
1575 PR binutils/23192
1576 * aarch64-asm-2.c: Regenerate.
1577 * aarch64-dis-2.c: Likewise.
1578 * aarch64-opc-2.c: Likewise.
1579 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1580 * aarch64-opc.c (operand_general_constraint_met_p,
1581 aarch64_print_operand): Likewise.
1582 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1583 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1584 fmlal2, fmlsl2.
1585 (AARCH64_OPERANDS): Add Em2.
1586
30aa1306
NC		 15872018-06-26 Nick Clifton <nickc@redhat.com>
1588
1589 * po/uk.po: Updated Ukranian translation.
1590 * po/de.po: Updated German translation.
1591 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1592
eca4b721
NC		 15932018-06-26 Nick Clifton <nickc@redhat.com>
1594
1595 * nfp-dis.c: Fix spelling mistake.
1596
71300e2c
NC		 15972018-06-24 Nick Clifton <nickc@redhat.com>
1598
1599 * configure: Regenerate.
1600 * po/opcodes.pot: Regenerate.
1601
719d8288
NC		 16022018-06-24 Nick Clifton <nickc@redhat.com>
1603
1604 2.31 branch created.
1605
514cd3a0
TC		 16062018-06-19 Tamar Christina <tamar.christina@arm.com>
1607
1608 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1609 * aarch64-asm-2.c: Regenerate.
1610 * aarch64-dis-2.c: Likewise.
1611
385e4d0f
MR		 16122018-06-21 Maciej W. Rozycki <macro@mips.com>
1613
1614 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1615 `-M ginv' option description.
1616
160d1b3d
SH		 16172018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
1618
1619 PR gas/23305
1620 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1621 la and lla.
1622
d0ac1c44
SM		 16232018-06-19 Simon Marchi <simon.marchi@ericsson.com>
1624
1625 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1626 * configure.ac: Remove AC_PREREQ.
1627 * Makefile.in: Re-generate.
1628 * aclocal.m4: Re-generate.
1629 * configure: Re-generate.
1630
6f20c942
FS		 16312018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1632
1633 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1634 mips64r6 descriptors.
1635 (parse_mips_ase_option): Handle -Mginv option.
1636 (print_mips_disassembler_options): Document -Mginv.
1637 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1638 (GINV): New macro.
1639 (mips_opcodes): Define ginvi and ginvt.
1640
730c3174
SE		 16412018-06-13 Scott Egerton <scott.egerton@imgtec.com>
1642 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1643
1644 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1645 * mips-opc.c (CRC, CRC64): New macros.
1646 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1647 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
1648 crc32cd for CRC64.
1649
cb366992
EB		 16502018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
1651
1652 PR 20319
1653 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1654 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1655
ce72cd46
AM		 16562018-06-06 Alan Modra <amodra@gmail.com>
1657
1658 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1659 setjmp. Move init for some other vars later too.
1660
4b8e28c7
MF		 16612018-06-04 Max Filippov <jcmvbkbc@gmail.com>
1662
1663 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1664 (dis_private): Add new fields for property section tracking.
1665 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1666 (xtensa_instruction_fits): New functions.
1667 (fetch_data): Bump minimal fetch size to 4.
1668 (print_insn_xtensa): Make struct dis_private static.
1669 Load and prepare property table on section change.
1670 Don't disassemble literals. Don't disassemble instructions that
1671 cross property table boundaries.
1672
55e99962
L		 16732018-06-01 H.J. Lu <hongjiu.lu@intel.com>
1674
1675 * configure: Regenerated.
1676
733bd0ab
JB		 16772018-06-01 Jan Beulich <jbeulich@suse.com>
1678
1679 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1680 * i386-tbl.h: Re-generate.
1681
dfd27d41
JB		 16822018-06-01 Jan Beulich <jbeulich@suse.com>
1683
1684 * i386-opc.tbl (sldt, str): Add NoRex64.
1685 * i386-tbl.h: Re-generate.
1686
64795710
JB		 16872018-06-01 Jan Beulich <jbeulich@suse.com>
1688
1689 * i386-opc.tbl (invpcid): Add Oword.
1690 * i386-tbl.h: Re-generate.
1691
030157d8
AM		 16922018-06-01 Alan Modra <amodra@gmail.com>
1693
1694 * sysdep.h (_bfd_error_handler): Don't declare.
1695 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
1696 * rl78-decode.opc: Likewise.
1697 * msp430-decode.c: Regenerate.
1698 * rl78-decode.c: Regenerate.
1699
a9660a6f
AP		 17002018-05-30 Amit Pawar <Amit.Pawar@amd.com>
1701
1702 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1703 * i386-init.h : Regenerated.
1704
277eb7f6
AM		 17052018-05-25 Alan Modra <amodra@gmail.com>
1706
1707 * Makefile.in: Regenerate.
1708 * po/POTFILES.in: Regenerate.
1709
98553ad3
PB		 17102018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
1711
1712 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1713 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1714 (insert_bab, extract_bab, insert_btab, extract_btab,
1715 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1716 (BAT, BBA VBA RBS XB6S): Delete macros.
1717 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1718 (BB, BD, RBX, XC6): Update for new macros.
1719 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1720 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1721 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1722 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1723
7b4ae824
JD		 17242018-05-18 John Darrington <john@darrington.wattle.id.au>
1725
1726 * Makefile.am: Add support for s12z architecture.
1727 * configure.ac: Likewise.
1728 * disassemble.c: Likewise.
1729 * disassemble.h: Likewise.
1730 * Makefile.in: Regenerate.
1731 * configure: Regenerate.
1732 * s12z-dis.c: New file.
1733 * s12z.h: New file.
1734
29e0f0a1
AM		 17352018-05-18 Alan Modra <amodra@gmail.com>
1736
1737 * nfp-dis.c: Don't #include libbfd.h.
1738 (init_nfp3200_priv): Use bfd_get_section_contents.
1739 (nit_nfp6000_mecsr_sec): Likewise.
1740
809276d2
NC		 17412018-05-17 Nick Clifton <nickc@redhat.com>
1742
1743 * po/zh_CN.po: Updated simplified Chinese translation.
1744
ff329288
TC		 17452018-05-16 Tamar Christina <tamar.christina@arm.com>
1746
1747 PR binutils/23109
1748 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1749 * aarch64-dis-2.c: Regenerate.
1750
f9830ec1
TC		 17512018-05-15 Tamar Christina <tamar.christina@arm.com>
1752
1753 PR binutils/21446
1754 * aarch64-asm.c (opintl.h): Include.
1755 (aarch64_ins_sysreg): Enforce read/write constraints.
1756 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1757 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1758 (F_REG_READ, F_REG_WRITE): New.
1759 * aarch64-opc.c (aarch64_print_operand): Generate notes for
1760 AARCH64_OPND_SYSREG.
1761 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1762 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1763 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1764 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1765 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1766 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1767 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1768 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1769 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1770 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1771 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1772 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1773 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1774 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1775 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1776 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1777 msr (F_SYS_WRITE), mrs (F_SYS_READ).
1778
7d02540a
TC		 17792018-05-15 Tamar Christina <tamar.christina@arm.com>
1780
1781 PR binutils/21446
1782 * aarch64-dis.c (no_notes: New.
1783 (parse_aarch64_dis_option): Support notes.
1784 (aarch64_decode_insn, print_operands): Likewise.
1785 (print_aarch64_disassembler_options): Document notes.
1786 * aarch64-opc.c (aarch64_print_operand): Support notes.
1787
561a72d4
TC		 17882018-05-15 Tamar Christina <tamar.christina@arm.com>
1789
1790 PR binutils/21446
1791 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1792 and take error struct.
1793 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1794 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1795 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1796 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1797 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1798 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1799 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1800 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1801 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1802 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1803 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1804 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1805 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1806 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1807 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1808 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1809 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1810 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1811 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1812 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1813 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1814 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1815 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1816 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1817 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1818 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1819 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1820 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1821 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1822 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1823 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1824 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1825 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1826 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1827 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1828 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1829 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1830 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1831 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1832 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1833 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1834 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1835 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1836 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1837 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1838 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1839 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1840 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1841 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1842 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1843 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1844 (determine_disassembling_preference, aarch64_decode_insn,
1845 print_insn_aarch64_word, print_insn_data): Take errors struct.
1846 (print_insn_aarch64): Use errors.
1847 * aarch64-asm-2.c: Regenerate.
1848 * aarch64-dis-2.c: Regenerate.
1849 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1850 boolean in aarch64_insert_operan.
1851 (print_operand_extractor): Likewise.
1852 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1853
1678bd35
FT		 18542018-05-15 Francois H. Theron <francois.theron@netronome.com>
1855
1856 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1857
06cfb1c8
L		 18582018-05-09 H.J. Lu <hongjiu.lu@intel.com>
1859
1860 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1861
84f9f8c3
AM		 18622018-05-09 Sebastian Rasmussen <sebras@gmail.com>
1863
1864 * cr16-opc.c (cr16_instruction): Comment typo fix.
1865 * hppa-dis.c (print_insn_hppa): Likewise.
1866
e6f372ba
JW		 18672018-05-08 Jim Wilson <jimw@sifive.com>
1868
1869 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1870 (match_c_slli64, match_srxi_as_c_srxi): New.
1871 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1872 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1873 <c.slli, c.srli, c.srai>: Use match_s_slli.
1874 <c.slli64, c.srli64, c.srai64>: New.
1875
f413a913
AM		 18762018-05-08 Alan Modra <amodra@gmail.com>
1877
1878 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1879 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1880 partition opcode space for index lookup.
1881
a87a6478
PB		 18822018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1883
1884 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1885 <insn_length>: ...with this. Update usage.
1886 Remove duplicate call to *info->memory_error_func.
1887
c0a30a9f
L		 18882018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1889 H.J. Lu <hongjiu.lu@intel.com>
1890
1891 * i386-dis.c (Gva): New.
1892 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1893 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1894 (prefix_table): New instructions (see prefix above).
1895 (mod_table): New instructions (see prefix above).
1896 (OP_G): Handle va_mode.
1897 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1898 CPU_MOVDIR64B_FLAGS.
1899 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1900 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1901 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1902 * i386-opc.tbl: Add movidir{i,64b}.
1903 * i386-init.h: Regenerated.
1904 * i386-tbl.h: Likewise.
1905
75c0a438
L		 19062018-05-07 H.J. Lu <hongjiu.lu@intel.com>
1907
1908 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1909 AddrPrefixOpReg.
1910 * i386-opc.h (AddrPrefixOp0): Renamed to ...
1911 (AddrPrefixOpReg): This.
1912 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1913 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1914
2ceb7719
PB		 19152018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1916
1917 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1918 (vle_num_opcodes): Likewise.
1919 (spe2_num_opcodes): Likewise.
1920 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1921 initialization loop.
1922 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1923 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
1924 only once.
1925
b3ac5c6c
TC		 19262018-05-01 Tamar Christina <tamar.christina@arm.com>
1927
1928 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1929
fe944acf
FT		 19302018-04-30 Francois H. Theron <francois.theron@netronome.com>
1931
1932 Makefile.am: Added nfp-dis.c.
1933 configure.ac: Added bfd_nfp_arch.
1934 disassemble.h: Added print_insn_nfp prototype.
1935 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1936 nfp-dis.c: New, for NFP support.
1937 po/POTFILES.in: Added nfp-dis.c to the list.
1938 Makefile.in: Regenerate.
1939 configure: Regenerate.
1940
e2195274
JB		 19412018-04-26 Jan Beulich <jbeulich@suse.com>
1942
1943 * i386-opc.tbl: Fold various non-memory operand AVX512VL
1944 templates into their base ones.
1945 * i386-tlb.h: Re-generate.
1946
59ef5df4
JB		 19472018-04-26 Jan Beulich <jbeulich@suse.com>
1948
1949 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1950 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1951 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1952 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1953 * i386-init.h: Re-generate.
1954
6e041cf4
JB		 19552018-04-26 Jan Beulich <jbeulich@suse.com>
1956
1957 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1958 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1959 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1960 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1961 comment.
1962 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1963 and CpuRegMask.
1964 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1965 CpuRegMask: Delete.
1966 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1967 cpuregzmm, and cpuregmask.
1968 * i386-init.h: Re-generate.
1969 * i386-tbl.h: Re-generate.
1970
0e0eea78
JB		 19712018-04-26 Jan Beulich <jbeulich@suse.com>
1972
1973 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1974 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1975 * i386-init.h: Re-generate.
1976
2f1bada2
JB		 19772018-04-26 Jan Beulich <jbeulich@suse.com>
1978
1979 * i386-gen.c (VexImmExt): Delete.
1980 * i386-opc.h (VexImmExt, veximmext): Delete.
1981 * i386-opc.tbl: Drop all VexImmExt uses.
1982 * i386-tlb.h: Re-generate.
1983
bacd1457
JB		 19842018-04-25 Jan Beulich <jbeulich@suse.com>
1985
1986 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1987 register-only forms.
1988 * i386-tlb.h: Re-generate.
1989
10bba94b
TC		 19902018-04-25 Tamar Christina <tamar.christina@arm.com>
1991
1992 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1993
c48935d7
IT		 19942018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1995
1996 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1997 PREFIX_0F1C.
1998 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1999 (cpu_flags): Add CpuCLDEMOTE.
2000 * i386-init.h: Regenerate.
2001 * i386-opc.h (enum): Add CpuCLDEMOTE,
2002 (i386_cpu_flags): Add cpucldemote.
2003 * i386-opc.tbl: Add cldemote.
2004 * i386-tbl.h: Regenerate.
2005
211dc24b
AM		 20062018-04-16 Alan Modra <amodra@gmail.com>
2007
2008 * Makefile.am: Remove sh5 and sh64 support.
2009 * configure.ac: Likewise.
2010 * disassemble.c: Likewise.
2011 * disassemble.h: Likewise.
2012 * sh-dis.c: Likewise.
2013 * sh64-dis.c: Delete.
2014 * sh64-opc.c: Delete.
2015 * sh64-opc.h: Delete.
2016 * Makefile.in: Regenerate.
2017 * configure: Regenerate.
2018 * po/POTFILES.in: Regenerate.
2019
a9a4b302
AM		 20202018-04-16 Alan Modra <amodra@gmail.com>
2021
2022 * Makefile.am: Remove w65 support.
2023 * configure.ac: Likewise.
2024 * disassemble.c: Likewise.
2025 * disassemble.h: Likewise.
2026 * w65-dis.c: Delete.
2027 * w65-opc.h: Delete.
2028 * Makefile.in: Regenerate.
2029 * configure: Regenerate.
2030 * po/POTFILES.in: Regenerate.
2031
04cb01fd
AM		 20322018-04-16 Alan Modra <amodra@gmail.com>
2033
2034 * configure.ac: Remove we32k support.
2035 * configure: Regenerate.
2036
c2bf1eec
AM		 20372018-04-16 Alan Modra <amodra@gmail.com>
2038
2039 * Makefile.am: Remove m88k support.
2040 * configure.ac: Likewise.
2041 * disassemble.c: Likewise.
2042 * disassemble.h: Likewise.
2043 * m88k-dis.c: Delete.
2044 * Makefile.in: Regenerate.
2045 * configure: Regenerate.
2046 * po/POTFILES.in: Regenerate.
2047
6793974d
AM		 20482018-04-16 Alan Modra <amodra@gmail.com>
2049
2050 * Makefile.am: Remove i370 support.
2051 * configure.ac: Likewise.
2052 * disassemble.c: Likewise.
2053 * disassemble.h: Likewise.
2054 * i370-dis.c: Delete.
2055 * i370-opc.c: Delete.
2056 * Makefile.in: Regenerate.
2057 * configure: Regenerate.
2058 * po/POTFILES.in: Regenerate.
2059
e82aa794
AM		 20602018-04-16 Alan Modra <amodra@gmail.com>
2061
2062 * Makefile.am: Remove h8500 support.
2063 * configure.ac: Likewise.
2064 * disassemble.c: Likewise.
2065 * disassemble.h: Likewise.
2066 * h8500-dis.c: Delete.
2067 * h8500-opc.h: Delete.
2068 * Makefile.in: Regenerate.
2069 * configure: Regenerate.
2070 * po/POTFILES.in: Regenerate.
2071
fceadf09
AM		 20722018-04-16 Alan Modra <amodra@gmail.com>
2073
2074 * configure.ac: Remove tahoe support.
2075 * configure: Regenerate.
2076
ae1d3843
L		 20772018-04-15 H.J. Lu <hongjiu.lu@intel.com>
2078
2079 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
2080 umwait.
2081 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
2082 64-bit mode.
2083 * i386-tbl.h: Regenerated.
2084
de89d0a3
IT		 20852018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2086
2087 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
2088 PREFIX_MOD_1_0FAE_REG_6.
2089 (va_mode): New.
2090 (OP_E_register): Use va_mode.
2091 * i386-dis-evex.h (prefix_table):
2092 New instructions (see prefixes above).
2093 * i386-gen.c (cpu_flag_init): Add WAITPKG.
2094 (cpu_flags): Likewise.
2095 * i386-opc.h (enum): Likewise.
2096 (i386_cpu_flags): Likewise.
2097 * i386-opc.tbl: Add umonitor, umwait, tpause.
2098 * i386-init.h: Regenerate.
2099 * i386-tbl.h: Likewise.
2100
a8eb42a8
AM		 21012018-04-11 Alan Modra <amodra@gmail.com>
2102
2103 * opcodes/i860-dis.c: Delete.
2104 * opcodes/i960-dis.c: Delete.
2105 * Makefile.am: Remove i860 and i960 support.
2106 * configure.ac: Likewise.
2107 * disassemble.c: Likewise.
2108 * disassemble.h: Likewise.
2109 * Makefile.in: Regenerate.
2110 * configure: Regenerate.
2111 * po/POTFILES.in: Regenerate.
2112
caf0678c
L		 21132018-04-04 H.J. Lu <hongjiu.lu@intel.com>
2114
2115 PR binutils/23025
2116 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
2117 to 0.
2118 (print_insn): Clear vex instead of vex.evex.
2119
4fb0d2b9
NC		 21202018-04-04 Nick Clifton <nickc@redhat.com>
2121
2122 * po/es.po: Updated Spanish translation.
2123
c39e5b26
JB		 21242018-03-28 Jan Beulich <jbeulich@suse.com>
2125
2126 * i386-gen.c (opcode_modifiers): Delete VecESize.
2127 * i386-opc.h (VecESize): Delete.
2128 (struct i386_opcode_modifier): Delete vecesize.
2129 * i386-opc.tbl: Drop VecESize.
2130 * i386-tlb.h: Re-generate.
2131
8e6e0792
JB		 21322018-03-28 Jan Beulich <jbeulich@suse.com>
2133
2134 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
2135 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
2136 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
2137 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
2138 * i386-tlb.h: Re-generate.
2139
9f123b91
JB		 21402018-03-28 Jan Beulich <jbeulich@suse.com>
2141
2142 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
2143 Fold AVX512 forms
2144 * i386-tlb.h: Re-generate.
2145
9646c87b
JB		 21462018-03-28 Jan Beulich <jbeulich@suse.com>
2147
2148 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
2149 (vex_len_table): Drop Y for vcvt*2si.
2150 (putop): Replace plain 'Y' handling by abort().
2151
c8d59609
NC		 21522018-03-28 Nick Clifton <nickc@redhat.com>
2153
2154 PR 22988
2155 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
2156 instructions with only a base address register.
2157 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
2158 handle AARHC64_OPND_SVE_ADDR_R.
2159 (aarch64_print_operand): Likewise.
2160 * aarch64-asm-2.c: Regenerate.
2161 * aarch64_dis-2.c: Regenerate.
2162 * aarch64-opc-2.c: Regenerate.
2163
b8c169f3
JB		 21642018-03-22 Jan Beulich <jbeulich@suse.com>
2165
2166 * i386-opc.tbl: Drop VecESize from register only insn forms and
2167 memory forms not allowing broadcast.
2168 * i386-tlb.h: Re-generate.
2169
96bc132a
JB		 21702018-03-22 Jan Beulich <jbeulich@suse.com>
2171
2172 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
2173 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
2174 sha256*): Drop Disp<N>.
2175
9f79e886
JB		 21762018-03-22 Jan Beulich <jbeulich@suse.com>
2177
2178 * i386-dis.c (EbndS, bnd_swap_mode): New.
2179 (prefix_table): Use EbndS.
2180 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
2181 * i386-opc.tbl (bndmov): Move misplaced Load.
2182 * i386-tlb.h: Re-generate.
2183
d6793fa1
JB		 21842018-03-22 Jan Beulich <jbeulich@suse.com>
2185
2186 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
2187 templates allowing memory operands and folded ones for register
2188 only flavors.
2189 * i386-tlb.h: Re-generate.
2190
f7768225
JB		 21912018-03-22 Jan Beulich <jbeulich@suse.com>
2192
2193 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
2194 256-bit templates. Drop redundant leftover Disp<N>.
2195 * i386-tlb.h: Re-generate.
2196
0e35537d
JW		 21972018-03-14 Kito Cheng <kito.cheng@gmail.com>
2198
2199 * riscv-opc.c (riscv_insn_types): New.
2200
b4a3689a
NC		 22012018-03-13 Nick Clifton <nickc@redhat.com>
2202
2203 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2204
d3d50934
L		 22052018-03-08 H.J. Lu <hongjiu.lu@intel.com>
2206
2207 * i386-opc.tbl: Add Optimize to clr.
2208 * i386-tbl.h: Regenerated.
2209
bd5dea88
L		 22102018-03-08 H.J. Lu <hongjiu.lu@intel.com>
2211
2212 * i386-gen.c (opcode_modifiers): Remove OldGcc.
2213 * i386-opc.h (OldGcc): Removed.
2214 (i386_opcode_modifier): Remove oldgcc.
2215 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
2216 instructions for old (<= 2.8.1) versions of gcc.
2217 * i386-tbl.h: Regenerated.
2218
e771e7c9
JB		 22192018-03-08 Jan Beulich <jbeulich@suse.com>
2220
2221 * i386-opc.h (EVEXDYN): New.
2222 * i386-opc.tbl: Fold various AVX512VL templates.
2223 * i386-tlb.h: Re-generate.
2224
ed438a93
JB		 22252018-03-08 Jan Beulich <jbeulich@suse.com>
2226
2227 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2228 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2229 vpexpandd, vpexpandq): Fold AFX512VF templates.
2230 * i386-tlb.h: Re-generate.
2231
454172a9
JB		 22322018-03-08 Jan Beulich <jbeulich@suse.com>
2233
2234 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
2235 Fold 128- and 256-bit VEX-encoded templates.
2236 * i386-tlb.h: Re-generate.
2237
36824150
JB		 22382018-03-08 Jan Beulich <jbeulich@suse.com>
2239
2240 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2241 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2242 vpexpandd, vpexpandq): Fold AVX512F templates.
2243 * i386-tlb.h: Re-generate.
2244
e7f5c0a9
JB		 22452018-03-08 Jan Beulich <jbeulich@suse.com>
2246
2247 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
2248 64-bit templates. Drop Disp<N>.
2249 * i386-tlb.h: Re-generate.
2250
25a4277f
JB		 22512018-03-08 Jan Beulich <jbeulich@suse.com>
2252
2253 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
2254 and 256-bit templates.
2255 * i386-tlb.h: Re-generate.
2256
d2224064
JB		 22572018-03-08 Jan Beulich <jbeulich@suse.com>
2258
2259 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
2260 * i386-tlb.h: Re-generate.
2261
1b193f0b
JB		 22622018-03-08 Jan Beulich <jbeulich@suse.com>
2263
2264 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
2265 Drop NoAVX.
2266 * i386-tlb.h: Re-generate.
2267
f2f6a710
JB		 22682018-03-08 Jan Beulich <jbeulich@suse.com>
2269
2270 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
2271 * i386-tlb.h: Re-generate.
2272
38e314eb
JB		 22732018-03-08 Jan Beulich <jbeulich@suse.com>
2274
2275 * i386-gen.c (opcode_modifiers): Delete FloatD.
2276 * i386-opc.h (FloatD): Delete.
2277 (struct i386_opcode_modifier): Delete floatd.
2278 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
2279 FloatD by D.
2280 * i386-tlb.h: Re-generate.
2281
d53e6b98
JB		 22822018-03-08 Jan Beulich <jbeulich@suse.com>
2283
2284 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
2285
2907c2f5
JB		 22862018-03-08 Jan Beulich <jbeulich@suse.com>
2287
2288 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
2289 * i386-tlb.h: Re-generate.
2290
73053c1f
JB		 22912018-03-08 Jan Beulich <jbeulich@suse.com>
2292
2293 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
2294 forms.
2295 * i386-tlb.h: Re-generate.
2296
52fe4420
AM		 22972018-03-07 Alan Modra <amodra@gmail.com>
2298
2299 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
2300 bfd_arch_rs6000.
2301 * disassemble.h (print_insn_rs6000): Delete.
2302 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
2303 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
2304 (print_insn_rs6000): Delete.
2305
a6743a54
AM		 23062018-03-03 Alan Modra <amodra@gmail.com>
2307
2308 * sysdep.h (opcodes_error_handler): Define.
2309 (_bfd_error_handler): Declare.
2310 * Makefile.am: Remove stray #.
2311 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
2312 EDIT" comment.
2313 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
2314 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
2315 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
2316 opcodes_error_handler to print errors. Standardize error messages.
2317 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
2318 and include opintl.h.
2319 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
2320 * i386-gen.c: Standardize error messages.
2321 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
2322 * Makefile.in: Regenerate.
2323 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
2324 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
2325 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
2326 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
2327 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
2328 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
2329 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
2330 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
2331 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
2332 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
2333 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
2334 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
2335 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2336
8305403a
L		 23372018-03-01 H.J. Lu <hongjiu.lu@intel.com>
2338
2339 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
2340 vpsub[bwdq] instructions.
2341 * i386-tbl.h: Regenerated.
2342
e184813f
AM		 23432018-03-01 Alan Modra <amodra@gmail.com>
2344
2345 * configure.ac (ALL_LINGUAS): Sort.
2346 * configure: Regenerate.
2347
5b616bef
TP		 23482018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
2349
2350 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
2351 macro by assignements.
2352
b6f8c7c4
L		 23532018-02-27 H.J. Lu <hongjiu.lu@intel.com>
2354
2355 PR gas/22871
2356 * i386-gen.c (opcode_modifiers): Add Optimize.
2357 * i386-opc.h (Optimize): New enum.
2358 (i386_opcode_modifier): Add optimize.
2359 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
2360 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
2361 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
2362 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
2363 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
2364 vpxord and vpxorq.
2365 * i386-tbl.h: Regenerated.
2366
e95b887f
AM		 23672018-02-26 Alan Modra <amodra@gmail.com>
2368
2369 * crx-dis.c (getregliststring): Allocate a large enough buffer
2370 to silence false positive gcc8 warning.
2371
0bccfb29
JW		 23722018-02-22 Shea Levy <shea@shealevy.com>
2373
2374 * disassemble.c (ARCH_riscv): Define if ARCH_all.
2375
6b6b6807
L		 23762018-02-22 H.J. Lu <hongjiu.lu@intel.com>
2377
2378 * i386-opc.tbl: Add {rex},
2379 * i386-tbl.h: Regenerated.
2380
75f31665
MR		 23812018-02-20 Maciej W. Rozycki <macro@mips.com>
2382
2383 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
2384 (mips16_opcodes): Replace `M' with `m' for "restore".
2385
e207bc53
TP		 23862018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
2387
2388 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
2389
87993319
MR		 23902018-02-13 Maciej W. Rozycki <macro@mips.com>
2391
2392 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
2393 variable to `function_index'.
2394
68d20676
NC		 23952018-02-13 Nick Clifton <nickc@redhat.com>
2396
2397 PR 22823
2398 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
2399 about truncation of printing.
2400
d2159fdc
HW		 24012018-02-12 Henry Wong <henry@stuffedcow.net>
2402
2403 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
2404
f174ef9f
NC		 24052018-02-05 Nick Clifton <nickc@redhat.com>
2406
2407 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2408
be3a8dca
IT		 24092018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2410
2411 * i386-dis.c (enum): Add pconfig.
2412 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
2413 (cpu_flags): Add CpuPCONFIG.
2414 * i386-opc.h (enum): Add CpuPCONFIG.
2415 (i386_cpu_flags): Add cpupconfig.
2416 * i386-opc.tbl: Add PCONFIG instruction.
2417 * i386-init.h: Regenerate.
2418 * i386-tbl.h: Likewise.
2419
3233d7d0
IT		 24202018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2421
2422 * i386-dis.c (enum): Add PREFIX_0F09.
2423 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
2424 (cpu_flags): Add CpuWBNOINVD.
2425 * i386-opc.h (enum): Add CpuWBNOINVD.
2426 (i386_cpu_flags): Add cpuwbnoinvd.
2427 * i386-opc.tbl: Add WBNOINVD instruction.
2428 * i386-init.h: Regenerate.
2429 * i386-tbl.h: Likewise.
2430
e925c834
JW		 24312018-01-17 Jim Wilson <jimw@sifive.com>
2432
2433 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2434
d777820b
IT		 24352018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2436
2437 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2438 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2439 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2440 (cpu_flags): Add CpuIBT, CpuSHSTK.
2441 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2442 (i386_cpu_flags): Add cpuibt, cpushstk.
2443 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2444 * i386-init.h: Regenerate.
2445 * i386-tbl.h: Likewise.
2446
f6efed01
NC		 24472018-01-16 Nick Clifton <nickc@redhat.com>
2448
2449 * po/pt_BR.po: Updated Brazilian Portugese translation.
2450 * po/de.po: Updated German translation.
2451
2721d702
JW		 24522018-01-15 Jim Wilson <jimw@sifive.com>
2453
2454 * riscv-opc.c (match_c_nop): New.
2455 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2456
616dcb87
NC		 24572018-01-15 Nick Clifton <nickc@redhat.com>
2458
2459 * po/uk.po: Updated Ukranian translation.
2460
3957a496
NC		 24612018-01-13 Nick Clifton <nickc@redhat.com>
2462
2463 * po/opcodes.pot: Regenerated.
2464
769c7ea5
NC		 24652018-01-13 Nick Clifton <nickc@redhat.com>
2466
2467 * configure: Regenerate.
2468
faf766e3
NC		 24692018-01-13 Nick Clifton <nickc@redhat.com>
2470
2471 2.30 branch created.
2472
888a89da
IT		 24732018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2474
2475 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2476 * i386-tbl.h: Regenerate.
2477
cbda583a
JB		 24782018-01-10 Jan Beulich <jbeulich@suse.com>
2479
2480 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2481 * i386-tbl.h: Re-generate.
2482
c9e92278
JB		 24832018-01-10 Jan Beulich <jbeulich@suse.com>
2484
2485 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2486 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2487 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2488 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2489 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2490 Disp8MemShift of AVX512VL forms.
2491 * i386-tbl.h: Re-generate.
2492
35fd2b2b
JW		 24932018-01-09 Jim Wilson <jimw@sifive.com>
2494
2495 * riscv-dis.c (maybe_print_address): If base_reg is zero,
2496 then the hi_addr value is zero.
2497
91d8b670
JG		 24982018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2499
2500 * arm-dis.c (arm_opcodes): Add csdb.
2501 (thumb32_opcodes): Add csdb.
2502
be2e7d95
JG		 25032018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2504
2505 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2506 * aarch64-asm-2.c: Regenerate.
2507 * aarch64-dis-2.c: Regenerate.
2508 * aarch64-opc-2.c: Regenerate.
2509
704a705d
L		 25102018-01-08 H.J. Lu <hongjiu.lu@intel.com>
2511
2512 PR gas/22681
2513 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2514 Remove AVX512 vmovd with 64-bit operands.
2515 * i386-tbl.h: Regenerated.
2516
35eeb78f
JW		 25172018-01-05 Jim Wilson <jimw@sifive.com>
2518
2519 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2520 jalr.
2521
219d1afa
AM		 25222018-01-03 Alan Modra <amodra@gmail.com>
2523
2524 Update year range in copyright notice of all files.
2525
1508bbf5
JB		 25262018-01-02 Jan Beulich <jbeulich@suse.com>
2527
2528 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2529 and OPERAND_TYPE_REGZMM entries.
2530
1e563868 2531For older changes see ChangeLog-2017
3499769a 2532\f
1e563868 2533Copyright (C) 2018 Free Software Foundation, Inc.
3499769a
AM		 2534
2535Copying and distribution of this file, with or without modification,
2536are permitted in any medium without royalty provided the copyright
2537notice and this notice are preserved.
2538
2539Local Variables:
2540mode: change-log
2541left-margin: 8
2542fill-column: 74
2543version-control: never
2544End:
GDB Binutils - Deliverables
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