Commit | Line | Data |
---|---|---|
f04265ec NC |
1 | 2015-09-22 Nick Clifton <nickc@redhat.com> |
2 | ||
3 | * rx-decode.opc (bwl): Use RX_Bad_Size. | |
4 | (sbwl): Likewise. | |
5 | (ubwl): Likewise. Rename to ubw. | |
6 | (uBWL): Rename to uBW. | |
7 | Replace all references to uBWL with uBW. | |
8 | * rx-decode.c: Regenerate. | |
9 | * rx-dis.c (size_names): Add entry for RX_Bad_Size. | |
10 | (opsize_names): Likewise. | |
11 | (print_insn_rx): Detect and report RX_Bad_Size. | |
12 | ||
6dca4fd1 AB |
13 | 2015-09-22 Anton Blanchard <anton@samba.org> |
14 | ||
15 | * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl. | |
16 | ||
38074311 JM |
17 | 2015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com> |
18 | ||
19 | * sparc-dis.c (print_insn_sparc): Handle the privileged register | |
20 | %pmcdper. | |
21 | ||
5f40e14d JS |
22 | 2015-08-24 Jan Stancek <jstancek@redhat.com> |
23 | ||
24 | * i386-dis.c (print_insn): Fix decoding of three byte operands. | |
25 | ||
ab4e4ed5 AF |
26 | 2015-08-21 Alexander Fomin <alexander.fomin@intel.com> |
27 | ||
28 | PR binutils/18257 | |
29 | * i386-dis.c: Use MOD_TABLE for most of mask instructions. | |
30 | (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1, | |
31 | MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1, | |
32 | MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1, | |
33 | MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1, | |
34 | MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1, | |
35 | MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1, | |
36 | MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1, | |
37 | MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1, | |
38 | MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1, | |
39 | MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1, | |
40 | MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1, | |
41 | MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1, | |
42 | MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1, | |
43 | MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1, | |
44 | MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1, | |
45 | MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1, | |
46 | MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0, | |
47 | MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0, | |
48 | MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0, | |
49 | MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0, | |
50 | MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0, | |
51 | MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0, | |
52 | MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0, | |
53 | MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0, | |
54 | MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0, | |
55 | MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0, | |
56 | MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0, | |
57 | MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0, | |
58 | MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0, | |
59 | MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0. | |
60 | (vex_w_table): Replace terminals with MOD_TABLE entries for | |
61 | most of mask instructions. | |
62 | ||
919b75f7 AM |
63 | 2015-08-17 Alan Modra <amodra@gmail.com> |
64 | ||
65 | * cgen.sh: Trim trailing space from cgen output. | |
66 | * ia64-gen.c (print_dependency_table): Don't generate trailing space. | |
67 | (print_dis_table): Likewise. | |
68 | * opc2c.c (dump_lines): Likewise. | |
69 | (orig_filename): Warning fix. | |
70 | * ia64-asmtab.c: Regenerate. | |
71 | ||
4ab90a7a AV |
72 | 2015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com> |
73 | ||
74 | * arm-dis.c (print_insn_arm): Disassembling for all targets V6 | |
75 | and higher with ARM instruction set will now mark the 26-bit | |
76 | versions of teq,tst,cmn and cmp as UNPREDICTABLE. | |
77 | (arm_opcodes): Fix for unpredictable nop being recognized as a | |
78 | teq. | |
79 | ||
40fc1451 SD |
80 | 2015-08-12 Simon Dardis <simon.dardis@imgtec.com> |
81 | ||
82 | * micromips-opc.c (micromips_opcodes): Re-order table so that move | |
83 | based on 'or' is first. | |
84 | * mips-opc.c (mips_builtin_opcodes): Ditto. | |
85 | ||
922c5db5 NC |
86 | 2015-08-11 Nick Clifton <nickc@redhat.com> |
87 | ||
88 | PR 18800 | |
89 | * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT | |
90 | instruction. | |
91 | ||
75fb7498 RS |
92 | 2015-08-10 Robert Suchanek <robert.suchanek@imgtec.com> |
93 | ||
94 | * mips-opc.c (mips_builtin_opcodes): Add "sigrie". | |
95 | ||
36aed29d AP |
96 | 2015-08-07 Amit Pawar <Amit.Pawar@amd.com> |
97 | ||
98 | * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS. | |
99 | * i386-init.h: Regenerated. | |
100 | ||
a8484f96 L |
101 | 2015-07-30 H.J. Lu <hongjiu.lu@intel.com> |
102 | ||
103 | PR binutils/13571 | |
104 | * i386-dis.c (MOD_0FC3): New. | |
105 | (PREFIX_0FC3): Renamed to ... | |
106 | (PREFIX_MOD_0_0FC3): This. | |
107 | (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3. | |
108 | (prefix_table): Replace Ma with Ev on movntiS. | |
109 | (mod_table): Add MOD_0FC3. | |
110 | ||
37a42ee9 L |
111 | 2015-07-27 H.J. Lu <hongjiu.lu@intel.com> |
112 | ||
113 | * configure: Regenerated. | |
114 | ||
070fe95d AM |
115 | 2015-07-23 Alan Modra <amodra@gmail.com> |
116 | ||
117 | PR 18708 | |
118 | * i386-dis.c (get64): Avoid signed integer overflow. | |
119 | ||
20c2a615 L |
120 | 2015-07-22 Alexander Fomin <alexander.fomin@intel.com> |
121 | ||
122 | PR binutils/18631 | |
123 | * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with | |
124 | "EXEvexHalfBcstXmmq" for the second operand. | |
125 | (EVEX_W_0F79_P_2): Likewise. | |
126 | (EVEX_W_0F7A_P_2): Likewise. | |
127 | (EVEX_W_0F7B_P_2): Likewise. | |
128 | ||
6f1c2142 AM |
129 | 2015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com> |
130 | ||
131 | * arm-dis.c (print_insn_coprocessor): Added support for quarter | |
132 | float bitfield format. | |
133 | (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new | |
134 | quarter float bitfield format. | |
135 | ||
8a643cc3 L |
136 | 2015-07-14 H.J. Lu <hongjiu.lu@intel.com> |
137 | ||
138 | * configure: Regenerated. | |
139 | ||
ef5a96d5 AM |
140 | 2015-07-03 Alan Modra <amodra@gmail.com> |
141 | ||
142 | * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*. | |
143 | * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add | |
144 | PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry. | |
145 | ||
c8c8175b SL |
146 | 2015-07-01 Sandra Loosemore <sandra@codesourcery.com> |
147 | Cesar Philippidis <cesar@codesourcery.com> | |
148 | ||
149 | * nios2-dis.c (nios2_extract_opcode): New. | |
150 | (nios2_disassembler_state): New. | |
151 | (nios2_find_opcode_hash): Use mach parameter to select correct | |
152 | disassembler state. | |
153 | (nios2_print_insn_arg): Extend to support new R2 argument letters | |
154 | and formats. | |
155 | (print_insn_nios2): Check for 16-bit instruction at end of memory. | |
156 | * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes. | |
157 | (NIOS2_NUM_OPCODES): Rename to... | |
158 | (NIOS2_NUM_R1_OPCODES): This. | |
159 | (nios2_r2_opcodes): New. | |
160 | (NIOS2_NUM_R2_OPCODES): New. | |
161 | (nios2_num_r2_opcodes): New. | |
162 | (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New. | |
163 | (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New. | |
164 | (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New. | |
165 | (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New. | |
166 | (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New. | |
167 | ||
9916071f AP |
168 | 2015-06-30 Amit Pawar <Amit.Pawar@amd.com> |
169 | ||
170 | * i386-dis.c (OP_Mwaitx): New. | |
171 | (rm_table): Add monitorx/mwaitx. | |
172 | * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS | |
173 | and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS. | |
174 | (operand_type_init): Add CpuMWAITX. | |
175 | * i386-opc.h (CpuMWAITX): New. | |
176 | (i386_cpu_flags): Add cpumwaitx. | |
177 | * i386-opc.tbl: Add monitorx and mwaitx. | |
178 | * i386-init.h: Regenerated. | |
179 | * i386-tbl.h: Likewise. | |
180 | ||
7b934113 PB |
181 | 2015-06-22 Peter Bergner <bergner@vnet.ibm.com> |
182 | ||
183 | * ppc-opc.c (insert_ls): Test for invalid LS operands. | |
184 | (insert_esync): New function. | |
185 | (LS, WC): Use insert_ls. | |
186 | (ESYNC): Use insert_esync. | |
187 | ||
bdc4de1b NC |
188 | 2015-06-22 Nick Clifton <nickc@redhat.com> |
189 | ||
190 | * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the | |
191 | requested region lies beyond it. | |
192 | * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when | |
193 | looking for 32-bit insns. | |
194 | * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading | |
195 | data. | |
196 | * sh-dis.c (print_insn_sh): Likewise. | |
197 | * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading | |
198 | blocks of instructions. | |
199 | * vax-dis.c (print_insn_vax): Check that the requested address | |
200 | does not clash with the stop_vma. | |
201 | ||
11a0cf2e PB |
202 | 2015-06-19 Peter Bergner <bergner@vnet.ibm.com> |
203 | ||
070fe95d | 204 | * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value. |
11a0cf2e PB |
205 | * ppc-opc.c (FXM4): Add non-zero optional value. |
206 | (TBR): Likewise. | |
207 | (SXL): Likewise. | |
208 | (insert_fxm): Handle new default operand value. | |
209 | (extract_fxm): Likewise. | |
210 | (insert_tbr): Likewise. | |
211 | (extract_tbr): Likewise. | |
212 | ||
bdfa8b95 MW |
213 | 2015-06-16 Matthew Wahab <matthew.wahab@arm.com> |
214 | ||
215 | * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1". | |
216 | ||
24b4cf66 SN |
217 | 2015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com> |
218 | ||
219 | * arm-dis.c (print_insn_coprocessor): Avoid negative shift. | |
220 | ||
99a2c561 PB |
221 | 2015-06-12 Peter Bergner <bergner@vnet.ibm.com> |
222 | ||
223 | * ppc-opc.c: Add comment accidentally removed by old commit. | |
224 | (MTMSRD_L): Delete. | |
225 | ||
40f77f82 AM |
226 | 2015-06-04 Peter Bergner <bergner@vnet.ibm.com> |
227 | ||
228 | * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic. | |
229 | ||
13be46a2 NC |
230 | 2015-06-04 Nick Clifton <nickc@redhat.com> |
231 | ||
232 | PR 18474 | |
233 | * msp430-dis.c (msp430_nooperands): Fix check for emulated insns. | |
234 | ||
ddfded2f MW |
235 | 2015-06-02 Matthew Wahab <matthew.wahab@arm.com> |
236 | ||
237 | * arm-dis.c (arm_opcodes): Add "setpan". | |
238 | (thumb_opcodes): Add "setpan". | |
239 | ||
1af1dd51 MW |
240 | 2015-06-02 Matthew Wahab <matthew.wahab@arm.com> |
241 | ||
242 | * arm-dis.c (select_arm_features): Rework to avoid used of redefined | |
243 | macros. | |
244 | ||
9e1f0fa7 MW |
245 | 2015-06-02 Matthew Wahab <matthew.wahab@arm.com> |
246 | ||
247 | * aarch64-tbl.h (aarch64_feature_rdma): New. | |
248 | (RDMA): New. | |
249 | (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions. | |
250 | * aarch64-asm-2.c: Regenerate. | |
251 | * aarch64-dis-2.c: Regenerate. | |
252 | * aarch64-opc-2.c: Regenerate. | |
253 | ||
290806fd MW |
254 | 2015-06-02 Matthew Wahab <matthew.wahab@arm.com> |
255 | ||
256 | * aarch64-tbl.h (aarch64_feature_lor): New. | |
257 | (LOR): New. | |
258 | (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr", | |
259 | "stllrb", "stllrh". | |
260 | * aarch64-asm-2.c: Regenerate. | |
261 | * aarch64-dis-2.c: Regenerate. | |
262 | * aarch64-opc-2.c: Regenerate. | |
263 | ||
f21cce2c MW |
264 | 2015-06-01 Matthew Wahab <matthew.wahab@arm.com> |
265 | ||
266 | * aarch64-opc.c (F_ARCHEXT): New. | |
267 | (aarch64_sys_regs): Add "pan". | |
268 | (aarch64_sys_reg_supported_p): New. | |
269 | (aarch64_pstatefields): Add "pan". | |
270 | (aarch64_pstatefield_supported_p): New. | |
271 | ||
d194d186 JB |
272 | 2015-06-01 Jan Beulich <jbeulich@suse.com> |
273 | ||
274 | * i386-tbl.h: Regenerate. | |
275 | ||
3a8547d2 JB |
276 | 2015-06-01 Jan Beulich <jbeulich@suse.com> |
277 | ||
278 | * i386-dis.c (print_insn): Swap rounding mode specifier and | |
279 | general purpose register in Intel mode. | |
280 | ||
015c54d5 JB |
281 | 2015-06-01 Jan Beulich <jbeulich@suse.com> |
282 | ||
283 | * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}. | |
284 | * i386-tbl.h: Regenerate. | |
285 | ||
071f0063 L |
286 | 2015-05-18 H.J. Lu <hongjiu.lu@intel.com> |
287 | ||
288 | * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp. | |
289 | * i386-init.h: Regenerated. | |
290 | ||
5db04b09 L |
291 | 2015-05-15 H.J. Lu <hongjiu.lu@intel.com> |
292 | ||
293 | PR binutis/18386 | |
294 | * i386-dis.c: Add comments for '@'. | |
295 | (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9. | |
296 | (enum x86_64_isa): New. | |
297 | (isa64): Likewise. | |
298 | (print_i386_disassembler_options): Add amd64 and intel64. | |
299 | (print_insn): Handle amd64 and intel64. | |
300 | (putop): Handle '@'. | |
301 | (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit. | |
302 | * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64. | |
303 | * i386-opc.h (AMD64): New. | |
304 | (CpuIntel64): Likewise. | |
305 | (i386_cpu_flags): Add cpuamd64 and cpuintel64. | |
306 | * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64. | |
307 | Mark direct call/jmp without Disp16|Disp32 as Intel64. | |
308 | * i386-init.h: Regenerated. | |
309 | * i386-tbl.h: Likewise. | |
310 | ||
4bc0608a PB |
311 | 2015-05-14 Peter Bergner <bergner@vnet.ibm.com> |
312 | ||
313 | * ppc-opc.c (IH) New define. | |
314 | (powerpc_opcodes) <wait>: Do not enable for POWER7. | |
315 | <tlbie>: Add RS operand for POWER7. | |
316 | <slbia>: Add IH operand for POWER6. | |
317 | ||
70cead07 L |
318 | 2015-05-11 H.J. Lu <hongjiu.lu@intel.com> |
319 | ||
320 | * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit | |
321 | direct branch. | |
322 | (jmp): Likewise. | |
323 | * i386-tbl.h: Regenerated. | |
324 | ||
7b6d09fb L |
325 | 2015-05-11 H.J. Lu <hongjiu.lu@intel.com> |
326 | ||
327 | * configure.ac: Support bfd_iamcu_arch. | |
328 | * disassemble.c (disassembler): Support bfd_iamcu_arch. | |
329 | * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and | |
330 | CPU_IAMCU_COMPAT_FLAGS. | |
331 | (cpu_flags): Add CpuIAMCU. | |
332 | * i386-opc.h (CpuIAMCU): New. | |
333 | (i386_cpu_flags): Add cpuiamcu. | |
334 | * configure: Regenerated. | |
335 | * i386-init.h: Likewise. | |
336 | * i386-tbl.h: Likewise. | |
337 | ||
31955f99 L |
338 | 2015-05-08 H.J. Lu <hongjiu.lu@intel.com> |
339 | ||
340 | PR binutis/18386 | |
341 | * i386-dis.c (X86_64_E8): New. | |
342 | (X86_64_E9): Likewise. | |
343 | Update comments on 'T', 'U', 'V'. Add comments for '^'. | |
344 | (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9. | |
345 | (x86_64_table): Add X86_64_E8 and X86_64_E9. | |
346 | (mod_table): Replace {T|} with ^ on Jcall/Jmp. | |
347 | (putop): Handle '^'. | |
348 | (OP_J): Ignore the operand size prefix in 64-bit. Don't check | |
349 | REX_W. | |
350 | ||
0952813b DD |
351 | 2015-04-30 DJ Delorie <dj@redhat.com> |
352 | ||
353 | * disassemble.c (disassembler): Choose suitable disassembler based | |
354 | on E_ABI. | |
355 | * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use | |
356 | it to decode mul/div insns. | |
357 | * rl78-decode.c: Regenerate. | |
358 | * rl78-dis.c (print_insn_rl78): Rename to... | |
359 | (print_insn_rl78_common): ...this, take ISA parameter. | |
360 | (print_insn_rl78): New. | |
361 | (print_insn_rl78_g10): New. | |
362 | (print_insn_rl78_g13): New. | |
363 | (print_insn_rl78_g14): New. | |
364 | (rl78_get_disassembler): New. | |
365 | ||
f9d3ecaa NC |
366 | 2015-04-29 Nick Clifton <nickc@redhat.com> |
367 | ||
368 | * po/fr.po: Updated French translation. | |
369 | ||
4fff86c5 PB |
370 | 2015-04-27 Peter Bergner <bergner@vnet.ibm.com> |
371 | ||
372 | * ppc-opc.c (DCBT_EO): New define. | |
373 | (powerpc_opcodes) <lbarx>: Enable for POWER8 and later. | |
374 | <lharx>: Likewise. | |
375 | <stbcx.>: Likewise. | |
376 | <sthcx.>: Likewise. | |
377 | <waitrsv>: Do not enable for POWER7 and later. | |
378 | <waitimpl>: Likewise. | |
379 | <dcbt>: Default to the two operand form of the instruction for all | |
380 | "old" cpus. For "new" cpus, use the operand ordering that matches | |
381 | whether the cpu is server or embedded. | |
382 | <dcbtst>: Likewise. | |
383 | ||
3b78cfe1 AK |
384 | 2015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com> |
385 | ||
386 | * s390-opc.c: New instruction type VV0UU2. | |
387 | * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK, | |
388 | and WFC. | |
389 | ||
04d824a4 JB |
390 | 2015-04-23 Jan Beulich <jbeulich@suse.com> |
391 | ||
392 | * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ". | |
393 | * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq, | |
394 | vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY. | |
395 | (vfpclasspd, vfpclassps): Add %XZ. | |
396 | ||
09708981 L |
397 | 2015-04-15 H.J. Lu <hongjiu.lu@intel.com> |
398 | ||
399 | * i386-dis.c (PREFIX_UD_SHIFT): Removed. | |
400 | (PREFIX_UD_REPZ): Likewise. | |
401 | (PREFIX_UD_REPNZ): Likewise. | |
402 | (PREFIX_UD_DATA): Likewise. | |
403 | (PREFIX_UD_ADDR): Likewise. | |
404 | (PREFIX_UD_LOCK): Likewise. | |
405 | ||
3888916d L |
406 | 2015-04-15 H.J. Lu <hongjiu.lu@intel.com> |
407 | ||
408 | * i386-dis.c (prefix_requirement): Removed. | |
409 | (print_insn): Don't set prefix_requirement. Check | |
410 | dp->prefix_requirement instead of prefix_requirement. | |
411 | ||
f24bcbaa L |
412 | 2015-04-15 H.J. Lu <hongjiu.lu@intel.com> |
413 | ||
414 | PR binutils/17898 | |
415 | * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ... | |
416 | (PREFIX_MOD_0_0FC7_REG_6): This. | |
417 | (PREFIX_MOD_3_0FC7_REG_6): New. | |
418 | (PREFIX_MOD_3_0FC7_REG_7): Likewise. | |
419 | (prefix_table): Replace PREFIX_0FC7_REG_6 with | |
420 | PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and | |
421 | PREFIX_MOD_3_0FC7_REG_7. | |
422 | (mod_table): Replace PREFIX_0FC7_REG_6 with | |
423 | PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and | |
424 | PREFIX_MOD_3_0FC7_REG_7. | |
425 | ||
507bd325 L |
426 | 2015-04-15 H.J. Lu <hongjiu.lu@intel.com> |
427 | ||
428 | * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed. | |
429 | (PREFIX_MANDATORY_REPNZ): Likewise. | |
430 | (PREFIX_MANDATORY_DATA): Likewise. | |
431 | (PREFIX_MANDATORY_ADDR): Likewise. | |
432 | (PREFIX_MANDATORY_LOCK): Likewise. | |
433 | (PREFIX_MANDATORY): Likewise. | |
434 | (PREFIX_UD_SHIFT): Set to 8 | |
435 | (PREFIX_UD_REPZ): Updated. | |
436 | (PREFIX_UD_REPNZ): Likewise. | |
437 | (PREFIX_UD_DATA): Likewise. | |
438 | (PREFIX_UD_ADDR): Likewise. | |
439 | (PREFIX_UD_LOCK): Likewise. | |
440 | (PREFIX_IGNORED_SHIFT): New. | |
441 | (PREFIX_IGNORED_REPZ): Likewise. | |
442 | (PREFIX_IGNORED_REPNZ): Likewise. | |
443 | (PREFIX_IGNORED_DATA): Likewise. | |
444 | (PREFIX_IGNORED_ADDR): Likewise. | |
445 | (PREFIX_IGNORED_LOCK): Likewise. | |
446 | (PREFIX_OPCODE): Likewise. | |
447 | (PREFIX_IGNORED): Likewise. | |
448 | (Bad_Opcode): Replace PREFIX_MANDATORY with 0. | |
449 | (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE. | |
450 | (three_byte_table): Likewise. | |
451 | (mod_table): Likewise. | |
452 | (mandatory_prefix): Renamed to ... | |
453 | (prefix_requirement): This. | |
454 | (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE. | |
455 | Update PREFIX_90 entry. | |
456 | (get_valid_dis386): Check prefix_requirement to see if a prefix | |
457 | should be ignored. | |
458 | (print_insn): Replace mandatory_prefix with prefix_requirement. | |
459 | ||
f0fba320 RL |
460 | 2015-04-15 Renlin Li <renlin.li@arm.com> |
461 | ||
462 | * arm-dis.c (thumb32_opcodes): Define 'D' format control code, | |
463 | use it for ssat and ssat16. | |
464 | (print_insn_thumb32): Add handle case for 'D' control code. | |
465 | ||
bf890a93 IT |
466 | 2015-04-06 Ilya Tocar <ilya.tocar@intel.com> |
467 | H.J. Lu <hongjiu.lu@intel.com> | |
468 | ||
469 | * i386-dis-evex.h (evex_table): Fill prefix_requirement field. | |
470 | * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ, | |
471 | PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK, | |
472 | PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA, | |
473 | PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define. | |
474 | (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX): | |
475 | Fill prefix_requirement field. | |
476 | (struct dis386): Add prefix_requirement field. | |
477 | (dis386): Fill prefix_requirement field. | |
478 | (dis386_twobyte): Ditto. | |
479 | (twobyte_has_mandatory_prefix_: Remove. | |
480 | (reg_table): Fill prefix_requirement field. | |
481 | (prefix_table): Ditto. | |
482 | (x86_64_table): Ditto. | |
483 | (three_byte_table): Ditto. | |
484 | (xop_table): Ditto. | |
485 | (vex_table): Ditto. | |
486 | (vex_len_table): Ditto. | |
487 | (vex_w_table): Ditto. | |
488 | (mod_table): Ditto. | |
489 | (bad_opcode): Ditto. | |
490 | (print_insn): Use prefix_requirement. | |
491 | (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4, | |
492 | FGRPde_3, FGRPdf_4): Fill prefix_requirement field. | |
493 | (float_reg): Ditto. | |
494 | ||
2f783c1f MF |
495 | 2015-03-30 Mike Frysinger <vapier@gentoo.org> |
496 | ||
497 | * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype. | |
498 | ||
b9d94d62 L |
499 | 2015-03-29 H.J. Lu <hongjiu.lu@intel.com> |
500 | ||
501 | * Makefile.in: Regenerated. | |
502 | ||
27c49e9a AB |
503 | 2015-03-25 Anton Blanchard <anton@samba.org> |
504 | ||
505 | * ppc-dis.c (disassemble_init_powerpc): Only initialise | |
506 | powerpc_opcd_indices and vle_opcd_indices once. | |
507 | ||
c4e676f1 AB |
508 | 2015-03-25 Anton Blanchard <anton@samba.org> |
509 | ||
510 | * ppc-opc.c (powerpc_opcodes): Add slbfee. | |
511 | ||
823d2571 TG |
512 | 2015-03-24 Terry Guo <terry.guo@arm.com> |
513 | ||
514 | * arm-dis.c (opcode32): Updated to use new arm feature struct. | |
515 | (opcode16): Likewise. | |
516 | (coprocessor_opcodes): Replace bit with feature struct. | |
517 | (neon_opcodes): Likewise. | |
518 | (arm_opcodes): Likewise. | |
519 | (thumb_opcodes): Likewise. | |
520 | (thumb32_opcodes): Likewise. | |
521 | (print_insn_coprocessor): Likewise. | |
522 | (print_insn_arm): Likewise. | |
523 | (select_arm_features): Follow new feature struct. | |
524 | ||
029f3522 GG |
525 | 2015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com> |
526 | ||
527 | * i386-dis.c (rm_table): Add clzero. | |
528 | * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS. | |
529 | Add CPU_CLZERO_FLAGS. | |
530 | (cpu_flags): Add CpuCLZERO. | |
531 | * i386-opc.h: Add CpuCLZERO. | |
532 | * i386-opc.tbl: Add clzero. | |
533 | * i386-init.h: Re-generated. | |
534 | * i386-tbl.h: Re-generated. | |
535 | ||
6914869a AB |
536 | 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com> |
537 | ||
538 | * mips-opc.c (decode_mips_operand): Fix constraint issues | |
539 | with u and y operands. | |
540 | ||
21e20815 AB |
541 | 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com> |
542 | ||
543 | * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions. | |
544 | ||
6b1d7593 AK |
545 | 2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com> |
546 | ||
547 | * s390-opc.c: Add new IBM z13 instructions. | |
548 | * s390-opc.txt: Likewise. | |
549 | ||
c8f89a34 JW |
550 | 2015-03-10 Renlin Li <renlin.li@arm.com> |
551 | ||
552 | * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb, | |
553 | stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and | |
554 | related alias. | |
555 | * aarch64-asm-2.c: Regenerate. | |
556 | * aarch64-dis-2.c: Likewise. | |
557 | * aarch64-opc-2.c: Likewise. | |
558 | ||
d8282f0e JW |
559 | 2015-03-03 Jiong Wang <jiong.wang@arm.com> |
560 | ||
561 | * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols. | |
562 | ||
ac994365 OE |
563 | 2015-02-25 Oleg Endo <olegendo@gcc.gnu.org> |
564 | ||
565 | * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of | |
566 | arch_sh_up. | |
567 | (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of | |
568 | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up. | |
569 | ||
fd63f640 V |
570 | 2015-02-23 Vinay <Vinay.G@kpit.com> |
571 | ||
572 | * rl78-decode.opc (MOV): Added space between two operands for | |
573 | 'mov' instruction in index addressing mode. | |
574 | * rl78-decode.c: Regenerate. | |
575 | ||
f63c1776 PA |
576 | 2015-02-19 Pedro Alves <palves@redhat.com> |
577 | ||
578 | * microblaze-dis.h [__cplusplus]: Wrap in extern "C". | |
579 | ||
07774fcc PA |
580 | 2015-02-10 Pedro Alves <palves@redhat.com> |
581 | Tom Tromey <tromey@redhat.com> | |
582 | ||
583 | * microblaze-opcm.h (or, and, xor): Rename to microblaze_or, | |
584 | microblaze_and, microblaze_xor. | |
585 | * microblaze-opc.h (opcodes): Adjust. | |
586 | ||
3f8107ab AM |
587 | 2015-01-28 James Bowman <james.bowman@ftdichip.com> |
588 | ||
589 | * Makefile.am: Add FT32 files. | |
590 | * configure.ac: Handle FT32. | |
591 | * disassemble.c (disassembler): Call print_insn_ft32. | |
592 | * ft32-dis.c: New file. | |
593 | * ft32-opc.c: New file. | |
594 | * Makefile.in: Regenerate. | |
595 | * configure: Regenerate. | |
596 | * po/POTFILES.in: Regenerate. | |
597 | ||
e5fe4957 KLC |
598 | 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com> |
599 | ||
600 | * nds32-asm.c (keyword_sr): Add new system registers. | |
601 | ||
1e2e8c52 AK |
602 | 2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com> |
603 | ||
604 | * s390-dis.c (s390_extract_operand): Support vector register | |
605 | operands. | |
606 | (s390_print_insn_with_opcode): Support new operands types and add | |
607 | new handling of optional operands. | |
608 | * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove | |
609 | and include opcode/s390.h instead. | |
610 | (struct op_struct): New field `flags'. | |
611 | (insertOpcode, insertExpandedMnemonic): New parameter `flags'. | |
612 | (dumpTable): Dump flags. | |
613 | (main): Parse flags from the s390-opc.txt file. Add z13 as cpu | |
614 | string. | |
615 | * s390-opc.c: Add new operands types, instruction formats, and | |
616 | instruction masks. | |
617 | (s390_opformats): Add new formats for .insn. | |
618 | * s390-opc.txt: Add new instructions. | |
619 | ||
b90efa5b | 620 | 2015-01-01 Alan Modra <amodra@gmail.com> |
bffb6004 | 621 | |
b90efa5b | 622 | Update year range in copyright notice of all files. |
bffb6004 | 623 | |
b90efa5b | 624 | For older changes see ChangeLog-2014 |
252b5132 | 625 | \f |
b90efa5b | 626 | Copyright (C) 2015 Free Software Foundation, Inc. |
752937aa NC |
627 | |
628 | Copying and distribution of this file, with or without modification, | |
629 | are permitted in any medium without royalty provided the copyright | |
630 | notice and this notice are preserved. | |
631 | ||
252b5132 | 632 | Local Variables: |
2f6d2f85 NC |
633 | mode: change-log |
634 | left-margin: 8 | |
635 | fill-column: 74 | |
252b5132 RH |
636 | version-control: never |
637 | End: |