projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
x86-64: generalize SIMD test expectations
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
d88bdcb4
PA		 12019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
2
3 PR 24854
4 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
5 encountering an unknown machine type.
6 (print_insn_arc): Handle arc_insn_length returning 0. In error
7 cases return -1 rather than calling abort.
8
bc750500
JB		 92019-08-07 Jan Beulich <jbeulich@suse.com>
10
11 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
12 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
13 IgnoreSize.
14 * i386-tbl.h: Re-generate.
15
23d188c7
BW		 162019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
17
18 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
19 instructions.
20
c0d6f62f
JW		 212019-07-30 Mel Chen <mel.chen@sifive.com>
22
23 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
24 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
25
26 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
27 fscsr.
28
0f3f7167
CZ		 292019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
30
31 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
32 and MPY class instructions.
33 (parse_option): Add nps400 option.
34 (print_arc_disassembler_options): Add nps400 info.
35
7e126ba3
CZ		 362019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
37
38 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
39 (bspop): Likewise.
40 (modapp): Likewise.
41 * arc-opc.c (RAD_CHK): Add.
42 * arc-tbl.h: Regenerate.
43
a028026d
KT		 442019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
45
46 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
47 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
48
ac79ff9e
NC		 492019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
50
51 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
52 instructions as UNPREDICTABLE.
53
231097b0
JM		 542019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
55
56 * bpf-desc.c: Regenerated.
57
1d942ae9
JB		 582019-07-17 Jan Beulich <jbeulich@suse.com>
59
60 * i386-gen.c (static_assert): Define.
61 (main): Use it.
62 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
63 (Opcode_Modifier_Num): ... this.
64 (Mem): Delete.
65
dfd69174
JB		 662019-07-16 Jan Beulich <jbeulich@suse.com>
67
68 * i386-gen.c (operand_types): Move RegMem ...
69 (opcode_modifiers): ... here.
70 * i386-opc.h (RegMem): Move to opcode modifer enum.
71 (union i386_operand_type): Move regmem field ...
72 (struct i386_opcode_modifier): ... here.
73 * i386-opc.tbl (RegMem): Define.
74 (mov, movq): Move RegMem on segment, control, debug, and test
75 register flavors.
76 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
77 to non-SSE2AVX flavor.
78 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
79 Move RegMem on register only flavors. Drop IgnoreSize from
80 legacy encoding flavors.
81 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
82 flavors.
83 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
84 register only flavors.
85 (vmovd): Move RegMem and drop IgnoreSize on register only
86 flavor. Change opcode and operand order to store form.
87 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
88
21df382b
JB		 892019-07-16 Jan Beulich <jbeulich@suse.com>
90
91 * i386-gen.c (operand_type_init, operand_types): Replace SReg
92 entries.
93 * i386-opc.h (SReg2, SReg3): Replace by ...
94 (SReg): ... this.
95 (union i386_operand_type): Replace sreg fields.
96 * i386-opc.tbl (mov, ): Use SReg.
97 (push, pop): Likewies. Drop i386 and x86-64 specific segment
98 register flavors.
99 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
100 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
101
3719fd55
JM		 1022019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
103
104 * bpf-desc.c: Regenerate.
105 * bpf-opc.c: Likewise.
106 * bpf-opc.h: Likewise.
107
92434a14
JM		 1082019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
109
110 * bpf-desc.c: Regenerate.
111 * bpf-opc.c: Likewise.
112
43dd7626
HPN		 1132019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
114
115 * arm-dis.c (print_insn_coprocessor): Rename index to
116 index_operand.
117
98602811
JW		 1182019-07-05 Kito Cheng <kito.cheng@sifive.com>
119
120 * riscv-opc.c (riscv_insn_types): Add r4 type.
121
122 * riscv-opc.c (riscv_insn_types): Add b and j type.
123
124 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
125 format for sb type and correct s type.
126
01c1ee4a
RS		 1272019-07-02 Richard Sandiford <richard.sandiford@arm.com>
128
129 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
130 SVE FMOV alias of FCPY.
131
83adff69
RS		 1322019-07-02 Richard Sandiford <richard.sandiford@arm.com>
133
134 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
135 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
136
89418844
RS		 1372019-07-02 Richard Sandiford <richard.sandiford@arm.com>
138
139 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
140 registers in an instruction prefixed by MOVPRFX.
141
41be57ca
MM		 1422019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
143
144 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
145 sve_size_13 icode to account for variant behaviour of
146 pmull{t,b}.
147 * aarch64-dis-2.c: Regenerate.
148 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
149 sve_size_13 icode to account for variant behaviour of
150 pmull{t,b}.
151 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
152 (OP_SVE_VVV_Q_D): Add new qualifier.
153 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
154 (struct aarch64_opcode): Split pmull{t,b} into those requiring
155 AES and those not.
156
9d3bf266
JB		 1572019-07-01 Jan Beulich <jbeulich@suse.com>
158
159 * opcodes/i386-gen.c (operand_type_init): Remove
160 OPERAND_TYPE_VEC_IMM4 entry.
161 (operand_types): Remove Vec_Imm4.
162 * opcodes/i386-opc.h (Vec_Imm4): Delete.
163 (union i386_operand_type): Remove vec_imm4.
164 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
165 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
166
c3949f43
JB		 1672019-07-01 Jan Beulich <jbeulich@suse.com>
168
169 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
170 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
171 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
172 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
173 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
174 monitorx, mwaitx): Drop ImmExt from operand-less forms.
175 * i386-tbl.h: Re-generate.
176
5641ec01
JB		 1772019-07-01 Jan Beulich <jbeulich@suse.com>
178
179 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
180 register operands.
181 * i386-tbl.h: Re-generate.
182
79dec6b7
JB		 1832019-07-01 Jan Beulich <jbeulich@suse.com>
184
185 * i386-opc.tbl (C): New.
186 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
187 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
188 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
189 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
190 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
191 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
192 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
193 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
194 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
195 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
196 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
197 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
198 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
199 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
200 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
201 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
202 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
203 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
204 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
205 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
206 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
207 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
208 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
209 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
210 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
211 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
212 flavors.
213 * i386-tbl.h: Re-generate.
214
a0a1771e
JB		 2152019-07-01 Jan Beulich <jbeulich@suse.com>
216
217 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
218 register operands.
219 * i386-tbl.h: Re-generate.
220
cd546e7b
JB		 2212019-07-01 Jan Beulich <jbeulich@suse.com>
222
223 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
224 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
225 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
226 * i386-tbl.h: Re-generate.
227
e3bba3fc
JB		 2282019-07-01 Jan Beulich <jbeulich@suse.com>
229
230 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
231 Disp8MemShift from register only templates.
232 * i386-tbl.h: Re-generate.
233
36cc073e
JB		 2342019-07-01 Jan Beulich <jbeulich@suse.com>
235
236 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
237 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
238 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
239 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
240 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
241 EVEX_W_0F11_P_3_M_1): Delete.
242 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
243 EVEX_W_0F11_P_3): New.
244 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
245 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
246 MOD_EVEX_0F11_PREFIX_3 table entries.
247 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
248 PREFIX_EVEX_0F11 table entries.
249 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
250 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
251 EVEX_W_0F11_P_3_M_{0,1} table entries.
252
219920a7
JB		 2532019-07-01 Jan Beulich <jbeulich@suse.com>
254
255 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
256 Delete.
257
e395f487
L		 2582019-06-27 H.J. Lu <hongjiu.lu@intel.com>
259
260 PR binutils/24719
261 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
262 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
263 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
264 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
265 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
266 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
267 EVEX_LEN_0F38C7_R_6_P_2_W_1.
268 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
269 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
270 PREFIX_EVEX_0F38C6_REG_6 entries.
271 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
272 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
273 EVEX_W_0F38C7_R_6_P_2 entries.
274 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
275 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
276 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
277 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
278 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
279 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
280 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
281
2b7bcc87
JB		 2822019-06-27 Jan Beulich <jbeulich@suse.com>
283
284 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
285 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
286 VEX_LEN_0F2D_P_3): Delete.
287 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
288 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
289 (prefix_table): ... here.
290
c1dc7af5
JB		 2912019-06-27 Jan Beulich <jbeulich@suse.com>
292
293 * i386-dis.c (Iq): Delete.
294 (Id): New.
295 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
296 TBM insns.
297 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
298 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
299 (OP_E_memory): Also honor needindex when deciding whether an
300 address size prefix needs printing.
301 (OP_I): Remove handling of q_mode. Add handling of d_mode.
302
d7560e2d
JW		 3032019-06-26 Jim Wilson <jimw@sifive.com>
304
305 PR binutils/24739
306 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
307 Set info->display_endian to info->endian_code.
308
2c703856
JB		 3092019-06-25 Jan Beulich <jbeulich@suse.com>
310
311 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
312 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
313 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
314 OPERAND_TYPE_ACC64 entries.
315 * i386-init.h: Re-generate.
316
54fbadc0
JB		 3172019-06-25 Jan Beulich <jbeulich@suse.com>
318
319 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
320 Delete.
321 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
322 of dqa_mode.
323 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
324 entries here.
325 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
326 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
327
a280ab8e
JB		 3282019-06-25 Jan Beulich <jbeulich@suse.com>
329
330 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
331 variables.
332
e1a1babd
JB		 3332019-06-25 Jan Beulich <jbeulich@suse.com>
334
335 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
336 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
337 movnti.
d7560e2d 338 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 339 * i386-tbl.h: Re-generate.
340
b8364fa7
JB		 3412019-06-25 Jan Beulich <jbeulich@suse.com>
342
343 * i386-opc.tbl (and): Mark Imm8S form for optimization.
344 * i386-tbl.h: Re-generate.
345
ad692897
L		 3462019-06-21 H.J. Lu <hongjiu.lu@intel.com>
347
348 * i386-dis-evex.h: Break into ...
349 * i386-dis-evex-len.h: New file.
350 * i386-dis-evex-mod.h: Likewise.
351 * i386-dis-evex-prefix.h: Likewise.
352 * i386-dis-evex-reg.h: Likewise.
353 * i386-dis-evex-w.h: Likewise.
354 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
355 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
356 i386-dis-evex-mod.h.
357
f0a6222e
L		 3582019-06-19 H.J. Lu <hongjiu.lu@intel.com>
359
360 PR binutils/24700
361 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
362 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
363 EVEX_W_0F385B_P_2.
364 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
365 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
366 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
367 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
368 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
369 EVEX_LEN_0F385B_P_2_W_1.
370 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
371 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
372 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
373 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
374 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
375 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
376 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
377 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
378 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
379 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
380
6e1c90b7
L		 3812019-06-17 H.J. Lu <hongjiu.lu@intel.com>
382
383 PR binutils/24691
384 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
385 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
386 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
387 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
388 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
389 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
390 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
391 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
392 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
393 EVEX_LEN_0F3A43_P_2_W_1.
394 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
395 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
396 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
397 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
398 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
399 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
400 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
401 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
402 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
403 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
404 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
405 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
406
bcc5a6eb
NC		 4072019-06-14 Nick Clifton <nickc@redhat.com>
408
409 * po/fr.po; Updated French translation.
410
e4c4ac46
SH		 4112019-06-13 Stafford Horne <shorne@gmail.com>
412
413 * or1k-asm.c: Regenerated.
414 * or1k-desc.c: Regenerated.
415 * or1k-desc.h: Regenerated.
416 * or1k-dis.c: Regenerated.
417 * or1k-ibld.c: Regenerated.
418 * or1k-opc.c: Regenerated.
419 * or1k-opc.h: Regenerated.
420 * or1k-opinst.c: Regenerated.
421
a0e44ef5
PB		 4222019-06-12 Peter Bergner <bergner@linux.ibm.com>
423
424 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
425
12efd68d
L		 4262019-06-05 H.J. Lu <hongjiu.lu@intel.com>
427
428 PR binutils/24633
429 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
430 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
431 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
432 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
433 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
434 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
435 EVEX_LEN_0F3A1B_P_2_W_1.
436 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
437 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
438 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
439 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
440 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
441 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
442 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
443 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
444
63c6fc6c
L		 4452019-06-04 H.J. Lu <hongjiu.lu@intel.com>
446
447 PR binutils/24626
448 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
449 EVEX.vvvv when disassembling VEX and EVEX instructions.
450 (OP_VEX): Set vex.register_specifier to 0 after readding
451 vex.register_specifier.
452 (OP_Vex_2src_1): Likewise.
453 (OP_Vex_2src_2): Likewise.
454 (OP_LWP_E): Likewise.
455 (OP_EX_Vex): Don't check vex.register_specifier.
456 (OP_XMM_Vex): Likewise.
457
9186c494
L		 4582019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
459 Lili Cui <lili.cui@intel.com>
460
461 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
462 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
463 instructions.
464 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
465 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
466 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
467 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
468 (i386_cpu_flags): Add cpuavx512_vp2intersect.
469 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
470 * i386-init.h: Regenerated.
471 * i386-tbl.h: Likewise.
472
5d79adc4
L		 4732019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
474 Lili Cui <lili.cui@intel.com>
475
476 * doc/c-i386.texi: Document enqcmd.
477 * testsuite/gas/i386/enqcmd-intel.d: New file.
478 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
479 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
480 * testsuite/gas/i386/enqcmd.d: Likewise.
481 * testsuite/gas/i386/enqcmd.s: Likewise.
482 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
483 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
484 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
485 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
486 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
487 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
488 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
489 and x86-64-enqcmd.
490
a9d96ab9
AH		 4912019-06-04 Alan Hayward <alan.hayward@arm.com>
492
493 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
494
4f6d070a
AM		 4952019-06-03 Alan Modra <amodra@gmail.com>
496
497 * ppc-dis.c (prefix_opcd_indices): Correct size.
498
a2f4b66c
L		 4992019-05-28 H.J. Lu <hongjiu.lu@intel.com>
500
501 PR gas/24625
502 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
503 Disp8ShiftVL.
504 * i386-tbl.h: Regenerated.
505
405b5bd8
AM		 5062019-05-24 Alan Modra <amodra@gmail.com>
507
508 * po/POTFILES.in: Regenerate.
509
8acf1435
PB		 5102019-05-24 Peter Bergner <bergner@linux.ibm.com>
511 Alan Modra <amodra@gmail.com>
512
513 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
514 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
515 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
516 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
517 XTOP>): Define and add entries.
518 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
519 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
520 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
521 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
522
dd7efa79
PB		 5232019-05-24 Peter Bergner <bergner@linux.ibm.com>
524 Alan Modra <amodra@gmail.com>
525
526 * ppc-dis.c (ppc_opts): Add "future" entry.
527 (PREFIX_OPCD_SEGS): Define.
528 (prefix_opcd_indices): New array.
529 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
530 (lookup_prefix): New function.
531 (print_insn_powerpc): Handle 64-bit prefix instructions.
532 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
533 (PMRR, POWERXX): Define.
534 (prefix_opcodes): New instruction table.
535 (prefix_num_opcodes): New constant.
536
79472b45
JM		 5372019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
538
539 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
540 * configure: Regenerated.
541 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
542 and cpu/bpf.opc.
543 (HFILES): Add bpf-desc.h and bpf-opc.h.
544 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
545 bpf-ibld.c and bpf-opc.c.
546 (BPF_DEPS): Define.
547 * Makefile.in: Regenerated.
548 * disassemble.c (ARCH_bpf): Define.
549 (disassembler): Add case for bfd_arch_bpf.
550 (disassemble_init_for_target): Likewise.
551 (enum epbf_isa_attr): Define.
552 * disassemble.h: extern print_insn_bpf.
553 * bpf-asm.c: Generated.
554 * bpf-opc.h: Likewise.
555 * bpf-opc.c: Likewise.
556 * bpf-ibld.c: Likewise.
557 * bpf-dis.c: Likewise.
558 * bpf-desc.h: Likewise.
559 * bpf-desc.c: Likewise.
560
ba6cd17f
SD		 5612019-05-21 Sudakshina Das <sudi.das@arm.com>
562
563 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
564 and VMSR with the new operands.
565
e39c1607
SD		 5662019-05-21 Sudakshina Das <sudi.das@arm.com>
567
568 * arm-dis.c (enum mve_instructions): New enum
569 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
570 and cneg.
571 (mve_opcodes): New instructions as above.
572 (is_mve_encoding_conflict): Add cases for csinc, csinv,
573 csneg and csel.
574 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
575
23d00a41
SD		 5762019-05-21 Sudakshina Das <sudi.das@arm.com>
577
578 * arm-dis.c (emun mve_instructions): Updated for new instructions.
579 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
580 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
581 uqshl, urshrl and urshr.
582 (is_mve_okay_in_it): Add new instructions to TRUE list.
583 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
584 (print_insn_mve): Updated to accept new %j,
585 %<bitfield>m and %<bitfield>n patterns.
586
cd4797ee
FS		 5872019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
588
589 * mips-opc.c (mips_builtin_opcodes): Change source register
590 constraint for DAUI.
591
999b073b
NC		 5922019-05-20 Nick Clifton <nickc@redhat.com>
593
594 * po/fr.po: Updated French translation.
595
14b456f2
AV		 5962019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
597 Michael Collison <michael.collison@arm.com>
598
599 * arm-dis.c (thumb32_opcodes): Add new instructions.
600 (enum mve_instructions): Likewise.
601 (enum mve_undefined): Add new reasons.
602 (is_mve_encoding_conflict): Handle new instructions.
603 (is_mve_undefined): Likewise.
604 (is_mve_unpredictable): Likewise.
605 (print_mve_undefined): Likewise.
606 (print_mve_size): Likewise.
607
f49bb598
AV		 6082019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
609 Michael Collison <michael.collison@arm.com>
610
611 * arm-dis.c (thumb32_opcodes): Add new instructions.
612 (enum mve_instructions): Likewise.
613 (is_mve_encoding_conflict): Handle new instructions.
614 (is_mve_undefined): Likewise.
615 (is_mve_unpredictable): Likewise.
616 (print_mve_size): Likewise.
617
56858bea
AV		 6182019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
619 Michael Collison <michael.collison@arm.com>
620
621 * arm-dis.c (thumb32_opcodes): Add new instructions.
622 (enum mve_instructions): Likewise.
623 (is_mve_encoding_conflict): Likewise.
624 (is_mve_unpredictable): Likewise.
625 (print_mve_size): Likewise.
626
e523f101
AV		 6272019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
628 Michael Collison <michael.collison@arm.com>
629
630 * arm-dis.c (thumb32_opcodes): Add new instructions.
631 (enum mve_instructions): Likewise.
632 (is_mve_encoding_conflict): Handle new instructions.
633 (is_mve_undefined): Likewise.
634 (is_mve_unpredictable): Likewise.
635 (print_mve_size): Likewise.
636
66dcaa5d
AV		 6372019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
638 Michael Collison <michael.collison@arm.com>
639
640 * arm-dis.c (thumb32_opcodes): Add new instructions.
641 (enum mve_instructions): Likewise.
642 (is_mve_encoding_conflict): Handle new instructions.
643 (is_mve_undefined): Likewise.
644 (is_mve_unpredictable): Likewise.
645 (print_mve_size): Likewise.
646 (print_insn_mve): Likewise.
647
d052b9b7
AV		 6482019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
649 Michael Collison <michael.collison@arm.com>
650
651 * arm-dis.c (thumb32_opcodes): Add new instructions.
652 (print_insn_thumb32): Handle new instructions.
653
ed63aa17
AV		 6542019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
655 Michael Collison <michael.collison@arm.com>
656
657 * arm-dis.c (enum mve_instructions): Add new instructions.
658 (enum mve_undefined): Add new reasons.
659 (is_mve_encoding_conflict): Handle new instructions.
660 (is_mve_undefined): Likewise.
661 (is_mve_unpredictable): Likewise.
662 (print_mve_undefined): Likewise.
663 (print_mve_size): Likewise.
664 (print_mve_shift_n): Likewise.
665 (print_insn_mve): Likewise.
666
897b9bbc
AV		 6672019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
668 Michael Collison <michael.collison@arm.com>
669
670 * arm-dis.c (enum mve_instructions): Add new instructions.
671 (is_mve_encoding_conflict): Handle new instructions.
672 (is_mve_unpredictable): Likewise.
673 (print_mve_rotate): Likewise.
674 (print_mve_size): Likewise.
675 (print_insn_mve): Likewise.
676
1c8f2df8
AV		 6772019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
678 Michael Collison <michael.collison@arm.com>
679
680 * arm-dis.c (enum mve_instructions): Add new instructions.
681 (is_mve_encoding_conflict): Handle new instructions.
682 (is_mve_unpredictable): Likewise.
683 (print_mve_size): Likewise.
684 (print_insn_mve): Likewise.
685
d3b63143
AV		 6862019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
687 Michael Collison <michael.collison@arm.com>
688
689 * arm-dis.c (enum mve_instructions): Add new instructions.
690 (enum mve_undefined): Add new reasons.
691 (is_mve_encoding_conflict): Handle new instructions.
692 (is_mve_undefined): Likewise.
693 (is_mve_unpredictable): Likewise.
694 (print_mve_undefined): Likewise.
695 (print_mve_size): Likewise.
696 (print_insn_mve): Likewise.
697
14925797
AV		 6982019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
699 Michael Collison <michael.collison@arm.com>
700
701 * arm-dis.c (enum mve_instructions): Add new instructions.
702 (is_mve_encoding_conflict): Handle new instructions.
703 (is_mve_undefined): Likewise.
704 (is_mve_unpredictable): Likewise.
705 (print_mve_size): Likewise.
706 (print_insn_mve): Likewise.
707
c507f10b
AV		 7082019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
709 Michael Collison <michael.collison@arm.com>
710
711 * arm-dis.c (enum mve_instructions): Add new instructions.
712 (enum mve_unpredictable): Add new reasons.
713 (enum mve_undefined): Likewise.
714 (is_mve_okay_in_it): Handle new isntructions.
715 (is_mve_encoding_conflict): Likewise.
716 (is_mve_undefined): Likewise.
717 (is_mve_unpredictable): Likewise.
718 (print_mve_vmov_index): Likewise.
719 (print_simd_imm8): Likewise.
720 (print_mve_undefined): Likewise.
721 (print_mve_unpredictable): Likewise.
722 (print_mve_size): Likewise.
723 (print_insn_mve): Likewise.
724
bf0b396d
AV		 7252019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
726 Michael Collison <michael.collison@arm.com>
727
728 * arm-dis.c (enum mve_instructions): Add new instructions.
729 (enum mve_unpredictable): Add new reasons.
730 (enum mve_undefined): Likewise.
731 (is_mve_encoding_conflict): Handle new instructions.
732 (is_mve_undefined): Likewise.
733 (is_mve_unpredictable): Likewise.
734 (print_mve_undefined): Likewise.
735 (print_mve_unpredictable): Likewise.
736 (print_mve_rounding_mode): Likewise.
737 (print_mve_vcvt_size): Likewise.
738 (print_mve_size): Likewise.
739 (print_insn_mve): Likewise.
740
ef1576a1
AV		 7412019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
742 Michael Collison <michael.collison@arm.com>
743
744 * arm-dis.c (enum mve_instructions): Add new instructions.
745 (enum mve_unpredictable): Add new reasons.
746 (enum mve_undefined): Likewise.
747 (is_mve_undefined): Handle new instructions.
748 (is_mve_unpredictable): Likewise.
749 (print_mve_undefined): Likewise.
750 (print_mve_unpredictable): Likewise.
751 (print_mve_size): Likewise.
752 (print_insn_mve): Likewise.
753
aef6d006
AV		 7542019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
755 Michael Collison <michael.collison@arm.com>
756
757 * arm-dis.c (enum mve_instructions): Add new instructions.
758 (enum mve_undefined): Add new reasons.
759 (insns): Add new instructions.
760 (is_mve_encoding_conflict):
761 (print_mve_vld_str_addr): New print function.
762 (is_mve_undefined): Handle new instructions.
763 (is_mve_unpredictable): Likewise.
764 (print_mve_undefined): Likewise.
765 (print_mve_size): Likewise.
766 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
767 (print_insn_mve): Handle new operands.
768
04d54ace
AV		 7692019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
770 Michael Collison <michael.collison@arm.com>
771
772 * arm-dis.c (enum mve_instructions): Add new instructions.
773 (enum mve_unpredictable): Add new reasons.
774 (is_mve_encoding_conflict): Handle new instructions.
775 (is_mve_unpredictable): Likewise.
776 (mve_opcodes): Add new instructions.
777 (print_mve_unpredictable): Handle new reasons.
778 (print_mve_register_blocks): New print function.
779 (print_mve_size): Handle new instructions.
780 (print_insn_mve): Likewise.
781
9743db03
AV		 7822019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
783 Michael Collison <michael.collison@arm.com>
784
785 * arm-dis.c (enum mve_instructions): Add new instructions.
786 (enum mve_unpredictable): Add new reasons.
787 (enum mve_undefined): Likewise.
788 (is_mve_encoding_conflict): Handle new instructions.
789 (is_mve_undefined): Likewise.
790 (is_mve_unpredictable): Likewise.
791 (coprocessor_opcodes): Move NEON VDUP from here...
792 (neon_opcodes): ... to here.
793 (mve_opcodes): Add new instructions.
794 (print_mve_undefined): Handle new reasons.
795 (print_mve_unpredictable): Likewise.
796 (print_mve_size): Handle new instructions.
797 (print_insn_neon): Handle vdup.
798 (print_insn_mve): Handle new operands.
799
143275ea
AV		 8002019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
801 Michael Collison <michael.collison@arm.com>
802
803 * arm-dis.c (enum mve_instructions): Add new instructions.
804 (enum mve_unpredictable): Add new values.
805 (mve_opcodes): Add new instructions.
806 (vec_condnames): New array with vector conditions.
807 (mve_predicatenames): New array with predicate suffixes.
808 (mve_vec_sizename): New array with vector sizes.
809 (enum vpt_pred_state): New enum with vector predication states.
810 (struct vpt_block): New struct type for vpt blocks.
811 (vpt_block_state): Global struct to keep track of state.
812 (mve_extract_pred_mask): New helper function.
813 (num_instructions_vpt_block): Likewise.
814 (mark_outside_vpt_block): Likewise.
815 (mark_inside_vpt_block): Likewise.
816 (invert_next_predicate_state): Likewise.
817 (update_next_predicate_state): Likewise.
818 (update_vpt_block_state): Likewise.
819 (is_vpt_instruction): Likewise.
820 (is_mve_encoding_conflict): Add entries for new instructions.
821 (is_mve_unpredictable): Likewise.
822 (print_mve_unpredictable): Handle new cases.
823 (print_instruction_predicate): Likewise.
824 (print_mve_size): New function.
825 (print_vec_condition): New function.
826 (print_insn_mve): Handle vpt blocks and new print operands.
827
f08d8ce3
AV		 8282019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
829
830 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
831 8, 14 and 15 for Armv8.1-M Mainline.
832
73cd51e5
AV		 8332019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
834 Michael Collison <michael.collison@arm.com>
835
836 * arm-dis.c (enum mve_instructions): New enum.
837 (enum mve_unpredictable): Likewise.
838 (enum mve_undefined): Likewise.
839 (struct mopcode32): New struct.
840 (is_mve_okay_in_it): New function.
841 (is_mve_architecture): Likewise.
842 (arm_decode_field): Likewise.
843 (arm_decode_field_multiple): Likewise.
844 (is_mve_encoding_conflict): Likewise.
845 (is_mve_undefined): Likewise.
846 (is_mve_unpredictable): Likewise.
847 (print_mve_undefined): Likewise.
848 (print_mve_unpredictable): Likewise.
849 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
850 (print_insn_mve): New function.
851 (print_insn_thumb32): Handle MVE architecture.
852 (select_arm_features): Force thumb for Armv8.1-m Mainline.
853
3076e594
NC		 8542019-05-10 Nick Clifton <nickc@redhat.com>
855
856 PR 24538
857 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
858 end of the table prematurely.
859
387e7624
FS		 8602019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
861
862 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
863 macros for R6.
864
0067be51
AM		 8652019-05-11 Alan Modra <amodra@gmail.com>
866
867 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
868 when -Mraw is in effect.
869
42e6288f
MM		 8702019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
871
872 * aarch64-dis-2.c: Regenerate.
873 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
874 (OP_SVE_BBB): New variant set.
875 (OP_SVE_DDDD): New variant set.
876 (OP_SVE_HHH): New variant set.
877 (OP_SVE_HHHU): New variant set.
878 (OP_SVE_SSS): New variant set.
879 (OP_SVE_SSSU): New variant set.
880 (OP_SVE_SHH): New variant set.
881 (OP_SVE_SBBU): New variant set.
882 (OP_SVE_DSS): New variant set.
883 (OP_SVE_DHHU): New variant set.
884 (OP_SVE_VMV_HSD_BHS): New variant set.
885 (OP_SVE_VVU_HSD_BHS): New variant set.
886 (OP_SVE_VVVU_SD_BH): New variant set.
887 (OP_SVE_VVVU_BHSD): New variant set.
888 (OP_SVE_VVV_QHD_DBS): New variant set.
889 (OP_SVE_VVV_HSD_BHS): New variant set.
890 (OP_SVE_VVV_HSD_BHS2): New variant set.
891 (OP_SVE_VVV_BHS_HSD): New variant set.
892 (OP_SVE_VV_BHS_HSD): New variant set.
893 (OP_SVE_VVV_SD): New variant set.
894 (OP_SVE_VVU_BHS_HSD): New variant set.
895 (OP_SVE_VZVV_SD): New variant set.
896 (OP_SVE_VZVV_BH): New variant set.
897 (OP_SVE_VZV_SD): New variant set.
898 (aarch64_opcode_table): Add sve2 instructions.
899
28ed815a
MM		 9002019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
901
902 * aarch64-asm-2.c: Regenerated.
903 * aarch64-dis-2.c: Regenerated.
904 * aarch64-opc-2.c: Regenerated.
905 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
906 for SVE_SHLIMM_UNPRED_22.
907 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
908 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
909 operand.
910
fd1dc4a0
MM		 9112019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
912
913 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
914 sve_size_tsz_bhs iclass encode.
915 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
916 sve_size_tsz_bhs iclass decode.
917
31e36ab3
MM		 9182019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
919
920 * aarch64-asm-2.c: Regenerated.
921 * aarch64-dis-2.c: Regenerated.
922 * aarch64-opc-2.c: Regenerated.
923 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
924 for SVE_Zm4_11_INDEX.
925 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
926 (fields): Handle SVE_i2h field.
927 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
928 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
929
1be5f94f
MM		 9302019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
931
932 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
933 sve_shift_tsz_bhsd iclass encode.
934 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
935 sve_shift_tsz_bhsd iclass decode.
936
3c17238b
MM		 9372019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
938
939 * aarch64-asm-2.c: Regenerated.
940 * aarch64-dis-2.c: Regenerated.
941 * aarch64-opc-2.c: Regenerated.
942 * aarch64-asm.c (aarch64_ins_sve_shrimm):
943 (aarch64_encode_variant_using_iclass): Handle
944 sve_shift_tsz_hsd iclass encode.
945 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
946 sve_shift_tsz_hsd iclass decode.
947 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
948 for SVE_SHRIMM_UNPRED_22.
949 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
950 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
951 operand.
952
cd50a87a
MM		 9532019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
954
955 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
956 sve_size_013 iclass encode.
957 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
958 sve_size_013 iclass decode.
959
3c705960
MM		 9602019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
961
962 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
963 sve_size_bh iclass encode.
964 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
965 sve_size_bh iclass decode.
966
0a57e14f
MM		 9672019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
968
969 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
970 sve_size_sd2 iclass encode.
971 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
972 sve_size_sd2 iclass decode.
973 * aarch64-opc.c (fields): Handle SVE_sz2 field.
974 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
975
c469c864
MM		 9762019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
977
978 * aarch64-asm-2.c: Regenerated.
979 * aarch64-dis-2.c: Regenerated.
980 * aarch64-opc-2.c: Regenerated.
981 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
982 for SVE_ADDR_ZX.
983 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
984 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
985
116adc27
MM		 9862019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
987
988 * aarch64-asm-2.c: Regenerated.
989 * aarch64-dis-2.c: Regenerated.
990 * aarch64-opc-2.c: Regenerated.
991 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
992 for SVE_Zm3_11_INDEX.
993 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
994 (fields): Handle SVE_i3l and SVE_i3h2 fields.
995 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
996 fields.
997 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
998
3bd82c86
MM		 9992019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1000
1001 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1002 sve_size_hsd2 iclass encode.
1003 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1004 sve_size_hsd2 iclass decode.
1005 * aarch64-opc.c (fields): Handle SVE_size field.
1006 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1007
adccc507
MM		 10082019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1009
1010 * aarch64-asm-2.c: Regenerated.
1011 * aarch64-dis-2.c: Regenerated.
1012 * aarch64-opc-2.c: Regenerated.
1013 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1014 for SVE_IMM_ROT3.
1015 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1016 (fields): Handle SVE_rot3 field.
1017 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1018 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1019
5cd99750
MM		 10202019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1021
1022 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1023 instructions.
1024
7ce2460a
MM		 10252019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1026
1027 * aarch64-tbl.h
1028 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1029 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1030 aarch64_feature_sve2bitperm): New feature sets.
1031 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1032 for feature set addresses.
1033 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1034 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1035
41cee089
FS		 10362019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1037 Faraz Shahbazker <fshahbazker@wavecomp.com>
1038
1039 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1040 argument and set ASE_EVA_R6 appropriately.
1041 (set_default_mips_dis_options): Pass ISA to above.
1042 (parse_mips_dis_option): Likewise.
1043 * mips-opc.c (EVAR6): New macro.
1044 (mips_builtin_opcodes): Add llwpe, scwpe.
1045
b83b4b13
SD		 10462019-05-01 Sudakshina Das <sudi.das@arm.com>
1047
1048 * aarch64-asm-2.c: Regenerated.
1049 * aarch64-dis-2.c: Regenerated.
1050 * aarch64-opc-2.c: Regenerated.
1051 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1052 AARCH64_OPND_TME_UIMM16.
1053 (aarch64_print_operand): Likewise.
1054 * aarch64-tbl.h (QL_IMM_NIL): New.
1055 (TME): New.
1056 (_TME_INSN): New.
1057 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1058
4a90ce95
JD		 10592019-04-29 John Darrington <john@darrington.wattle.id.au>
1060
1061 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1062
a45328b9
AB		 10632019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1064 Faraz Shahbazker <fshahbazker@wavecomp.com>
1065
1066 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1067
d10be0cb
JD		 10682019-04-24 John Darrington <john@darrington.wattle.id.au>
1069
1070 * s12z-opc.h: Add extern "C" bracketing to help
1071 users who wish to use this interface in c++ code.
1072
a679f24e
JD		 10732019-04-24 John Darrington <john@darrington.wattle.id.au>
1074
1075 * s12z-opc.c (bm_decode): Handle bit map operations with the
1076 "reserved0" mode.
1077
32c36c3c
AV		 10782019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1079
1080 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1081 specifier. Add entries for VLDR and VSTR of system registers.
1082 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1083 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1084 of %J and %K format specifier.
1085
efd6b359
AV		 10862019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1087
1088 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1089 Add new entries for VSCCLRM instruction.
1090 (print_insn_coprocessor): Handle new %C format control code.
1091
6b0dd094
AV		 10922019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1093
1094 * arm-dis.c (enum isa): New enum.
1095 (struct sopcode32): New structure.
1096 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1097 set isa field of all current entries to ANY.
1098 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1099 Only match an entry if its isa field allows the current mode.
1100
4b5a202f
AV		 11012019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1102
1103 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1104 CLRM.
1105 (print_insn_thumb32): Add logic to print %n CLRM register list.
1106
60f993ce
AV		 11072019-04-15 Sudakshina Das <sudi.das@arm.com>
1108
1109 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1110 and %Q patterns.
1111
f6b2b12d
AV		 11122019-04-15 Sudakshina Das <sudi.das@arm.com>
1113
1114 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1115 (print_insn_thumb32): Edit the switch case for %Z.
1116
1889da70
AV		 11172019-04-15 Sudakshina Das <sudi.das@arm.com>
1118
1119 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1120
65d1bc05
AV		 11212019-04-15 Sudakshina Das <sudi.das@arm.com>
1122
1123 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1124
1caf72a5
AV		 11252019-04-15 Sudakshina Das <sudi.das@arm.com>
1126
1127 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1128
f1c7f421
AV		 11292019-04-15 Sudakshina Das <sudi.das@arm.com>
1130
1131 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1132 Arm register with r13 and r15 unpredictable.
1133 (thumb32_opcodes): New instructions for bfx and bflx.
1134
4389b29a
AV		 11352019-04-15 Sudakshina Das <sudi.das@arm.com>
1136
1137 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1138
e5d6e09e
AV		 11392019-04-15 Sudakshina Das <sudi.das@arm.com>
1140
1141 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1142
e12437dc
AV		 11432019-04-15 Sudakshina Das <sudi.das@arm.com>
1144
1145 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1146
031254f2
AV		 11472019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1148
1149 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1150
e5a557ac
JD		 11512019-04-12 John Darrington <john@darrington.wattle.id.au>
1152
1153 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1154 "optr". ("operator" is a reserved word in c++).
1155
bd7ceb8d
SD		 11562019-04-11 Sudakshina Das <sudi.das@arm.com>
1157
1158 * aarch64-opc.c (aarch64_print_operand): Add case for
1159 AARCH64_OPND_Rt_SP.
1160 (verify_constraints): Likewise.
1161 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1162 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1163 to accept Rt|SP as first operand.
1164 (AARCH64_OPERANDS): Add new Rt_SP.
1165 * aarch64-asm-2.c: Regenerated.
1166 * aarch64-dis-2.c: Regenerated.
1167 * aarch64-opc-2.c: Regenerated.
1168
e54010f1
SD		 11692019-04-11 Sudakshina Das <sudi.das@arm.com>
1170
1171 * aarch64-asm-2.c: Regenerated.
1172 * aarch64-dis-2.c: Likewise.
1173 * aarch64-opc-2.c: Likewise.
1174 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1175
7e96e219
RS		 11762019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1177
1178 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1179
6f2791d5
L		 11802019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1181
1182 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1183 * i386-init.h: Regenerated.
1184
e392bad3
AM		 11852019-04-07 Alan Modra <amodra@gmail.com>
1186
1187 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1188 op_separator to control printing of spaces, comma and parens
1189 rather than need_comma, need_paren and spaces vars.
1190
dffaa15c
AM		 11912019-04-07 Alan Modra <amodra@gmail.com>
1192
1193 PR 24421
1194 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1195 (print_insn_neon, print_insn_arm): Likewise.
1196
d6aab7a1
XG		 11972019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1198
1199 * i386-dis-evex.h (evex_table): Updated to support BF16
1200 instructions.
1201 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1202 and EVEX_W_0F3872_P_3.
1203 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1204 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1205 * i386-opc.h (enum): Add CpuAVX512_BF16.
1206 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1207 * i386-opc.tbl: Add AVX512 BF16 instructions.
1208 * i386-init.h: Regenerated.
1209 * i386-tbl.h: Likewise.
1210
66e85460
AM		 12112019-04-05 Alan Modra <amodra@gmail.com>
1212
1213 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1214 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1215 to favour printing of "-" branch hint when using the "y" bit.
1216 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1217
c2b1c275
AM		 12182019-04-05 Alan Modra <amodra@gmail.com>
1219
1220 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1221 opcode until first operand is output.
1222
aae9718e
PB		 12232019-04-04 Peter Bergner <bergner@linux.ibm.com>
1224
1225 PR gas/24349
1226 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1227 (valid_bo_post_v2): Add support for 'at' branch hints.
1228 (insert_bo): Only error on branch on ctr.
1229 (get_bo_hint_mask): New function.
1230 (insert_boe): Add new 'branch_taken' formal argument. Add support
1231 for inserting 'at' branch hints.
1232 (extract_boe): Add new 'branch_taken' formal argument. Add support
1233 for extracting 'at' branch hints.
1234 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1235 (BOE): Delete operand.
1236 (BOM, BOP): New operands.
1237 (RM): Update value.
1238 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1239 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1240 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1241 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1242 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1243 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1244 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1245 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1246 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1247 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1248 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1249 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1250 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1251 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1252 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1253 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1254 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1255 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1256 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1257 bttarl+>: New extended mnemonics.
1258
96a86c01
AM		 12592019-03-28 Alan Modra <amodra@gmail.com>
1260
1261 PR 24390
1262 * ppc-opc.c (BTF): Define.
1263 (powerpc_opcodes): Use for mtfsb*.
1264 * ppc-dis.c (print_insn_powerpc): Print fields with both
1265 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1266
796d6298
TC		 12672019-03-25 Tamar Christina <tamar.christina@arm.com>
1268
1269 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1270 (mapping_symbol_for_insn): Implement new algorithm.
1271 (print_insn): Remove duplicate code.
1272
60df3720
TC		 12732019-03-25 Tamar Christina <tamar.christina@arm.com>
1274
1275 * aarch64-dis.c (print_insn_aarch64):
1276 Implement override.
1277
51457761
TC		 12782019-03-25 Tamar Christina <tamar.christina@arm.com>
1279
1280 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1281 order.
1282
53b2f36b
TC		 12832019-03-25 Tamar Christina <tamar.christina@arm.com>
1284
1285 * aarch64-dis.c (last_stop_offset): New.
1286 (print_insn_aarch64): Use stop_offset.
1287
89199bb5
L		 12882019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1289
1290 PR gas/24359
1291 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1292 CPU_ANY_AVX2_FLAGS.
1293 * i386-init.h: Regenerated.
1294
97ed31ae
L		 12952019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1296
1297 PR gas/24348
1298 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1299 vmovdqu16, vmovdqu32 and vmovdqu64.
1300 * i386-tbl.h: Regenerated.
1301
0919bfe9
AK		 13022019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1303
1304 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1305 from vstrszb, vstrszh, and vstrszf.
1306
13072019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1308
1309 * s390-opc.txt: Add instruction descriptions.
1310
21820ebe
JW		 13112019-02-08 Jim Wilson <jimw@sifive.com>
1312
1313 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1314 <bne>: Likewise.
1315
f7dd2fb2
TC		 13162019-02-07 Tamar Christina <tamar.christina@arm.com>
1317
1318 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1319
6456d318
TC		 13202019-02-07 Tamar Christina <tamar.christina@arm.com>
1321
1322 PR binutils/23212
1323 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1324 * aarch64-opc.c (verify_elem_sd): New.
1325 (fields): Add FLD_sz entr.
1326 * aarch64-tbl.h (_SIMD_INSN): New.
1327 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1328 fmulx scalar and vector by element isns.
1329
4a83b610
NC		 13302019-02-07 Nick Clifton <nickc@redhat.com>
1331
1332 * po/sv.po: Updated Swedish translation.
1333
fc60b8c8
AK		 13342019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1335
1336 * s390-mkopc.c (main): Accept arch13 as cpu string.
1337 * s390-opc.c: Add new instruction formats and instruction opcode
1338 masks.
1339 * s390-opc.txt: Add new arch13 instructions.
1340
e10620d3
TC		 13412019-01-25 Sudakshina Das <sudi.das@arm.com>
1342
1343 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1344 (aarch64_opcode): Change encoding for stg, stzg
1345 st2g and st2zg.
1346 * aarch64-asm-2.c: Regenerated.
1347 * aarch64-dis-2.c: Regenerated.
1348 * aarch64-opc-2.c: Regenerated.
1349
20a4ca55
SD		 13502019-01-25 Sudakshina Das <sudi.das@arm.com>
1351
1352 * aarch64-asm-2.c: Regenerated.
1353 * aarch64-dis-2.c: Likewise.
1354 * aarch64-opc-2.c: Likewise.
1355 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1356
550fd7bf
SD		 13572019-01-25 Sudakshina Das <sudi.das@arm.com>
1358 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1359
1360 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1361 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1362 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1363 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1364 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1365 case for ldstgv_indexed.
1366 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1367 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1368 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1369 * aarch64-asm-2.c: Regenerated.
1370 * aarch64-dis-2.c: Regenerated.
1371 * aarch64-opc-2.c: Regenerated.
1372
d9938630
NC		 13732019-01-23 Nick Clifton <nickc@redhat.com>
1374
1375 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1376
375cd423
NC		 13772019-01-21 Nick Clifton <nickc@redhat.com>
1378
1379 * po/de.po: Updated German translation.
1380 * po/uk.po: Updated Ukranian translation.
1381
57299f48
CX		 13822019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1383 * mips-dis.c (mips_arch_choices): Fix typo in
1384 gs464, gs464e and gs264e descriptors.
1385
f48dfe41
NC		 13862019-01-19 Nick Clifton <nickc@redhat.com>
1387
1388 * configure: Regenerate.
1389 * po/opcodes.pot: Regenerate.
1390
f974f26c
NC		 13912018-06-24 Nick Clifton <nickc@redhat.com>
1392
1393 2.32 branch created.
1394
39f286cd
JD		 13952019-01-09 John Darrington <john@darrington.wattle.id.au>
1396
448b8ca8
JD		 1397 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
1398 if it is null.
1399 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 1400 zero.
1401
3107326d
AP		 14022019-01-09 Andrew Paprocki <andrew@ishiboo.com>
1403
1404 * configure: Regenerate.
1405
7e9ca91e
AM		 14062019-01-07 Alan Modra <amodra@gmail.com>
1407
1408 * configure: Regenerate.
1409 * po/POTFILES.in: Regenerate.
1410
ef1ad42b
JD		 14112019-01-03 John Darrington <john@darrington.wattle.id.au>
1412
1413 * s12z-opc.c: New file.
1414 * s12z-opc.h: New file.
1415 * s12z-dis.c: Removed all code not directly related to display
1416 of instructions. Used the interface provided by the new files
1417 instead.
1418 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 1419 * Makefile.in: Regenerate.
ef1ad42b 1420 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 1421 * configure: Regenerate.
ef1ad42b 1422
82704155
AM		 14232019-01-01 Alan Modra <amodra@gmail.com>
1424
1425 Update year range in copyright notice of all files.
1426
d5c04e1b 1427For older changes see ChangeLog-2018
3499769a 1428\f
d5c04e1b 1429Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 1430
1431Copying and distribution of this file, with or without modification,
1432are permitted in any medium without royalty provided the copyright
1433notice and this notice are preserved.
1434
1435Local Variables:
1436mode: change-log
1437left-margin: 8
1438fill-column: 74
1439version-control: never
1440End:
GDB Binutils - Deliverables
This page took 0.25098 seconds and 4 git commands to generate.