bfd/
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
6b6e92f4
NC
12004-05-05 Peter Barada <peter@the-baradas.com>
2
3 * m68k-dis.c(print_insn_m68k): Add new chips, use core
4 variants in arch_mask. Only set m68881/68851 for 68k chips.
5 * m68k-op.c: Switch from ColdFire chips to core variants.
6
a404d431
AM
72004-05-05 Alan Modra <amodra@bigpond.net.au>
8
9 PR 146.
10 * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
11
f3806e43
BE
122004-04-29 Ben Elliston <bje@au.ibm.com>
13
520ceea4
BE
14 * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
15 (powerpc_opcodes): Add "dbczl" instruction for PPC970.
f3806e43 16
1f1799d5
KK
172004-04-22 Kaz Kojima <kkojima@rr.iij4u.or.jp>
18
19 * sh-dis.c (print_insn_sh): Print the value in constant pool
20 as a symbol if it looks like a symbol.
21
fd99574b
NC
222004-04-22 Peter Barada <peter@the-baradas.com>
23
24 * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
25 appropriate ColdFire architectures.
26 (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
27 mask addressing.
28 Add EMAC instructions, fix MAC instructions. Remove
29 macmw/macml/msacmw/msacml instructions since mask addressing now
30 supported.
31
b4781d44
JJ
322004-04-20 Jakub Jelinek <jakub@redhat.com>
33
34 * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
35 (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
36 suffix. Use fmov*x macros, create all 3 fpsize variants in one
37 macro. Adjust all users.
38
91809fda
NC
392004-04-15 Anil Paranjpe <anilp1@kpitcummins.com>
40
41 * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
42 separately.
43
f4453dfa
NC
442004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
45
46 * m32r-asm.c: Regenerate.
47
9b0de91a
SS
482004-03-29 Stan Shebs <shebs@apple.com>
49
50 * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
51 used.
52
e20c0b3d
AM
532004-03-19 Alan Modra <amodra@bigpond.net.au>
54
55 * aclocal.m4: Regenerate.
56 * config.in: Regenerate.
57 * configure: Regenerate.
58 * po/POTFILES.in: Regenerate.
59 * po/opcodes.pot: Regenerate.
60
fdd12ef3
AM
612004-03-16 Alan Modra <amodra@bigpond.net.au>
62
63 * ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
64 PPC_OPERANDS_GPR_0.
65 * ppc-opc.c (RA0): Define.
66 (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
67 (RAOPT): Rename from RAO. Update all uses.
a9c3619e 68 (powerpc_opcodes): Use RA0 as appropriate.
fdd12ef3 69
2dc111b3 702004-03-15 Aldy Hernandez <aldyh@redhat.com>
fdd12ef3
AM
71
72 * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
2dc111b3 73
7bfeee7b
AM
742004-03-15 Alan Modra <amodra@bigpond.net.au>
75
76 * sparc-dis.c (print_insn_sparc): Update getword prototype.
77
7ffdda93
ML
782004-03-12 Michal Ludvig <mludvig@suse.cz>
79
80 * i386-dis.c (GRPPLOCK): Delete.
7bfeee7b 81 (grps): Delete GRPPLOCK entry.
7ffdda93 82
cc0ec051
AM
832004-03-12 Alan Modra <amodra@bigpond.net.au>
84
85 * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
86 (M, Mp): Use OP_M.
87 (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
88 (GRPPADLCK): Define.
89 (dis386): Use NOP_Fixup on "nop".
90 (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
91 (twobyte_has_modrm): Set for 0xa7.
92 (padlock_table): Delete. Move to..
93 (grps): ..here, using OP_0f07. Use OP_Ofae on lfence, mfence
94 and clflush.
95 (print_insn): Revert PADLOCK_SPECIAL code.
96 (OP_E): Delete sfence, lfence, mfence checks.
97
4fd61dcb
JJ
982004-03-12 Jakub Jelinek <jakub@redhat.com>
99
100 * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
101 (INVLPG_Fixup): New function.
102 (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
103
0f10071e
ML
1042004-03-12 Michal Ludvig <mludvig@suse.cz>
105
106 * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
107 (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
108 (padlock_table): New struct with PadLock instructions.
109 (print_insn): Handle PADLOCK_SPECIAL.
110
c02908d2
AM
1112004-03-12 Alan Modra <amodra@bigpond.net.au>
112
113 * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
114 (OP_E): Twiddle clflush to sfence here.
115
d5bb7600
NC
1162004-03-08 Nick Clifton <nickc@redhat.com>
117
118 * po/de.po: Updated German translation.
119
ae51a426
JR
1202003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>
121
122 * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
123 nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu.
124 * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
125 accordingly.
126
676a64f4
RS
1272004-03-01 Richard Sandiford <rsandifo@redhat.com>
128
129 * frv-asm.c: Regenerate.
130 * frv-desc.c: Regenerate.
131 * frv-desc.h: Regenerate.
132 * frv-dis.c: Regenerate.
133 * frv-ibld.c: Regenerate.
134 * frv-opc.c: Regenerate.
135 * frv-opc.h: Regenerate.
136
c7a48b9a
RS
1372004-03-01 Richard Sandiford <rsandifo@redhat.com>
138
139 * frv-desc.c, frv-opc.c: Regenerate.
140
8ae0baa2
RS
1412004-03-01 Richard Sandiford <rsandifo@redhat.com>
142
143 * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
144
ce11586c
JR
1452004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
146
147 * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
148 Also correct mistake in the comment.
149
6a5709a5
JR
1502004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
151
152 * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
153 ensure that double registers have even numbers.
154 Add REG_N_B01 for nn01 (binary 01) nibble to ensure
155 that reserved instruction 0xfffd does not decode the same
156 as 0xfdfd (ftrv).
157 * sh-opc.h: Add REG_N_D nibble type and use it whereever
158 REG_N refers to a double register.
159 Add REG_N_B01 nibble type and use it instead of REG_NM
160 in ftrv.
161 Adjust the bit patterns in a few comments.
162
e5d2b64f 1632004-02-25 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM
164
165 * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
e5d2b64f 166
1f04b05f
AH
1672004-02-20 Aldy Hernandez <aldyh@redhat.com>
168
169 * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
170
2f3b8700
AH
1712004-02-20 Aldy Hernandez <aldyh@redhat.com>
172
173 * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
174
f0b26da6 1752004-02-20 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM
176
177 * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
178 mtivor32, mtivor33, mtivor34.
f0b26da6 179
23d59c56 1802004-02-19 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM
181
182 * ppc-opc.c (powerpc_opcodes): Add mfmcar.
23d59c56 183
34920d91
NC
1842004-02-10 Petko Manolov <petkan@nucleusys.com>
185
186 * arm-opc.h Maverick accumulator register opcode fixes.
187
44d86481
BE
1882004-02-13 Ben Elliston <bje@wasabisystems.com>
189
190 * m32r-dis.c: Regenerate.
191
17707c23
MS
1922004-01-27 Michael Snyder <msnyder@redhat.com>
193
194 * sh-opc.h (sh_table): "fsrra", not "fssra".
195
fe3a9bc4
NC
1962004-01-23 Andrew Over <andrew.over@cs.anu.edu.au>
197
198 * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
199 contraints.
200
ff24f124
JJ
2012004-01-19 Andrew Over <andrew.over@cs.anu.edu.au>
202
203 * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
204
a02a862a
AM
2052004-01-19 Alan Modra <amodra@bigpond.net.au>
206
207 * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
208 1. Don't print scale factor on AT&T mode when index missing.
209
d164ea7f
AO
2102004-01-16 Alexandre Oliva <aoliva@redhat.com>
211
212 * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
213 when loaded into XR registers.
214
cb10e79a
RS
2152004-01-14 Richard Sandiford <rsandifo@redhat.com>
216
217 * frv-desc.h: Regenerate.
218 * frv-desc.c: Regenerate.
219 * frv-opc.c: Regenerate.
220
f532f3fa
MS
2212004-01-13 Michael Snyder <msnyder@redhat.com>
222
223 * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
224
e45d0630
PB
2252004-01-09 Paul Brook <paul@codesourcery.com>
226
227 * arm-opc.h (arm_opcodes): Move generic mcrr after known
228 specific opcodes.
229
3ba7a1aa
DJ
2302004-01-07 Daniel Jacobowitz <drow@mvista.com>
231
232 * Makefile.am (libopcodes_la_DEPENDENCIES)
233 (libopcodes_la_LIBADD): Revert 2003-05-17 change. Add explanatory
234 comment about the problem.
235 * Makefile.in: Regenerate.
236
ba2d3f07
AO
2372004-01-06 Alexandre Oliva <aoliva@redhat.com>
238
239 2003-12-19 Alexandre Oliva <aoliva@redhat.com>
240 * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
241 cut&paste errors in shifting/truncating numerical operands.
242 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
243 * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
244 (parse_uslo16): Likewise.
245 (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
246 (parse_d12): Parse gotoff12 and gotofffuncdesc12.
247 (parse_s12): Likewise.
248 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
249 * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
250 (parse_uslo16): Likewise.
251 (parse_uhi16): Parse gothi and gotfuncdeschi.
252 (parse_d12): Parse got12 and gotfuncdesc12.
253 (parse_s12): Likewise.
254
3ab48931
NC
2552004-01-02 Albert Bartoszko <albar@nt.kegel.com.pl>
256
257 * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
258 instruction which looks similar to an 'rla' instruction.
a0bd404e 259
c9e214e5 260For older changes see ChangeLog-0203
252b5132
RH
261\f
262Local Variables:
2f6d2f85
NC
263mode: change-log
264left-margin: 8
265fill-column: 74
252b5132
RH
266version-control: never
267End:
This page took 0.247051 seconds and 4 git commands to generate.