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Set EI_OSABI to ELFOSABI_GNU for local IFUNC symbols
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
40fc1451
SD		 12015-08-12 Simon Dardis <simon.dardis@imgtec.com>
2
3 * micromips-opc.c (micromips_opcodes): Re-order table so that move
4 based on 'or' is first.
5 * mips-opc.c (mips_builtin_opcodes): Ditto.
6
922c5db5
NC		 72015-08-11 Nick Clifton <nickc@redhat.com>
8
9 PR 18800
10 * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
11 instruction.
12
75fb7498
RS		 132015-08-10 Robert Suchanek <robert.suchanek@imgtec.com>
14
15 * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
16
36aed29d
AP		 172015-08-07 Amit Pawar <Amit.Pawar@amd.com>
18
19 * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
20 * i386-init.h: Regenerated.
21
a8484f96
L		 222015-07-30 H.J. Lu <hongjiu.lu@intel.com>
23
24 PR binutils/13571
25 * i386-dis.c (MOD_0FC3): New.
26 (PREFIX_0FC3): Renamed to ...
27 (PREFIX_MOD_0_0FC3): This.
28 (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
29 (prefix_table): Replace Ma with Ev on movntiS.
30 (mod_table): Add MOD_0FC3.
31
37a42ee9
L		 322015-07-27 H.J. Lu <hongjiu.lu@intel.com>
33
34 * configure: Regenerated.
35
070fe95d
AM		 362015-07-23 Alan Modra <amodra@gmail.com>
37
38 PR 18708
39 * i386-dis.c (get64): Avoid signed integer overflow.
40
20c2a615
L		 412015-07-22 Alexander Fomin <alexander.fomin@intel.com>
42
43 PR binutils/18631
44 * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
45 "EXEvexHalfBcstXmmq" for the second operand.
46 (EVEX_W_0F79_P_2): Likewise.
47 (EVEX_W_0F7A_P_2): Likewise.
48 (EVEX_W_0F7B_P_2): Likewise.
49
6f1c2142
AM		 502015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
51
52 * arm-dis.c (print_insn_coprocessor): Added support for quarter
53 float bitfield format.
54 (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
55 quarter float bitfield format.
56
8a643cc3
L		 572015-07-14 H.J. Lu <hongjiu.lu@intel.com>
58
59 * configure: Regenerated.
60
ef5a96d5
AM		 612015-07-03 Alan Modra <amodra@gmail.com>
62
63 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
64 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
65 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
66
c8c8175b
SL		 672015-07-01 Sandra Loosemore <sandra@codesourcery.com>
68 Cesar Philippidis <cesar@codesourcery.com>
69
70 * nios2-dis.c (nios2_extract_opcode): New.
71 (nios2_disassembler_state): New.
72 (nios2_find_opcode_hash): Use mach parameter to select correct
73 disassembler state.
74 (nios2_print_insn_arg): Extend to support new R2 argument letters
75 and formats.
76 (print_insn_nios2): Check for 16-bit instruction at end of memory.
77 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
78 (NIOS2_NUM_OPCODES): Rename to...
79 (NIOS2_NUM_R1_OPCODES): This.
80 (nios2_r2_opcodes): New.
81 (NIOS2_NUM_R2_OPCODES): New.
82 (nios2_num_r2_opcodes): New.
83 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
84 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
85 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
86 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
87 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
88
9916071f
AP		 892015-06-30 Amit Pawar <Amit.Pawar@amd.com>
90
91 * i386-dis.c (OP_Mwaitx): New.
92 (rm_table): Add monitorx/mwaitx.
93 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
94 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
95 (operand_type_init): Add CpuMWAITX.
96 * i386-opc.h (CpuMWAITX): New.
97 (i386_cpu_flags): Add cpumwaitx.
98 * i386-opc.tbl: Add monitorx and mwaitx.
99 * i386-init.h: Regenerated.
100 * i386-tbl.h: Likewise.
101
7b934113
PB		 1022015-06-22 Peter Bergner <bergner@vnet.ibm.com>
103
104 * ppc-opc.c (insert_ls): Test for invalid LS operands.
105 (insert_esync): New function.
106 (LS, WC): Use insert_ls.
107 (ESYNC): Use insert_esync.
108
bdc4de1b
NC		 1092015-06-22 Nick Clifton <nickc@redhat.com>
110
111 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
112 requested region lies beyond it.
113 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
114 looking for 32-bit insns.
115 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
116 data.
117 * sh-dis.c (print_insn_sh): Likewise.
118 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
119 blocks of instructions.
120 * vax-dis.c (print_insn_vax): Check that the requested address
121 does not clash with the stop_vma.
122
11a0cf2e
PB		 1232015-06-19 Peter Bergner <bergner@vnet.ibm.com>
124
070fe95d 125 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
11a0cf2e
PB		 126 * ppc-opc.c (FXM4): Add non-zero optional value.
127 (TBR): Likewise.
128 (SXL): Likewise.
129 (insert_fxm): Handle new default operand value.
130 (extract_fxm): Likewise.
131 (insert_tbr): Likewise.
132 (extract_tbr): Likewise.
133
bdfa8b95
MW		 1342015-06-16 Matthew Wahab <matthew.wahab@arm.com>
135
136 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
137
24b4cf66
SN		 1382015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
139
140 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
141
99a2c561
PB		 1422015-06-12 Peter Bergner <bergner@vnet.ibm.com>
143
144 * ppc-opc.c: Add comment accidentally removed by old commit.
145 (MTMSRD_L): Delete.
146
40f77f82
AM		 1472015-06-04 Peter Bergner <bergner@vnet.ibm.com>
148
149 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
150
13be46a2
NC		 1512015-06-04 Nick Clifton <nickc@redhat.com>
152
153 PR 18474
154 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
155
ddfded2f
MW		 1562015-06-02 Matthew Wahab <matthew.wahab@arm.com>
157
158 * arm-dis.c (arm_opcodes): Add "setpan".
159 (thumb_opcodes): Add "setpan".
160
1af1dd51
MW		 1612015-06-02 Matthew Wahab <matthew.wahab@arm.com>
162
163 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
164 macros.
165
9e1f0fa7
MW		 1662015-06-02 Matthew Wahab <matthew.wahab@arm.com>
167
168 * aarch64-tbl.h (aarch64_feature_rdma): New.
169 (RDMA): New.
170 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
171 * aarch64-asm-2.c: Regenerate.
172 * aarch64-dis-2.c: Regenerate.
173 * aarch64-opc-2.c: Regenerate.
174
290806fd
MW		 1752015-06-02 Matthew Wahab <matthew.wahab@arm.com>
176
177 * aarch64-tbl.h (aarch64_feature_lor): New.
178 (LOR): New.
179 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
180 "stllrb", "stllrh".
181 * aarch64-asm-2.c: Regenerate.
182 * aarch64-dis-2.c: Regenerate.
183 * aarch64-opc-2.c: Regenerate.
184
f21cce2c
MW		 1852015-06-01 Matthew Wahab <matthew.wahab@arm.com>
186
187 * aarch64-opc.c (F_ARCHEXT): New.
188 (aarch64_sys_regs): Add "pan".
189 (aarch64_sys_reg_supported_p): New.
190 (aarch64_pstatefields): Add "pan".
191 (aarch64_pstatefield_supported_p): New.
192
d194d186
JB		 1932015-06-01 Jan Beulich <jbeulich@suse.com>
194
195 * i386-tbl.h: Regenerate.
196
3a8547d2
JB		 1972015-06-01 Jan Beulich <jbeulich@suse.com>
198
199 * i386-dis.c (print_insn): Swap rounding mode specifier and
200 general purpose register in Intel mode.
201
015c54d5
JB		 2022015-06-01 Jan Beulich <jbeulich@suse.com>
203
204 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
205 * i386-tbl.h: Regenerate.
206
071f0063
L		 2072015-05-18 H.J. Lu <hongjiu.lu@intel.com>
208
209 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
210 * i386-init.h: Regenerated.
211
5db04b09
L		 2122015-05-15 H.J. Lu <hongjiu.lu@intel.com>
213
214 PR binutis/18386
215 * i386-dis.c: Add comments for '@'.
216 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
217 (enum x86_64_isa): New.
218 (isa64): Likewise.
219 (print_i386_disassembler_options): Add amd64 and intel64.
220 (print_insn): Handle amd64 and intel64.
221 (putop): Handle '@'.
222 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
223 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
224 * i386-opc.h (AMD64): New.
225 (CpuIntel64): Likewise.
226 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
227 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
228 Mark direct call/jmp without Disp16|Disp32 as Intel64.
229 * i386-init.h: Regenerated.
230 * i386-tbl.h: Likewise.
231
4bc0608a
PB		 2322015-05-14 Peter Bergner <bergner@vnet.ibm.com>
233
234 * ppc-opc.c (IH) New define.
235 (powerpc_opcodes) <wait>: Do not enable for POWER7.
236 <tlbie>: Add RS operand for POWER7.
237 <slbia>: Add IH operand for POWER6.
238
70cead07
L		 2392015-05-11 H.J. Lu <hongjiu.lu@intel.com>
240
241 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
242 direct branch.
243 (jmp): Likewise.
244 * i386-tbl.h: Regenerated.
245
7b6d09fb
L		 2462015-05-11 H.J. Lu <hongjiu.lu@intel.com>
247
248 * configure.ac: Support bfd_iamcu_arch.
249 * disassemble.c (disassembler): Support bfd_iamcu_arch.
250 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
251 CPU_IAMCU_COMPAT_FLAGS.
252 (cpu_flags): Add CpuIAMCU.
253 * i386-opc.h (CpuIAMCU): New.
254 (i386_cpu_flags): Add cpuiamcu.
255 * configure: Regenerated.
256 * i386-init.h: Likewise.
257 * i386-tbl.h: Likewise.
258
31955f99
L		 2592015-05-08 H.J. Lu <hongjiu.lu@intel.com>
260
261 PR binutis/18386
262 * i386-dis.c (X86_64_E8): New.
263 (X86_64_E9): Likewise.
264 Update comments on 'T', 'U', 'V'. Add comments for '^'.
265 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
266 (x86_64_table): Add X86_64_E8 and X86_64_E9.
267 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
268 (putop): Handle '^'.
269 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
270 REX_W.
271
0952813b
DD		 2722015-04-30 DJ Delorie <dj@redhat.com>
273
274 * disassemble.c (disassembler): Choose suitable disassembler based
275 on E_ABI.
276 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
277 it to decode mul/div insns.
278 * rl78-decode.c: Regenerate.
279 * rl78-dis.c (print_insn_rl78): Rename to...
280 (print_insn_rl78_common): ...this, take ISA parameter.
281 (print_insn_rl78): New.
282 (print_insn_rl78_g10): New.
283 (print_insn_rl78_g13): New.
284 (print_insn_rl78_g14): New.
285 (rl78_get_disassembler): New.
286
f9d3ecaa
NC		 2872015-04-29 Nick Clifton <nickc@redhat.com>
288
289 * po/fr.po: Updated French translation.
290
4fff86c5
PB		 2912015-04-27 Peter Bergner <bergner@vnet.ibm.com>
292
293 * ppc-opc.c (DCBT_EO): New define.
294 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
295 <lharx>: Likewise.
296 <stbcx.>: Likewise.
297 <sthcx.>: Likewise.
298 <waitrsv>: Do not enable for POWER7 and later.
299 <waitimpl>: Likewise.
300 <dcbt>: Default to the two operand form of the instruction for all
301 "old" cpus. For "new" cpus, use the operand ordering that matches
302 whether the cpu is server or embedded.
303 <dcbtst>: Likewise.
304
3b78cfe1
AK		 3052015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
306
307 * s390-opc.c: New instruction type VV0UU2.
308 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
309 and WFC.
310
04d824a4
JB		 3112015-04-23 Jan Beulich <jbeulich@suse.com>
312
313 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
314 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
315 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
316 (vfpclasspd, vfpclassps): Add %XZ.
317
09708981
L		 3182015-04-15 H.J. Lu <hongjiu.lu@intel.com>
319
320 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
321 (PREFIX_UD_REPZ): Likewise.
322 (PREFIX_UD_REPNZ): Likewise.
323 (PREFIX_UD_DATA): Likewise.
324 (PREFIX_UD_ADDR): Likewise.
325 (PREFIX_UD_LOCK): Likewise.
326
3888916d
L		 3272015-04-15 H.J. Lu <hongjiu.lu@intel.com>
328
329 * i386-dis.c (prefix_requirement): Removed.
330 (print_insn): Don't set prefix_requirement. Check
331 dp->prefix_requirement instead of prefix_requirement.
332
f24bcbaa
L		 3332015-04-15 H.J. Lu <hongjiu.lu@intel.com>
334
335 PR binutils/17898
336 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
337 (PREFIX_MOD_0_0FC7_REG_6): This.
338 (PREFIX_MOD_3_0FC7_REG_6): New.
339 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
340 (prefix_table): Replace PREFIX_0FC7_REG_6 with
341 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
342 PREFIX_MOD_3_0FC7_REG_7.
343 (mod_table): Replace PREFIX_0FC7_REG_6 with
344 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
345 PREFIX_MOD_3_0FC7_REG_7.
346
507bd325
L		 3472015-04-15 H.J. Lu <hongjiu.lu@intel.com>
348
349 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
350 (PREFIX_MANDATORY_REPNZ): Likewise.
351 (PREFIX_MANDATORY_DATA): Likewise.
352 (PREFIX_MANDATORY_ADDR): Likewise.
353 (PREFIX_MANDATORY_LOCK): Likewise.
354 (PREFIX_MANDATORY): Likewise.
355 (PREFIX_UD_SHIFT): Set to 8
356 (PREFIX_UD_REPZ): Updated.
357 (PREFIX_UD_REPNZ): Likewise.
358 (PREFIX_UD_DATA): Likewise.
359 (PREFIX_UD_ADDR): Likewise.
360 (PREFIX_UD_LOCK): Likewise.
361 (PREFIX_IGNORED_SHIFT): New.
362 (PREFIX_IGNORED_REPZ): Likewise.
363 (PREFIX_IGNORED_REPNZ): Likewise.
364 (PREFIX_IGNORED_DATA): Likewise.
365 (PREFIX_IGNORED_ADDR): Likewise.
366 (PREFIX_IGNORED_LOCK): Likewise.
367 (PREFIX_OPCODE): Likewise.
368 (PREFIX_IGNORED): Likewise.
369 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
370 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
371 (three_byte_table): Likewise.
372 (mod_table): Likewise.
373 (mandatory_prefix): Renamed to ...
374 (prefix_requirement): This.
375 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
376 Update PREFIX_90 entry.
377 (get_valid_dis386): Check prefix_requirement to see if a prefix
378 should be ignored.
379 (print_insn): Replace mandatory_prefix with prefix_requirement.
380
f0fba320
RL		 3812015-04-15 Renlin Li <renlin.li@arm.com>
382
383 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
384 use it for ssat and ssat16.
385 (print_insn_thumb32): Add handle case for 'D' control code.
386
bf890a93
IT		 3872015-04-06 Ilya Tocar <ilya.tocar@intel.com>
388 H.J. Lu <hongjiu.lu@intel.com>
389
390 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
391 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
392 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
393 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
394 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
395 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
396 Fill prefix_requirement field.
397 (struct dis386): Add prefix_requirement field.
398 (dis386): Fill prefix_requirement field.
399 (dis386_twobyte): Ditto.
400 (twobyte_has_mandatory_prefix_: Remove.
401 (reg_table): Fill prefix_requirement field.
402 (prefix_table): Ditto.
403 (x86_64_table): Ditto.
404 (three_byte_table): Ditto.
405 (xop_table): Ditto.
406 (vex_table): Ditto.
407 (vex_len_table): Ditto.
408 (vex_w_table): Ditto.
409 (mod_table): Ditto.
410 (bad_opcode): Ditto.
411 (print_insn): Use prefix_requirement.
412 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
413 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
414 (float_reg): Ditto.
415
2f783c1f
MF		 4162015-03-30 Mike Frysinger <vapier@gentoo.org>
417
418 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
419
b9d94d62
L		 4202015-03-29 H.J. Lu <hongjiu.lu@intel.com>
421
422 * Makefile.in: Regenerated.
423
27c49e9a
AB		 4242015-03-25 Anton Blanchard <anton@samba.org>
425
426 * ppc-dis.c (disassemble_init_powerpc): Only initialise
427 powerpc_opcd_indices and vle_opcd_indices once.
428
c4e676f1
AB		 4292015-03-25 Anton Blanchard <anton@samba.org>
430
431 * ppc-opc.c (powerpc_opcodes): Add slbfee.
432
823d2571
TG		 4332015-03-24 Terry Guo <terry.guo@arm.com>
434
435 * arm-dis.c (opcode32): Updated to use new arm feature struct.
436 (opcode16): Likewise.
437 (coprocessor_opcodes): Replace bit with feature struct.
438 (neon_opcodes): Likewise.
439 (arm_opcodes): Likewise.
440 (thumb_opcodes): Likewise.
441 (thumb32_opcodes): Likewise.
442 (print_insn_coprocessor): Likewise.
443 (print_insn_arm): Likewise.
444 (select_arm_features): Follow new feature struct.
445
029f3522
GG		 4462015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
447
448 * i386-dis.c (rm_table): Add clzero.
449 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
450 Add CPU_CLZERO_FLAGS.
451 (cpu_flags): Add CpuCLZERO.
452 * i386-opc.h: Add CpuCLZERO.
453 * i386-opc.tbl: Add clzero.
454 * i386-init.h: Re-generated.
455 * i386-tbl.h: Re-generated.
456
6914869a
AB		 4572015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
458
459 * mips-opc.c (decode_mips_operand): Fix constraint issues
460 with u and y operands.
461
21e20815
AB		 4622015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
463
464 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
465
6b1d7593
AK		 4662015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
467
468 * s390-opc.c: Add new IBM z13 instructions.
469 * s390-opc.txt: Likewise.
470
c8f89a34
JW		 4712015-03-10 Renlin Li <renlin.li@arm.com>
472
473 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
474 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
475 related alias.
476 * aarch64-asm-2.c: Regenerate.
477 * aarch64-dis-2.c: Likewise.
478 * aarch64-opc-2.c: Likewise.
479
d8282f0e
JW		 4802015-03-03 Jiong Wang <jiong.wang@arm.com>
481
482 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
483
ac994365
OE		 4842015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
485
486 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
487 arch_sh_up.
488 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
489 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
490
fd63f640
V		 4912015-02-23 Vinay <Vinay.G@kpit.com>
492
493 * rl78-decode.opc (MOV): Added space between two operands for
494 'mov' instruction in index addressing mode.
495 * rl78-decode.c: Regenerate.
496
f63c1776
PA		 4972015-02-19 Pedro Alves <palves@redhat.com>
498
499 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
500
07774fcc
PA		 5012015-02-10 Pedro Alves <palves@redhat.com>
502 Tom Tromey <tromey@redhat.com>
503
504 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
505 microblaze_and, microblaze_xor.
506 * microblaze-opc.h (opcodes): Adjust.
507
3f8107ab
AM		 5082015-01-28 James Bowman <james.bowman@ftdichip.com>
509
510 * Makefile.am: Add FT32 files.
511 * configure.ac: Handle FT32.
512 * disassemble.c (disassembler): Call print_insn_ft32.
513 * ft32-dis.c: New file.
514 * ft32-opc.c: New file.
515 * Makefile.in: Regenerate.
516 * configure: Regenerate.
517 * po/POTFILES.in: Regenerate.
518
e5fe4957
KLC		 5192015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
520
521 * nds32-asm.c (keyword_sr): Add new system registers.
522
1e2e8c52
AK		 5232015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
524
525 * s390-dis.c (s390_extract_operand): Support vector register
526 operands.
527 (s390_print_insn_with_opcode): Support new operands types and add
528 new handling of optional operands.
529 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
530 and include opcode/s390.h instead.
531 (struct op_struct): New field `flags'.
532 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
533 (dumpTable): Dump flags.
534 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
535 string.
536 * s390-opc.c: Add new operands types, instruction formats, and
537 instruction masks.
538 (s390_opformats): Add new formats for .insn.
539 * s390-opc.txt: Add new instructions.
540
b90efa5b 5412015-01-01 Alan Modra <amodra@gmail.com>
bffb6004 542
b90efa5b 543 Update year range in copyright notice of all files.
bffb6004 544
b90efa5b 545For older changes see ChangeLog-2014
252b5132 546\f
b90efa5b 547Copyright (C) 2015 Free Software Foundation, Inc.
752937aa
NC		 548
549Copying and distribution of this file, with or without modification,
550are permitted in any medium without royalty provided the copyright
551notice and this notice are preserved.
552
252b5132 553Local Variables:
2f6d2f85
NC		 554mode: change-log
555left-margin: 8
556fill-column: 74
252b5132
RH		 557version-control: never
558End:
GDB Binutils - Deliverables
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