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a1a280bb
DD		 12005-10-21 DJ Delorie <dj@redhat.com>
2
3 * m32c-asm.c: Regenerate.
4 * m32c-desc.c: Regenerate.
5 * m32c-desc.h: Regenerate.
6 * m32c-dis.c: Regenerate.
7 * m32c-ibld.c: Regenerate.
8 * m32c-opc.c: Regenerate.
9 * m32c-opc.h: Regenerate.
10
b7d48530
NC		 112005-10-21 Nick Clifton <nickc@redhat.com>
12
13 * bfin-dis.c: Tidy up code, removing redundant constructs.
14
8dd744b6
MS		 152005-10-19 Martin Schwidefsky <schwidefsky@de.ibm.com>
16
17 * s390-opc.txt: Add unnormalized hfp multiply and multiply-and-add
18 instructions.
19
e74eb924
NC		 202005-10-18 Nick Clifton <nickc@redhat.com>
21
22 * m32r-asm.c: Regenerate after updating m32r.opc.
23
471e4e36
JZ		 242005-10-18 Jie Zhang <jie.zhang@analog.com>
25
26 * bfin-dis.c (print_insn_bfin): Do proper endian transform when
27 reading instruction from memory.
28
5e03663f
NC		 292005-10-18 Nick Clifton <nickc@redhat.com>
30
31 * m32r-asm.c: Regenerate after updating m32r.opc.
32
ab7c9a26
NC		 332005-10-14 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
34
35 * m32r-asm.c: Regenerate after updating m32r.opc.
36
19590ef7
RE		 372005-10-08 James Lemke <jim@wasabisystems.com>
38
39 * arm-dis.c (coprocessor_opcodes): Fix mask for various Maverick CDP
40 operations.
41
6edfbbad
DJ		 422005-10-06 Daniel Jacobowitz <dan@codesourcery.com>
43
44 * ppc-dis.c (struct dis_private): Remove.
45 (powerpc_dialect): Avoid aliasing warnings.
46 (print_insn_big_powerpc, print_insn_little_powerpc): Likewise.
47
095f2843
NC		 482005-09-30 Nick Clifton <nickc@redhat.com>
49
50 * po/ga.po: New Irish translation.
51 * configure.in (ALL_LINGUAS): Add "ga".
52 * configure: Regenerate.
53
fdd3b9b3
L		 542005-09-30 H.J. Lu <hongjiu.lu@intel.com>
55
56 * Makefile.am: Run "make dep-am".
57 * Makefile.in: Regenerated.
58 * aclocal.m4: Likewise.
59 * configure: Likewise.
60
4b7f6baa
CM		 612005-09-30 Catherine Moore <clm@cm00re.com>
62
63 * Makefile.am: Bfin support.
64 * Makefile.in: Regenerated.
65 * aclocal.m4: Regenerated.
66 * bfin-dis.c: New file.
67 * configure.in: Bfin support.
68 * configure: Regenerated.
69 * disassemble.c (ARCH_bfin): Define.
70 (disassembler): Add case for bfd_arch_bfin.
71
1a114b12
JB		 722005-09-28 Jan Beulich <jbeulich@novell.com>
73
74 * i386-dis.c (stack_v_mode): Renamed from branch_v_mode.
75 (indirEv): Use it.
76 (stackEv): New.
77 (Ob64, Ov64): Rename to Ob, Ov. Delete unused original definitions.
78 (dis386): Document and use new 'V' meta character. Use it for
79 single-byte push/pop opcode forms. Use stackEv for mod-r/m push/pop
80 opcode forms. Correct typo in 'pop ss'. Replace Ob64/Ov64 by Ob/Ov.
81 (putop): 'q' suffix for 'T' and 'U' meta depends on DFLAG. Mark
82 data prefix as used whenever DFLAG was examined. Handle 'V'.
83 (intel_operand_size): Use stack_v_mode.
84 (OP_E): Use stack_v_mode, but handle only the special case of
85 64-bit mode without operand size override here; fall through to
86 v_mode case otherwise.
87 (OP_REG): Special case rAX_reg ... rDI_reg only when 64-bit mode
88 and no operand size override is present.
89 (OP_J): Use get32s for obtaining the displacement also when rex64
90 is present.
91
3eb17e6b
PB		 922005-09-08 Paul Brook <paul@codesourcery.com>
93
94 * arm-dis.c (arm_opcodes, thumb32_opcodes): Rename smi to smc.
95
61cc0267
CF		 962005-09-06 Chao-ying Fu <fu@mips.com>
97
98 * mips-opc.c (MT32): New define.
99 (mips_builtin_opcodes): Move "bc0f", "bc0fl", "bc0t", "bc0tl" to the
100 bottom to avoid opcode collision with "mftr" and "mttr".
101 Add MT instructions.
102 * mips-dis.c (mips_arch_choices): Enable INSN_MT for mips32r2.
103 (print_insn_args): Add supports for +t, +T, !, $, *, &, g operand
104 formats.
105
b13dd07a
PB		 1062005-09-02 Paul Brook <paul@codesourcery.com>
107
108 * arm-dis.c (coprocessor_opcodes): Add null terminator.
109
8f06b2d8
PB		 1102005-09-02 Paul Brook <paul@codesourcery.com>
111
112 * arm-dis.c (coprocessor_opcodes): New.
113 (arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
114 (print_insn_coprocessor): New function.
115 (print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
116 format characters.
117 (print_insn_thumb32): Use print_insn_coprocessor.
118
a2dfd01f
PB		 1192005-08-30 Paul Brook <paul@codesourcery.com>
120
121 * arm-dis.c (thumb_opcodes): Disassemble sub(3) as subs.
122
3f31e633
JB		 1232005-08-26 Jan Beulich <jbeulich@novell.com>
124
125 * i386-dis.c (intel_operand_size): New, broken out from OP_E for
126 re-use.
127 (OP_E): Call intel_operand_size, move call site out of mode
128 dependent code.
129 (OP_OFF): Call intel_operand_size if suffix_always. Remove
130 ATTRIBUTE_UNUSED from parameters.
131 (OP_OFF64): Likewise.
132 (OP_ESreg): Call intel_operand_size.
133 (OP_DSreg): Likewise.
134 (OP_DIR): Use colon rather than semicolon as separator of far
135 jump/call operands.
136
fd25c5a9
CF		 1372005-08-25 Chao-ying Fu <fu@mips.com>
138
139 * mips-opc.c (WR_a, RD_a, MOD_a, DSP_VOLA, D32): New define.
140 (mips_builtin_opcodes): Add DSP instructions.
141 * mips-dis.c (mips_arch_choices): Enable INSN_DSP for mips32, mips32r2,
142 mips64, mips64r2.
143 (print_insn_args): Add supports for 3, 4, 5, 6, 7, 8, 9, 0, :, ', @
144 operand formats.
145
dd8b7c22
DU		 1462005-08-23 David Ung <davidu@mips.com>
147
148 * mips16-opc.c (mips16_opcodes): Add the MIPS16e jalrc/jrc
149 instructions to the table.
150
c17ae8a2
AM		 1512005-08-18 Alan Modra <amodra@bigpond.net.au>
152
848cf006 153 * a29k-dis.c: Delete.
c17ae8a2
AM		 154 * Makefile.am: Remove a29k support.
155 * configure.in: Likewise.
156 * disassemble.c: Likewise.
157 * Makefile.in: Regenerate.
158 * configure: Regenerate.
159 * po/POTFILES.in: Regenerate.
160
36ae0db3
DJ		 1612005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
162
163 * ppc-dis.c (powerpc_dialect): Handle e300.
164 (print_ppc_disassembler_options): Likewise.
165 * ppc-opc.c (PPCE300): Define.
166 (powerpc_opcodes): Mark icbt as available for the e300.
167
63a3357b
DA		 1682005-08-13 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
169
170 * hppa-dis.c (print_insn_hppa): Don't print '%' before register names.
171 Use "rp" instead of "%r2" in "b,l" insns.
172
ad101263
MS		 1732005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
174
175 * s390-dis.c (print_insn_s390): Print unsigned operands with %u.
176 * s390-mkopc.c (s390_opcode_cpu_val): Add support for cpu type z9-109.
177 (main): Likewise.
178 * s390-opc.c (I32_16, U32_16, M_16): Add defines 32 bit immediates
179 and 4 bit optional masks.
180 (INSTR_RIL_RI, INSTR_RIL_RU, INSTR_RRF_M0RR, INSTR_RSE_CCRD,
181 INSTR_RSY_CCRD, INSTR_SSF_RRDRD): Add new instruction formats.
182 (MASK_RIL_RI, MASK_RIL_RU, MASK_RRF_M0RR, MASK_RSE_CCRD,
183 MASK_RSY_CCRD, MASK_SSF_RRDRD): Likewise.
184 (s390_opformats): Likewise.
185 * s390-opc.txt: Add new instructions for cpu type z9-109.
186
f1fa1093
DA		 1872005-08-05 John David Anglin <dave.anglin@nrc-crnc.gc.ca>
188
189 * hppa-dis.c (print_insn_hppa): Prefix 21-bit values with "L%".
190
e9f89963
PB		 1912005-07-29 Paul Brook <paul@codesourcery.com>
192
193 * arm-dis.c: Fix disassebly of thumb2 writeback addressing modes.
194
92e90b6e
PB		 1952005-07-29 Paul Brook <paul@codesourcery.com>
196
197 * arm-dis.c (thumb32_opc): Fix addressing mode for tbh.
198 (print_insn_thumb32): Fix decoding of thumb2 'I' operands.
199
fd54057a
DD		 2002005-07-25 DJ Delorie <dj@redhat.com>
201
202 * m32c-asm.c Regenerate.
203 * m32c-dis.c Regenerate.
204
760c0f6a
DD		 2052005-07-20 DJ Delorie <dj@redhat.com>
206
207 * disassemble.c (disassemble_init_for_target): M32C ISAs are
208 enums, so convert them to bit masks, which attributes are.
209
85da3a56
NC		 2102005-07-18 Nick Clifton <nickc@redhat.com>
211
212 * configure.in: Restore alpha ordering to list of arches.
213 * configure: Regenerate.
214 * disassemble.c: Restore alpha ordering to list of arches.
215
2162005-07-18 Nick Clifton <nickc@redhat.com>
217
218 * m32c-asm.c: Regenerate.
219 * m32c-desc.c: Regenerate.
220 * m32c-desc.h: Regenerate.
221 * m32c-dis.c: Regenerate.
222 * m32c-ibld.h: Regenerate.
223 * m32c-opc.c: Regenerate.
224 * m32c-opc.h: Regenerate.
225
22cbf2e7
L		 2262005-07-18 H.J. Lu <hongjiu.lu@intel.com>
227
228 * i386-dis.c (PNI_Fixup): Update comment.
229 (VMX_Fixup): Properly handle the suffix check.
230
0aea0460
DA		 2312005-07-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
232
233 * hppa-dis.c (print_insn_hppa): Add space after 'w' in wide-mode
234 mfctl disassembly.
235
0f82ff91
AM		 2362005-07-16 Alan Modra <amodra@bigpond.net.au>
237
238 * Makefile.am: Run "make dep-am".
239 (stamp-m32c): Fix cpu dependencies.
240 * Makefile.in: Regenerate.
241 * ip2k-dis.c: Regenerate.
242
90700ea2
L		 2432007-07-15 H.J. Lu <hongjiu.lu@intel.com>
244
245 * i386-dis.c (OP_VMX): New. Handle Intel VMX Instructions.
246 (VMX_Fixup): New. Fix up Intel VMX Instructions.
247 (Em): New.
248 (Gm): New.
249 (VM): New.
250 (dis386_twobyte): Updated entries 0x78 and 0x79.
251 (twobyte_has_modrm): Likewise.
252 (grps): Use OP_VMX in the "sgdtIQ" entry. Updated GRP9.
253 (OP_G): Handle m_mode.
254
49f58d10
JB		 2552005-07-14 Jim Blandy <jimb@redhat.com>
256
257 Add support for the Renesas M32C and M16C.
258 * m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c, m32c-opc.c: New.
259 * m32c-desc.h, m32c-opc.h: New.
260 * Makefile.am (HFILES): List m32c-desc.h and m32c-opc.h.
261 (CFILES): List m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c,
262 m32c-opc.c.
263 (ALL_MACHINES): List m32c-asm.lo, m32c-desc.lo, m32c-dis.lo,
264 m32c-ibld.lo, m32c-opc.lo.
265 (CLEANFILES): List stamp-m32c.
266 (M32C_DEPS): List stamp-m32c, if CGEN_MAINT.
267 (CGEN_CPUS): Add m32c.
268 (m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c, m32c-opc.c)
269 (m32c-desc.h, m32c-opc.h): Depend on M32C_DEPS.
270 (m32c_opc_h): New variable.
271 (stamp-m32c, m32c-asm.lo, m32c-desc.lo, m32c-dis.lo, m32c-ibld.lo)
272 (m32c-opc.lo): New rules.
273 * Makefile.in: Regenerated.
274 * configure.in: Add case for bfd_m32c_arch.
275 * configure: Regenerated.
276 * disassemble.c (ARCH_m32c): New.
277 [ARCH_m32c]: #include "m32c-desc.h".
278 (disassembler) [ARCH_m32c]: Add case for bfd_arch_m32c.
279 (disassemble_init_for_target) [ARCH_m32c]: Same.
280
281 * cgen-ops.h, cgen-types.h: New files.
282 * Makefile.am (HFILES): List them.
283 * Makefile.in: Regenerated.
284
0fd3a477
JW		 2852005-07-07 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
286
287 * arc-dis.c, arm-dis.c, cris-dis.c, crx-dis.c, d10v-dis.c,
288 d30v-dis.c, fr30-dis.c, h8300-dis.c, h8500-dis.c, i860-dis.c,
289 ia64-dis.c, ip2k-dis.c, m10200-dis.c, m10300-dis.c,
290 m88k-dis.c, mcore-dis.c, mips-dis.c, ms1-dis.c, or32-dis.c,
291 ppc-dis.c, sh64-dis.c, sparc-dis.c, tic4x-dis.c, tic80-dis.c,
292 v850-dis.c: Fix format bugs.
293 * ia64-gen.c (fail, warn): Add format attribute.
294 * or32-opc.c (debug): Likewise.
295
22f8fcbd
NC		 2962005-07-07 Khem Raj <kraj@mvista.com>
297
298 * arm-dis.c (opcode32 arm_opcodes): Fix ARM VFP fadds instruction
299 disassembly pattern.
300
d125c27b
AM		 3012005-07-06 Alan Modra <amodra@bigpond.net.au>
302
303 * Makefile.am (stamp-m32r): Fix path to cpu files.
304 (stamp-m32r, stamp-iq2000): Likewise.
305 * Makefile.in: Regenerate.
306 * m32r-asm.c: Regenerate.
307 * po/POTFILES.in: Remove arm-opc.h. Add ms1-asm.c, ms1-desc.c,
308 ms1-desc.h, ms1-dis.c, ms1-ibld.c, ms1-opc.c, ms1-opc.h.
309
3ec2b351
NC		 3102005-07-05 Nick Clifton <nickc@redhat.com>
311
312 * iq2000-asm.c: Regenerate.
313 * ms1-asm.c: Regenerate.
314
30123838
JB		 3152005-07-05 Jan Beulich <jbeulich@novell.com>
316
317 * i386-dis.c (SVME_Fixup): New.
318 (grps): Use it for the lidt entry.
319 (PNI_Fixup): Call OP_M rather than OP_E.
320 (INVLPG_Fixup): Likewise.
321
b0eec63e
L		 3222005-07-04 H.J. Lu <hongjiu.lu@intel.com>
323
324 * tic30-dis.c (cnvt_tmsfloat_ieee): Use HUGE_VALF if defined.
325
47b0e7ad
NC		 3262005-07-01 Nick Clifton <nickc@redhat.com>
327
328 * a29k-dis.c: Update to ISO C90 style function declarations and
329 fix formatting.
330 * alpha-opc.c: Likewise.
331 * arc-dis.c: Likewise.
332 * arc-opc.c: Likewise.
333 * avr-dis.c: Likewise.
334 * cgen-asm.in: Likewise.
335 * cgen-dis.in: Likewise.
336 * cgen-ibld.in: Likewise.
337 * cgen-opc.c: Likewise.
338 * cris-dis.c: Likewise.
339 * d10v-dis.c: Likewise.
340 * d30v-dis.c: Likewise.
341 * d30v-opc.c: Likewise.
342 * dis-buf.c: Likewise.
343 * dlx-dis.c: Likewise.
344 * h8300-dis.c: Likewise.
345 * h8500-dis.c: Likewise.
346 * hppa-dis.c: Likewise.
347 * i370-dis.c: Likewise.
348 * i370-opc.c: Likewise.
349 * m10200-dis.c: Likewise.
350 * m10300-dis.c: Likewise.
351 * m68k-dis.c: Likewise.
352 * m88k-dis.c: Likewise.
353 * mips-dis.c: Likewise.
354 * mmix-dis.c: Likewise.
355 * msp430-dis.c: Likewise.
356 * ns32k-dis.c: Likewise.
357 * or32-dis.c: Likewise.
358 * or32-opc.c: Likewise.
359 * pdp11-dis.c: Likewise.
360 * pj-dis.c: Likewise.
361 * s390-dis.c: Likewise.
362 * sh-dis.c: Likewise.
363 * sh64-dis.c: Likewise.
364 * sparc-dis.c: Likewise.
365 * sparc-opc.c: Likewise.
366 * sysdep.h: Likewise.
367 * tic30-dis.c: Likewise.
368 * tic4x-dis.c: Likewise.
369 * tic80-dis.c: Likewise.
370 * v850-dis.c: Likewise.
371 * v850-opc.c: Likewise.
372 * vax-dis.c: Likewise.
373 * w65-dis.c: Likewise.
374 * z8kgen.c: Likewise.
375
376 * fr30-*: Regenerate.
377 * frv-*: Regenerate.
378 * ip2k-*: Regenerate.
379 * iq2000-*: Regenerate.
380 * m32r-*: Regenerate.
381 * ms1-*: Regenerate.
382 * openrisc-*: Regenerate.
383 * xstormy16-*: Regenerate.
384
cc16ba8c
BE		 3852005-06-23 Ben Elliston <bje@gnu.org>
386
387 * m68k-dis.c: Use ISC C90.
388 * m68k-opc.c: Formatting fixes.
389
4b185e97
DU		 3902005-06-16 David Ung <davidu@mips.com>
391
392 * mips16-opc.c (mips16_opcodes): Add the following MIPS16e
393 instructions to the table; seb/seh/sew/zeb/zeh/zew.
394
ac188222
DB		 3952005-06-15 Dave Brolley <brolley@redhat.com>
396
397 Contribute Morpho ms1 on behalf of Red Hat
398 * ms1-asm.c, ms1-desc.c, ms1-dis.c, ms1-ibld.c, ms1-opc.c,
399 ms1-opc.h: New files, Morpho ms1 target.
400
401 2004-05-14 Stan Cox <scox@redhat.com>
402
403 * disassemble.c (ARCH_ms1): Define.
404 (disassembler): Handle bfd_arch_ms1
405
406 2004-05-13 Michael Snyder <msnyder@redhat.com>
407
408 * Makefile.am, Makefile.in: Add ms1 target.
409 * configure.in: Ditto.
410
6b5d3a4d
ZW		 4112005-06-08 Zack Weinberg <zack@codesourcery.com>
412
413 * arm-opc.h: Delete; fold contents into ...
414 * arm-dis.c: ... here. Move includes of internal COFF headers
415 next to includes of internal ELF headers.
416 (streq, WORD_ADDRESS, BDISP, BDISP23): Delete, unused.
417 (struct arm_opcode): Rename struct opcode32. Make 'assembler' const.
418 (struct thumb_opcode): Rename struct opcode16. Make 'assembler' const.
419 (arm_conditional, arm_fp_const, arm_shift, arm_regname, regnames)
420 (iwmmxt_wwnames, iwmmxt_wwssnames):
421 Make const.
422 (regnames): Remove iWMMXt coprocessor register sets.
423 (iwmmxt_regnames, iwmmxt_cregnames): New statics.
424 (get_arm_regnames): Adjust fourth argument to match above changes.
425 (set_iwmmxt_regnames): Delete.
426 (print_insn_arm): Constify 'c'. Use ISO syntax for function
427 pointer calls. Expand sole use of BDISP. Use iwmmxt_regnames
428 and iwmmxt_cregnames, not set_iwmmxt_regnames.
429 (print_insn_thumb16, print_insn_thumb32): Constify 'c'. Use
430 ISO syntax for function pointer calls.
431
4a5329c6
ZW		 4322005-06-07 Zack Weinberg <zack@codesourcery.com>
433
434 * arm-dis.c: Split up the comments describing the format codes, so
435 that the ARM and 16-bit Thumb opcode tables each have comments
436 preceding them that describe all the codes, and only the codes,
437 valid in those tables. (32-bit Thumb table is already like this.)
438 Reorder the lists in all three comments to match the order in
439 which the codes are implemented.
440 Remove all forward declarations of static functions. Convert all
441 function definitions to ISO C format.
442 (print_insn_arm, print_insn_thumb16, print_insn_thumb32):
443 Return nothing.
444 (print_insn_thumb16): Remove unused case 'I'.
445 (print_insn): Update for changed calling convention of subroutines.
446
3d456fa1
JB		 4472005-05-25 Jan Beulich <jbeulich@novell.com>
448
449 * i386-dis.c (OP_E): In Intel mode, display 32-bit displacements in
450 hex (but retain it being displayed as signed). Remove redundant
451 checks. Add handling of displacements for 16-bit addressing in Intel
452 mode.
453
2888cb7a
JB		 4542005-05-25 Jan Beulich <jbeulich@novell.com>
455
456 * i386-dis.c (prefix_name): Remove pointless mode_64bit check.
457 (OP_E): Remove redundant REX_EXTZ handling. Remove pointless
458 masking of 'rm' in 16-bit memory address handling.
459
1ed8e1e4
AM		 4602005-05-19 Anton Blanchard <anton@samba.org>
461
462 * ppc-dis.c (powerpc_dialect): Handle "-Mpower5".
463 (print_ppc_disassembler_options): Document it.
464 * ppc-opc.c (SVC_LEV): Define.
465 (LEV): Allow optional operand.
466 (POWER5): Define.
467 (powerpc_opcodes): Extend "sc". Adjust "svc" and "svcl". Add
468 "hrfid", "popcntb", "fsqrtes", "fsqrtes.", "fre" and "fre.".
469
49cc2e69
KC		 4702005-05-19 Kelley Cook <kcook@gcc.gnu.org>
471
472 * Makefile.in: Regenerate.
473
c19d1205
ZW		 4742005-05-17 Zack Weinberg <zack@codesourcery.com>
475
476 * arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
477 instructions. Adjust disassembly of some opcodes to match
478 unified syntax.
479 (thumb32_opcodes): New table.
480 (print_insn_thumb): Rename print_insn_thumb16; don't handle
481 two-halfword branches here.
482 (print_insn_thumb32): New function.
483 (print_insn): Choose among print_insn_arm, print_insn_thumb16,
484 and print_insn_thumb32. Be consistent about order of
485 halfwords when printing 32-bit instructions.
486
003519a7
L		 4872005-05-07 H.J. Lu <hongjiu.lu@intel.com>
488
489 PR 843
490 * i386-dis.c (branch_v_mode): New.
491 (indirEv): Use branch_v_mode instead of v_mode.
492 (OP_E): Handle branch_v_mode.
493
920a34a7
L		 4942005-05-07 H.J. Lu <hongjiu.lu@intel.com>
495
496 * d10v-dis.c (dis_2_short): Support 64bit host.
497
5de773c1
NC		 4982005-05-07 Nick Clifton <nickc@redhat.com>
499
500 * po/nl.po: Updated translation.
501
f4321104
NC		 5022005-05-07 Nick Clifton <nickc@redhat.com>
503
504 * Update the address and phone number of the FSF organization in
505 the GPL notices in the following files:
506 a29k-dis.c, aclocal.m4, alpha-dis.c, alpha-opc.c, arc-dis.c,
507 arc-dis.h, arc-ext.c, arc-ext.h, arc-opc.c, arm-dis.c, arm-opc.h,
508 avr-dis.c, cgen-asm.c, cgen-asm.in, cgen-dis.c, cgen-dis.in,
509 cgen-ibld.in, cgen-opc.c, cgen.sh, cris-dis.c, cris-opc.c,
510 crx-dis.c, crx-opc.c, d10v-dis.c, d10v-opc.c, d30v-dis.c,
511 d30v-opc.c, dis-buf.c, dis-init.c, disassemble.c, dlx-dis.c,
512 fr30-asm.c, fr30-desc.c, fr30-desc.h, fr30-dis.c, fr30-ibld.c,
513 fr30-opc.c, fr30-opc.h, frv-asm.c, frv-desc.c, frv-desc.h,
514 frv-dis.c, frv-ibld.c, frv-opc.c, frv-opc.h, h8300-dis.c,
515 h8500-dis.c, h8500-opc.h, hppa-dis.c, i370-dis.c, i370-opc.c,
516 i386-dis.c, i860-dis.c, i960-dis.c, ia64-asmtab.h, ia64-dis.c,
517 ia64-gen.c, ia64-opc-a.c, ia64-opc-b.c, ia64-opc-d.c,
518 ia64-opc-f.c, ia64-opc-i.c, ia64-opc-m.c, ia64-opc-x.c,
519 ia64-opc.c, ia64-opc.h, ip2k-asm.c, ip2k-desc.c, ip2k-desc.h,
520 ip2k-dis.c, ip2k-ibld.c, ip2k-opc.c, ip2k-opc.h, iq2000-asm.c,
521 iq2000-desc.c, iq2000-desc.h, iq2000-dis.c, iq2000-ibld.c,
522 iq2000-opc.c, iq2000-opc.h, m10200-dis.c, m10200-opc.c,
523 m10300-dis.c, m10300-opc.c, m32r-asm.c, m32r-desc.c, m32r-desc.h,
524 m32r-dis.c, m32r-ibld.c, m32r-opc.c, m32r-opc.h, m32r-opinst.c,
525 m68hc11-dis.c, m68hc11-opc.c, m68k-dis.c, m68k-opc.c, m88k-dis.c,
526 maxq-dis.c, mcore-dis.c, mcore-opc.h, mips-dis.c, mips-opc.c,
527 mips16-opc.c, mmix-dis.c, mmix-opc.c, msp430-dis.c, ns32k-dis.c,
528 openrisc-asm.c, openrisc-desc.c, openrisc-desc.h, openrisc-dis.c,
529 openrisc-ibld.c, openrisc-opc.c, openrisc-opc.h, opintl.h,
530 or32-dis.c, or32-opc.c, pdp11-dis.c, pdp11-opc.c, pj-dis.c,
531 pj-opc.c, ppc-dis.c, ppc-opc.c, s390-dis.c, s390-mkopc.c,
532 s390-opc.c, sh-dis.c, sh-opc.h, sh64-dis.c, sh64-opc.c,
533 sh64-opc.h, sparc-dis.c, sparc-opc.c, sysdep.h, tic30-dis.c,
534 tic4x-dis.c, tic54x-dis.c, tic54x-opc.c, tic80-dis.c, tic80-opc.c,
535 v850-dis.c, v850-opc.c, vax-dis.c, w65-dis.c, w65-opc.h,
536 xstormy16-asm.c, xstormy16-desc.c, xstormy16-desc.h,
537 xstormy16-dis.c, xstormy16-ibld.c, xstormy16-opc.c,
538 xstormy16-opc.h, xtensa-dis.c, z8k-dis.c, z8kgen.c
539
10b076a2
JW		 5402005-05-05 James E Wilson <wilson@specifixinc.com>
541
542 * ia64-opc.c: Include sysdep.h before libiberty.h.
543
022716b6
NC		 5442005-05-05 Nick Clifton <nickc@redhat.com>
545
546 * configure.in (ALL_LINGUAS): Add vi.
547 * configure: Regenerate.
548 * po/vi.po: New.
549
db5152b4
JG		 5502005-04-26 Jerome Guitton <guitton@gnat.com>
551
552 * configure.in: Fix the check for basename declaration.
553 * configure: Regenerate.
554
eed0d89a
AM		 5552005-04-19 Alan Modra <amodra@bigpond.net.au>
556
557 * ppc-opc.c (RTO): Define.
558 (powerpc_opcodes <tlbsx, tlbsx., tlbre>): Combine PPC403 and BOOKE
559 entries to suit PPC440.
560
791fe849
MK		 5612005-04-18 Mark Kettenis <kettenis@gnu.org>
562
563 * i386-dis.c: Insert hyphens into selected VIA PadLock extensions.
564 Add xcrypt-ctr.
565
ffe58f7c
NC		 5662005-04-14 Nick Clifton <nickc@redhat.com>
567
568 * po/fi.po: New translation: Finnish.
569 * configure.in (ALL_LINGUAS): Add fi.
570 * configure: Regenerate.
571
9e9b66a9
AM		 5722005-04-14 Alan Modra <amodra@bigpond.net.au>
573
574 * Makefile.am (NO_WERROR): Define.
575 * configure.in: Invoke AM_BINUTILS_WARNINGS.
576 * Makefile.in: Regenerate.
577 * aclocal.m4: Regenerate.
578 * configure: Regenerate.
579
9494d739
NC		 5802005-04-04 Nick Clifton <nickc@redhat.com>
581
582 * fr30-asm.c: Regenerate.
583 * frv-asm.c: Regenerate.
584 * iq2000-asm.c: Regenerate.
585 * m32r-asm.c: Regenerate.
586 * openrisc-asm.c: Regenerate.
587
6128c599
JB		 5882005-04-01 Jan Beulich <jbeulich@novell.com>
589
590 * i386-dis.c (PNI_Fixup): Neither mwait nor monitor have any
591 visible operands in Intel mode. The first operand of monitor is
592 %rax in 64-bit mode.
593
373ff435
JB		 5942005-04-01 Jan Beulich <jbeulich@novell.com>
595
596 * i386-dis.c (INVLPG_Fixup): Decode rdtscp; change code to allow for
597 easier future additions.
598
4bd60896
JG		 5992005-03-31 Jerome Guitton <guitton@gnat.com>
600
601 * configure.in: Check for basename.
602 * configure: Regenerate.
603 * config.in: Ditto.
604
4cc91dba
L		 6052005-03-29 H.J. Lu <hongjiu.lu@intel.com>
606
607 * i386-dis.c (SEG_Fixup): New.
608 (Sv): New.
609 (dis386): Use "Sv" for 0x8c and 0x8e.
610
ec72cfe5
NC		 6112005-03-21 Jan-Benedict Glaw <jbglaw@lug-owl.de>
612 Nick Clifton <nickc@redhat.com>
c19d1205 613
ec72cfe5
NC		 614 * vax-dis.c: (entry_addr): New varible: An array of user supplied
615 function entry mask addresses.
616 (entry_addr_occupied_slots): New variable: The number of occupied
c19d1205 617 elements in entry_addr.
ec72cfe5
NC		 618 (entry_addr_total_slots): New variable: The total number of
619 elements in entry_addr.
620 (parse_disassembler_options): New function. Fills in the entry_addr
621 array.
622 (free_entry_array): New function. Release the memory used by the
623 entry addr array. Suppressed because there is no way to call it.
624 (is_function_entry): Check if a given address is a function's
625 start address by looking at supplied entry mask addresses and
626 symbol information, if available.
627 (print_insn_vax): Use parse_disassembler_options and is_function_entry.
628
85064c79
L		 6292005-03-23 H.J. Lu <hongjiu.lu@intel.com>
630
631 * cris-dis.c (print_with_operands): Use ~31L for long instead
632 of ~31.
633
de7141c7
L		 6342005-03-20 H.J. Lu <hongjiu.lu@intel.com>
635
636 * mmix-opc.c (O): Revert the last change.
637 (Z): Likewise.
638
e493ab45
L		 6392005-03-19 H.J. Lu <hongjiu.lu@intel.com>
640
641 * mmix-opc.c (O): Use 24UL instead of 24 for unsigned long.
642 (Z): Likewise.
643
d8d7c459
HPN		 6442005-03-19 Hans-Peter Nilsson <hp@bitrange.com>
645
646 * mmix-opc.c (O, Z): Force expression as unsigned long.
647
ebdb0383
NC		 6482005-03-18 Nick Clifton <nickc@redhat.com>
649
650 * ip2k-asm.c: Regenerate.
651 * op/opcodes.pot: Regenerate.
652
1ad12f97
NC		 6532005-03-16 Nick Clifton <nickc@redhat.com>
654 Ben Elliston <bje@au.ibm.com>
655
569acd2c 656 * configure.in (werror): New switch: Add -Werror to the
1ad12f97 657 compiler command line. Enabled by default. Disable via
569acd2c 658 --disable-werror.
1ad12f97
NC		 659 * configure: Regenerate.
660
4eb30afc
AM		 6612005-03-16 Alan Modra <amodra@bigpond.net.au>
662
663 * ppc-dis.c (powerpc_dialect): Don't set PPC_OPCODE_ALTIVEC when
664 BOOKE.
665
ea8409f7
AM		 6662005-03-15 Alan Modra <amodra@bigpond.net.au>
667
729ae8d2
AM		 668 * po/es.po: Commit new Spanish translation.
669
ea8409f7
AM		 670 * po/fr.po: Commit new French translation.
671
4f495e61
NC		 6722005-03-14 Jan-Benedict Glaw <jbglaw@lug-owl.de>
673
674 * vax-dis.c: Fix spelling error
675 (print_insn_vax): Use ".word 0x0012 # Entry mask: r1 r2 >" instead
676 of just "Entry mask: < r1 ... >"
677
0a003adc
ZW		 6782005-03-12 Zack Weinberg <zack@codesourcery.com>
679
680 * arm-dis.c (arm_opcodes): Document %E and %V.
681 Add entries for v6T2 ARM instructions:
682 bfc bfi mls strht ldrht ldrsht ldrsbt movw movt rbit ubfx sbfx.
683 (print_insn_arm): Add support for %E and %V.
885fc257 684 (thumb_opcodes): Add ARMv6K instructions nop, sev, wfe, wfi, yield.
0a003adc 685
da99ee72
AM		 6862005-03-10 Jeff Baker <jbaker@qnx.com>
687 Alan Modra <amodra@bigpond.net.au>
688
689 * ppc-opc.c (insert_sprg, extract_sprg): New Functions.
690 (powerpc_operands <SPRG>): Call the above. Bit field is 5 bits.
691 (SPRG_MASK): Delete.
692 (XSPRG_MASK): Mask off extra bits now part of sprg field.
0a003adc 693 (powerpc_opcodes): Asjust mfsprg and mtsprg to suit new mask. Move
da99ee72
AM		 694 mfsprg4..7 after msprg and consolidate.
695
220abb21
AM		 6962005-03-09 Jan-Benedict Glaw <jbglaw@lug-owl.de>
697
698 * vax-dis.c (entry_mask_bit): New array.
699 (print_insn_vax): Decode function entry mask.
700
0e06657a
AH		 7012005-03-07 Aldy Hernandez <aldyh@redhat.com>
702
703 * ppc-opc.c (powerpc_opcodes): Fix encoding of efscfd.
704
06647dfd
AM		 7052005-03-05 Alan Modra <amodra@bigpond.net.au>
706
707 * po/opcodes.pot: Regenerate.
708
82b829a7
RR		 7092005-03-03 Ramana Radhakrishnan <ramana.radhakrishnan@codito.com>
710
220abb21 711 * arc-dis.c (a4_decoding_class): New enum.
06647dfd
AM		 712 (dsmOneArcInst): Use the enum values for the decoding class.
713 Remove redundant case in the switch for decodingClass value 11.
82b829a7 714
c4a530c5
JB		 7152005-03-02 Jan Beulich <jbeulich@novell.com>
716
717 * i386-dis.c (print_insn): Suppress lock prefix printing for cr8...15
718 accesses.
719 (OP_C): Consider lock prefix in non-64-bit modes.
720
47d8304e
AM		 7212005-02-24 Alan Modra <amodra@bigpond.net.au>
722
723 * cris-dis.c (format_hex): Remove ineffective warning fix.
724 * crx-dis.c (make_instruction): Warning fix.
725 * frv-asm.c: Regenerate.
726
ec36c4a4
NC		 7272005-02-23 Nick Clifton <nickc@redhat.com>
728
33b71eeb
NC		 729 * cgen-dis.in: Use bfd_byte for buffers that are passed to
730 read_memory.
06647dfd 731
33b71eeb 732 * ia64-opc.c (locate_opcode_ent): Initialise opval array.
06647dfd 733
ec36c4a4
NC		 734 * crx-dis.c (make_instruction): Move argument structure into inner
735 scope and ensure that all of its fields are initialised before
736 they are used.
737
33b71eeb
NC		 738 * fr30-asm.c: Regenerate.
739 * fr30-dis.c: Regenerate.
740 * frv-asm.c: Regenerate.
741 * frv-dis.c: Regenerate.
742 * ip2k-asm.c: Regenerate.
743 * ip2k-dis.c: Regenerate.
744 * iq2000-asm.c: Regenerate.
745 * iq2000-dis.c: Regenerate.
746 * m32r-asm.c: Regenerate.
747 * m32r-dis.c: Regenerate.
748 * openrisc-asm.c: Regenerate.
749 * openrisc-dis.c: Regenerate.
750 * xstormy16-asm.c: Regenerate.
751 * xstormy16-dis.c: Regenerate.
752
53c9ebc5
AM		 7532005-02-22 Alan Modra <amodra@bigpond.net.au>
754
755 * arc-ext.c: Warning fixes.
756 * arc-ext.h: Likewise.
757 * cgen-opc.c: Likewise.
758 * ia64-gen.c: Likewise.
759 * maxq-dis.c: Likewise.
760 * ns32k-dis.c: Likewise.
761 * w65-dis.c: Likewise.
762 * ia64-asmtab.c: Regenerate.
763
610ad19b
AM		 7642005-02-22 Alan Modra <amodra@bigpond.net.au>
765
766 * fr30-desc.c: Regenerate.
767 * fr30-desc.h: Regenerate.
768 * fr30-opc.c: Regenerate.
769 * fr30-opc.h: Regenerate.
770 * frv-desc.c: Regenerate.
771 * frv-desc.h: Regenerate.
772 * frv-opc.c: Regenerate.
773 * frv-opc.h: Regenerate.
774 * ip2k-desc.c: Regenerate.
775 * ip2k-desc.h: Regenerate.
776 * ip2k-opc.c: Regenerate.
777 * ip2k-opc.h: Regenerate.
778 * iq2000-desc.c: Regenerate.
779 * iq2000-desc.h: Regenerate.
780 * iq2000-opc.c: Regenerate.
781 * iq2000-opc.h: Regenerate.
782 * m32r-desc.c: Regenerate.
783 * m32r-desc.h: Regenerate.
784 * m32r-opc.c: Regenerate.
785 * m32r-opc.h: Regenerate.
786 * m32r-opinst.c: Regenerate.
787 * openrisc-desc.c: Regenerate.
788 * openrisc-desc.h: Regenerate.
789 * openrisc-opc.c: Regenerate.
790 * openrisc-opc.h: Regenerate.
791 * xstormy16-desc.c: Regenerate.
792 * xstormy16-desc.h: Regenerate.
793 * xstormy16-opc.c: Regenerate.
794 * xstormy16-opc.h: Regenerate.
795
db9db6f2
AM		 7962005-02-21 Alan Modra <amodra@bigpond.net.au>
797
798 * Makefile.am: Run "make dep-am"
799 * Makefile.in: Regenerate.
800
bf143b25
NC		 8012005-02-15 Nick Clifton <nickc@redhat.com>
802
803 * cgen-dis.in (print_address): Add an ATTRIBUTE_UNUSED to prevent
804 compile time warnings.
805 (print_keyword): Likewise.
806 (default_print_insn): Likewise.
807
808 * fr30-desc.c: Regenerated.
809 * fr30-desc.h: Regenerated.
810 * fr30-dis.c: Regenerated.
811 * fr30-opc.c: Regenerated.
812 * fr30-opc.h: Regenerated.
813 * frv-desc.c: Regenerated.
814 * frv-dis.c: Regenerated.
815 * frv-opc.c: Regenerated.
816 * ip2k-asm.c: Regenerated.
817 * ip2k-desc.c: Regenerated.
818 * ip2k-desc.h: Regenerated.
819 * ip2k-dis.c: Regenerated.
820 * ip2k-opc.c: Regenerated.
821 * ip2k-opc.h: Regenerated.
822 * iq2000-desc.c: Regenerated.
823 * iq2000-dis.c: Regenerated.
824 * iq2000-opc.c: Regenerated.
825 * m32r-asm.c: Regenerated.
826 * m32r-desc.c: Regenerated.
827 * m32r-desc.h: Regenerated.
828 * m32r-dis.c: Regenerated.
829 * m32r-opc.c: Regenerated.
830 * m32r-opc.h: Regenerated.
831 * m32r-opinst.c: Regenerated.
832 * openrisc-desc.c: Regenerated.
833 * openrisc-desc.h: Regenerated.
834 * openrisc-dis.c: Regenerated.
835 * openrisc-opc.c: Regenerated.
836 * openrisc-opc.h: Regenerated.
837 * xstormy16-desc.c: Regenerated.
838 * xstormy16-desc.h: Regenerated.
839 * xstormy16-dis.c: Regenerated.
840 * xstormy16-opc.c: Regenerated.
841 * xstormy16-opc.h: Regenerated.
842
d6098898
L		 8432005-02-14 H.J. Lu <hongjiu.lu@intel.com>
844
845 * dis-buf.c (perror_memory): Use sprintf_vma to print out
846 address.
847
5a84f3e0
NC		 8482005-02-11 Nick Clifton <nickc@redhat.com>
849
bc18c937
NC		 850 * iq2000-asm.c: Regenerate.
851
5a84f3e0
NC		 852 * frv-dis.c: Regenerate.
853
0a40490e
JB		 8542005-02-07 Jim Blandy <jimb@redhat.com>
855
856 * Makefile.am (CGEN): Load guile.scm before calling the main
857 application script.
858 * Makefile.in: Regenerated.
859 * cgen.sh: Be prepared for the 'cgen' argument to contain spaces.
860 Simply pass the cgen-opc.scm path to ${cgen} as its first
861 argument; ${cgen} itself now contains the '-s', or whatever is
862 appropriate for the Scheme being used.
863
c46f8c51
AC		 8642005-01-31 Andrew Cagney <cagney@gnu.org>
865
866 * configure: Regenerate to track ../gettext.m4.
867
60b9a617
JB		 8682005-01-31 Jan Beulich <jbeulich@novell.com>
869
870 * ia64-gen.c (NELEMS): Define.
871 (shrink): Generate alias with missing second predicate register when
872 opcode has two outputs and these are both predicates.
873 * ia64-opc-i.c (FULL17): Define.
874 (ia64_opcodes_i): Add mov-to-pr alias without second input. Use FULL17
875 here to generate output template.
876 (TBITCM, TNATCM): Undefine after use.
877 * ia64-opc-m.c (ia64_opcodes_i): Add alloc alias without ar.pfs as
878 first input. Add ld16 aliases without ar.csd as second output. Add
879 st16 aliases without ar.csd as second input. Add cmpxchg aliases
880 without ar.ccv as third input. Add cmp8xchg16 aliases without ar.csd/
881 ar.ccv as third/fourth inputs. Consolidate through...
882 (CMPXCHG_acq, CMPXCHG_rel, CMPXCHG_1, CMPXCHG_2, CMPXCHG_4, CMPXCHG_8,
883 CMPXCHGn, CMP8XCHG16, CMPXCHG_ALL): Define.
884 * ia64-asmtab.c: Regenerate.
885
a53bf506
AC		 8862005-01-27 Andrew Cagney <cagney@gnu.org>
887
888 * configure: Regenerate to track ../gettext.m4 change.
889
90219bd0
AO		 8902005-01-25 Alexandre Oliva <aoliva@redhat.com>
891
892 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
893 * frv-asm.c: Rebuilt.
894 * frv-desc.c: Rebuilt.
895 * frv-desc.h: Rebuilt.
896 * frv-dis.c: Rebuilt.
897 * frv-ibld.c: Rebuilt.
898 * frv-opc.c: Rebuilt.
899 * frv-opc.h: Rebuilt.
900
45181ed1
AC		 9012005-01-24 Andrew Cagney <cagney@gnu.org>
902
903 * configure: Regenerate, ../gettext.m4 was updated.
904
9e836e3d
FF		 9052005-01-21 Fred Fish <fnf@specifixinc.com>
906
907 * mips-opc.c: Change INSN_ALIAS to INSN2_ALIAS.
908 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
909 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
910 * mips-dis.c: Ditto.
911
5e8cb021
AM		 9122005-01-20 Alan Modra <amodra@bigpond.net.au>
913
914 * ppc-opc.c (powerpc_opcodes): Add optional 'l' arg to tlbiel.
915
986e18a5
FF		 9162005-01-19 Fred Fish <fnf@specifixinc.com>
917
918 * mips-dis.c (no_aliases): New disassembly option flag.
919 (set_default_mips_dis_options): Init no_aliases to zero.
920 (parse_mips_dis_option): Handle no-aliases option.
921 (print_insn_mips): Ignore table entries that are aliases
922 if no_aliases is set.
923 (print_insn_mips16): Ditto.
924 * mips-opc.c (mips_builtin_opcodes): Add initializer column for
925 new pinfo2 member and add INSN_ALIAS initializers as needed. Also
926 move WR_MACC and RD_MACC initializers from pinfo to pinfo2.
927 * mips16-opc.c (mips16_opcodes): Ditto.
928
e38bc3b5
NC		 9292005-01-17 Andrew Stubbs <andrew.stubbs@st.com>
930
931 * sh-opc.h (arch_sh2a_or_sh3e,arch_sh2a_or_sh4): Correct definition.
932 (inheritance diagram): Add missing edge.
933 (arch_sh1_up): Rename arch_sh_up to match external name to make life
934 easier for the testsuite.
935 (arch_sh4_nofp_up): Likewise, rename arch_sh4_nofpu_up.
936 (arch_sh4a_nofp_up): Likewise, rename arch_sh4a_nofpu_up.
610ad19b 937 (arch_sh2a_nofpu_or_sh4_nommu_nofpu_up): Add missing
e38bc3b5
NC		 938 arch_sh2a_or_sh4_up child.
939 (sh_table): Do renaming as above.
940 Correct comment for ldc.l for gas testsuite to read.
941 Remove rogue mul.l from sh1 (duplicate of the one for sh2).
942 Correct comments for movy.w and movy.l for gas testsuite to read.
943 Correct comments for fmov.d and fmov.s for gas testsuite to read.
944
9df48ba9
L		 9452005-01-12 H.J. Lu <hongjiu.lu@intel.com>
946
947 * i386-dis.c (OP_E): Don't ignore scale in SIB for 64 bit mode.
948
2033b4b9
L		 9492005-01-12 H.J. Lu <hongjiu.lu@intel.com>
950
951 * i386-dis.c (OP_E): Ignore scale when index == 0x4 in SIB.
952
0bcb06d2
AS		 9532005-01-10 Andreas Schwab <schwab@suse.de>
954
955 * disassemble.c (disassemble_init_for_target) <case
956 bfd_arch_ia64>: Set skip_zeroes to 16.
957 <case bfd_arch_tic4x>: Set skip_zeroes to 32.
958
47add74d
TL		 9592004-12-23 Tomer Levi <Tomer.Levi@nsc.com>
960
961 * crx-opc.c: Mark 'bcop' instruction as RELAXABLE.
962
246f4c05
SS		 9632004-12-14 Svein E. Seldal <Svein.Seldal@solidas.com>
964
965 * avr-dis.c: Prettyprint. Added printing of symbol names in all
966 memory references. Convert avr_operand() to C90 formatting.
967
0e1200e5
TL		 9682004-12-05 Tomer Levi <Tomer.Levi@nsc.com>
969
970 * crx-dis.c (print_arg): Use 'info->print_address_func' for address printing.
971
89a649f7
TL		 9722004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
973
974 * crx-opc.c (crx_optab): Mark all rbase_disps* operands as signed.
975 (no_op_insn): Initialize array with instructions that have no
976 operands.
977 * crx-dis.c (make_instruction): Get rid of COP_BRANCH_INS operand swapping.
978
6255809c
RE		 9792004-11-29 Richard Earnshaw <rearnsha@arm.com>
980
981 * arm-dis.c: Correct top-level comment.
982
2fbad815
RE		 9832004-11-27 Richard Earnshaw <rearnsha@arm.com>
984
985 * arm-opc.h (arm_opcode, thumb_opcode): Add extra field for the
986 architecuture defining the insn.
987 (arm_opcodes, thumb_opcodes): Delete. Move to ...
6b8725b9
RE		 988 * arm-dis.c (arm_opcodes, thumb_opcodes): Here. Add architecutre
989 field.
2fbad815
RE		 990 Also include opcode/arm.h.
991 * Makefile.am (arm-dis.lo): Update dependency list.
992 * Makefile.in: Regenerate.
993
d81acc42
NC		 9942004-11-22 Ravi Ramaseshan <ravi.ramaseshan@codito.com>
995
996 * opcode/arc-opc.c (insert_base): Modify ls_operand[LS_OFFSET] to
997 reflect the change to the short immediate syntax.
998
ca4f2377
AM		 9992004-11-19 Alan Modra <amodra@bigpond.net.au>
1000
5da8bf1b
AM		 1001 * or32-opc.c (debug): Warning fix.
1002 * po/POTFILES.in: Regenerate.
1003
ca4f2377
AM		 1004 * maxq-dis.c: Formatting.
1005 (print_insn): Warning fix.
1006
b7693d02
DJ		 10072004-11-17 Daniel Jacobowitz <dan@codesourcery.com>
1008
1009 * arm-dis.c (WORD_ADDRESS): Define.
1010 (print_insn): Use it. Correct big-endian end-of-section handling.
1011
300dac7e
NC		 10122004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1013 Vineet Sharma <vineets@noida.hcltech.com>
1014
1015 * maxq-dis.c: New file.
1016 * disassemble.c (ARCH_maxq): Define.
610ad19b 1017 (disassembler): Add 'print_insn_maxq_little' for handling maxq
300dac7e
NC		 1018 instructions..
1019 * configure.in: Add case for bfd_maxq_arch.
1020 * configure: Regenerate.
1021 * Makefile.am: Add support for maxq-dis.c
1022 * Makefile.in: Regenerate.
1023 * aclocal.m4: Regenerate.
1024
42048ee7
TL		 10252004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1026
1027 * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
1028 mode.
1029 * crx-dis.c: Likewise.
1030
bd21e58e
HPN		 10312004-11-04 Hans-Peter Nilsson <hp@axis.com>
1032
1033 Generally, handle CRISv32.
1034 * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
1035 (struct cris_disasm_data): New type.
1036 (format_reg, format_hex, cris_constraint, print_flags)
1037 (get_opcode_entry): Add struct cris_disasm_data * parameter. All
1038 callers changed.
1039 (format_sup_reg, print_insn_crisv32_with_register_prefix)
1040 (print_insn_crisv32_without_register_prefix)
1041 (print_insn_crisv10_v32_with_register_prefix)
1042 (print_insn_crisv10_v32_without_register_prefix)
1043 (cris_parse_disassembler_options): New functions.
1044 (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
1045 parameter. All callers changed.
1046 (get_opcode_entry): Call malloc, not xmalloc. Return NULL on
1047 failure.
1048 (cris_constraint) <case 'Y', 'U'>: New cases.
1049 (bytes_to_skip): Handle 'Y' and 'N' as 's'. Skip size is 4 bytes
1050 for constraint 'n'.
1051 (print_with_operands) <case 'Y'>: New case.
1052 (print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
1053 <case 'N', 'Y', 'Q'>: New cases.
1054 (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
1055 (print_insn_cris_with_register_prefix)
1056 (print_insn_cris_without_register_prefix): Call
1057 cris_parse_disassembler_options.
1058 * cris-opc.c (cris_spec_regs): Mention that this table isn't used
1059 for CRISv32 and the size of immediate operands. New v32-only
1060 entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
1061 spc. Add v32-only 4-byte entries for p2, p3, p5 and p6. Change
1062 ccr, ibr, irp to be v0..v10. Change bar, dccr to be v8..v10.
1063 Change brp to be v3..v10.
1064 (cris_support_regs): New vector.
1065 (cris_opcodes): Update head comment. New format characters '[',
1066 ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
1067 Add new opcodes for v32 and adjust existing opcodes to accommodate
1068 differences to earlier variants.
1069 (cris_cond15s): New vector.
1070
9306ca4a
JB		 10712004-11-04 Jan Beulich <jbeulich@novell.com>
1072
1073 * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
1074 (indirEb): Remove.
1075 (Mp): Use f_mode rather than none at all.
1076 (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
1077 replaces what previously was x_mode; x_mode now means 128-bit SSE
1078 operands.
1079 (dis386): Make far jumps and calls have an 'l' prefix only in AT&T
1080 mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
1081 pinsrw's second operand is Edqw.
1082 (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
1083 operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
1084 fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
1085 mode when an operand size override is present or always suffixing.
1086 More instructions will need to be added to this group.
1087 (putop): Handle new macro chars 'C' (short/long suffix selector),
1088 'I' (Intel mode override for following macro char), and 'J' (for
1089 adding the 'l' prefix to far branches in AT&T mode). When an
1090 alternative was specified in the template, honor macro character when
1091 specified for Intel mode.
1092 (OP_E): Handle new *_mode values. Correct pointer specifications for
1093 memory operands. Consolidate output of index register.
1094 (OP_G): Handle new *_mode values.
1095 (OP_I): Handle const_1_mode.
1096 (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
1097 respective opcode prefix bits have been consumed.
1098 (OP_EM, OP_EX): Provide some default handling for generating pointer
1099 specifications.
1100
f39c96a9
TL		 11012004-10-28 Tomer Levi <Tomer.Levi@nsc.com>
1102
1103 * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
1104 COP_INST macro.
1105
812337be
TL		 11062004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1107
1108 * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
1109 (getregliststring): Support HI/LO and user registers.
610ad19b 1110 * crx-opc.c (crx_instruction): Update data structure according to the
812337be
TL		 1111 rearrangement done in CRX opcode header file.
1112 (crx_regtab): Likewise.
1113 (crx_optab): Likewise.
610ad19b 1114 (crx_instruction): Reorder load/stor instructions, remove unsupported
812337be
TL		 1115 formats.
1116 support new Co-Processor instruction 'cpi'.
1117
4030fa5a
NC		 11182004-10-27 Nick Clifton <nickc@redhat.com>
1119
1120 * opcodes/iq2000-asm.c: Regenerate.
1121 * opcodes/iq2000-desc.c: Regenerate.
1122 * opcodes/iq2000-desc.h: Regenerate.
1123 * opcodes/iq2000-dis.c: Regenerate.
1124 * opcodes/iq2000-ibld.c: Regenerate.
1125 * opcodes/iq2000-opc.c: Regenerate.
1126 * opcodes/iq2000-opc.h: Regenerate.
1127
fc3d45e8
TL		 11282004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1129
1130 * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
1131 us4, us5 (respectively).
1132 Remove unsupported 'popa' instruction.
1133 Reverse operands order in store co-processor instructions.
1134
3c55da70
AM		 11352004-10-15 Alan Modra <amodra@bigpond.net.au>
1136
1137 * Makefile.am: Run "make dep-am"
1138 * Makefile.in: Regenerate.
1139
7fa3d080
BW		 11402004-10-12 Bob Wilson <bob.wilson@acm.org>
1141
1142 * xtensa-dis.c: Use ISO C90 formatting.
1143
e612bb4d
AM		 11442004-10-09 Alan Modra <amodra@bigpond.net.au>
1145
1146 * ppc-opc.c: Revert 2004-09-09 change.
1147
43cd72b9
BW		 11482004-10-07 Bob Wilson <bob.wilson@acm.org>
1149
1150 * xtensa-dis.c (state_names): Delete.
1151 (fetch_data): Use xtensa_isa_maxlength.
1152 (print_xtensa_operand): Replace operand parameter with opcode/operand
1153 pair. Remove print_sr_name parameter. Use new xtensa-isa.h functions.
1154 (print_insn_xtensa): Use new xtensa-isa.h functions. Handle multislot
1155 instruction bundles. Use xmalloc instead of malloc.
1156
bbac1f2a
NC		 11572004-10-07 David Gibson <david@gibson.dropbear.id.au>
1158
1159 * ppc-opc.c: Replace literal "0"s with NULLs in pointer
1160 initializers.
1161
48c9f030
NC		 11622004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1163
1164 * crx-opc.c (crx_instruction): Support Co-processor insns.
1165 * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
1166 (getregliststring): Change function to use the above enum.
1167 (print_arg): Handle CO-Processor insns.
1168 (crx_cinvs): Add 'b' option to invalidate the branch-target
1169 cache.
1170
12c64a4e
AH		 11712004-10-06 Aldy Hernandez <aldyh@redhat.com>
1172
1173 * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
1174 efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
1175 efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
1176 efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
1177 efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
1178
14127cc4
NC		 11792004-10-01 Bill Farmer <Bill@the-farmers.freeserve.co.uk>
1180
1181 * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
1182 rather than add it.
1183
0dd132b6
NC		 11842004-09-30 Paul Brook <paul@codesourcery.com>
1185
1186 * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
1187 * arm-opc.h: Document %e. Add ARMv6ZK instructions.
1188
3f85e526
L		 11892004-09-17 H.J. Lu <hongjiu.lu@intel.com>
1190
1191 * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
1192 (CONFIG_STATUS_DEPENDENCIES): New.
1193 (Makefile): Removed.
1194 (config.status): Likewise.
1195 * Makefile.in: Regenerated.
1196
8ae85421
AM		 11972004-09-17 Alan Modra <amodra@bigpond.net.au>
1198
1199 * Makefile.am: Run "make dep-am".
1200 * Makefile.in: Regenerate.
1201 * aclocal.m4: Regenerate.
1202 * configure: Regenerate.
1203 * po/POTFILES.in: Regenerate.
1204 * po/opcodes.pot: Regenerate.
1205
24443139
AS		 12062004-09-11 Andreas Schwab <schwab@suse.de>
1207
1208 * configure: Rebuild.
1209
2a309db0
AM		 12102004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1211
1212 * ppc-opc.c (L): Make this field not optional.
1213
42851540
NC		 12142004-09-03 Tomer Levi <Tomer.Levi@nsc.com>
1215
1216 * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
1217 Fix parameter to 'm[t|f]csr' insns.
1218
979273e3
NN		 12192004-08-30 Nathanael Nerode <neroden@gcc.gnu.org>
1220
1221 * configure.in: Autoupdate to autoconf 2.59.
1222 * aclocal.m4: Rebuild with aclocal 1.4p6.
1223 * configure: Rebuild with autoconf 2.59.
1224 * Makefile.in: Rebuild with automake 1.4p6 (picking up
1225 bfd changes for autoconf 2.59 on the way).
1226 * config.in: Rebuild with autoheader 2.59.
1227
ac28a1cb
RS		 12282004-08-27 Richard Sandiford <rsandifo@redhat.com>
1229
1230 * frv-desc.[ch], frv-opc.[ch]: Regenerated.
1231
30d1c836
ML		 12322004-07-30 Michal Ludvig <mludvig@suse.cz>
1233
1234 * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
1235 (GRPPADLCK2): New define.
1236 (twobyte_has_modrm): True for 0xA6.
1237 (grps): GRPPADLCK2 for opcode 0xA6.
1238
0b0ac059
AO		 12392004-07-29 Alexandre Oliva <aoliva@redhat.com>
1240
1241 Introduce SH2a support.
1242 * sh-opc.h (arch_sh2a_base): Renumber.
1243 (arch_sh2a_nofpu_base): Remove.
1244 (arch_sh_base_mask): Adjust.
1245 (arch_opann_mask): New.
1246 (arch_sh2a, arch_sh2a_nofpu): Adjust.
1247 (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
1248 (sh_table): Adjust whitespace.
1249 2004-02-24 Corinna Vinschen <vinschen@redhat.com>
1250 * sh-opc.h (arch_sh2a_nofpu_up): New. Use instead of arch_sh2a_up in
1251 instruction list throughout.
1252 (arch_sh2a_up): Redefine to include fpu instruction set. Use instead
1253 of arch_sh2a in instruction list throughout.
1254 (arch_sh2e_up): Accomodate above changes.
1255 (arch_sh2_up): Ditto.
1256 2004-02-20 Corinna Vinschen <vinschen@redhat.com>
1257 * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
1258 2004-02-18 Corinna Vinschen <vinschen@redhat.com>
1259 * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
1260 * sh-opc.h (arch_sh2a_nofpu): New.
1261 (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
1262 (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
1263 instruction.
1264 2004-01-20 DJ Delorie <dj@redhat.com>
1265 * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
1266 2003-12-29 DJ Delorie <dj@redhat.com>
1267 * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
1268 sh_opcode_info, sh_table): Add sh2a support.
1269 (arch_op32): New, to tag 32-bit opcodes.
1270 * sh-dis.c (print_insn_sh): Support sh2a opcodes.
1271 2003-12-02 Michael Snyder <msnyder@redhat.com>
1272 * sh-opc.h (arch_sh2a): Add.
1273 * sh-dis.c (arch_sh2a): Handle.
1274 * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
1275
670ec21d
NC		 12762004-07-27 Tomer Levi <Tomer.Levi@nsc.com>
1277
1278 * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
1279
ed049af3
NC		 12802004-07-22 Nick Clifton <nickc@redhat.com>
1281
1282 PR/280
1283 * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
1284 insns - this is done by objdump itself.
1285 * h8500-dis.c (print_insn_h8500): Likewise.
1286
20f0a1fc
NC		 12872004-07-21 Jan Beulich <jbeulich@novell.com>
1288
1289 * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
1290 regardless of address size prefix in effect.
1291 (ptr_reg): Size or address registers does not depend on rex64, but
1292 on the presence of an address size override.
1293 (OP_MMX): Use rex.x only for xmm registers.
1294 (OP_EM): Use rex.z only for xmm registers.
1295
6f14957b
MR		 12962004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
1297
1298 * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
1299 move/branch operations to the bottom so that VR5400 multimedia
1300 instructions take precedence in disassembly.
1301
1586d91e
MR		 13022004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
1303
1304 * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
1305 ISA-specific "break" encoding.
1306
982de27a
NC		 13072004-07-13 Elvis Chiang <elvisfb@gmail.com>
1308
1309 * arm-opc.h: Fix typo in comment.
1310
4300ab10
AS		 13112004-07-11 Andreas Schwab <schwab@suse.de>
1312
1313 * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
1314
8577e690
AS		 13152004-07-09 Andreas Schwab <schwab@suse.de>
1316
1317 * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
1318
1fe1f39c
NC		 13192004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1320
1321 * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
1322 (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
1323 (crx-dis.lo): New target.
1324 (crx-opc.lo): Likewise.
1325 * Makefile.in: Regenerate.
1326 * configure.in: Handle bfd_crx_arch.
1327 * configure: Regenerate.
1328 * crx-dis.c: New file.
1329 * crx-opc.c: New file.
1330 * disassemble.c (ARCH_crx): Define.
1331 (disassembler): Handle ARCH_crx.
1332
7a33b495
JW		 13332004-06-29 James E Wilson <wilson@specifixinc.com>
1334
1335 * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
1336 * ia64-asmtab.c: Regnerate.
1337
98e69875
AM		 13382004-06-28 Alan Modra <amodra@bigpond.net.au>
1339
1340 * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
1341 (extract_fxm): Don't test dialect.
1342 (XFXFXM_MASK): Include the power4 bit.
1343 (XFXM): Add p4 param.
1344 (powerpc_opcodes): Add mfocrf and mtocrf. Adjust mtcr.
1345
a53b85e2
AO		 13462004-06-27 Alexandre Oliva <aoliva@redhat.com>
1347
1348 2003-07-21 Richard Sandiford <rsandifo@redhat.com>
1349 * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
1350
d0618d1c
AM		 13512004-06-26 Alan Modra <amodra@bigpond.net.au>
1352
1353 * ppc-opc.c (BH, XLBH_MASK): Define.
1354 (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
1355
1d9f512f
AM		 13562004-06-24 Alan Modra <amodra@bigpond.net.au>
1357
1358 * i386-dis.c (x_mode): Comment.
1359 (two_source_ops): File scope.
1360 (float_mem): Correct fisttpll and fistpll.
1361 (float_mem_mode): New table.
1362 (dofloat): Use it.
1363 (OP_E): Correct intel mode PTR output.
1364 (ptr_reg): Use open_char and close_char.
1365 (PNI_Fixup): Handle possible suffix on sidt. Use op1out etc. for
1366 operands. Set two_source_ops.
1367
52886d70
AM		 13682004-06-15 Alan Modra <amodra@bigpond.net.au>
1369
1370 * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
1371 instead of _raw_size.
1372
bad9ceea
JJ		 13732004-06-08 Jakub Jelinek <jakub@redhat.com>
1374
1375 * ia64-gen.c (in_iclass): Handle more postinc st
1376 and ld variants.
1377 * ia64-asmtab.c: Rebuilt.
1378
0451f5df
MS		 13792004-06-01 Martin Schwidefsky <schwidefsky@de.ibm.com>
1380
1381 * s390-opc.txt: Correct architecture mask for some opcodes.
1382 lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
1383 in the esa mode as well.
1384
f6f9408f
JR		 13852004-05-28 Andrew Stubbs <andrew.stubbs@superh.com>
1386
1387 * sh-dis.c (target_arch): Make unsigned.
1388 (print_insn_sh): Replace (most of) switch with a call to
1389 sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
1390 * sh-opc.h: Redefine architecture flags values.
1391 Add sh3-nommu architecture.
1392 Reorganise <arch>_up macros so they make more visual sense.
1393 (SH_MERGE_ARCH_SET): Define new macro.
1394 (SH_VALID_BASE_ARCH_SET): Likewise.
1395 (SH_VALID_MMU_ARCH_SET): Likewise.
1396 (SH_VALID_CO_ARCH_SET): Likewise.
1397 (SH_VALID_ARCH_SET): Likewise.
1398 (SH_MERGE_ARCH_SET_VALID): Likewise.
1399 (SH_ARCH_SET_HAS_FPU): Likewise.
1400 (SH_ARCH_SET_HAS_DSP): Likewise.
1401 (SH_ARCH_UNKNOWN_ARCH): Likewise.
1402 (sh_get_arch_from_bfd_mach): Add prototype.
1403 (sh_get_arch_up_from_bfd_mach): Likewise.
1404 (sh_get_bfd_mach_from_arch_set): Likewise.
1405 (sh_merge_bfd_arc): Likewise.
1406
be8c092b
NC		 14072004-05-24 Peter Barada <peter@the-baradas.com>
1408
1409 * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
610ad19b
AM		 1410 into new match_insn_m68k function. Loop over canidate
1411 matches and select first that completely matches.
be8c092b
NC		 1412 * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
1413 * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
610ad19b 1414 to verify addressing for MAC/EMAC.
be8c092b
NC		 1415 * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
1416 reigster halves since 'fpu' and 'spl' look misleading.
1417 * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
1418 * m68k-opc.c: Rearragne mac/emac cases to use longest for
1419 first, tighten up match masks.
1420 * m68k-opc.c: Add 'size' field to struct m68k_opcode. Produce
1421 'size' from special case code in print_insn_m68k to
1422 determine decode size of insns.
1423
a30e9cc4
AM		 14242004-05-19 Alan Modra <amodra@bigpond.net.au>
1425
1426 * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
1427 well as when -mpower4.
1428
9598fbe5
NC		 14292004-05-13 Nick Clifton <nickc@redhat.com>
1430
1431 * po/fr.po: Updated French translation.
1432
6b6e92f4
NC		 14332004-05-05 Peter Barada <peter@the-baradas.com>
1434
1435 * m68k-dis.c(print_insn_m68k): Add new chips, use core
1436 variants in arch_mask. Only set m68881/68851 for 68k chips.
1437 * m68k-op.c: Switch from ColdFire chips to core variants.
1438
a404d431
AM		 14392004-05-05 Alan Modra <amodra@bigpond.net.au>
1440
a30e9cc4 1441 PR 147.
a404d431
AM		 1442 * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
1443
f3806e43
BE		 14442004-04-29 Ben Elliston <bje@au.ibm.com>
1445
520ceea4
BE		 1446 * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
1447 (powerpc_opcodes): Add "dbczl" instruction for PPC970.
f3806e43 1448
1f1799d5
KK		 14492004-04-22 Kaz Kojima <kkojima@rr.iij4u.or.jp>
1450
1451 * sh-dis.c (print_insn_sh): Print the value in constant pool
1452 as a symbol if it looks like a symbol.
1453
fd99574b
NC		 14542004-04-22 Peter Barada <peter@the-baradas.com>
1455
1456 * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
1457 appropriate ColdFire architectures.
1458 (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
1459 mask addressing.
1460 Add EMAC instructions, fix MAC instructions. Remove
1461 macmw/macml/msacmw/msacml instructions since mask addressing now
1462 supported.
1463
b4781d44
JJ		 14642004-04-20 Jakub Jelinek <jakub@redhat.com>
1465
1466 * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
1467 (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
1468 suffix. Use fmov*x macros, create all 3 fpsize variants in one
1469 macro. Adjust all users.
1470
91809fda 14712004-04-15 Anil Paranjpe <anilp1@kpitcummins.com>
610ad19b 1472
91809fda
NC		 1473 * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
1474 separately.
1475
f4453dfa
NC		 14762004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
1477
1478 * m32r-asm.c: Regenerate.
1479
9b0de91a
SS		 14802004-03-29 Stan Shebs <shebs@apple.com>
1481
1482 * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
1483 used.
1484
e20c0b3d
AM		 14852004-03-19 Alan Modra <amodra@bigpond.net.au>
1486
1487 * aclocal.m4: Regenerate.
1488 * config.in: Regenerate.
1489 * configure: Regenerate.
1490 * po/POTFILES.in: Regenerate.
1491 * po/opcodes.pot: Regenerate.
1492
fdd12ef3
AM		 14932004-03-16 Alan Modra <amodra@bigpond.net.au>
1494
1495 * ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
1496 PPC_OPERANDS_GPR_0.
1497 * ppc-opc.c (RA0): Define.
1498 (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
1499 (RAOPT): Rename from RAO. Update all uses.
a9c3619e 1500 (powerpc_opcodes): Use RA0 as appropriate.
fdd12ef3 1501
2dc111b3 15022004-03-15 Aldy Hernandez <aldyh@redhat.com>
fdd12ef3
AM		 1503
1504 * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
2dc111b3 1505
7bfeee7b
AM		 15062004-03-15 Alan Modra <amodra@bigpond.net.au>
1507
1508 * sparc-dis.c (print_insn_sparc): Update getword prototype.
1509
7ffdda93
ML		 15102004-03-12 Michal Ludvig <mludvig@suse.cz>
1511
1512 * i386-dis.c (GRPPLOCK): Delete.
7bfeee7b 1513 (grps): Delete GRPPLOCK entry.
7ffdda93 1514
cc0ec051
AM		 15152004-03-12 Alan Modra <amodra@bigpond.net.au>
1516
1517 * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
1518 (M, Mp): Use OP_M.
1519 (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
1520 (GRPPADLCK): Define.
1521 (dis386): Use NOP_Fixup on "nop".
1522 (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
1523 (twobyte_has_modrm): Set for 0xa7.
1524 (padlock_table): Delete. Move to..
1525 (grps): ..here, using OP_0f07. Use OP_Ofae on lfence, mfence
1526 and clflush.
1527 (print_insn): Revert PADLOCK_SPECIAL code.
1528 (OP_E): Delete sfence, lfence, mfence checks.
1529
4fd61dcb
JJ		 15302004-03-12 Jakub Jelinek <jakub@redhat.com>
1531
1532 * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
1533 (INVLPG_Fixup): New function.
1534 (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
1535
0f10071e
ML		 15362004-03-12 Michal Ludvig <mludvig@suse.cz>
1537
1538 * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
1539 (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
1540 (padlock_table): New struct with PadLock instructions.
1541 (print_insn): Handle PADLOCK_SPECIAL.
1542
c02908d2
AM		 15432004-03-12 Alan Modra <amodra@bigpond.net.au>
1544
1545 * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
1546 (OP_E): Twiddle clflush to sfence here.
1547
d5bb7600
NC		 15482004-03-08 Nick Clifton <nickc@redhat.com>
1549
1550 * po/de.po: Updated German translation.
1551
ae51a426
JR		 15522003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>
1553
1554 * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
1555 nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu.
1556 * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
1557 accordingly.
1558
676a64f4
RS		 15592004-03-01 Richard Sandiford <rsandifo@redhat.com>
1560
1561 * frv-asm.c: Regenerate.
1562 * frv-desc.c: Regenerate.
1563 * frv-desc.h: Regenerate.
1564 * frv-dis.c: Regenerate.
1565 * frv-ibld.c: Regenerate.
1566 * frv-opc.c: Regenerate.
1567 * frv-opc.h: Regenerate.
1568
c7a48b9a
RS		 15692004-03-01 Richard Sandiford <rsandifo@redhat.com>
1570
1571 * frv-desc.c, frv-opc.c: Regenerate.
1572
8ae0baa2
RS		 15732004-03-01 Richard Sandiford <rsandifo@redhat.com>
1574
1575 * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
1576
ce11586c
JR		 15772004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
1578
1579 * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
1580 Also correct mistake in the comment.
1581
6a5709a5
JR		 15822004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
1583
1584 * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
1585 ensure that double registers have even numbers.
1586 Add REG_N_B01 for nn01 (binary 01) nibble to ensure
1587 that reserved instruction 0xfffd does not decode the same
1588 as 0xfdfd (ftrv).
1589 * sh-opc.h: Add REG_N_D nibble type and use it whereever
1590 REG_N refers to a double register.
1591 Add REG_N_B01 nibble type and use it instead of REG_NM
1592 in ftrv.
1593 Adjust the bit patterns in a few comments.
1594
e5d2b64f 15952004-02-25 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 1596
1597 * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
e5d2b64f 1598
1f04b05f
AH		 15992004-02-20 Aldy Hernandez <aldyh@redhat.com>
1600
1601 * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
1602
2f3b8700
AH		 16032004-02-20 Aldy Hernandez <aldyh@redhat.com>
1604
1605 * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
1606
f0b26da6 16072004-02-20 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 1608
1609 * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
1610 mtivor32, mtivor33, mtivor34.
f0b26da6 1611
23d59c56 16122004-02-19 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 1613
1614 * ppc-opc.c (powerpc_opcodes): Add mfmcar.
23d59c56 1615
34920d91
NC		 16162004-02-10 Petko Manolov <petkan@nucleusys.com>
1617
1618 * arm-opc.h Maverick accumulator register opcode fixes.
1619
44d86481
BE		 16202004-02-13 Ben Elliston <bje@wasabisystems.com>
1621
1622 * m32r-dis.c: Regenerate.
1623
17707c23
MS		 16242004-01-27 Michael Snyder <msnyder@redhat.com>
1625
1626 * sh-opc.h (sh_table): "fsrra", not "fssra".
1627
fe3a9bc4
NC		 16282004-01-23 Andrew Over <andrew.over@cs.anu.edu.au>
1629
1630 * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
1631 contraints.
1632
ff24f124
JJ		 16332004-01-19 Andrew Over <andrew.over@cs.anu.edu.au>
1634
1635 * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
1636
a02a862a
AM		 16372004-01-19 Alan Modra <amodra@bigpond.net.au>
1638
1639 * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
1640 1. Don't print scale factor on AT&T mode when index missing.
1641
d164ea7f
AO		 16422004-01-16 Alexandre Oliva <aoliva@redhat.com>
1643
1644 * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
1645 when loaded into XR registers.
1646
cb10e79a
RS		 16472004-01-14 Richard Sandiford <rsandifo@redhat.com>
1648
1649 * frv-desc.h: Regenerate.
1650 * frv-desc.c: Regenerate.
1651 * frv-opc.c: Regenerate.
1652
f532f3fa
MS		 16532004-01-13 Michael Snyder <msnyder@redhat.com>
1654
1655 * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
1656
e45d0630
PB		 16572004-01-09 Paul Brook <paul@codesourcery.com>
1658
1659 * arm-opc.h (arm_opcodes): Move generic mcrr after known
1660 specific opcodes.
1661
3ba7a1aa
DJ		 16622004-01-07 Daniel Jacobowitz <drow@mvista.com>
1663
1664 * Makefile.am (libopcodes_la_DEPENDENCIES)
1665 (libopcodes_la_LIBADD): Revert 2003-05-17 change. Add explanatory
1666 comment about the problem.
1667 * Makefile.in: Regenerate.
1668
ba2d3f07
AO		 16692004-01-06 Alexandre Oliva <aoliva@redhat.com>
1670
1671 2003-12-19 Alexandre Oliva <aoliva@redhat.com>
1672 * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
1673 cut&paste errors in shifting/truncating numerical operands.
1674 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
1675 * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
1676 (parse_uslo16): Likewise.
1677 (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
1678 (parse_d12): Parse gotoff12 and gotofffuncdesc12.
1679 (parse_s12): Likewise.
1680 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
1681 * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
1682 (parse_uslo16): Likewise.
1683 (parse_uhi16): Parse gothi and gotfuncdeschi.
1684 (parse_d12): Parse got12 and gotfuncdesc12.
1685 (parse_s12): Likewise.
1686
3ab48931
NC		 16872004-01-02 Albert Bartoszko <albar@nt.kegel.com.pl>
1688
1689 * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
1690 instruction which looks similar to an 'rla' instruction.
a0bd404e 1691
c9e214e5 1692For older changes see ChangeLog-0203
252b5132
RH		 1693\f
1694Local Variables:
2f6d2f85
NC		 1695mode: change-log
1696left-margin: 8
1697fill-column: 74
252b5132
RH		 1698version-control: never
1699End:
GDB Binutils - Deliverables
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