Commit | Line | Data |
---|---|---|
dd5181d5 KT |
1 | 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> |
2 | ||
3 | * arm-dis.c (arm_opcodes): Add entries for CRC instructions. | |
4 | (thumb32_opcodes): Likewise. | |
5 | (print_insn_thumb32): Handle 'S' control char. | |
6 | ||
87a8d6cb NC |
7 | 2013-03-08 Yann Sionneau <yann.sionneau@gmail.com> |
8 | ||
9 | * lm32-desc.c: Regenerate. | |
10 | ||
99dce992 L |
11 | 2013-03-01 H.J. Lu <hongjiu.lu@intel.com> |
12 | ||
13 | * i386-reg.tbl (riz): Add RegRex64. | |
14 | * i386-tbl.h: Regenerated. | |
15 | ||
e60bb1dd YZ |
16 | 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com> |
17 | ||
18 | * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros. | |
19 | (aarch64_feature_crc): New static. | |
20 | (CRC): New macro. | |
21 | (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w, | |
22 | crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions. | |
23 | * aarch64-asm-2.c: Re-generate. | |
24 | * aarch64-dis-2.c: Ditto. | |
25 | * aarch64-opc-2.c: Ditto. | |
26 | ||
c7570fcd AM |
27 | 2013-02-27 Alan Modra <amodra@gmail.com> |
28 | ||
29 | * rl78-decode.opc (rl78_decode_opcode): Fix typo. | |
30 | * rl78-decode.c: Regenerate. | |
31 | ||
151fa98f NC |
32 | 2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com> |
33 | ||
34 | * rl78-decode.opc: Fix encoding of DIVWU insn. | |
35 | * rl78-decode.c: Regenerate. | |
36 | ||
5c111e37 L |
37 | 2013-02-19 H.J. Lu <hongjiu.lu@intel.com> |
38 | ||
39 | PR gas/15159 | |
40 | * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1. | |
41 | ||
42 | * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS. | |
43 | (cpu_flags): Add CpuSMAP. | |
44 | ||
45 | * i386-opc.h (CpuSMAP): New. | |
46 | (i386_cpu_flags): Add cpusmap. | |
47 | ||
48 | * i386-opc.tbl: Add clac and stac. | |
49 | ||
50 | * i386-init.h: Regenerated. | |
51 | * i386-tbl.h: Likewise. | |
52 | ||
9d1df426 NC |
53 | 2013-02-15 Markos Chandras <markos.chandras@imgtec.com> |
54 | ||
55 | * metag-dis.c: Initialize outf->bytes_per_chunk to 4 | |
56 | which also makes the disassembler output be in little | |
57 | endian like it should be. | |
58 | ||
a1ccaec9 YZ |
59 | 2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com> |
60 | ||
61 | * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name' | |
62 | fields to NULL. | |
63 | (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP. | |
64 | ||
ef068ef4 | 65 | 2013-02-13 Maciej W. Rozycki <macro@codesourcery.com> |
5417f71e MR |
66 | |
67 | * mips-dis.c (is_compressed_mode_p): Only match symbols from the | |
68 | section disassembled. | |
69 | ||
6fe6ded9 RE |
70 | 2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> |
71 | ||
72 | * arm-dis.c: Update strht pattern. | |
73 | ||
0aa27725 RS |
74 | 2013-02-09 Jürgen Urban <JuergenUrban@gmx.de> |
75 | ||
76 | * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for | |
77 | single-float. Disable ll, lld, sc and scd for EE. Disable the | |
78 | trunc.w.s macro for EE. | |
79 | ||
36591ba1 SL |
80 | 2013-02-06 Sandra Loosemore <sandra@codesourcery.com> |
81 | Andrew Jenner <andrew@codesourcery.com> | |
82 | ||
83 | Based on patches from Altera Corporation. | |
84 | ||
85 | * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and | |
86 | nios2-opc.c. | |
87 | * Makefile.in: Regenerated. | |
88 | * configure.in: Add case for bfd_nios2_arch. | |
89 | * configure: Regenerated. | |
90 | * disassemble.c (ARCH_nios2): Define. | |
91 | (disassembler): Add case for bfd_arch_nios2. | |
92 | * nios2-dis.c: New file. | |
93 | * nios2-opc.c: New file. | |
94 | ||
545093a4 AM |
95 | 2013-02-04 Alan Modra <amodra@gmail.com> |
96 | ||
97 | * po/POTFILES.in: Regenerate. | |
98 | * rl78-decode.c: Regenerate. | |
99 | * rx-decode.c: Regenerate. | |
100 | ||
e30181a5 YZ |
101 | 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com> |
102 | ||
103 | * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and | |
104 | ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2. | |
105 | * aarch64-asm.c (convert_xtl_to_shll): New function. | |
106 | (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by | |
107 | calling convert_xtl_to_shll. | |
108 | * aarch64-dis.c (convert_shll_to_xtl): New function. | |
109 | (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by | |
110 | calling convert_shll_to_xtl. | |
111 | * aarch64-gen.c: Update copyright year. | |
112 | * aarch64-asm-2.c: Re-generate. | |
113 | * aarch64-dis-2.c: Re-generate. | |
114 | * aarch64-opc-2.c: Re-generate. | |
115 | ||
78c8d46c NC |
116 | 2013-01-24 Nick Clifton <nickc@redhat.com> |
117 | ||
118 | * v850-dis.c: Add support for e3v5 architecture. | |
119 | * v850-opc.c: Likewise. | |
120 | ||
f5555712 YZ |
121 | 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com> |
122 | ||
123 | * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI. | |
124 | * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise. | |
125 | * aarch64-opc.c (operand_general_constraint_met_p): For | |
78c8d46c | 126 | AARCH64_MOD_LSL, move the range check on the shift amount before the |
f5555712 YZ |
127 | alignment check; change to call set_sft_amount_out_of_range_error |
128 | instead of set_imm_out_of_range_error. | |
129 | * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL. | |
130 | (aarch64_opcode_table): Remove the OP enumerator from the asimdimm | |
131 | 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to | |
132 | SIMD_IMM_SFT. | |
133 | ||
2f81ff92 L |
134 | 2013-01-16 H.J. Lu <hongjiu.lu@intel.com> |
135 | ||
136 | * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64. | |
137 | ||
138 | * i386-init.h: Regenerated. | |
139 | * i386-tbl.h: Likewise. | |
140 | ||
dd42f060 NC |
141 | 2013-01-15 Nick Clifton <nickc@redhat.com> |
142 | ||
143 | * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE | |
144 | values. | |
145 | * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute. | |
146 | ||
a4533ed8 NC |
147 | 2013-01-14 Will Newton <will.newton@imgtec.com> |
148 | ||
149 | * metag-dis.c (REG_WIDTH): Increase to 64. | |
150 | ||
5817ffd1 PB |
151 | 2013-01-10 Peter Bergner <bergner@vnet.ibm.com> |
152 | ||
153 | * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries. | |
154 | * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK, | |
155 | XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines. | |
156 | (SH6): Update. | |
157 | <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.", | |
158 | "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.", | |
159 | "treclaim.", "tsr.">: Add POWER8 HTM opcodes. | |
160 | <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes. | |
161 | ||
a3c62988 NC |
162 | 2013-01-10 Will Newton <will.newton@imgtec.com> |
163 | ||
164 | * Makefile.am: Add Meta. | |
165 | * configure.in: Add Meta. | |
166 | * disassemble.c: Add Meta support. | |
167 | * metag-dis.c: New file. | |
168 | * Makefile.in: Regenerate. | |
169 | * configure: Regenerate. | |
170 | ||
73335eae NC |
171 | 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com> |
172 | ||
173 | * cr16-dis.c (make_instruction): Rename to cr16_make_instruction. | |
174 | (match_opcode): Rename to cr16_match_opcode. | |
175 | ||
e407c74b NC |
176 | 2013-01-04 Juergen Urban <JuergenUrban@gmx.de> |
177 | ||
178 | * mips-dis.c: Add names for CP0 registers of r5900. | |
179 | * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for | |
180 | instructions sq and lq. | |
181 | Add support for MIPS r5900 CPU. | |
182 | Add support for 128 bit MMI (Multimedia Instructions). | |
183 | Add support for EE instructions (Emotion Engine). | |
184 | Disable unsupported floating point instructions (64 bit and | |
185 | undefined compare operations). | |
186 | Enable instructions of MIPS ISA IV which are supported by r5900. | |
187 | Disable 64 bit co processor instructions. | |
188 | Disable 64 bit multiplication and division instructions. | |
189 | Disable instructions for co-processor 2 and 3, because these are | |
190 | not supported (preparation for later VU0 support (Vector Unit)). | |
191 | Disable cvt.w.s because this behaves like trunc.w.s and the | |
192 | correct execution can't be ensured on r5900. | |
193 | Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This | |
194 | will confuse less developers and compilers. | |
195 | ||
a32c3ff8 NC |
196 | 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com> |
197 | ||
fb098a1e YZ |
198 | * aarch64-opc.c (aarch64_print_operand): Change to print |
199 | AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal | |
200 | in comment. | |
201 | * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag | |
202 | from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and | |
203 | OP_MOV_IMM_WIDE. | |
204 | ||
205 | 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com> | |
206 | ||
207 | * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP, | |
208 | PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM. | |
a32c3ff8 | 209 | |
62658407 L |
210 | 2013-01-02 H.J. Lu <hongjiu.lu@intel.com> |
211 | ||
212 | * i386-gen.c (process_copyright): Update copyright year to 2013. | |
213 | ||
bab4becb | 214 | 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com> |
5bf135a7 | 215 | |
bab4becb NC |
216 | * cr16-dis.c (match_opcode,make_instruction): Remove static |
217 | declaration. | |
218 | (dwordU,wordU): Moved typedefs to opcode/cr16.h | |
219 | (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'. | |
5bf135a7 | 220 | |
bab4becb | 221 | For older changes see ChangeLog-2012 |
252b5132 | 222 | \f |
bab4becb | 223 | Copyright (C) 2013 Free Software Foundation, Inc. |
752937aa NC |
224 | |
225 | Copying and distribution of this file, with or without modification, | |
226 | are permitted in any medium without royalty provided the copyright | |
227 | notice and this notice are preserved. | |
228 | ||
252b5132 | 229 | Local Variables: |
2f6d2f85 NC |
230 | mode: change-log |
231 | left-margin: 8 | |
232 | fill-column: 74 | |
252b5132 RH |
233 | version-control: never |
234 | End: |