projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
libctf: eliminate dtd_u, part 5: structs / unions
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
80d49d6a
KLC		 12021-03-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
2
3 * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
4
7fce7ea9
PW		 52021-03-12 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
6
7 * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
8 icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
9
78c84bf9
AM		 102021-03-12 Alan Modra <amodra@gmail.com>
11
12 * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
13
fd1fd061
JB		 142021-03-11 Jan Beulich <jbeulich@suse.com>
15
16 * i386-dis.c (OP_XMM): Re-order checks.
17
ac7a2311
JB		 182021-03-11 Jan Beulich <jbeulich@suse.com>
19
20 * i386-dis.c (putop): Drop need_vex check when also checking
21 vex.evex.
22 (intel_operand_size, OP_E_memory): Drop vex.evex check when also
23 checking vex.b.
24
da944c8a
JB		 252021-03-11 Jan Beulich <jbeulich@suse.com>
26
27 * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
28 checks. Move case label past broadcast check.
29
b763d508
JB		 302021-03-10 Jan Beulich <jbeulich@suse.com>
31
32 * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
33 vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
34 REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
35 EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
36 EVEX_W_0F38C7_M_0_L_2): Delete.
37 (REG_EVEX_0F38C7_M_0_L_2): New.
38 (intel_operand_size): Handle VEX and EVEX the same for
39 vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
40 vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
41 (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
42 vex_vsib_q_w_d_mode uses.
43 * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
44 0F38A1, and 0F38A3 entries.
45 * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
46 entry.
47 * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
48 * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
49 0F38A3 entries.
50
32e31ad7
JB		 512021-03-10 Jan Beulich <jbeulich@suse.com>
52
53 * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
54 REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
55 MOD_VEX_0FXOP_09_12): Rename to ...
56 (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
57 REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
58 (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
59 RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
60 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
61 X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
62 (reg_table): Adjust comments.
63 (x86_64_table): Move X86_64_0F24, X86_64_0F26,
64 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
65 X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
66 (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
67 (vex_len_table): Adjust opcode 0A_12 entry.
68 (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
69 MOD_C5_32BIT, and MOD_XOP_09_12 entries.
70 (rm_table): Move hreset entry.
71
85ba7507
JB		 722021-03-10 Jan Beulich <jbeulich@suse.com>
73
74 * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
75 EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
76 EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
77 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
78 EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
79 (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
80 (get_valid_dis386): Also handle 512-bit vector length when
81 vectoring into vex_len_table[].
82 * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
83 0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
84 entries.
85 * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
86 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
87 * i386-dis-evex-prefix.h: Adjust 0F7E entry.
88 * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
89 entries.
90
066f82b9
JB		 912021-03-10 Jan Beulich <jbeulich@suse.com>
92
93 * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
94 Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
95 EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
96 * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
97 entries.
98 * i386-dis-evex-len.h (evex_len_table): Likewise.
99 * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
100
fc681dd6
JB		 1012021-03-10 Jan Beulich <jbeulich@suse.com>
102
103 * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
104 MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
105 MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
106 MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
107 MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
108 MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
109 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
110 MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
111 EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
112 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
113 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
114 EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
115 EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
116 EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
117 EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
118 EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
119 EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
120 EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
121 EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
122 EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
123 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
124 EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
125 EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
126 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
127 EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
128 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
129 EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
130 EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
131 EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
132 EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
133 EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
134 EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
135 REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
136 REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
137 MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
138 MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
139 EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
140 EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
141 EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
142 EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
143 EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
144 EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
145 EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
146 EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
147 EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
148 EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
149 EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
150 EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
151 EVEX_W_0F3A43_L_n): New.
152 * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
153 0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
154 0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
155 * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
156 for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
157 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
158 0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
159 * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
160 0F385B, 0F38C6, and 0F38C7 entries.
161 * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
162 0F38C6 and 0F38C7.
163 * i386-dis-evex-w.h: No longer link to evex_len_table[] for
164 opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
165 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
166 evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
167
13954a31
JB		 1682021-03-10 Jan Beulich <jbeulich@suse.com>
169
170 * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
171 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
172 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
173 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
174 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
175 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
176 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
177 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
178 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
179 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
180 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
181 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
182 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
183 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
184 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
185 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
186 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
187 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
188 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
189 MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
190 MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
191 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
192 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
193 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
194 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
195 PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
196 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
197 PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
198 PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
199 PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
200 VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
201 VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
202 VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
203 VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
204 VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
205 VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
206 VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
207 VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
208 VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
209 VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
210 VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
211 VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
212 VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
213 VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
214 VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
215 VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
216 VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
217 VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
218 VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
219 VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
220 VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
221 VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
222 VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
223 VEX_W_0F99_P_2_LEN_0): Delete.
224 MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
225 MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
226 MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
227 MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
228 MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
229 PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
230 PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
231 PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
232 PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
233 PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
234 PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
235 PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
236 PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
237 PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
238 PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
239 PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
240 PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
241 PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
242 PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
243 VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
244 VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
245 VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
246 VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
247 VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
248 VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
249 VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
250 VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
251 (prefix_table): No longer link to vex_len_table[] for opcodes
252 0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
253 0F92, 0F93, 0F98, and 0F99.
254 (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
255 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
256 0F98, and 0F99.
257 (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
258 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
259 0F98, and 0F99.
260 (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
261 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
262 0F98, and 0F99.
263 (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
264 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
265 0F98, and 0F99.
266
14d10c6c
JB		 2672021-03-10 Jan Beulich <jbeulich@suse.com>
268
269 * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
270 Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
271 REG_VEX_0F73_M_0 respectively.
272 (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
273 MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
274 MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
275 MOD_VEX_0F73_REG_7): Delete.
276 (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
277 (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
278 PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
279 PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
280 PREFIX_VEX_0F3AF0_L_0 respectively.
281 (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
282 VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
283 VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
284 VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
285 (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
286 VEX_LEN_0F38F7): New.
287 (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
288 (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
289 0F72, and 0F73. No longer link to vex_len_table[] for opcode
290 0F38F3.
291 (prefix_table): No longer link to vex_len_table[] for opcodes
292 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
293 (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
294 0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
295 0F38F6, 0F38F7, and 0F3AF0.
296 (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
297 prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
298 (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
299 0F73.
300
00ec1875
JB		 3012021-03-10 Jan Beulich <jbeulich@suse.com>
302
303 * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
304 REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
305 (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
306 MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
307 MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
308 (MOD_0F71, MOD_0F72, MOD_0F73): New.
309 (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
310 73.
311 (reg_table): No longer link to mod_table[] for opcodes 0F71,
312 0F72, and 0F73.
313 (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
314 0F73.
315
31941983
JB		 3162021-03-10 Jan Beulich <jbeulich@suse.com>
317
318 * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
319 MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
320 (reg_table): Don't link to mod_table[] where not needed. Add
321 PREFIX_IGNORED to nop entries.
322 (prefix_table): Replace PREFIX_OPCODE in nop entries.
323 (mod_table): Add nop entries next to prefetch ones. Drop
324 MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
325 MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
326 (rm_table): Add PREFIX_IGNORED to nop entries. Drop
327 PREFIX_OPCODE from endbr* entries.
328 (get_valid_dis386): Also consider entry's name when zapping
329 vindex.
330 (print_insn): Handle PREFIX_IGNORED.
331
742732c7
JB		 3322021-03-09 Jan Beulich <jbeulich@suse.com>
333
334 * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
335 IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
336 element.
337 * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
338 HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
339 (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
340 PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
341 (struct i386_opcode_modifier): Delete notrackprefixok,
342 islockable, hleprefixok, and repprefixok fields. Add prefixok
343 field.
344 * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
345 HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
346 (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
347 not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
348 Replace HLEPrefixOk.
349 * opcodes/i386-tbl.h: Re-generate.
350
e93a3b27
JB		 3512021-03-09 Jan Beulich <jbeulich@suse.com>
352
353 * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
354 * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
355 64-bit form.
356 * opcodes/i386-tbl.h: Re-generate.
357
75363b6d
JB		 3582021-03-03 Jan Beulich <jbeulich@suse.com>
359
360 * i386-gen.c (output_i386_opcode): Don't get operand count. Look
361 for {} instead of {0}. Don't look for '0'.
362 * i386-opc.tbl: Drop operand count field. Drop redundant operand
363 size specifiers.
364
5a9f5403
NC		 3652021-02-19 Nelson Chu <nelson.chu@sifive.com>
366
367 PR 27158
368 * riscv-dis.c (print_insn_args): Updated encoding macros.
369 * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
370 (match_c_addi16sp): Updated encoding macros.
371 (match_c_lui): Likewise.
372 (match_c_lui_with_hint): Likewise.
373 (match_c_addi4spn): Likewise.
374 (match_c_slli): Likewise.
375 (match_slli_as_c_slli): Likewise.
376 (match_c_slli64): Likewise.
377 (match_srxi_as_c_srxi): Likewise.
378 (riscv_insn_types): Added .insn css/cl/cs.
379
3d73d29e
NC		 3802021-02-18 Nelson Chu <nelson.chu@sifive.com>
381
382 * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
383 (default_priv_spec): Updated type to riscv_spec_class.
384 (parse_riscv_dis_option): Updated.
385 * riscv-opc.c: Moved stuff and make the file tidy.
386
b9b204b3
AM		 3872021-02-17 Alan Modra <amodra@gmail.com>
388
389 * wasm32-dis.c: Include limits.h.
390 (CHAR_BIT): Provide backup define.
391 (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
392 Correct signed overflow checking.
393
394ae71f
JB		 3942021-02-16 Jan Beulich <jbeulich@suse.com>
395
396 * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
397 * i386-tbl.h: Re-generate.
398
b818b220
JB		 3992021-02-16 Jan Beulich <jbeulich@suse.com>
400
401 * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
402 Oword.
403 * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
404
ba2b480f
AK		 4052021-02-15 Andreas Krebbel <krebbel@linux.ibm.com>
406
407 * s390-mkopc.c (main): Accept arch14 as cpu string.
408 * s390-opc.txt: Add new arch14 instructions.
409
95148614
NA		 4102021-02-04 Nick Alcock <nick.alcock@oracle.com>
411
412 * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
413 favour of LIBINTL.
414 * configure: Regenerated.
415
bfd428bc
MF		 4162021-02-08 Mike Frysinger <vapier@gentoo.org>
417
418 * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
419 * tic54x-opc.c (regs): Rename to ...
420 (tic54x_regs): ... this.
421 (mmregs): Rename to ...
422 (tic54x_mmregs): ... this.
423 (condition_codes): Rename to ...
424 (tic54x_condition_codes): ... this.
425 (cc2_codes): Rename to ...
426 (tic54x_cc2_codes): ... this.
427 (cc3_codes): Rename to ...
428 (tic54x_cc3_codes): ... this.
429 (status_bits): Rename to ...
430 (tic54x_status_bits): ... this.
431 (misc_symbols): Rename to ...
432 (tic54x_misc_symbols): ... this.
433
24075dcc
NC		 4342021-02-04 Nelson Chu <nelson.chu@sifive.com>
435
436 * riscv-opc.c (MASK_RVB_IMM): Removed.
437 (riscv_opcodes): Removed zb* instructions.
438 (riscv_ext_version_table): Removed versions for zb*.
439
c3ffb8f3
AM		 4402021-01-26 Alan Modra <amodra@gmail.com>
441
442 * i386-gen.c (parse_template): Ensure entire template_instance
443 is initialised.
444
1942a048
NC		 4452021-01-15 Nelson Chu <nelson.chu@sifive.com>
446
447 * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
448 (riscv_fpr_names_abi): Likewise.
449 (riscv_opcodes): Likewise.
450 (riscv_insn_types): Likewise.
451
b800637e
NC		 4522021-01-15 Nelson Chu <nelson.chu@sifive.com>
453
454 * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
455
dcd709e0
NC		 4562021-01-15 Nelson Chu <nelson.chu@sifive.com>
457
458 * riscv-dis.c: Comments tidy and improvement.
459 * riscv-opc.c: Likewise.
460
5347ed60
AM		 4612021-01-13 Alan Modra <amodra@gmail.com>
462
463 * Makefile.in: Regenerate.
464
d546b610
L		 4652021-01-12 H.J. Lu <hongjiu.lu@intel.com>
466
467 PR binutils/26792
468 * configure.ac: Use GNU_MAKE_JOBSERVER.
469 * aclocal.m4: Regenerated.
470 * configure: Likewise.
471
6d104cac
NC		 4722021-01-12 Nick Clifton <nickc@redhat.com>
473
474 * po/sr.po: Updated Serbian translation.
475
83b33c6c
L		 4762021-01-11 H.J. Lu <hongjiu.lu@intel.com>
477
478 PR ld/27173
479 * configure: Regenerated.
480
82c70b08
KT		 4812021-01-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
482
483 * aarch64-asm-2.c: Regenerate.
484 * aarch64-dis-2.c: Likewise.
485 * aarch64-opc-2.c: Likewise.
486 * aarch64-opc.c (aarch64_print_operand):
487 Delete handling of AARCH64_OPND_CSRE_CSR.
488 * aarch64-tbl.h (aarch64_feature_csre): Delete.
489 (CSRE): Likewise.
490 (_CSRE_INSN): Likewise.
491 (aarch64_opcode_table): Delete csr.
492
a8aa72b9
NC		 4932021-01-11 Nick Clifton <nickc@redhat.com>
494
495 * po/de.po: Updated German translation.
496 * po/fr.po: Updated French translation.
497 * po/pt_BR.po: Updated Brazilian Portuguese translation.
498 * po/sv.po: Updated Swedish translation.
499 * po/uk.po: Updated Ukranian translation.
500
a4966cd9
L		 5012021-01-09 H.J. Lu <hongjiu.lu@intel.com>
502
503 * configure: Regenerated.
504
573fe3fb
NC		 5052021-01-09 Nick Clifton <nickc@redhat.com>
506
507 * configure: Regenerate.
508 * po/opcodes.pot: Regenerate.
509
055bc77a
NC		 5102021-01-09 Nick Clifton <nickc@redhat.com>
511
512 * 2.36 release branch crated.
513
aae7fcb8
PB		 5142021-01-08 Peter Bergner <bergner@linux.ibm.com>
515
516 * ppc-opc.c (insert_dw, (extract_dw): New functions.
517 (DW, (XRC_MASK): Define.
518 (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
519
64307045
AM		 5202021-01-09 Alan Modra <amodra@gmail.com>
521
522 * configure: Regenerate.
523
ed205222
NC		 5242021-01-08 Nick Clifton <nickc@redhat.com>
525
526 * po/sv.po: Updated Swedish translation.
527
fb932b57
NC		 5282021-01-08 Nick Clifton <nickc@redhat.com>
529
e84c8716
NC		 530 PR 27129
531 * aarch64-dis.c (determine_disassembling_preference): Move call to
532 aarch64_match_operands_constraint outside of the assertion.
533 * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
534 Replace with a return of FALSE.
535
fb932b57
NC		 536 PR 27139
537 * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
538 core system register.
539
f4782128
ST		 5402021-01-07 Samuel Thibault <samuel.thibault@gnu.org>
541
542 * configure: Regenerate.
543
1b0927db
NC		 5442021-01-07 Nick Clifton <nickc@redhat.com>
545
546 * po/fr.po: Updated French translation.
547
3b288c8e
FN		 5482021-01-07 Fredrik Noring <noring@nocrew.org>
549
550 * m68k-opc.c (chkl): Change minimum architecture requirement to
551 m68020.
552
aa881ecd
PT		 5532021-01-07 Philipp Tomsich <prt@gnu.org>
554
555 * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
556
2652cfad
CXW		 5572021-01-07 Claire Xenia Wolf <claire@symbioticeda.com>
558 Jim Wilson <jimw@sifive.com>
559 Andrew Waterman <andrew@sifive.com>
560 Maxim Blinov <maxim.blinov@embecosm.com>
561 Kito Cheng <kito.cheng@sifive.com>
562 Nelson Chu <nelson.chu@sifive.com>
563
564 * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
565 (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
566
250d07de
AM		 5672021-01-01 Alan Modra <amodra@gmail.com>
568
569 Update year range in copyright notice of all files.
570
c2795844 571For older changes see ChangeLog-2020
3499769a 572\f
c2795844 573Copyright (C) 2021 Free Software Foundation, Inc.
3499769a
AM		 574
575Copying and distribution of this file, with or without modification,
576are permitted in any medium without royalty provided the copyright
577notice and this notice are preserved.
578
579Local Variables:
580mode: change-log
581left-margin: 8
582fill-column: 74
583version-control: never
584End:
GDB Binutils - Deliverables
This page took 0.342972 seconds and 4 git commands to generate.