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[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
86fa6981
L		 12017-03-09 H.J. Lu <hongjiu.lu@intel.com>
2
3 * i386-gen.c (opcode_modifiers): Replace S with Load.
4 * i386-opc.h (S): Removed.
5 (Load): New.
6 (i386_opcode_modifier): Replace s with load.
7 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
8 and {evex}. Replace S with Load.
9 * i386-tbl.h: Regenerated.
10
c1fe188b
L		 112017-03-09 H.J. Lu <hongjiu.lu@intel.com>
12
13 * i386-opc.tbl: Use CpuCET on rdsspq.
14 * i386-tbl.h: Regenerated.
15
4b8b687e
PB		 162017-03-08 Peter Bergner <bergner@vnet.ibm.com>
17
18 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
19 <vsx>: Do not use PPC_OPCODE_VSX3;
20
1437d063
PB		 212017-03-08 Peter Bergner <bergner@vnet.ibm.com>
22
23 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
24
603555e5
L		 252017-03-06 H.J. Lu <hongjiu.lu@intel.com>
26
27 * i386-dis.c (REG_0F1E_MOD_3): New enum.
28 (MOD_0F1E_PREFIX_1): Likewise.
29 (MOD_0F38F5_PREFIX_2): Likewise.
30 (MOD_0F38F6_PREFIX_0): Likewise.
31 (RM_0F1E_MOD_3_REG_7): Likewise.
32 (PREFIX_MOD_0_0F01_REG_5): Likewise.
33 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
34 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
35 (PREFIX_0F1E): Likewise.
36 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
37 (PREFIX_0F38F5): Likewise.
38 (dis386_twobyte): Use PREFIX_0F1E.
39 (reg_table): Add REG_0F1E_MOD_3.
40 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
41 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
42 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
43 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
44 (three_byte_table): Use PREFIX_0F38F5.
45 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
46 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
47 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
48 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
49 PREFIX_MOD_3_0F01_REG_5_RM_2.
50 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
51 (cpu_flags): Add CpuCET.
52 * i386-opc.h (CpuCET): New enum.
53 (CpuUnused): Commented out.
54 (i386_cpu_flags): Add cpucet.
55 * i386-opc.tbl: Add Intel CET instructions.
56 * i386-init.h: Regenerated.
57 * i386-tbl.h: Likewise.
58
73f07bff
AM		 592017-03-06 Alan Modra <amodra@gmail.com>
60
61 PR 21124
62 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
63 (extract_raq, extract_ras, extract_rbx): New functions.
64 (powerpc_operands): Use opposite corresponding insert function.
65 (Q_MASK): Define.
66 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
67 register restriction.
68
65b48a81
PB		 692017-02-28 Peter Bergner <bergner@vnet.ibm.com>
70
71 * disassemble.c Include "safe-ctype.h".
72 (disassemble_init_for_target): Handle s390 init.
73 (remove_whitespace_and_extra_commas): New function.
74 (disassembler_options_cmp): Likewise.
75 * arm-dis.c: Include "libiberty.h".
76 (NUM_ELEM): Delete.
77 (regnames): Use long disassembler style names.
78 Add force-thumb and no-force-thumb options.
79 (NUM_ARM_REGNAMES): Rename from this...
80 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
81 (get_arm_regname_num_options): Delete.
82 (set_arm_regname_option): Likewise.
83 (get_arm_regnames): Likewise.
84 (parse_disassembler_options): Likewise.
85 (parse_arm_disassembler_option): Rename from this...
86 (parse_arm_disassembler_options): ...to this. Make static.
87 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
88 (print_insn): Use parse_arm_disassembler_options.
89 (disassembler_options_arm): New function.
90 (print_arm_disassembler_options): Handle updated regnames.
91 * ppc-dis.c: Include "libiberty.h".
92 (ppc_opts): Add "32" and "64" entries.
93 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
94 (powerpc_init_dialect): Add break to switch statement.
95 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
96 (disassembler_options_powerpc): New function.
97 (print_ppc_disassembler_options): Use ARRAY_SIZE.
98 Remove printing of "32" and "64".
99 * s390-dis.c: Include "libiberty.h".
100 (init_flag): Remove unneeded variable.
101 (struct s390_options_t): New structure type.
102 (options): New structure.
103 (init_disasm): Rename from this...
104 (disassemble_init_s390): ...to this. Add initializations for
105 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
106 (print_insn_s390): Delete call to init_disasm.
107 (disassembler_options_s390): New function.
108 (print_s390_disassembler_options): Print using information from
109 struct 'options'.
110 * po/opcodes.pot: Regenerate.
111
15c7c1d8
JB		 1122017-02-28 Jan Beulich <jbeulich@suse.com>
113
114 * i386-dis.c (PCMPESTR_Fixup): New.
115 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
116 (prefix_table): Use PCMPESTR_Fixup.
117 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
118 PCMPESTR_Fixup.
119 (vex_w_table): Delete VPCMPESTR{I,M} entries.
120 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
121 Split 64-bit and non-64-bit variants.
122 * opcodes/i386-tbl.h: Re-generate.
123
582e12bf
RS		 1242017-02-24 Richard Sandiford <richard.sandiford@arm.com>
125
126 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
127 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
128 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
129 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
130 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
131 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
132 (OP_SVE_V_HSD): New macros.
133 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
134 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
135 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
136 (aarch64_opcode_table): Add new SVE instructions.
137 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
138 for rotation operands. Add new SVE operands.
139 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
140 (ins_sve_quad_index): Likewise.
141 (ins_imm_rotate): Split into...
142 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
143 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
144 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
145 functions.
146 (aarch64_ins_sve_addr_ri_s4): New function.
147 (aarch64_ins_sve_quad_index): Likewise.
148 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
149 * aarch64-asm-2.c: Regenerate.
150 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
151 (ext_sve_quad_index): Likewise.
152 (ext_imm_rotate): Split into...
153 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
154 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
155 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
156 functions.
157 (aarch64_ext_sve_addr_ri_s4): New function.
158 (aarch64_ext_sve_quad_index): Likewise.
159 (aarch64_ext_sve_index): Allow quad indices.
160 (do_misc_decoding): Likewise.
161 * aarch64-dis-2.c: Regenerate.
162 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
163 aarch64_field_kinds.
164 (OPD_F_OD_MASK): Widen by one bit.
165 (OPD_F_NO_ZR): Bump accordingly.
166 (get_operand_field_width): New function.
167 * aarch64-opc.c (fields): Add new SVE fields.
168 (operand_general_constraint_met_p): Handle new SVE operands.
169 (aarch64_print_operand): Likewise.
170 * aarch64-opc-2.c: Regenerate.
171
f482d304
RS		 1722017-02-24 Richard Sandiford <richard.sandiford@arm.com>
173
174 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
175 (aarch64_feature_compnum): ...this.
176 (SIMD_V8_3): Replace with...
177 (COMPNUM): ...this.
178 (CNUM_INSN): New macro.
179 (aarch64_opcode_table): Use it for the complex number instructions.
180
7db2c588
JB		 1812017-02-24 Jan Beulich <jbeulich@suse.com>
182
183 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
184
1e9d41d4
SL		 1852017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
186
187 Add support for associating SPARC ASIs with an architecture level.
188 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
189 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
190 decoding of SPARC ASIs.
191
53c4d625
JB		 1922017-02-23 Jan Beulich <jbeulich@suse.com>
193
194 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
195 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
196
11648de5
JB		 1972017-02-21 Jan Beulich <jbeulich@suse.com>
198
199 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
200 1 (instead of to itself). Correct typo.
201
f98d33be
AW		 2022017-02-14 Andrew Waterman <andrew@sifive.com>
203
204 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
205 pseudoinstructions.
206
773fb663
RS		 2072017-02-15 Richard Sandiford <richard.sandiford@arm.com>
208
209 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
210 (aarch64_sys_reg_supported_p): Handle them.
211
cc07cda6
CZ		 2122017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
213
214 * arc-opc.c (UIMM6_20R): Define.
215 (SIMM12_20): Use above.
216 (SIMM12_20R): Define.
217 (SIMM3_5_S): Use above.
218 (UIMM7_A32_11R_S): Define.
219 (UIMM7_9_S): Use above.
220 (UIMM3_13R_S): Define.
221 (SIMM11_A32_7_S): Use above.
222 (SIMM9_8R): Define.
223 (UIMM10_A32_8_S): Use above.
224 (UIMM8_8R_S): Define.
225 (W6): Use above.
226 (arc_relax_opcodes): Use all above defines.
227
66a5a740
VG		 2282017-02-15 Vineet Gupta <vgupta@synopsys.com>
229
230 * arc-regs.h: Distinguish some of the registers different on
231 ARC700 and HS38 cpus.
232
7e0de605
AM		 2332017-02-14 Alan Modra <amodra@gmail.com>
234
235 PR 21118
236 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
237 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
238
54064fdb
AM		 2392017-02-11 Stafford Horne <shorne@gmail.com>
240 Alan Modra <amodra@gmail.com>
241
242 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
243 Use insn_bytes_value and insn_int_value directly instead. Don't
244 free allocated memory until function exit.
245
dce75bf9
NP		 2462017-02-10 Nicholas Piggin <npiggin@gmail.com>
247
248 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
249
1b7e3d2f
NC		 2502017-02-03 Nick Clifton <nickc@redhat.com>
251
252 PR 21096
253 * aarch64-opc.c (print_register_list): Ensure that the register
254 list index will fir into the tb buffer.
255 (print_register_offset_address): Likewise.
256 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
257
8ec5cf65
AD		 2582017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
259
260 PR 21056
261 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
262 instructions when the previous fetch packet ends with a 32-bit
263 instruction.
264
a1aa5e81
DD		 2652017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
266
267 * pru-opc.c: Remove vague reference to a future GDB port.
268
add3afb2
NC		 2692017-01-20 Nick Clifton <nickc@redhat.com>
270
271 * po/ga.po: Updated Irish translation.
272
c13a63b0
SN		 2732017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
274
275 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
276
9608051a
YQ		 2772017-01-13 Yao Qi <yao.qi@linaro.org>
278
279 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
280 if FETCH_DATA returns 0.
281 (m68k_scan_mask): Likewise.
282 (print_insn_m68k): Update code to handle -1 return value.
283
f622ea96
YQ		 2842017-01-13 Yao Qi <yao.qi@linaro.org>
285
286 * m68k-dis.c (enum print_insn_arg_error): New.
287 (NEXTBYTE): Replace -3 with
288 PRINT_INSN_ARG_MEMORY_ERROR.
289 (NEXTULONG): Likewise.
290 (NEXTSINGLE): Likewise.
291 (NEXTDOUBLE): Likewise.
292 (NEXTDOUBLE): Likewise.
293 (NEXTPACKED): Likewise.
294 (FETCH_ARG): Likewise.
295 (FETCH_DATA): Update comments.
296 (print_insn_arg): Update comments. Replace magic numbers with
297 enum.
298 (match_insn_m68k): Likewise.
299
620214f7
IT		 3002017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
301
302 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
303 * i386-dis-evex.h (evex_table): Updated.
304 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
305 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
306 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
307 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
308 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
309 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
310 * i386-init.h: Regenerate.
311 * i386-tbl.h: Ditto.
312
d95014a2
YQ		 3132017-01-12 Yao Qi <yao.qi@linaro.org>
314
315 * msp430-dis.c (msp430_singleoperand): Return -1 if
316 msp430dis_opcode_signed returns false.
317 (msp430_doubleoperand): Likewise.
318 (msp430_branchinstr): Return -1 if
319 msp430dis_opcode_unsigned returns false.
320 (msp430x_calla_instr): Likewise.
321 (print_insn_msp430): Likewise.
322
0ae60c3e
NC		 3232017-01-05 Nick Clifton <nickc@redhat.com>
324
325 PR 20946
326 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
327 could not be matched.
328 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
329 NULL.
330
d74d4880
SN		 3312017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
332
333 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
334 (aarch64_opcode_table): Use RCPC_INSN.
335
cc917fd9
KC		 3362017-01-03 Kito Cheng <kito.cheng@gmail.com>
337
338 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
339 extension.
340 * riscv-opcodes/all-opcodes: Likewise.
341
b52d3cfc
DP		 3422017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
343
344 * riscv-dis.c (print_insn_args): Add fall through comment.
345
f90c58d5
NC		 3462017-01-03 Nick Clifton <nickc@redhat.com>
347
348 * po/sr.po: New Serbian translation.
349 * configure.ac (ALL_LINGUAS): Add sr.
350 * configure: Regenerate.
351
f47b0d4a
AM		 3522017-01-02 Alan Modra <amodra@gmail.com>
353
354 * epiphany-desc.h: Regenerate.
355 * epiphany-opc.h: Regenerate.
356 * fr30-desc.h: Regenerate.
357 * fr30-opc.h: Regenerate.
358 * frv-desc.h: Regenerate.
359 * frv-opc.h: Regenerate.
360 * ip2k-desc.h: Regenerate.
361 * ip2k-opc.h: Regenerate.
362 * iq2000-desc.h: Regenerate.
363 * iq2000-opc.h: Regenerate.
364 * lm32-desc.h: Regenerate.
365 * lm32-opc.h: Regenerate.
366 * m32c-desc.h: Regenerate.
367 * m32c-opc.h: Regenerate.
368 * m32r-desc.h: Regenerate.
369 * m32r-opc.h: Regenerate.
370 * mep-desc.h: Regenerate.
371 * mep-opc.h: Regenerate.
372 * mt-desc.h: Regenerate.
373 * mt-opc.h: Regenerate.
374 * or1k-desc.h: Regenerate.
375 * or1k-opc.h: Regenerate.
376 * xc16x-desc.h: Regenerate.
377 * xc16x-opc.h: Regenerate.
378 * xstormy16-desc.h: Regenerate.
379 * xstormy16-opc.h: Regenerate.
380
2571583a
AM		 3812017-01-02 Alan Modra <amodra@gmail.com>
382
383 Update year range in copyright notice of all files.
384
5c1ad6b5 385For older changes see ChangeLog-2016
3499769a 386\f
5c1ad6b5 387Copyright (C) 2017 Free Software Foundation, Inc.
3499769a
AM		 388
389Copying and distribution of this file, with or without modification,
390are permitted in any medium without royalty provided the copyright
391notice and this notice are preserved.
392
393Local Variables:
394mode: change-log
395left-margin: 8
396fill-column: 74
397version-control: never
398End:
GDB Binutils - Deliverables
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