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[python] Add gdb.Type.name attribute.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
b0b0c9fc
MR		 12014-01-03 Maciej W. Rozycki <macro@codesourcery.com>
2
3 * nds32-asm.c (parse_operand): Fix out-of-range integer constant.
4
6b9d3259
KLC		 52013-12-17 Kuan-Lin Chen <kuanlinchentw@gmail.com>
6
7 * nds32-dis.c (sr_map): Add system register table for disassembling.
8 (usr_map): Fix typo.
9 * nds32-asm.c (keyword_sr): Add embedded debug registers.
10
4a357820
MZ		 112013-12-17 Michael Zolotukhin <michael.v.zolotukhin@gmail.com>
12
13 * i386-dis.c (MOD_FF_REG_3): New.
14 (MOD_FF_REG_5): Likewise.
15 (mod_table): Add MOD_FF_REG_3 and MOD_FF_REG_5.
16 (reg_table): Use MOD_FF_REG_3 and MOD_FF_REG_5.
17
dc76d757
AB		 182013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
19
20 * mips-dis.c: Add mips_cp1_names pointer.
21 (mips_cp1_names_numeric): New array.
22 (mips_cp1_names_mips3264): New array.
23 (mips_arch_choice): Add cp1_names.
24 (mips_arch_choices): Add relevant cp1 register name array to each of
25 the elements.
26 (set_default_mips_dis_options): Add support for setting up the
27 mips_cp1_names pointer.
28 (parse_mips_dis_option): Add support for the cp1-names command line
29 variable. Also setup the mips_cp1_names pointer.
30 (print_reg): Print out name of the cp1 register.
31
e269fea7
AB		 322013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
33
34 * micromips-opc.c (decode_micromips_operand): Reduced range of +o, +u,
35 +v and +w.
36 (micromips_opcodes): Reduced element index range for sldi, splati,
37 copy_s, copy_u, insert and insve instructions.
38 * opcodes/mips-opc.c (decode_mips_operand): Reduced range of +o, +u,
39 +v and +w.
40 (mips_builtin_opcodes): Reduced element index range for sldi, splati,
41 copy_s, copy_u, insert and insve instructions.
42
1332de01
JBG		 432013-12-13 Jan-Benedict Glaw <jbglaw@lug-owl.de>
44
45 * nds32-dis.c (mnemonic_96): Fix typo.
46
35c08157
KLC		 472013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
48 Wei-Cheng Wang <cole945@gmail.com>
49
50 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nds32-asm.c
51 and nds32-dis.c.
52 * Makefile.in: Regenerate.
53 * configure.in: Add case for bfd_nds32_arch.
54 * configure: Regenerate.
55 * disassemble.c (ARCH_nds32): Define.
56 * nds32-asm.c: New file for nds32.
57 * nds32-asm.h: New file for nds32.
58 * nds32-dis.c: New file for nds32.
59 * nds32-opc.h: New file for nds32.
60
61d4014c
NC		 612013-12-05 Nick Clifton <nickc@redhat.com>
62
63 * s390-mkopc.c (dumpTable): Provide a format string to printf so
64 that compiling with -Werror=format-security does not produce an
65 error.
66
87b8eed7
YZ		 672013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
68
69 * aarch64-opc.c (aarch64_pstatefields): Update.
70
8f8c3854
CM		 712013-11-19 Catherine Moore <clm@codesourcery.com>
72
73 * micromips-opc.c (LM): Define.
74 (micromips_opcodes): Add LM to load instructions.
75 * mips-opc.c (prefe): Add LM attribute.
76
a203d9b7
YZ		 772013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
78
79 Revert
80
81 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
82
83 * aarch64-opc.c (CPENT): New define.
84 (F_READONLY, F_WRITEONLY): Likewise.
85 (aarch64_sys_regs): Add trace unit registers.
86 (aarch64_sys_reg_readonly_p): New function.
87 (aarch64_sys_reg_writeonly_p): Ditto.
88
75468c93
YZ		 892013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
90
91 * aarch64-opc.c (CPENT): New define.
92 (F_READONLY, F_WRITEONLY): Likewise.
93 (aarch64_sys_regs): Add trace unit registers.
94 (aarch64_sys_reg_readonly_p): New function.
95 (aarch64_sys_reg_writeonly_p): Ditto.
96
caeba11c
MR		 972013-11-15 Maciej W. Rozycki <macro@codesourcery.com>
98
99 * mips-opc.c (mips_builtin_opcodes): Add RD_2 to "mfcr" and
100 "mtcr".
101
b83a9376
CM		 1022013-11-11 Catherine Moore <clm@codesourcery.com>
103
104 * mips-dis.c (print_insn_mips): Use
105 INSN_LOAD_MEMORY instead of INSN_LOAD_MEMORY_DELAY.
106 (print_insn_micromips): Likewise.
107 * mips-opc.c (LDD): Remove.
108 (CLD): Include INSN_LOAD_MEMORY.
109 (LM): New.
110 (mips_builtin_opcodes): Use LM instead of LDD.
111 Add LM to load instructions.
112
d56da83e
L		 1132013-11-08 H.J. Lu <hongjiu.lu@intel.com>
114
115 PR gas/16140
116 * i386-gen.c (cpu_flag_init): Remove CpuNop from CPU_K6_2_FLAGS.
117 * i386-init.h: Regenerated.
118
49eec193
YZ		 1192013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
120
121 * aarch64-opc.c (F_DEPRECATED): New macro.
122 (aarch64_sys_regs): Update; flag "spsr_svc" and "spsr_hyp" with
123 F_DEPRECATED.
124 (aarch64_print_operand): Call aarch64_sys_reg_deprecated_p on
125 AARCH64_OPND_SYSREG.
126
68a64283
YZ		 1272013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
128
129 * aarch64-dis.c (convert_ubfm_to_lsl): Check for cond != '111x'.
130 (convert_from_csel): Likewise.
131 * aarch64-opc.c (operand_general_constraint_met_p): Handle
132 AARCH64_OPND_CLASS_COND and AARCH64_OPND_COND1.
133 (aarch64_print_operand): Handle AARCH64_OPND_COND1.
134 * aarch64-tbl.h (aarch64_opcode_table): Use COND1 instead of
135 COND for cinc, cset, cinv, csetm and cneg.
136 (AARCH64_OPERANDS): Add entry for AARCH64_OPND_COND1.
137 * aarch64-asm-2.c: Re-generated.
138 * aarch64-dis-2.c: Ditto.
139 * aarch64-opc-2.c: Ditto.
140
4e50d5f8
YZ		 1412013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
142
143 * aarch64-opc.c (set_syntax_error): New function.
144 (operand_general_constraint_met_p): Replace set_other_error
145 with set_syntax_error.
146
7d4a7d10
AA		 1472013-10-30 Andreas Arnez <arnez@linux.vnet.ibm.com>
148
149 * s390-dis.c (init_disasm): Default to full 'zarch' opcode
150 availability even for 31-bit programs.
151
85181173
RR		 1522013-10-15 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
153
154 * arm-dis.c (neon_opcodes): Adjust print string for vshll.
155
4edbb8e3
CF		 1562013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
157
158 * micromips-opc.c (decode_micromips_operand): Add +T, +U, +V, +W,
159 +d, +e, +h, +k, +l, +n, +o, +u, +v, +w, +x,
160 +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
161 (MSA): New define.
162 (MSA64): New define.
163 (micromips_opcodes): Add MSA instructions.
164 * mips-dis.c (msa_control_names): New array.
165 (mips_abi_choice): Add ASE_MSA to mips32r2.
166 Remove ASE_MDMX from mips64r2.
167 Add ASE_MSA and ASE_MSA64 to mips64r2.
168 (parse_mips_dis_option): Handle -Mmsa.
169 (print_reg): Handle cases for OP_REG_MSA and OP_REG_MSA_CTRL.
170 (print_insn_arg): Handle cases for OP_IMM_INDEX and OP_REG_INDEX.
171 (print_mips_disassembler_options): Print -Mmsa.
172 * mips-opc.c (decode_mips_operand): Add +T, +U, +V, +W, +d, +e, +h, +k,
173 +l, +n, +o, +u, +v, +w, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
174 (MSA): New define.
175 (MSA64): New define.
176 (mips_builtin_op): Add MSA instructions.
177
ae335a4e
SL		 1782013-10-13 Sandra Loosemore <sandra@codesourcery.com>
179
180 * nios2-opc.c (nios2_builtin_reg): Use "sstatus" rather than "ba"
181 as the primary name of r30.
182
6c75cc62
L		 1832013-10-12 Jan Beulich <jbeulich@suse.com>
184
185 * i386-dis.c (intel_operand_size): Move v_bnd_mode alongside the
186 default case.
187 (OP_E_register): Move v_bnd_mode alongside m_mode.
188 * i386-opc.tbl (bndcl, bndcu, bndcn): Split 32- and 64-bit variants.
189 Drop Reg16 and Disp16. Add NoRex64.
190 (bndmk, bndmov, bndldx, bndstx): Drop Disp16.
191 * i386-tbl.h: Re-generate.
192
0e1c2434
SK		 1932013-10-10 Sean Keys <skeys@ipdatasys.com>
194
195 * xgate-opc.c (xgate_opcode): Remove short_hand field from opcode
196 table.
197 * xgate-dis.c (print_insn): Refactor to work with table change.
198
7903e530
RM		 1992013-10-10 Roland McGrath <mcgrathr@google.com>
200
9ce09ba2
RM		 201 * i386-dis.c (oappend_maybe_intel): New function.
202 (OP_ST, OP_STi, append_seg, OP_I, OP_I64, OP_sI, OP_ESreg): Use it.
203 (OP_C, OP_T, CMP_Fixup, OP_EX_VexImmW): Likewise.
204 (VCMP_Fixup, VPCMP_Fixup, PCLMUL_Fixup): Likewise.
205
2b4e983c
RM		 206 * cr16-opc.c (REG): Cast NAME to 'reg' enum type to suppress
207 possible compiler warnings when the union's initializer is
208 actually meant for the 'preg' enum typed member.
209 * crx-opc.c (REG): Likewise.
210
7903e530
RM		 211 * v850-dis.c (v850_cacheop_codes, v850_prefop_codes):
212 Remove duplicate const qualifier.
213
79e0e31d
JB		 2142013-10-08 Jan Beulich <jbeulich@suse.com>
215
216 * i386-opc.tbl (invlpg): Use Anysize instead of Unspecified.
217 (clflush): Use Anysize instead of Byte|Unspecified.
218 (prefetch*): Likewise.
219 * i386-tbl.h: Re-generate.
220
45099dfa
CF		 2212013-10-07 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
222
223 * micromips-opc.c (micromips_opcodes): Fix dmfgc0 and dmtgc0.
224
916fae91
L		 2252013-09-30 H.J. Lu <hongjiu.lu@intel.com>
226
227 * i386-opc.tbl: Add Size64 to movq/vmovq with Reg64 operand.
228 * i386-init.h: Regenerated.
229
c7b0bd56
SE		 2302013-09-30 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
231
232 * i386-gen.c (cpu_flag_init): Add CPU_BDVER4_FLAGS.
233 * i386-init.h: Regenerated.
234
cc9afea3
AM		 2352013-09-20 Alan Modra <amodra@gmail.com>
236
237 * configure: Regenerate.
238
e3f9e852
RS		 2392013-09-17 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
240
241 * s390-opc.txt (clih): Make the immediate unsigned.
242
74db7efb
NC		 2432013-09-04 Roland McGrath <mcgrathr@google.com>
244
245 PR gas/15914
246 * arm-dis.c (arm_opcodes): Add udf.
247 (thumb_opcodes): Use "udf" mnemonic rather than UNDEFINED_INSTRUCTION.
248 (thumb32_opcodes): Add udf.w.
249 (print_insn_thumb32): Handle %H as the thumb32_opcodes comment says.
250
c8094e01
AK		 2512013-09-02 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
252
253 * s390-opc.txt: Fix description for fiebra, fidbra, and fixbra.
254 For the load fp integer instructions only the suppression flag was
255 new with z196 version.
256
7e105031
NC		 2572013-08-28 Nick Clifton <nickc@redhat.com>
258
259 * aarch64-opc.c (aarch64_logical_immediate_p): Return FALSE if the
260 immediate is not suitable for the 32-bit ABI.
261
fb6f3895
MR		 2622013-08-23 Maciej W. Rozycki <macro@codesourcery.com>
263
264 * micromips-opc.c (micromips_opcodes): Use RD_4 for "alnv.ps",
265 replacing NODS.
266
9aff4b7a
NC		 2672013-08-23 Yuri Chornoivan <yurchor@ukr.net>
268
269 PR binutils/15834
270 * aarch64-asm.c: Fix typos.
271 * aarch64-dis.c: Likewise.
272 * msp430-dis.c: Likewise.
273
5e0dc5ba
RS		 2742013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
275
276 * micromips-opc.c (micromips_opcodes): Replace "dext" and "dins"
277 macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases.
278 Use +H rather than +C for the real "dext".
279 * mips-opc.c (mips_builtin_opcodes): Likewise.
280
0f35dbc4
RS		 2812013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
282
283 * mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros.
284 * micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG
285 and OPTIONAL_MAPPED_REG.
286 * mips-opc.c (decode_mips_operand): Likewise.
287 * mips16-opc.c (decode_mips16_operand): Likewise.
288 * mips-dis.c (print_insn_arg): Handle OP_OPTIONAL_REG.
289
79ceb7cb
L		 2902013-08-19 H.J. Lu <hongjiu.lu@intel.com>
291
292 * i386-dis.c (PREFIX_EVEX_0F3A3E): Removed.
293 (PREFIX_EVEX_0F3A3F): Likewise.
294 * i386-dis-evex.h (evex_table): Updated.
295
ee5734f0
RS		 2962013-08-06 Jürgen Urban <JuergenUrban@gmx.de>
297
298 * mips-opc.c (mips_builtin_opcodes): Add a suffixless version of
299 VCLIPW.
300
d6787ef9
EB		 3012013-08-05 Eric Botcazou <ebotcazou@adacore.com>
302 Konrad Eisele <konrad@gaisler.com>
303
304 * sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for
305 bfd_mach_sparc.
306 * sparc-opc.c (MASK_LEON): Define.
307 (v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON.
308 (letandleon): New macro.
309 (v9andleon): Likewise.
310 (sparc_opc): Add leon.
311 (umac): Enable for letandleon.
312 (smac): Likewise.
313 (casa): Enable for v9andleon.
314 (cas): Likewise.
315 (casl): Likewise.
316
14daeee3
RS		 3172013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
318 Richard Sandiford <rdsandiford@googlemail.com>
319
320 * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
321 OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
322 (print_vu0_channel): New function.
323 (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
324 (print_insn_args): Handle '#'.
325 (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
326 * mips-opc.c (mips_vu0_channel_mask): New constant.
327 (decode_mips_operand): Handle new VU0 operand types.
328 (VU0, VU0CH): New macros.
329 (mips_builtin_opcodes): Add VU0 opcodes. Use "+7" rather than "E"
330 for LQC2 and SQC2. Use "+9" rather than "G" for EE CFC2 and CTC2.
331 Use "+6" rather than "G" for QMFC2 and QMTC2.
332
3ccad066
RS		 3332013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
334
335 * mips-formats.h (PCREL): Reorder parameters and update the definition
336 to match new mips_pcrel_operand layout.
337 (JUMP, JALX, BRANCH): Update accordingly.
338 * mips16-opc.c (decode_mips16_operand): Likewise.
339
df34fbcc
RS		 3402013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
341
342 * micromips-opc.c (WR_s): Delete.
343
fc76e730
RS		 3442013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
345
346 * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
347 New macros.
348 (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
349 (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
350 (mips_builtin_opcodes): Use the new position-based read-write flags
351 instead of field-based ones. Use UDI for "udi..." instructions.
352 * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
353 New macros.
354 (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
355 (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
356 (WR_SP, RD_16): New macros.
357 (RD_SP): Redefine as an INSN2_* flag.
358 (MOD_SP): Redefine in terms of RD_SP and WR_SP.
359 (mips16_opcodes): Use the new position-based read-write flags
360 instead of field-based ones. Use RD_16 for "nop". Move RD_SP to
361 pinfo2 field.
362 * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
363 New macros.
364 (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
365 (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
366 (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
367 (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
368 (micromips_opcodes): Use the new position-based read-write flags
369 instead of field-based ones.
370 * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
371 (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
372 of field-based flags.
373
26545944
RS		 3742013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
375
376 * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
377 (WR_SP): Replace with...
378 (MOD_SP): ...this.
379 (mips16_opcodes): Update accordingly.
380 * mips-dis.c (print_insn_mips16): Likewise.
381
a8d92fc6
RS		 3822013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
383
384 * mips16-opc.c (mips16_opcodes): Reformat.
385
6a819047
RS		 3862013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
387
388 * mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
389 for operands that are hard-coded to $0.
390 * micromips-opc.c (micromips_opcodes): Likewise.
391
344c74a6
RS		 3922013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
393
394 * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
395 for the single-operand forms of JALR and JALR.HB.
396 * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
397 and JALRS.HB.
398
41989114
RS		 3992013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
400
401 * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
402 instructions. Fix them to use WR_MACC instead of WR_CC and
403 add missing RD_MACCs.
404
6d075bce
RS		 4052013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
406
407 * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
408
4f6ffcd3
PB		 4092013-07-29 Peter Bergner <bergner@vnet.ibm.com>
410
411 * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
412
43234a1e
L		 4132013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
414 Alexander Ivchenko <alexander.ivchenko@intel.com>
415 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
416 Sergey Lega <sergey.s.lega@intel.com>
417 Anna Tikhonova <anna.tikhonova@intel.com>
418 Ilya Tocar <ilya.tocar@intel.com>
419 Andrey Turetskiy <andrey.turetskiy@intel.com>
420 Ilya Verbin <ilya.verbin@intel.com>
421 Kirill Yukhin <kirill.yukhin@intel.com>
422 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
423
424 * i386-dis-evex.h: New.
425 * i386-dis.c (OP_Rounding): New.
426 (VPCMP_Fixup): New.
427 (OP_Mask): New.
428 (Rdq): New.
429 (XMxmmq): New.
430 (EXdScalarS): New.
431 (EXymm): New.
432 (EXEvexHalfBcstXmmq): New.
433 (EXxmm_mdq): New.
434 (EXEvexXGscat): New.
435 (EXEvexXNoBcst): New.
436 (VPCMP): New.
437 (EXxEVexR): New.
438 (EXxEVexS): New.
439 (XMask): New.
440 (MaskG): New.
441 (MaskE): New.
442 (MaskR): New.
443 (MaskVex): New.
444 (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
445 evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
446 evex_rounding_mode, evex_sae_mode, mask_mode.
447 (USE_EVEX_TABLE): New.
448 (EVEX_TABLE): New.
449 (EVEX enum): New.
450 (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
451 REG_EVEX_0F38C7.
452 (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
453 MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
454 MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
455 MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
456 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5,
457 MOD_EVEX_0F38C7_REG_6.
458 (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
459 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
460 PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
461 PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
462 PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
463 PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
464 PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
465 PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
466 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
467 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
468 PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
469 PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
470 PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
471 PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
472 PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
473 PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
474 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
475 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
476 PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
477 PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
478 PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
479 PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
480 PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
481 PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
482 PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
483 PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
484 PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
485 PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
486 PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
487 PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
488 PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
489 PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
490 PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
491 PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
492 PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
493 PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
494 PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
495 PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
496 PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
497 PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
498 PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
499 PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
500 PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
501 PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
502 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
503 PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
504 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
505 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
506 PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
507 PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
508 PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
509 PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
510 PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
511 PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
512 PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
513 PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
514 PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
515 PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
516 PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
517 PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
518 PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
519 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
520 PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
521 PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
522 PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
523 PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
524 PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
525 PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
526 PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
527 PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
528 PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
529 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
530 PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
531 PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
532 PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
533 PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
534 PREFIX_EVEX_0F3A55.
535 (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
536 VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
537 VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
538 VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
539 VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
540 VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
541 VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
542 VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
543 VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
544 VEX_W_0F3A32_P_2_LEN_0.
545 (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
546 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
547 EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
548 EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
549 EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
550 EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
551 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
552 EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
553 EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
554 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
555 EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
556 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
557 EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
558 EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
559 EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
560 EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
561 EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
562 EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
563 EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
564 EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
565 EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
566 EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
567 EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
568 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
569 EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
570 EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
571 EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
572 EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
573 EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
574 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
575 EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
576 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
577 EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
578 EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
579 EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
580 EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
581 EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
582 EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
583 EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
584 EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
585 EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
586 EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
587 EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
588 EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
589 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
590 EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
591 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
592 EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
593 EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
594 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
595 EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
596 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
597 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
598 EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
599 (struct vex): Add fields evex, r, v, mask_register_specifier,
600 zeroing, ll, b.
601 (intel_names_xmm): Add upper 16 registers.
602 (att_names_xmm): Ditto.
603 (intel_names_ymm): Ditto.
604 (att_names_ymm): Ditto.
605 (names_zmm): New.
606 (intel_names_zmm): Ditto.
607 (att_names_zmm): Ditto.
608 (names_mask): Ditto.
609 (intel_names_mask): Ditto.
610 (att_names_mask): Ditto.
611 (names_rounding): Ditto.
612 (names_broadcast): Ditto.
613 (x86_64_table): Add escape to evex-table.
614 (reg_table): Include reg_table evex-entries from
615 i386-dis-evex.h. Fix prefetchwt1 instruction.
616 (prefix_table): Add entries for new instructions.
617 (vex_table): Ditto.
618 (vex_len_table): Ditto.
619 (vex_w_table): Ditto.
620 (mod_table): Ditto.
621 (get_valid_dis386): Properly handle new instructions.
622 (print_insn): Handle zmm and mask registers, print mask operand.
623 (intel_operand_size): Support EVEX, new modes and sizes.
624 (OP_E_register): Handle new modes.
625 (OP_E_memory): Ditto.
626 (OP_G): Ditto.
627 (OP_XMM): Ditto.
628 (OP_EX): Ditto.
629 (OP_VEX): Ditto.
630 * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
631 CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
632 CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
633 (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
634 CpuAVX512PF and CpuVREX.
635 (operand_type_init): Add OPERAND_TYPE_REGZMM,
636 OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
637 (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
638 StaticRounding, SAE, Disp8MemShift, NoDefMask.
639 (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
640 * i386-init.h: Regenerate.
641 * i386-opc.h (CpuAVX512F): New.
642 (CpuAVX512CD): New.
643 (CpuAVX512ER): New.
644 (CpuAVX512PF): New.
645 (CpuVREX): New.
646 (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
647 cpuavx512pf and cpuvrex fields.
648 (VecSIB): Add VecSIB512.
649 (EVex): New.
650 (Masking): New.
651 (VecESize): New.
652 (Broadcast): New.
653 (StaticRounding): New.
654 (SAE): New.
655 (Disp8MemShift): New.
656 (NoDefMask): New.
657 (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
658 staticrounding, sae, disp8memshift and nodefmask.
659 (RegZMM): New.
660 (Zmmword): Ditto.
661 (Vec_Disp8): Ditto.
662 (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
663 fields.
664 (RegVRex): New.
665 * i386-opc.tbl: Add AVX512 instructions.
666 * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
667 registers, mask registers.
668 * i386-tbl.h: Regenerate.
669
1d2db237
RS		 6702013-07-25 Aaro Koskinen <aaro.koskinen@iki.fi>
671
672 PR gas/15220
673 * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
674 Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
675
a0046408
L		 6762013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
677
678 * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
679 PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
680 PREFIX_0F3ACC.
681 (prefix_table): Updated.
682 (three_byte_table): Likewise.
683 * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
684 (cpu_flags): Add CpuSHA.
685 (i386_cpu_flags): Add cpusha.
686 * i386-init.h: Regenerate.
687 * i386-opc.h (CpuSHA): New.
688 (CpuUnused): Restored.
689 (i386_cpu_flags): Add cpusha.
690 * i386-opc.tbl: Add SHA instructions.
691 * i386-tbl.h: Regenerate.
692
7e8b059b
L		 6932013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
694 Kirill Yukhin <kirill.yukhin@intel.com>
695 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
696
697 * i386-dis.c (BND_Fixup): New.
698 (Ebnd): New.
699 (Ev_bnd): New.
700 (Gbnd): New.
701 (BND): New.
702 (v_bnd_mode): New.
703 (bnd_mode): New.
c623f86c
L		 704 (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
705 MOD_0F1B_PREFIX_1.
706 (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
7e8b059b
L		 707 (dis tables): Replace XX with BND for near branch and call
708 instructions.
709 (prefix_table): Add new entries.
710 (mod_table): Likewise.
711 (names_bnd): New.
712 (intel_names_bnd): New.
713 (att_names_bnd): New.
714 (BND_PREFIX): New.
715 (prefix_name): Handle BND_PREFIX.
716 (print_insn): Initialize names_bnd.
717 (intel_operand_size): Handle new modes.
718 (OP_E_register): Likewise.
719 (OP_E_memory): Likewise.
720 (OP_G): Likewise.
721 * i386-gen.c (cpu_flag_init): Add CpuMPX.
722 (cpu_flags): Add CpuMPX.
723 (operand_type_init): Add RegBND.
724 (opcode_modifiers): Add BNDPrefixOk.
725 (operand_types): Add RegBND.
726 * i386-init.h: Regenerate.
727 * i386-opc.h (CpuMPX): New.
728 (CpuUnused): Comment out.
729 (i386_cpu_flags): Add cpumpx.
730 (BNDPrefixOk): New.
731 (i386_opcode_modifier): Add bndprefixok.
732 (RegBND): New.
733 (i386_operand_type): Add regbnd.
734 * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
735 Add MPX instructions and bnd prefix.
736 * i386-reg.tbl: Add bnd0-bnd3 registers.
737 * i386-tbl.h: Regenerate.
738
b56e23fb
RS		 7392013-07-17 Richard Sandiford <rdsandiford@googlemail.com>
740
741 * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
742 ATTRIBUTE_UNUSED.
743
e7ae278d
RS		 7442013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
745
746 * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
747 special rules.
748 * Makefile.in: Regenerate.
749 * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
750 all fields. Reformat.
751
c3c07478
RS		 7522013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
753
754 * mips16-opc.c: Include mips-formats.h.
755 (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
756 static arrays.
757 (decode_mips16_operand): New function.
758 * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
759 (print_insn_arg): Handle OP_ENTRY_EXIT list.
760 Abort for OP_SAVE_RESTORE_LIST.
761 (print_mips16_insn_arg): Change interface. Use mips_operand
762 structures. Delete GET_OP_S. Move GET_OP definition to...
763 (print_insn_mips16): ...here. Call init_print_arg_state.
764 Update the call to print_mips16_insn_arg.
765
ab902481
RS		 7662013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
767
768 * mips-formats.h: New file.
769 * mips-opc.c: Include mips-formats.h.
770 (reg_0_map): New static array.
771 (decode_mips_operand): New function.
772 * micromips-opc.c: Remove <stdio.h> include. Include mips-formats.h.
773 (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
774 (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
775 (int_c_map): New static arrays.
776 (decode_micromips_operand): New function.
777 * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
778 (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
779 (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
780 (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
781 (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
782 (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
783 (micromips_imm_b_map, micromips_imm_c_map): Delete.
784 (print_reg): New function.
785 (mips_print_arg_state): New structure.
786 (init_print_arg_state, print_insn_arg): New functions.
787 (print_insn_args): Change interface and use mips_operand structures.
788 Delete GET_OP_S. Move GET_OP definition to...
789 (print_insn_mips): ...here. Update the call to print_insn_args.
790 (print_insn_micromips): Use print_insn_args.
791
cc537e56
RS		 7922013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
793
794 * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
795 in macros.
796
7a5f87ce
RS		 7972013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
798
799 * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
800 ADDA.S, MULA.S and SUBA.S.
801
41741fa4
L		 8022013-07-08 H.J. Lu <hongjiu.lu@intel.com>
803
804 PR gas/13572
805 * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
806 * i386-tbl.h: Regenerated.
807
f2ae14a1
RS		 8082013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
809
810 * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
811 and SD A(B) macros up.
812 * micromips-opc.c (micromips_opcodes): Likewise.
813
04c9d415
RS		 8142013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
815
816 * mips16-opc.c: Add entries for argumentless "entry" and "exit"
817 instructions.
818
5c324c16
RS		 8192013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
820
821 * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
822 MDMX-like instructions.
823 * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
824 printing "Q" operands for INSN_5400 instructions.
825
23e69e47
RS		 8262013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
827
828 * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
829 "+S" for "cins".
830 * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
831 Combine cases.
832
27c5c572
RS		 8332013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
834
835 * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
836 "jalx".
837 * mips16-opc.c (mips16_opcodes): Likewise.
838 * micromips-opc.c (micromips_opcodes): Likewise.
839 * mips-dis.c (print_insn_args, print_mips16_insn_arg)
840 (print_insn_mips16): Handle "+i".
841 (print_insn_micromips): Likewise. Conditionally preserve the
842 ISA bit for "a" but not for "+i".
843
e76ff5ab
RS		 8442013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
845
846 * micromips-opc.c (WR_mhi): Rename to..
847 (WR_mh): ...this.
848 (micromips_opcodes): Update "movep" entry accordingly. Replace
849 "mh,mi" with "mh".
850 * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
851 (micromips_to_32_reg_h_map1): ...this.
852 (micromips_to_32_reg_i_map): Rename to...
853 (micromips_to_32_reg_h_map2): ...this.
854 (print_micromips_insn): Remove "mi" case. Print both registers
855 in the pair for "mh".
856
fa7616a4
RS		 8572013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
858
859 * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
860 * micromips-opc.c (micromips_opcodes): Likewise.
861 * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
862 and "+T" handling. Check for a "0" suffix when deciding whether to
863 use coprocessor 0 names. In that case, also check for ",H" selectors.
864
fb798c50
AK		 8652013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
866
867 * s390-opc.c (J12_12, J24_24): New macros.
868 (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
869 (MASK_MII_UPI): Rename to MASK_MII_UPP.
870 * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
871
58ae08f2
AM		 8722013-07-04 Alan Modra <amodra@gmail.com>
873
874 * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
875
b5e04c2b
NC		 8762013-06-26 Nick Clifton <nickc@redhat.com>
877
878 * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
879 field when checking for type 2 nop.
880 * rx-decode.c: Regenerate.
881
833794fc
MR		 8822013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
883
884 * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
885 and "movep" macros.
886
1bbce132
MR		 8872013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
888
889 * mips-dis.c (is_mips16_plt_tail): New function.
890 (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
891 word.
892 (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
893
34c911a4
NC		 8942013-06-21 DJ Delorie <dj@redhat.com>
895
896 * msp430-decode.opc: New.
897 * msp430-decode.c: New/generated.
898 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
899 (MAINTAINER_CLEANFILES): Likewise.
900 Add rule to build msp430-decode.c frommsp430decode.opc
901 using the opc2c program.
902 * Makefile.in: Regenerate.
903 * configure.in: Add msp430-decode.lo to msp430 architecture files.
904 * configure: Regenerate.
905
b9eead84
YZ		 9062013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
907
908 * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
909 (SYMTAB_AVAILABLE): Removed.
910 (#include "elf/aarch64.h): Ditto.
911
7f3c4072
CM		 9122013-06-17 Catherine Moore <clm@codesourcery.com>
913 Maciej W. Rozycki <macro@codesourcery.com>
914 Chao-Ying Fu <fu@mips.com>
915
916 * micromips-opc.c (EVA): Define.
917 (TLBINV): Define.
918 (micromips_opcodes): Add EVA opcodes.
919 * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
920 (print_insn_args): Handle EVA offsets.
921 (print_insn_micromips): Likewise.
922 * mips-opc.c (EVA): Define.
923 (TLBINV): Define.
924 (mips_builtin_opcodes): Add EVA opcodes.
925
de40ceb6
AM		 9262013-06-17 Alan Modra <amodra@gmail.com>
927
928 * Makefile.am (mips-opc.lo): Add rules to create automatic
929 dependency files. Pass archdefs.
930 (micromips-opc.lo, mips16-opc.lo): Likewise.
931 * Makefile.in: Regenerate.
932
3531d549
DD		 9332013-06-14 DJ Delorie <dj@redhat.com>
934
935 * rx-decode.opc (rx_decode_opcode): Bit operations on
936 registers are 32-bit operations, not 8-bit operations.
937 * rx-decode.c: Regenerate.
938
ba92f7fb
CF		 9392013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
940
941 * micromips-opc.c (IVIRT): New define.
942 (IVIRT64): New define.
943 (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
944 tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
945
946 * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
947 dmtgc0 to print cp0 names.
948
9daf7bab
SL		 9492013-06-09 Sandra Loosemore <sandra@codesourcery.com>
950
951 * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
952 argument.
953
d301a56b
RS		 9542013-06-08 Catherine Moore <clm@codesourcery.com>
955 Richard Sandiford <rdsandiford@googlemail.com>
956
957 * micromips-opc.c (D32, D33, MC): Update definitions.
958 (micromips_opcodes): Initialize ase field.
959 * mips-dis.c (mips_arch_choice): Add ase field.
960 (mips_arch_choices): Initialize ase field.
961 (set_default_mips_dis_options): Declare and setup mips_ase.
962 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
963 MT32, MC): Update definitions.
964 (mips_builtin_opcodes): Initialize ase field.
965
a3dcb6c5
RS		 9662013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
967
968 * s390-opc.txt (flogr): Require a register pair destination.
969
6cf1d90c
AK		 9702013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
971
972 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
973 instruction format.
974
c77c0862
RS		 9752013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
976
977 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
978
c0637f3a
PB		 9792013-05-20 Peter Bergner <bergner@vnet.ibm.com>
980
981 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
982 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
983 XLS_MASK, PPCVSX2): New defines.
984 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
985 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
986 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
987 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
988 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
989 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
990 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
991 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
992 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
993 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
994 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
995 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
996 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
997 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
998 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
999 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
1000 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
1001 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
1002 <lxvx, stxvx>: New extended mnemonics.
1003
4934fdaf
AM		 10042013-05-17 Alan Modra <amodra@gmail.com>
1005
1006 * ia64-raw.tbl: Replace non-ASCII char.
1007 * ia64-waw.tbl: Likewise.
1008 * ia64-asmtab.c: Regenerate.
1009
6091d651
SE		 10102013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
1011
1012 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
1013 * i386-init.h: Regenerated.
1014
d2865ed3
YZ		 10152013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
1016
1017 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
1018 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
1019 check from [0, 255] to [-128, 255].
1020
b015e599
AP		 10212013-05-09 Andrew Pinski <apinski@cavium.com>
1022
1023 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
1024 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
1025 (parse_mips_dis_option): Handle the virt option.
1026 (print_insn_args): Handle "+J".
1027 (print_mips_disassembler_options): Print out message about virt64.
1028 * mips-opc.c (IVIRT): New define.
1029 (IVIRT64): New define.
1030 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
1031 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
1032 Move rfe to the bottom as it conflicts with tlbgp.
1033
9f0682fe
AM		 10342013-05-09 Alan Modra <amodra@gmail.com>
1035
1036 * ppc-opc.c (extract_vlesi): Properly sign extend.
1037 (extract_vlensi): Likewise. Comment reason for setting invalid.
1038
13761a11
NC		 10392013-05-02 Nick Clifton <nickc@redhat.com>
1040
1041 * msp430-dis.c: Add support for MSP430X instructions.
1042
e3031850
SL		 10432013-04-24 Sandra Loosemore <sandra@codesourcery.com>
1044
1045 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
1046 to "eccinj".
1047
17310e56
NC		 10482013-04-17 Wei-chen Wang <cole945@gmail.com>
1049
1050 PR binutils/15369
1051 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
1052 of CGEN_CPU_ENDIAN.
1053 (hash_insns_list): Likewise.
1054
731df338
JK		 10552013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
1056
1057 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
1058 warning workaround.
1059
5f77db52
JB		 10602013-04-08 Jan Beulich <jbeulich@suse.com>
1061
1062 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
1063 * i386-tbl.h: Re-generate.
1064
0afd1215
DM		 10652013-04-06 David S. Miller <davem@davemloft.net>
1066
1067 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
1068 of an opcode, prefer the one with F_PREFERRED set.
1069 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
1070 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
1071 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
1072 mark existing mnenomics as aliases. Add "cc" suffix to edge
1073 instructions generating condition codes, mark existing mnenomics
1074 as aliases. Add "fp" prefix to VIS compare instructions, mark
1075 existing mnenomics as aliases.
1076
41702d50
NC		 10772013-04-03 Nick Clifton <nickc@redhat.com>
1078
1079 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
1080 destination address by subtracting the operand from the current
1081 address.
1082 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
1083 a positive value in the insn.
1084 (extract_u16_loop): Do not negate the returned value.
1085 (D16_LOOP): Add V850_INVERSE_PCREL flag.
1086
1087 (ceilf.sw): Remove duplicate entry.
1088 (cvtf.hs): New entry.
1089 (cvtf.sh): Likewise.
1090 (fmaf.s): Likewise.
1091 (fmsf.s): Likewise.
1092 (fnmaf.s): Likewise.
1093 (fnmsf.s): Likewise.
1094 (maddf.s): Restrict to E3V5 architectures.
1095 (msubf.s): Likewise.
1096 (nmaddf.s): Likewise.
1097 (nmsubf.s): Likewise.
1098
55cf16e1
L		 10992013-03-27 H.J. Lu <hongjiu.lu@intel.com>
1100
1101 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
1102 check address mode.
1103 (print_insn): Pass sizeflag to get_sib.
1104
51dcdd4d
NC		 11052013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
1106
1107 PR binutils/15068
1108 * tic6x-dis.c: Add support for displaying 16-bit insns.
1109
795b8e6b
NC		 11102013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
1111
1112 PR gas/15095
1113 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
1114 individual msb and lsb halves in src1 & src2 fields. Discard the
1115 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
1116 follow what Ti SDK does in that case as any value in the src1
1117 field yields the same output with SDK disassembler.
1118
314d60dd
ME		 11192013-03-12 Michael Eager <eager@eagercon.com>
1120
795b8e6b 1121 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
314d60dd 1122
dad60f8e
SL		 11232013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
1124
1125 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
1126
f5cb796a
SL		 11272013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
1128
1129 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
1130
21fde85c
SL		 11312013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
1132
1133 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
1134
dd5181d5
KT		 11352013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1136
1137 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
1138 (thumb32_opcodes): Likewise.
1139 (print_insn_thumb32): Handle 'S' control char.
1140
87a8d6cb
NC		 11412013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
1142
1143 * lm32-desc.c: Regenerate.
1144
99dce992
L		 11452013-03-01 H.J. Lu <hongjiu.lu@intel.com>
1146
1147 * i386-reg.tbl (riz): Add RegRex64.
1148 * i386-tbl.h: Regenerated.
1149
e60bb1dd
YZ		 11502013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
1151
1152 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
1153 (aarch64_feature_crc): New static.
1154 (CRC): New macro.
1155 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
1156 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
1157 * aarch64-asm-2.c: Re-generate.
1158 * aarch64-dis-2.c: Ditto.
1159 * aarch64-opc-2.c: Ditto.
1160
c7570fcd
AM		 11612013-02-27 Alan Modra <amodra@gmail.com>
1162
1163 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
1164 * rl78-decode.c: Regenerate.
1165
151fa98f
NC		 11662013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
1167
1168 * rl78-decode.opc: Fix encoding of DIVWU insn.
1169 * rl78-decode.c: Regenerate.
1170
5c111e37
L		 11712013-02-19 H.J. Lu <hongjiu.lu@intel.com>
1172
1173 PR gas/15159
1174 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
1175
1176 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
1177 (cpu_flags): Add CpuSMAP.
1178
1179 * i386-opc.h (CpuSMAP): New.
1180 (i386_cpu_flags): Add cpusmap.
1181
1182 * i386-opc.tbl: Add clac and stac.
1183
1184 * i386-init.h: Regenerated.
1185 * i386-tbl.h: Likewise.
1186
9d1df426
NC		 11872013-02-15 Markos Chandras <markos.chandras@imgtec.com>
1188
1189 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
1190 which also makes the disassembler output be in little
1191 endian like it should be.
1192
a1ccaec9
YZ		 11932013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
1194
1195 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
1196 fields to NULL.
1197 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
1198
ef068ef4 11992013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
5417f71e
MR		 1200
1201 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
1202 section disassembled.
1203
6fe6ded9
RE		 12042013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1205
1206 * arm-dis.c: Update strht pattern.
1207
0aa27725
RS		 12082013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
1209
1210 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
1211 single-float. Disable ll, lld, sc and scd for EE. Disable the
1212 trunc.w.s macro for EE.
1213
36591ba1
SL		 12142013-02-06 Sandra Loosemore <sandra@codesourcery.com>
1215 Andrew Jenner <andrew@codesourcery.com>
1216
1217 Based on patches from Altera Corporation.
1218
1219 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
1220 nios2-opc.c.
1221 * Makefile.in: Regenerated.
1222 * configure.in: Add case for bfd_nios2_arch.
1223 * configure: Regenerated.
1224 * disassemble.c (ARCH_nios2): Define.
1225 (disassembler): Add case for bfd_arch_nios2.
1226 * nios2-dis.c: New file.
1227 * nios2-opc.c: New file.
1228
545093a4
AM		 12292013-02-04 Alan Modra <amodra@gmail.com>
1230
1231 * po/POTFILES.in: Regenerate.
1232 * rl78-decode.c: Regenerate.
1233 * rx-decode.c: Regenerate.
1234
e30181a5
YZ		 12352013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
1236
1237 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
1238 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
1239 * aarch64-asm.c (convert_xtl_to_shll): New function.
1240 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1241 calling convert_xtl_to_shll.
1242 * aarch64-dis.c (convert_shll_to_xtl): New function.
1243 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1244 calling convert_shll_to_xtl.
1245 * aarch64-gen.c: Update copyright year.
1246 * aarch64-asm-2.c: Re-generate.
1247 * aarch64-dis-2.c: Re-generate.
1248 * aarch64-opc-2.c: Re-generate.
1249
78c8d46c
NC		 12502013-01-24 Nick Clifton <nickc@redhat.com>
1251
1252 * v850-dis.c: Add support for e3v5 architecture.
1253 * v850-opc.c: Likewise.
1254
f5555712
YZ		 12552013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
1256
1257 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
1258 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
1259 * aarch64-opc.c (operand_general_constraint_met_p): For
78c8d46c 1260 AARCH64_MOD_LSL, move the range check on the shift amount before the
f5555712
YZ		 1261 alignment check; change to call set_sft_amount_out_of_range_error
1262 instead of set_imm_out_of_range_error.
1263 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
1264 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
1265 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
1266 SIMD_IMM_SFT.
1267
2f81ff92
L		 12682013-01-16 H.J. Lu <hongjiu.lu@intel.com>
1269
1270 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
1271
1272 * i386-init.h: Regenerated.
1273 * i386-tbl.h: Likewise.
1274
dd42f060
NC		 12752013-01-15 Nick Clifton <nickc@redhat.com>
1276
1277 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
1278 values.
1279 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
1280
a4533ed8
NC		 12812013-01-14 Will Newton <will.newton@imgtec.com>
1282
1283 * metag-dis.c (REG_WIDTH): Increase to 64.
1284
5817ffd1
PB		 12852013-01-10 Peter Bergner <bergner@vnet.ibm.com>
1286
1287 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
1288 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
1289 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
1290 (SH6): Update.
1291 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
1292 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
1293 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
1294 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
1295
a3c62988
NC		 12962013-01-10 Will Newton <will.newton@imgtec.com>
1297
1298 * Makefile.am: Add Meta.
1299 * configure.in: Add Meta.
1300 * disassemble.c: Add Meta support.
1301 * metag-dis.c: New file.
1302 * Makefile.in: Regenerate.
1303 * configure: Regenerate.
1304
73335eae
NC		 13052013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
1306
1307 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
1308 (match_opcode): Rename to cr16_match_opcode.
1309
e407c74b
NC		 13102013-01-04 Juergen Urban <JuergenUrban@gmx.de>
1311
1312 * mips-dis.c: Add names for CP0 registers of r5900.
1313 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
1314 instructions sq and lq.
1315 Add support for MIPS r5900 CPU.
1316 Add support for 128 bit MMI (Multimedia Instructions).
1317 Add support for EE instructions (Emotion Engine).
1318 Disable unsupported floating point instructions (64 bit and
1319 undefined compare operations).
1320 Enable instructions of MIPS ISA IV which are supported by r5900.
1321 Disable 64 bit co processor instructions.
1322 Disable 64 bit multiplication and division instructions.
1323 Disable instructions for co-processor 2 and 3, because these are
1324 not supported (preparation for later VU0 support (Vector Unit)).
1325 Disable cvt.w.s because this behaves like trunc.w.s and the
1326 correct execution can't be ensured on r5900.
1327 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
1328 will confuse less developers and compilers.
1329
a32c3ff8
NC		 13302013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
1331
fb098a1e
YZ		 1332 * aarch64-opc.c (aarch64_print_operand): Change to print
1333 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
1334 in comment.
1335 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
1336 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
1337 OP_MOV_IMM_WIDE.
1338
13392013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
1340
1341 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
1342 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
a32c3ff8 1343
62658407
L		 13442013-01-02 H.J. Lu <hongjiu.lu@intel.com>
1345
1346 * i386-gen.c (process_copyright): Update copyright year to 2013.
1347
bab4becb 13482013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
5bf135a7 1349
bab4becb
NC		 1350 * cr16-dis.c (match_opcode,make_instruction): Remove static
1351 declaration.
1352 (dwordU,wordU): Moved typedefs to opcode/cr16.h
1353 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
5bf135a7 1354
bab4becb 1355For older changes see ChangeLog-2012
252b5132 1356\f
bab4becb 1357Copyright (C) 2013 Free Software Foundation, Inc.
752937aa
NC		 1358
1359Copying and distribution of this file, with or without modification,
1360are permitted in any medium without royalty provided the copyright
1361notice and this notice are preserved.
1362
252b5132 1363Local Variables:
2f6d2f85
NC		 1364mode: change-log
1365left-margin: 8
1366fill-column: 74
252b5132
RH		 1367version-control: never
1368End:
GDB Binutils - Deliverables
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