[deliverable/binutils-gdb.git] / opcodes / ChangeLog

2013-02-25  Kaushik Phatak  <Kaushik.Phatak@kpitcummins.com>

	* rl78-decode.opc: Fix encoding of DIVWU insn.
	* rl78-decode.c: Regenerate.

2013-02-19  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/15159
	* i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.

	* i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
	(cpu_flags): Add CpuSMAP.

	* i386-opc.h (CpuSMAP): New.
	(i386_cpu_flags): Add cpusmap.

	* i386-opc.tbl: Add clac and stac.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2013-02-15  Markos Chandras  <markos.chandras@imgtec.com>

	* metag-dis.c: Initialize outf->bytes_per_chunk to 4
	which also makes the disassembler output be in little
	endian like it should be.

2013-02-14  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
	fields to NULL.
	(aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.

2013-02-13  Maciej W. Rozycki  <macro@codesourcery.com>

	* mips-dis.c (is_compressed_mode_p): Only match symbols from the
	section disassembled.

2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* arm-dis.c: Update strht pattern.

2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>

	* mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
	single-float.  Disable ll, lld, sc and scd for EE.  Disable the
	trunc.w.s macro for EE.

2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
            Andrew Jenner <andrew@codesourcery.com>

	Based on patches from Altera Corporation.

	* Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
	nios2-opc.c.
	* Makefile.in: Regenerated.
	* configure.in: Add case for bfd_nios2_arch.
	* configure: Regenerated.
	* disassemble.c (ARCH_nios2): Define.
	(disassembler): Add case for bfd_arch_nios2.
	* nios2-dis.c: New file.
	* nios2-opc.c: New file.

2013-02-04  Alan Modra  <amodra@gmail.com>

	* po/POTFILES.in: Regenerate.
	* rl78-decode.c: Regenerate.
	* rx-decode.c: Regenerate.

2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
	ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
	* aarch64-asm.c (convert_xtl_to_shll): New function.
	(convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	calling convert_xtl_to_shll.
	* aarch64-dis.c (convert_shll_to_xtl): New function.
	(convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	calling convert_shll_to_xtl.
	* aarch64-gen.c: Update copyright year.
	* aarch64-asm-2.c: Re-generate.
	* aarch64-dis-2.c: Re-generate.
	* aarch64-opc-2.c: Re-generate.

2013-01-24  Nick Clifton  <nickc@redhat.com>

	* v850-dis.c: Add support for e3v5 architecture.
	* v850-opc.c: Likewise.

2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
	* aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
	* aarch64-opc.c (operand_general_constraint_met_p): For
	AARCH64_MOD_LSL, move the range check on the shift amount before the
	alignment check; change to call set_sft_amount_out_of_range_error
	instead of set_imm_out_of_range_error.
	* aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
	(aarch64_opcode_table): Remove the OP enumerator from the asimdimm
	8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
	SIMD_IMM_SFT.

2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2013-01-15  Nick Clifton  <nickc@redhat.com>

	* v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
	values.
	* v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.

2013-01-14  Will Newton <will.newton@imgtec.com>

	* metag-dis.c (REG_WIDTH): Increase to 64.

2013-01-10  Peter Bergner <bergner@vnet.ibm.com>

	* ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
	* ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
	XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
	(SH6): Update.
	<"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
	"tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
	"treclaim.", "tsr.">: Add POWER8 HTM opcodes.
	<"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.

2013-01-10  Will Newton <will.newton@imgtec.com>

	* Makefile.am: Add Meta.
	* configure.in: Add Meta.
	* disassemble.c: Add Meta support.
	* metag-dis.c: New file.
	* Makefile.in: Regenerate.
	* configure: Regenerate.

2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>

	* cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
	(match_opcode): Rename to cr16_match_opcode.

2013-01-04  Juergen Urban <JuergenUrban@gmx.de>

	* mips-dis.c: Add names for CP0 registers of r5900.
	* mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
	instructions sq and lq.
	Add support for MIPS r5900 CPU.
	Add support for 128 bit MMI (Multimedia Instructions).
	Add support for EE instructions (Emotion Engine).
	Disable unsupported floating point instructions (64 bit and
	undefined compare operations).
	Enable instructions of MIPS ISA IV which are supported by r5900.
	Disable 64 bit co processor instructions.
	Disable 64 bit multiplication and division instructions.
	Disable instructions for co-processor 2 and 3, because these are
	not supported (preparation for later VU0 support (Vector Unit)).
	Disable cvt.w.s because this behaves like trunc.w.s and the
	correct execution can't be ensured on r5900.
	Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
	will confuse less developers and compilers.

2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-opc.c (aarch64_print_operand): Change to print
	AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
	in comment.
	* aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
	from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
	OP_MOV_IMM_WIDE.

2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
	PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.

2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (process_copyright): Update copyright year to 2013.

2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>

	* cr16-dis.c (match_opcode,make_instruction): Remove static
	declaration.
	(dwordU,wordU): Moved typedefs to opcode/cr16.h
	(cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.

For older changes see ChangeLog-2012
\f
Copyright (C) 2013 Free Software Foundation, Inc.

Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.

Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
Commit	Line	Data
151fa98f NC	1	2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
	2
	3	* rl78-decode.opc: Fix encoding of DIVWU insn.
	4	* rl78-decode.c: Regenerate.
	5
5c111e37 L	6	2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
	7
	8	PR gas/15159
	9	* i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
	10
	11	* i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
	12	(cpu_flags): Add CpuSMAP.
	13
	14	* i386-opc.h (CpuSMAP): New.
	15	(i386_cpu_flags): Add cpusmap.
	16
	17	* i386-opc.tbl: Add clac and stac.
	18
	19	* i386-init.h: Regenerated.
	20	* i386-tbl.h: Likewise.
	21
9d1df426 NC	22	2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
	23
	24	* metag-dis.c: Initialize outf->bytes_per_chunk to 4
	25	which also makes the disassembler output be in little
	26	endian like it should be.
	27
a1ccaec9 YZ	28	2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
	29
	30	* aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
	31	fields to NULL.
	32	(aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
	33
ef068ef4	34	2013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
5417f71e MR	35
	36	* mips-dis.c (is_compressed_mode_p): Only match symbols from the
	37	section disassembled.
	38
6fe6ded9 RE	39	2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
	40
	41	* arm-dis.c: Update strht pattern.
	42
0aa27725 RS	43	2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
	44
	45	* mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
	46	single-float. Disable ll, lld, sc and scd for EE. Disable the
	47	trunc.w.s macro for EE.
	48
36591ba1 SL	49	2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
	50	Andrew Jenner <andrew@codesourcery.com>
	51
	52	Based on patches from Altera Corporation.
	53
	54	* Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
	55	nios2-opc.c.
	56	* Makefile.in: Regenerated.
	57	* configure.in: Add case for bfd_nios2_arch.
	58	* configure: Regenerated.
	59	* disassemble.c (ARCH_nios2): Define.
	60	(disassembler): Add case for bfd_arch_nios2.
	61	* nios2-dis.c: New file.
	62	* nios2-opc.c: New file.
	63
545093a4 AM	64	2013-02-04 Alan Modra <amodra@gmail.com>
	65
	66	* po/POTFILES.in: Regenerate.
	67	* rl78-decode.c: Regenerate.
	68	* rx-decode.c: Regenerate.
	69
e30181a5 YZ	70	2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
	71
	72	* aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
	73	ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
	74	* aarch64-asm.c (convert_xtl_to_shll): New function.
	75	(convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	76	calling convert_xtl_to_shll.
	77	* aarch64-dis.c (convert_shll_to_xtl): New function.
	78	(convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	79	calling convert_shll_to_xtl.
	80	* aarch64-gen.c: Update copyright year.
	81	* aarch64-asm-2.c: Re-generate.
	82	* aarch64-dis-2.c: Re-generate.
	83	* aarch64-opc-2.c: Re-generate.
	84
78c8d46c NC	85	2013-01-24 Nick Clifton <nickc@redhat.com>
	86
	87	* v850-dis.c: Add support for e3v5 architecture.
	88	* v850-opc.c: Likewise.
	89
f5555712 YZ	90	2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
	91
	92	* aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
	93	* aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
	94	* aarch64-opc.c (operand_general_constraint_met_p): For
78c8d46c	95	AARCH64_MOD_LSL, move the range check on the shift amount before the
f5555712 YZ	96	alignment check; change to call set_sft_amount_out_of_range_error
	97	instead of set_imm_out_of_range_error.
	98	* aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
	99	(aarch64_opcode_table): Remove the OP enumerator from the asimdimm
	100	8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
	101	SIMD_IMM_SFT.
	102
2f81ff92 L	103	2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
	104
	105	* i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
	106
	107	* i386-init.h: Regenerated.
	108	* i386-tbl.h: Likewise.
	109
dd42f060 NC	110	2013-01-15 Nick Clifton <nickc@redhat.com>
	111
	112	* v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
	113	values.
	114	* v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
	115
a4533ed8 NC	116	2013-01-14 Will Newton <will.newton@imgtec.com>
	117
	118	* metag-dis.c (REG_WIDTH): Increase to 64.
	119
5817ffd1 PB	120	2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
	121
	122	* ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
	123	* ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
	124	XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
	125	(SH6): Update.
	126	<"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
	127	"tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
	128	"treclaim.", "tsr.">: Add POWER8 HTM opcodes.
	129	<"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
	130
a3c62988 NC	131	2013-01-10 Will Newton <will.newton@imgtec.com>
	132
	133	* Makefile.am: Add Meta.
	134	* configure.in: Add Meta.
	135	* disassemble.c: Add Meta support.
	136	* metag-dis.c: New file.
	137	* Makefile.in: Regenerate.
	138	* configure: Regenerate.
	139
73335eae NC	140	2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
	141
	142	* cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
	143	(match_opcode): Rename to cr16_match_opcode.
	144
e407c74b NC	145	2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
	146
	147	* mips-dis.c: Add names for CP0 registers of r5900.
	148	* mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
	149	instructions sq and lq.
	150	Add support for MIPS r5900 CPU.
	151	Add support for 128 bit MMI (Multimedia Instructions).
	152	Add support for EE instructions (Emotion Engine).
	153	Disable unsupported floating point instructions (64 bit and
	154	undefined compare operations).
	155	Enable instructions of MIPS ISA IV which are supported by r5900.
	156	Disable 64 bit co processor instructions.
	157	Disable 64 bit multiplication and division instructions.
	158	Disable instructions for co-processor 2 and 3, because these are
	159	not supported (preparation for later VU0 support (Vector Unit)).
	160	Disable cvt.w.s because this behaves like trunc.w.s and the
	161	correct execution can't be ensured on r5900.
	162	Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
	163	will confuse less developers and compilers.
	164
a32c3ff8 NC	165	2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
a32c3ff8 NC	166
fb098a1e YZ	167	* aarch64-opc.c (aarch64_print_operand): Change to print
	168	AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
	169	in comment.
	170	* aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
	171	from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
	172	OP_MOV_IMM_WIDE.
	173
	174	2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
	175
	176	* aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
	177	PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
a32c3ff8	178
62658407 L	179	2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
	180
	181	* i386-gen.c (process_copyright): Update copyright year to 2013.
	182
bab4becb	183	2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
5bf135a7	184
bab4becb NC	185	* cr16-dis.c (match_opcode,make_instruction): Remove static
	186	declaration.
	187	(dwordU,wordU): Moved typedefs to opcode/cr16.h
	188	(cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
5bf135a7	189
bab4becb	190	For older changes see ChangeLog-2012
252b5132	191	\f
bab4becb	192	Copyright (C) 2013 Free Software Foundation, Inc.
752937aa NC	193
	194	Copying and distribution of this file, with or without modification,
	195	are permitted in any medium without royalty provided the copyright
	196	notice and this notice are preserved.
	197
252b5132	198	Local Variables:
2f6d2f85 NC	199	mode: change-log
	200	left-margin: 8
	201	fill-column: 74
252b5132 RH	202	version-control: never
252b5132 RH	203	End: