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MIPS/opcodes: Correct an `interaction' comment typo
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
5f5c6e03
MR		 12016-12-07 Maciej W. Rozycki <macro@imgtec.com>
2
3 * mips-dis.c (print_mips16_insn_arg): Fix comment typo.
4
343fa690
MR		 52016-12-07 Maciej W. Rozycki <macro@imgtec.com>
6
7 * mips16-opc.c (mips16_opcodes): Update comment naming structure
8 members.
9
6725647c
MR		 102016-12-07 Maciej W. Rozycki <macro@imgtec.com>
11
12 * mips-dis.c (print_mips_disassembler_options): Reformat output.
13
c28eeff2
SN		 142016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
15
16 * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
17 (print_insn_coprocessor): Add 'V' format for neon D or Q regs.
18
49e8a725
SN		 192016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
20
21 * arm-dis.c (coprocessor_opcodes): Add vjcvt.
22
a37a2806
NC		 232016-12-01 Nick Clifton <nickc@redhat.com>
24
25 PR binutils/20893
26 * i386-dis.c (OP_VEX): Replace call to abort with a append of bad
27 opcode designator.
28
abe7c33b
CZ		 292016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
30
31 * arc-opc.c (insert_ra_chk): New function.
32 (insert_rb_chk): Likewise.
33 (insert_rad): Update text error message.
34 (insert_rcd): Likewise.
35 (insert_rhv2): Likewise.
36 (insert_r0): Likewise.
37 (insert_r1): Likewise.
38 (insert_r2): Likewise.
39 (insert_r3): Likewise.
40 (insert_sp): Likewise.
41 (insert_gp): Likewise.
42 (insert_pcl): Likewise.
43 (insert_blink): Likewise.
44 (insert_ilink1): Likewise.
45 (insert_ilink2): Likewise.
46 (insert_ras): Likewise.
47 (insert_rbs): Likewise.
48 (insert_rcs): Likewise.
49 (insert_simm3s): Likewise.
50 (insert_rrange): Likewise.
51 (insert_fpel): Likewise.
52 (insert_blinkel): Likewise.
53 (insert_pcel): Likewise.
54 (insert_nps_3bit_dst): Likewise.
55 (insert_nps_3bit_dst_short): Likewise.
56 (insert_nps_3bit_src2_short): Likewise.
57 (insert_nps_bitop_size_2b): Likewise.
58 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
59 (RA_CHK): Define.
60 (RB): Adjust.
61 (RB_CHK): Define.
62 (RC): Adjust.
63 * arc-dis.c (print_insn_arc): Add LOAD and STORE class.
64 * arc-tbl.h (div, divu): All instructions are DIVREM class.
65 Change first insn argument to check for LP_COUNT usage.
66 (rem): Likewise.
67 (ld, ldd): All instructions are LOAD class. Change first insn
68 argument to check for LP_COUNT usage.
69 (st, std): All instructions are STORE class.
70 (mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
71 Change first insn argument to check for LP_COUNT usage.
72 (mov): All instructions are MOVE class. Change first insn
73 argument to check for LP_COUNT usage.
74
ee881e5d
CZ		 752016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
76
77 * arc-dis.c (is_compatible_p): Remove function.
78 (skip_this_opcode): Don't add any decoding class to decode list.
79 Remove warning.
80 (find_format_from_table): Go through all opcodes, and warn if we
81 use a guessed mnemonic.
82
abfcb414
AP		 832016-11-28 Ramiro Polla <ramiro@hex-rays.com>
84 Amit Pawar <amit.pawar@amd.com>
85
86 PR binutils/20637
87 * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
88 instructions.
89
96fe4562
AM		 902016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
91
92 * configure: Regenerate.
93
6884417a
JM		 942016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
95
96 * sparc-opc.c (HWS_V8): Definition moved from
97 gas/config/tc-sparc.c.
98 (HWS_V9): Likewise.
99 (HWS_VA): Likewise.
100 (HWS_VB): Likewise.
101 (HWS_VC): Likewise.
102 (HWS_VD): Likewise.
103 (HWS_VE): Likewise.
104 (HWS_VV): Likewise.
105 (HWS_VM): Likewise.
106 (HWS2_VM): Likewise.
107 (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
108 existing entries.
109
c4b943d7
CZ		 1102016-11-22 Claudiu Zissulescu <claziss@synopsys.com>
111
112 * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
113 instructions.
114
c2c4ff8d
SN		 1152016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
116
117 * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
118 (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
119 (aarch64_opcode_table): Add fcmla and fcadd.
120 (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
121 * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
122 * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
123 * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
124 * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
125 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
126 * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
127 (operand_general_constraint_met_p): Rotate and index range check.
128 (aarch64_print_operand): Handle rotate operand.
129 * aarch64-asm-2.c: Regenerate.
130 * aarch64-dis-2.c: Likewise.
131 * aarch64-opc-2.c: Likewise.
132
28617675
SN		 1332016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
134
135 * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
136 * aarch64-asm-2.c: Regenerate.
137 * aarch64-dis-2.c: Regenerate.
138 * aarch64-opc-2.c: Regenerate.
139
ccfc90a3
SN		 1402016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
141
142 * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
143 (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
144 * aarch64-asm-2.c: Regenerate.
145 * aarch64-dis-2.c: Regenerate.
146 * aarch64-opc-2.c: Regenerate.
147
3f06e550
SN		 1482016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
149
150 * aarch64-tbl.h (QL_X1NIL): New.
151 (arch64_opcode_table): Add ldraa, ldrab.
152 (AARCH64_OPERANDS): Add "ADDR_SIMM10".
153 * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
154 * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
155 * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
156 * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
157 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
158 * aarch64-opc.c (fields): Add data for FLD_S_simm10.
159 (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
160 (aarch64_print_operand): Likewise.
161 * aarch64-asm-2.c: Regenerate.
162 * aarch64-dis-2.c: Regenerate.
163 * aarch64-opc-2.c: Regenerate.
164
74f5402d
SN		 1652016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
166
167 * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
168 brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
169 * aarch64-asm-2.c: Regenerate.
170 * aarch64-dis-2.c: Regenerate.
171 * aarch64-opc-2.c: Regenerate.
172
c84364ec
SN		 1732016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
174
175 * aarch64-tbl.h (arch64_opcode_table): Add pacga.
176 (AARCH64_OPERANDS): Add Rm_SP.
177 * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
178 * aarch64-asm-2.c: Regenerate.
179 * aarch64-dis-2.c: Regenerate.
180 * aarch64-opc-2.c: Regenerate.
181
a2cfc830
SN		 1822016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
183
184 * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
185 autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
186 autdzb, xpaci, xpacd.
187 * aarch64-asm-2.c: Regenerate.
188 * aarch64-dis-2.c: Regenerate.
189 * aarch64-opc-2.c: Regenerate.
190
b0bfa7b5
SN		 1912016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
192
193 * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
194 apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
195 apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
196 (aarch64_sys_reg_supported_p): Add feature test for new registers.
197
8787d804
SN		 1982016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
199
200 * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
201 (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
202 autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
203 autibsp.
204 * aarch64-asm-2.c: Regenerate.
205 * aarch64-dis-2.c: Regenerate.
206
3d731f69
SN		 2072016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
208
209 * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
210
60227d64
L		 2112016-11-09 H.J. Lu <hongjiu.lu@intel.com>
212
213 PR binutils/20799
214 * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
215 * i386-dis.c (EdqwS): Removed.
216 (dqw_swap_mode): Likewise.
217 (intel_operand_size): Don't check dqw_swap_mode.
218 (OP_E_register): Likewise.
219 (OP_E_memory): Likewise.
220 (OP_G): Likewise.
221 (OP_EX): Likewise.
222 * i386-opc.tbl: Remove "S" from EVEX vpextrw.
223 * i386-tbl.h: Regerated.
224
7efeed17
L		 2252016-11-09 H.J. Lu <hongjiu.lu@intel.com>
226
227 * i386-opc.tbl: Merge AVX512F vmovq.
1032d6eb 228 * i386-tbl.h: Regerated.
7efeed17 229
1f334aeb
L		 2302016-11-08 H.J. Lu <hongjiu.lu@intel.com>
231
232 PR binutils/20701
233 * i386-dis.c (THREE_BYTE_0F7A): Removed.
234 (dis386_twobyte): Don't use THREE_BYTE_0F7A.
235 (three_byte_table): Remove THREE_BYTE_0F7A.
236
48c97fa1
L		 2372016-11-07 H.J. Lu <hongjiu.lu@intel.com>
238
239 PR binutils/20775
240 * i386-dis.c (FGRPd9_2): Replace 0 with 1.
241 (FGRPd9_4): Replace 1 with 2.
242 (FGRPd9_5): Replace 2 with 3.
243 (FGRPd9_6): Replace 3 with 4.
244 (FGRPd9_7): Replace 4 with 5.
245 (FGRPda_5): Replace 5 with 6.
246 (FGRPdb_4): Replace 6 with 7.
247 (FGRPde_3): Replace 7 with 8.
248 (FGRPdf_4): Replace 8 with 9.
249 (fgrps): Add an entry for Bad_Opcode.
250
b437d035
AB		 2512016-11-04 Andrew Burgess <andrew.burgess@embecosm.com>
252
253 * arc-opc.c (arc_flag_operands): Add F_DI14.
254 (arc_flag_classes): Add C_DI14.
255 * arc-nps400-tbl.h: Add new exc instructions.
256
5a736821
GM		 2572016-11-03 Graham Markall <graham.markall@embecosm.com>
258
259 * arc-dis.c (arc_insn_length): Return length 8 for instructions with
260 major opcode 0xa.
261 * arc-nps-400-tbl.h: Add dcmac instruction.
262 * arc-opc.c (arc_operands): Added operands for dcmac instruction.
263 (insert_nps_rbdouble_64): Added.
264 (extract_nps_rbdouble_64): Added.
265 (insert_nps_proto_size): Added.
266 (extract_nps_proto_size): Added.
267
bdfe53e3
AB		 2682016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
269
270 * arc-dis.c (struct arc_operand_iterator): Remove all fields
271 relating to long instruction processing, add new limm field.
272 (OPCODE): Rename to...
273 (OPCODE_32BIT_INSN): ...this.
274 (OPCODE_AC): Delete.
275 (skip_this_opcode): Handle different instruction lengths, update
276 macro name.
277 (special_flag_p): Update parameter type.
278 (find_format_from_table): Update for more instruction lengths.
279 (find_format_long_instructions): Delete.
280 (find_format): Update for more instruction lengths.
281 (arc_insn_length): Likewise.
282 (extract_operand_value): Update for more instruction lengths.
283 (operand_iterator_next): Remove code relating to long
284 instructions.
285 (arc_opcode_to_insn_type): New function.
286 (print_insn_arc):Update for more instructions lengths.
287 * arc-ext.c (extInstruction_t): Change argument type.
288 * arc-ext.h (extInstruction_t): Change argument type.
289 * arc-fxi.h: Change type unsigned to unsigned long long
290 extensively throughout.
291 * arc-nps400-tbl.h: Add long instructions taken from
292 arc_long_opcodes table in arc-opc.c.
293 * arc-opc.c: Update parameter types on insert/extract handlers.
294 (arc_long_opcodes): Delete.
295 (arc_num_long_opcodes): Delete.
296 (arc_opcode_len): Update for more instruction lengths.
297
90f61cce
GM		 2982016-11-03 Graham Markall <graham.markall@embecosm.com>
299
300 * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
301
06fe285f
GM		 3022016-11-03 Graham Markall <graham.markall@embecosm.com>
303
304 * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
305 with arc_opcode_len.
306 (find_format_long_instructions): Likewise.
307 * arc-opc.c (arc_opcode_len): New function.
308
ecf64ec6
AB		 3092016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
310
311 * arc-nps400-tbl.h: Fix some instruction masks.
312
d039fef3
L		 3132016-11-03 H.J. Lu <hongjiu.lu@intel.com>
314
315 * i386-dis.c (REG_82): Removed.
316 (X86_64_82_REG_0): Likewise.
317 (X86_64_82_REG_1): Likewise.
318 (X86_64_82_REG_2): Likewise.
319 (X86_64_82_REG_3): Likewise.
320 (X86_64_82_REG_4): Likewise.
321 (X86_64_82_REG_5): Likewise.
322 (X86_64_82_REG_6): Likewise.
323 (X86_64_82_REG_7): Likewise.
324 (X86_64_82): New.
325 (dis386): Use X86_64_82 instead of REG_82.
326 (reg_table): Remove REG_82.
327 (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
328 X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
329 X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
330 X86_64_82_REG_7.
331
8b89fe14
L		 3322016-11-03 H.J. Lu <hongjiu.lu@intel.com>
333
334 PR binutils/20754
335 * i386-dis.c (REG_82): New.
336 (X86_64_82_REG_0): Likewise.
337 (X86_64_82_REG_1): Likewise.
338 (X86_64_82_REG_2): Likewise.
339 (X86_64_82_REG_3): Likewise.
340 (X86_64_82_REG_4): Likewise.
341 (X86_64_82_REG_5): Likewise.
342 (X86_64_82_REG_6): Likewise.
343 (X86_64_82_REG_7): Likewise.
344 (dis386): Use REG_82.
345 (reg_table): Add REG_82.
346 (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
347 X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
348 X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
349
7148c369
L		 3502016-11-03 H.J. Lu <hongjiu.lu@intel.com>
351
352 * i386-dis.c (REG_82): Renamed to ...
353 (REG_83): This.
354 (dis386): Updated.
355 (reg_table): Likewise.
356
47acf0bd
IT		 3572016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
358
359 * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
360 * i386-dis-evex.h (evex_table): Updated.
361 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
362 CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
363 (cpu_flags): Add CpuAVX512_4VNNIW.
364 * i386-opc.h (enum): (AVX512_4VNNIW): New.
365 (i386_cpu_flags): Add cpuavx512_4vnniw.
366 * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
367 * i386-init.h: Regenerate.
368 * i386-tbl.h: Ditto.
369
920d2ddc
IT		 3702016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
371
372 * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
373 PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
374 * i386-dis-evex.h (evex_table): Updated.
375 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
376 CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
377 (cpu_flags): Add CpuAVX512_4FMAPS.
378 (opcode_modifiers): Add ImplicitQuadGroup modifier.
379 * i386-opc.h (AVX512_4FMAP): New.
380 (i386_cpu_flags): Add cpuavx512_4fmaps.
381 (ImplicitQuadGroup): New.
382 (i386_opcode_modifier): Add implicitquadgroup.
383 * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
384 * i386-init.h: Regenerate.
385 * i386-tbl.h: Ditto.
386
e23eba97
NC		 3872016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
388 Andrew Waterman <andrew@sifive.com>
389
390 Add support for RISC-V architecture.
391 * configure.ac: Add entry for bfd_riscv_arch.
392 * configure: Regenerate.
393 * disassemble.c (disassembler): Add support for riscv.
394 (disassembler_usage): Likewise.
395 * riscv-dis.c: New file.
396 * riscv-opc.c: New file.
397
b5cefcca
L		 3982016-10-21 H.J. Lu <hongjiu.lu@intel.com>
399
400 * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
401 (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
402 (rm_table): Update the RM_0FAE_REG_7 entry.
403 * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
404 (cpu_flags): Remove CpuPCOMMIT.
405 * i386-opc.h (CpuPCOMMIT): Removed.
406 (i386_cpu_flags): Remove cpupcommit.
407 * i386-opc.tbl: Remove pcommit.
408 * i386-init.h: Regenerated.
409 * i386-tbl.h: Likewise.
410
9889cbb1
L		 4112016-10-20 H.J. Lu <hongjiu.lu@intel.com>
412
413 PR binutis/20705
414 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
415 the highest bit in VEX.vvvv for the 3-byte VEX prefix in
416 32-bit mode. Don't check vex.register_specifier in 32-bit
417 mode.
418 (OP_VEX): Check for invalid mask registers.
419
28596323
L		 4202016-10-18 H.J. Lu <hongjiu.lu@intel.com>
421
422 PR binutis/20699
423 * i386-dis.c (OP_E_memory): Check addr32flag in stead of
424 sizeflag.
425
da8d7d66
L		 4262016-10-18 H.J. Lu <hongjiu.lu@intel.com>
427
428 PR binutis/20704
429 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
430
eaf02703
MR		 4312016-10-18 Maciej W. Rozycki <macro@imgtec.com>
432
433 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
434 local variable to `index_regno'.
435
decf5bd1
CM		 4362016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
437
438 * arc-tbl.h: Removed any "inv.+" instructions from the table.
439
e5b06ef0
CZ		 4402016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
441
442 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
443 usage on ISA basis.
444
93562a34
JW		 4452016-10-11 Jiong Wang <jiong.wang@arm.com>
446
447 PR target/20666
448 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
449
362c0c4d
JW		 4502016-10-07 Jiong Wang <jiong.wang@arm.com>
451
452 PR target/20667
453 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
454 available.
455
1047201f
AM		 4562016-10-07 Alan Modra <amodra@gmail.com>
457
458 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
459
1a0670f3
AM		 4602016-10-06 Alan Modra <amodra@gmail.com>
461
462 * aarch64-opc.c: Spell fall through comments consistently.
463 * i386-dis.c: Likewise.
464 * aarch64-dis.c: Add missing fall through comments.
465 * aarch64-opc.c: Likewise.
466 * arc-dis.c: Likewise.
467 * arm-dis.c: Likewise.
468 * i386-dis.c: Likewise.
469 * m68k-dis.c: Likewise.
470 * mep-asm.c: Likewise.
471 * ns32k-dis.c: Likewise.
472 * sh-dis.c: Likewise.
473 * tic4x-dis.c: Likewise.
474 * tic6x-dis.c: Likewise.
475 * vax-dis.c: Likewise.
476
2b804145
AM		 4772016-10-06 Alan Modra <amodra@gmail.com>
478
479 * arc-ext.c (create_map): Add missing break.
480 * msp430-decode.opc (encode_as): Likewise.
481 * msp430-decode.c: Regenerate.
482
616ec358
AM		 4832016-10-06 Alan Modra <amodra@gmail.com>
484
485 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
486 * crx-dis.c (print_insn_crx): Likewise.
487
72da393d
L		 4882016-09-30 H.J. Lu <hongjiu.lu@intel.com>
489
490 PR binutils/20657
491 * i386-dis.c (putop): Don't assign alt twice.
492
744ce302
JW		 4932016-09-29 Jiong Wang <jiong.wang@arm.com>
494
495 PR target/20553
496 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
497
a5721ba2
AM		 4982016-09-29 Alan Modra <amodra@gmail.com>
499
500 * ppc-opc.c (L): Make compulsory.
501 (LOPT): New, optional form of L.
502 (HTM_R): Define as LOPT.
503 (L0, L1): Delete.
504 (L32OPT): New, optional for 32-bit L.
505 (L2OPT): New, 2-bit L for dcbf.
506 (SVC_LEC): Update.
507 (L2): Define.
508 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
509 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
510 <dcbf>: Use L2OPT.
511 <tlbiel, tlbie>: Use LOPT.
512 <wclr, wclrall>: Use L2.
513
c5da1932
VZ		 5142016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
515
516 * Makefile.in: Regenerate.
517 * configure: Likewise.
518
2b848ebd
CZ		 5192016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
520
521 * arc-ext-tbl.h (EXTINSN2OPF): Define.
522 (EXTINSN2OP): Use EXTINSN2OPF.
523 (bspeekm, bspop, modapp): New extension instructions.
524 * arc-opc.c (F_DNZ_ND): Define.
525 (F_DNZ_D): Likewise.
526 (F_SIZEB1): Changed.
527 (C_DNZ_D): Define.
528 (C_HARD): Changed.
529 * arc-tbl.h (dbnz): New instruction.
530 (prealloc): Allow it for ARC EM.
531 (xbfu): Likewise.
532
ad43e107
RS		 5332016-09-21 Richard Sandiford <richard.sandiford@arm.com>
534
535 * aarch64-opc.c (print_immediate_offset_address): Print spaces
536 after commas in addresses.
537 (aarch64_print_operand): Likewise.
538
ab3b8fcf
RS		 5392016-09-21 Richard Sandiford <richard.sandiford@arm.com>
540
541 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
542 rather than "should be" or "expected to be" in error messages.
543
bb7eff52
RS		 5442016-09-21 Richard Sandiford <richard.sandiford@arm.com>
545
546 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
547 (print_mnemonic_name): ...here.
548 (print_comment): New function.
549 (print_aarch64_insn): Call it.
550 * aarch64-opc.c (aarch64_conds): Add SVE names.
551 (aarch64_print_operand): Print alternative condition names in
552 a comment.
553
c0890d26
RS		 5542016-09-21 Richard Sandiford <richard.sandiford@arm.com>
555
556 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
557 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
558 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
559 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
560 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
561 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
562 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
563 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
564 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
565 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
566 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
567 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
568 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
569 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
570 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
571 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
572 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
573 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
574 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
575 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
576 (OP_SVE_XWU, OP_SVE_XXU): New macros.
577 (aarch64_feature_sve): New variable.
578 (SVE): New macro.
579 (_SVE_INSN): Likewise.
580 (aarch64_opcode_table): Add SVE instructions.
581 * aarch64-opc.h (extract_fields): Declare.
582 * aarch64-opc-2.c: Regenerate.
583 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
584 * aarch64-asm-2.c: Regenerate.
585 * aarch64-dis.c (extract_fields): Make global.
586 (do_misc_decoding): Handle the new SVE aarch64_ops.
587 * aarch64-dis-2.c: Regenerate.
588
116b6019
RS		 5892016-09-21 Richard Sandiford <richard.sandiford@arm.com>
590
591 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
592 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
593 aarch64_field_kinds.
594 * aarch64-opc.c (fields): Add corresponding entries.
595 * aarch64-asm.c (aarch64_get_variant): New function.
596 (aarch64_encode_variant_using_iclass): Likewise.
597 (aarch64_opcode_encode): Call it.
598 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
599 (aarch64_opcode_decode): Call it.
600
047cd301
RS		 6012016-09-21 Richard Sandiford <richard.sandiford@arm.com>
602
603 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
604 and FP register operands.
605 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
606 (FLD_SVE_Vn): New aarch64_field_kinds.
607 * aarch64-opc.c (fields): Add corresponding entries.
608 (aarch64_print_operand): Handle the new SVE core and FP register
609 operands.
610 * aarch64-opc-2.c: Regenerate.
611 * aarch64-asm-2.c: Likewise.
612 * aarch64-dis-2.c: Likewise.
613
165d4950
RS		 6142016-09-21 Richard Sandiford <richard.sandiford@arm.com>
615
616 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
617 immediate operands.
618 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
619 * aarch64-opc.c (fields): Add corresponding entry.
620 (operand_general_constraint_met_p): Handle the new SVE FP immediate
621 operands.
622 (aarch64_print_operand): Likewise.
623 * aarch64-opc-2.c: Regenerate.
624 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
625 (ins_sve_float_zero_one): New inserters.
626 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
627 (aarch64_ins_sve_float_half_two): Likewise.
628 (aarch64_ins_sve_float_zero_one): Likewise.
629 * aarch64-asm-2.c: Regenerate.
630 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
631 (ext_sve_float_zero_one): New extractors.
632 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
633 (aarch64_ext_sve_float_half_two): Likewise.
634 (aarch64_ext_sve_float_zero_one): Likewise.
635 * aarch64-dis-2.c: Regenerate.
636
e950b345
RS		 6372016-09-21 Richard Sandiford <richard.sandiford@arm.com>
638
639 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
640 integer immediate operands.
641 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
642 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
643 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
644 * aarch64-opc.c (fields): Add corresponding entries.
645 (operand_general_constraint_met_p): Handle the new SVE integer
646 immediate operands.
647 (aarch64_print_operand): Likewise.
648 (aarch64_sve_dupm_mov_immediate_p): New function.
649 * aarch64-opc-2.c: Regenerate.
650 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
651 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
652 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
653 (aarch64_ins_limm): ...here.
654 (aarch64_ins_inv_limm): New function.
655 (aarch64_ins_sve_aimm): Likewise.
656 (aarch64_ins_sve_asimm): Likewise.
657 (aarch64_ins_sve_limm_mov): Likewise.
658 (aarch64_ins_sve_shlimm): Likewise.
659 (aarch64_ins_sve_shrimm): Likewise.
660 * aarch64-asm-2.c: Regenerate.
661 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
662 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
663 * aarch64-dis.c (decode_limm): New function, split out from...
664 (aarch64_ext_limm): ...here.
665 (aarch64_ext_inv_limm): New function.
666 (decode_sve_aimm): Likewise.
667 (aarch64_ext_sve_aimm): Likewise.
668 (aarch64_ext_sve_asimm): Likewise.
669 (aarch64_ext_sve_limm_mov): Likewise.
670 (aarch64_top_bit): Likewise.
671 (aarch64_ext_sve_shlimm): Likewise.
672 (aarch64_ext_sve_shrimm): Likewise.
673 * aarch64-dis-2.c: Regenerate.
674
98907a70
RS		 6752016-09-21 Richard Sandiford <richard.sandiford@arm.com>
676
677 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
678 operands.
679 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
680 the AARCH64_MOD_MUL_VL entry.
681 (value_aligned_p): Cope with non-power-of-two alignments.
682 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
683 (print_immediate_offset_address): Likewise.
684 (aarch64_print_operand): Likewise.
685 * aarch64-opc-2.c: Regenerate.
686 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
687 (ins_sve_addr_ri_s9xvl): New inserters.
688 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
689 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
690 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
691 * aarch64-asm-2.c: Regenerate.
692 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
693 (ext_sve_addr_ri_s9xvl): New extractors.
694 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
695 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
696 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
697 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
698 * aarch64-dis-2.c: Regenerate.
699
4df068de
RS		 7002016-09-21 Richard Sandiford <richard.sandiford@arm.com>
701
702 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
703 address operands.
704 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
705 (FLD_SVE_xs_22): New aarch64_field_kinds.
706 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
707 (get_operand_specific_data): New function.
708 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
709 FLD_SVE_xs_14 and FLD_SVE_xs_22.
710 (operand_general_constraint_met_p): Handle the new SVE address
711 operands.
712 (sve_reg): New array.
713 (get_addr_sve_reg_name): New function.
714 (aarch64_print_operand): Handle the new SVE address operands.
715 * aarch64-opc-2.c: Regenerate.
716 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
717 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
718 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
719 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
720 (aarch64_ins_sve_addr_rr_lsl): Likewise.
721 (aarch64_ins_sve_addr_rz_xtw): Likewise.
722 (aarch64_ins_sve_addr_zi_u5): Likewise.
723 (aarch64_ins_sve_addr_zz): Likewise.
724 (aarch64_ins_sve_addr_zz_lsl): Likewise.
725 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
726 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
727 * aarch64-asm-2.c: Regenerate.
728 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
729 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
730 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
731 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
732 (aarch64_ext_sve_addr_ri_u6): Likewise.
733 (aarch64_ext_sve_addr_rr_lsl): Likewise.
734 (aarch64_ext_sve_addr_rz_xtw): Likewise.
735 (aarch64_ext_sve_addr_zi_u5): Likewise.
736 (aarch64_ext_sve_addr_zz): Likewise.
737 (aarch64_ext_sve_addr_zz_lsl): Likewise.
738 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
739 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
740 * aarch64-dis-2.c: Regenerate.
741
2442d846
RS		 7422016-09-21 Richard Sandiford <richard.sandiford@arm.com>
743
744 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
745 AARCH64_OPND_SVE_PATTERN_SCALED.
746 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
747 * aarch64-opc.c (fields): Add a corresponding entry.
748 (set_multiplier_out_of_range_error): New function.
749 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
750 (operand_general_constraint_met_p): Handle
751 AARCH64_OPND_SVE_PATTERN_SCALED.
752 (print_register_offset_address): Use PRIi64 to print the
753 shift amount.
754 (aarch64_print_operand): Likewise. Handle
755 AARCH64_OPND_SVE_PATTERN_SCALED.
756 * aarch64-opc-2.c: Regenerate.
757 * aarch64-asm.h (ins_sve_scale): New inserter.
758 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
759 * aarch64-asm-2.c: Regenerate.
760 * aarch64-dis.h (ext_sve_scale): New inserter.
761 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
762 * aarch64-dis-2.c: Regenerate.
763
245d2e3f
RS		 7642016-09-21 Richard Sandiford <richard.sandiford@arm.com>
765
766 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
767 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
768 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
769 (FLD_SVE_prfop): Likewise.
770 * aarch64-opc.c: Include libiberty.h.
771 (aarch64_sve_pattern_array): New variable.
772 (aarch64_sve_prfop_array): Likewise.
773 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
774 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
775 AARCH64_OPND_SVE_PRFOP.
776 * aarch64-asm-2.c: Regenerate.
777 * aarch64-dis-2.c: Likewise.
778 * aarch64-opc-2.c: Likewise.
779
d50c751e
RS		 7802016-09-21 Richard Sandiford <richard.sandiford@arm.com>
781
782 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
783 AARCH64_OPND_QLF_P_[ZM].
784 (aarch64_print_operand): Print /z and /m where appropriate.
785
f11ad6bc
RS		 7862016-09-21 Richard Sandiford <richard.sandiford@arm.com>
787
788 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
789 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
790 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
791 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
792 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
793 * aarch64-opc.c (fields): Add corresponding entries here.
794 (operand_general_constraint_met_p): Check that SVE register lists
795 have the correct length. Check the ranges of SVE index registers.
796 Check for cases where p8-p15 are used in 3-bit predicate fields.
797 (aarch64_print_operand): Handle the new SVE operands.
798 * aarch64-opc-2.c: Regenerate.
799 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
800 * aarch64-asm.c (aarch64_ins_sve_index): New function.
801 (aarch64_ins_sve_reglist): Likewise.
802 * aarch64-asm-2.c: Regenerate.
803 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
804 * aarch64-dis.c (aarch64_ext_sve_index): New function.
805 (aarch64_ext_sve_reglist): Likewise.
806 * aarch64-dis-2.c: Regenerate.
807
0c608d6b
RS		 8082016-09-21 Richard Sandiford <richard.sandiford@arm.com>
809
810 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
811 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
812 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
813 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
814 tied operands.
815
01dbfe4c
RS		 8162016-09-21 Richard Sandiford <richard.sandiford@arm.com>
817
818 * aarch64-opc.c (get_offset_int_reg_name): New function.
819 (print_immediate_offset_address): Likewise.
820 (print_register_offset_address): Take the base and offset
821 registers as parameters.
822 (aarch64_print_operand): Update caller accordingly. Use
823 print_immediate_offset_address.
824
72e9f319
RS		 8252016-09-21 Richard Sandiford <richard.sandiford@arm.com>
826
827 * aarch64-opc.c (BANK): New macro.
828 (R32, R64): Take a register number as argument
829 (int_reg): Use BANK.
830
8a7f0c1b
RS		 8312016-09-21 Richard Sandiford <richard.sandiford@arm.com>
832
833 * aarch64-opc.c (print_register_list): Add a prefix parameter.
834 (aarch64_print_operand): Update accordingly.
835
aa2aa4c6
RS		 8362016-09-21 Richard Sandiford <richard.sandiford@arm.com>
837
838 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
839 for FPIMM.
840 * aarch64-asm.h (ins_fpimm): New inserter.
841 * aarch64-asm.c (aarch64_ins_fpimm): New function.
842 * aarch64-asm-2.c: Regenerate.
843 * aarch64-dis.h (ext_fpimm): New extractor.
844 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
845 (aarch64_ext_fpimm): New function.
846 * aarch64-dis-2.c: Regenerate.
847
b5464a68
RS		 8482016-09-21 Richard Sandiford <richard.sandiford@arm.com>
849
850 * aarch64-asm.c: Include libiberty.h.
851 (insert_fields): New function.
852 (aarch64_ins_imm): Use it.
853 * aarch64-dis.c (extract_fields): New function.
854 (aarch64_ext_imm): Use it.
855
42408347
RS		 8562016-09-21 Richard Sandiford <richard.sandiford@arm.com>
857
858 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
859 with an esize parameter.
860 (operand_general_constraint_met_p): Update accordingly.
861 Fix misindented code.
862 * aarch64-asm.c (aarch64_ins_limm): Update call to
863 aarch64_logical_immediate_p.
864
4989adac
RS		 8652016-09-21 Richard Sandiford <richard.sandiford@arm.com>
866
867 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
868
bd11d5d8
RS		 8692016-09-21 Richard Sandiford <richard.sandiford@arm.com>
870
871 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
872
f807f43d
CZ		 8732016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
874
875 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
876
fd486b63
PB		 8772016-09-14 Peter Bergner <bergner@vnet.ibm.com>
878
879 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
880 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
881 xor3>: Delete mnemonics.
882 <cp_abort>: Rename mnemonic from ...
883 <cpabort>: ...to this.
884 <setb>: Change to a X form instruction.
885 <sync>: Change to 1 operand form.
886 <copy>: Delete mnemonic.
887 <copy_first>: Rename mnemonic from ...
888 <copy>: ...to this.
889 <paste, paste.>: Delete mnemonics.
890 <paste_last>: Rename mnemonic from ...
891 <paste.>: ...to this.
892
dce08442
AK		 8932016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
894
895 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
896
952c3f51
AK		 8972016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
898
899 * s390-mkopc.c (main): Support alternate arch strings.
900
8b71537b
PS		 9012016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
902
903 * s390-opc.txt: Fix kmctr instruction type.
904
5b64d091
L		 9052016-09-07 H.J. Lu <hongjiu.lu@intel.com>
906
907 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
908 * i386-init.h: Regenerated.
909
7763838e
CM		 9102016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
911
912 * opcodes/arc-dis.c (print_insn_arc): Changed.
913
1b8b6532
JM		 9142016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
915
916 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
917 camellia_fl.
918
1a336194
TP		 9192016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
920
921 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
922 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
923 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
924
6b40c462
L		 9252016-08-24 H.J. Lu <hongjiu.lu@intel.com>
926
927 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
928 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
929 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
930 PREFIX_MOD_3_0FAE_REG_4.
931 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
932 PREFIX_MOD_3_0FAE_REG_4.
933 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
934 (cpu_flags): Add CpuPTWRITE.
935 * i386-opc.h (CpuPTWRITE): New.
936 (i386_cpu_flags): Add cpuptwrite.
937 * i386-opc.tbl: Add ptwrite instruction.
938 * i386-init.h: Regenerated.
939 * i386-tbl.h: Likewise.
940
ab548d2d
AK		 9412016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
942
943 * arc-dis.h: Wrap around in extern "C".
944
344bde0a
RS		 9452016-08-23 Richard Sandiford <richard.sandiford@arm.com>
946
947 * aarch64-tbl.h (V8_2_INSN): New macro.
948 (aarch64_opcode_table): Use it.
949
5ce912d8
RS		 9502016-08-23 Richard Sandiford <richard.sandiford@arm.com>
951
952 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
953 CORE_INSN, __FP_INSN and SIMD_INSN.
954
9d30b0bd
RS		 9552016-08-23 Richard Sandiford <richard.sandiford@arm.com>
956
957 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
958 (aarch64_opcode_table): Update uses accordingly.
959
dfdaec14
AJ		 9602016-07-25 Andrew Jenner <andrew@codesourcery.com>
961 Kwok Cheung Yeung <kcy@codesourcery.com>
962
963 opcodes/
964 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
965 'e_cmplwi' to 'e_cmpli' instead.
966 (OPVUPRT, OPVUPRT_MASK): Define.
967 (powerpc_opcodes): Add E200Z4 insns.
968 (vle_opcodes): Add context save/restore insns.
969
7bd374a4
MR		 9702016-07-27 Maciej W. Rozycki <macro@imgtec.com>
971
972 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
973 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
974 "j".
975
db18dbab
GM		 9762016-07-27 Graham Markall <graham.markall@embecosm.com>
977
978 * arc-nps400-tbl.h: Change block comments to GNU format.
979 * arc-dis.c: Add new globals addrtypenames,
980 addrtypenames_max, and addtypeunknown.
981 (get_addrtype): New function.
982 (print_insn_arc): Print colons and address types when
983 required.
984 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
985 define insert and extract functions for all address types.
986 (arc_operands): Add operands for colon and all address
987 types.
988 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
989 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
990 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
991 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
992 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
993 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
994
fecd57f9
L		 9952016-07-21 H.J. Lu <hongjiu.lu@intel.com>
996
997 * configure: Regenerated.
998
37fd5ef3
CZ		 9992016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
1000
1001 * arc-dis.c (skipclass): New structure.
1002 (decodelist): New variable.
1003 (is_compatible_p): New function.
1004 (new_element): Likewise.
1005 (skip_class_p): Likewise.
1006 (find_format_from_table): Use skip_class_p function.
1007 (find_format): Decode first the extension instructions.
1008 (print_insn_arc): Select either ARCEM or ARCHS based on elf
1009 e_flags.
1010 (parse_option): New function.
1011 (parse_disassembler_options): Likewise.
1012 (print_arc_disassembler_options): Likewise.
1013 (print_insn_arc): Use parse_disassembler_options function. Proper
1014 select ARCv2 cpu variant.
1015 * disassemble.c (disassembler_usage): Add ARC disassembler
1016 options.
1017
92281a5b
MR		 10182016-07-13 Maciej W. Rozycki <macro@imgtec.com>
1019
1020 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
1021 annotation from the "nal" entry and reorder it beyond "bltzal".
1022
6e7ced37
JM		 10232016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
1024
1025 * sparc-opc.c (ldtxa): New macro.
1026 (sparc_opcodes): Use the macro defined above to add entries for
1027 the LDTXA instructions.
1028 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
1029 instruction.
1030
2f831b9a 10312016-07-07 James Bowman <james.bowman@ftdichip.com>
1032
1033 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
1034 and "jmpc".
1035
c07315e0
JB		 10362016-07-01 Jan Beulich <jbeulich@suse.com>
1037
1038 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
1039 (movzb): Adjust to cover all permitted suffixes.
1040 (movzw): New.
1041 * i386-tbl.h: Re-generate.
1042
9243100a
JB		 10432016-07-01 Jan Beulich <jbeulich@suse.com>
1044
1045 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
1046 (lgdt): Remove Tbyte from non-64-bit variant.
1047 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
1048 xsaves64, xsavec64): Remove Disp16.
1049 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
1050 Remove Disp32S from non-64-bit variants. Remove Disp16 from
1051 64-bit variants.
1052 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
1053 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
1054 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
1055 64-bit variants.
1056 * i386-tbl.h: Re-generate.
1057
8325cc63
JB		 10582016-07-01 Jan Beulich <jbeulich@suse.com>
1059
1060 * i386-opc.tbl (xlat): Remove RepPrefixOk.
1061 * i386-tbl.h: Re-generate.
1062
838441e4
YQ		 10632016-06-30 Yao Qi <yao.qi@linaro.org>
1064
1065 * arm-dis.c (print_insn): Fix typo in comment.
1066
dab26bf4
RS		 10672016-06-28 Richard Sandiford <richard.sandiford@arm.com>
1068
1069 * aarch64-opc.c (operand_general_constraint_met_p): Check the
1070 range of ldst_elemlist operands.
1071 (print_register_list): Use PRIi64 to print the index.
1072 (aarch64_print_operand): Likewise.
1073
5703197e
TS		 10742016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1075
1076 * mcore-opc.h: Remove sentinal.
1077 * mcore-dis.c (print_insn_mcore): Adjust.
1078
ce440d63
GM		 10792016-06-23 Graham Markall <graham.markall@embecosm.com>
1080
1081 * arc-opc.c: Correct description of availability of NPS400
1082 features.
1083
6fd3a02d
PB		 10842016-06-22 Peter Bergner <bergner@vnet.ibm.com>
1085
1086 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
1087 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
1088 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
1089 xor3>: New mnemonics.
1090 <setb>: Change to a VX form instruction.
1091 (insert_sh6): Add support for rldixor.
1092 (extract_sh6): Likewise.
1093
6b477896
TS		 10942016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1095
1096 * arc-ext.h: Wrap in extern C.
1097
bdd582db
GM		 10982016-06-21 Graham Markall <graham.markall@embecosm.com>
1099
1100 * arc-dis.c (arc_insn_length): Add comment on instruction length.
1101 Use same method for determining instruction length on ARC700 and
1102 NPS-400.
1103 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
1104 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
1105 with the NPS400 subclass.
1106 * arc-opc.c: Likewise.
1107
96074adc
JM		 11082016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1109
1110 * sparc-opc.c (rdasr): New macro.
1111 (wrasr): Likewise.
1112 (rdpr): Likewise.
1113 (wrpr): Likewise.
1114 (rdhpr): Likewise.
1115 (wrhpr): Likewise.
1116 (sparc_opcodes): Use the macros above to fix and expand the
1117 definition of read/write instructions from/to
1118 asr/privileged/hyperprivileged instructions.
1119 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1120 %hva_mask_nz. Prefer softint_set and softint_clear over
1121 set_softint and clear_softint.
1122 (print_insn_sparc): Support %ver in Rd.
1123
7a10c22f
JM		 11242016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1125
1126 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1127 architecture according to the hardware capabilities they require.
1128
4f26fb3a
JM		 11292016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1130
1131 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1132 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1133 bfd_mach_sparc_v9{c,d,e,v,m}.
1134 * sparc-opc.c (MASK_V9C): Define.
1135 (MASK_V9D): Likewise.
1136 (MASK_V9E): Likewise.
1137 (MASK_V9V): Likewise.
1138 (MASK_V9M): Likewise.
1139 (v6): Add MASK_V9{C,D,E,V,M}.
1140 (v6notlet): Likewise.
1141 (v7): Likewise.
1142 (v8): Likewise.
1143 (v9): Likewise.
1144 (v9andleon): Likewise.
1145 (v9a): Likewise.
1146 (v9b): Likewise.
1147 (v9c): Define.
1148 (v9d): Likewise.
1149 (v9e): Likewise.
1150 (v9v): Likewise.
1151 (v9m): Likewise.
1152 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1153
3ee6e4fb
NC		 11542016-06-15 Nick Clifton <nickc@redhat.com>
1155
1156 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1157 constants to match expected behaviour.
1158 (nds32_parse_opcode): Likewise. Also for whitespace.
1159
02f3be19
AB		 11602016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
1161
1162 * arc-opc.c (extract_rhv1): Extract value from insn.
1163
6f9f37ed 11642016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM		 1165
1166 * arc-nps400-tbl.h: Add ldbit instruction.
1167 * arc-opc.c: Add flag classes required for ldbit.
1168
6f9f37ed 11692016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM		 1170
1171 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1172 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1173 support the above instructions.
1174
6f9f37ed 11752016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM		 1176
1177 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1178 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1179 csma, cbba, zncv, and hofs.
1180 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1181 support the above instructions.
1182
11832016-06-06 Graham Markall <graham.markall@embecosm.com>
1184
1185 * arc-nps400-tbl.h: Add andab and orab instructions.
1186
11872016-06-06 Graham Markall <graham.markall@embecosm.com>
1188
1189 * arc-nps400-tbl.h: Add addl-like instructions.
1190
11912016-06-06 Graham Markall <graham.markall@embecosm.com>
1192
1193 * arc-nps400-tbl.h: Add mxb and imxb instructions.
1194
11952016-06-06 Graham Markall <graham.markall@embecosm.com>
1196
1197 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1198 instructions.
1199
b2cc3f6f
AK		 12002016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1201
1202 * s390-dis.c (option_use_insn_len_bits_p): New file scope
1203 variable.
1204 (init_disasm): Handle new command line option "insnlength".
1205 (print_s390_disassembler_options): Mention new option in help
1206 output.
1207 (print_insn_s390): Use the encoded insn length when dumping
1208 unknown instructions.
1209
1857fe72
DC		 12102016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
1211
1212 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1213 to the address and set as symbol address for LDS/ STS immediate operands.
1214
14b57c7c
AM		 12152016-06-07 Alan Modra <amodra@gmail.com>
1216
1217 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
1218 cpu for "vle" to e500.
1219 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1220 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1221 (PPCNONE): Delete, substitute throughout.
1222 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
1223 except for major opcode 4 and 31.
1224 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1225
4d1464f2
MW		 12262016-06-07 Matthew Wahab <matthew.wahab@arm.com>
1227
1228 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1229 ARM_EXT_RAS in relevant entries.
1230
026122a6
PB		 12312016-06-03 Peter Bergner <bergner@vnet.ibm.com>
1232
1233 PR binutils/20196
1234 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1235 opcodes for E6500.
1236
07f5af7d
L		 12372016-06-03 H.J. Lu <hongjiu.lu@intel.com>
1238
1239 PR binutis/18386
1240 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1241 (indir_v_mode): New.
1242 Add comments for '&'.
1243 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1244 (putop): Handle '&'.
1245 (intel_operand_size): Handle indir_v_mode.
1246 (OP_E_register): Likewise.
1247 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
1248 64-bit indirect call/jmp for AMD64.
1249 * i386-tbl.h: Regenerated
1250
4eb6f892
AB		 12512016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
1252
1253 * arc-dis.c (struct arc_operand_iterator): New structure.
1254 (find_format_from_table): All the old content from find_format,
1255 with some minor adjustments, and parameter renaming.
1256 (find_format_long_instructions): New function.
1257 (find_format): Rewritten.
1258 (arc_insn_length): Add LSB parameter.
1259 (extract_operand_value): New function.
1260 (operand_iterator_next): New function.
1261 (print_insn_arc): Use new functions to find opcode, and iterator
1262 over operands.
1263 * arc-opc.c (insert_nps_3bit_dst_short): New function.
1264 (extract_nps_3bit_dst_short): New function.
1265 (insert_nps_3bit_src2_short): New function.
1266 (extract_nps_3bit_src2_short): New function.
1267 (insert_nps_bitop1_size): New function.
1268 (extract_nps_bitop1_size): New function.
1269 (insert_nps_bitop2_size): New function.
1270 (extract_nps_bitop2_size): New function.
1271 (insert_nps_bitop_mod4_msb): New function.
1272 (extract_nps_bitop_mod4_msb): New function.
1273 (insert_nps_bitop_mod4_lsb): New function.
1274 (extract_nps_bitop_mod4_lsb): New function.
1275 (insert_nps_bitop_dst_pos3_pos4): New function.
1276 (extract_nps_bitop_dst_pos3_pos4): New function.
1277 (insert_nps_bitop_ins_ext): New function.
1278 (extract_nps_bitop_ins_ext): New function.
1279 (arc_operands): Add new operands.
1280 (arc_long_opcodes): New global array.
1281 (arc_num_long_opcodes): New global.
1282 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1283
1fe0971e
TS		 12842016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1285
1286 * nds32-asm.h: Add extern "C".
1287 * sh-opc.h: Likewise.
1288
315f180f
GM		 12892016-06-01 Graham Markall <graham.markall@embecosm.com>
1290
1291 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1292 0,b,limm to the rflt instruction.
1293
a2b5fccc
TS		 12942016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1295
1296 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1297 constant.
1298
0cbd0046
L		 12992016-05-29 H.J. Lu <hongjiu.lu@intel.com>
1300
1301 PR gas/20145
1302 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1303 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1304 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1305 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1306 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1307 * i386-init.h: Regenerated.
1308
1848e567
L		 13092016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1310
1311 PR gas/20145
1312 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
1313 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
1314 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1315 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1316 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
1317 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1318 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1319 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
1320 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1321 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1322 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
1323 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
1324 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
1325 CpuRegMask for AVX512.
1326 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1327 and CpuRegMask.
1328 (set_bitfield_from_cpu_flag_init): New function.
1329 (set_bitfield): Remove const on f. Call
1330 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1331 * i386-opc.h (CpuRegMMX): New.
1332 (CpuRegXMM): Likewise.
1333 (CpuRegYMM): Likewise.
1334 (CpuRegZMM): Likewise.
1335 (CpuRegMask): Likewise.
1336 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1337 and cpuregmask.
1338 * i386-init.h: Regenerated.
1339 * i386-tbl.h: Likewise.
1340
e92bae62
L		 13412016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1342
1343 PR gas/20154
1344 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1345 (opcode_modifiers): Add AMD64 and Intel64.
1346 (main): Properly verify CpuMax.
1347 * i386-opc.h (CpuAMD64): Removed.
1348 (CpuIntel64): Likewise.
1349 (CpuMax): Set to CpuNo64.
1350 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1351 (AMD64): New.
1352 (Intel64): Likewise.
1353 (i386_opcode_modifier): Add amd64 and intel64.
1354 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1355 on call and jmp.
1356 * i386-init.h: Regenerated.
1357 * i386-tbl.h: Likewise.
1358
e89c5eaa
L		 13592016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1360
1361 PR gas/20154
1362 * i386-gen.c (main): Fail if CpuMax is incorrect.
1363 * i386-opc.h (CpuMax): Set to CpuIntel64.
1364 * i386-tbl.h: Regenerated.
1365
77d66e7b
NC		 13662016-05-27 Nick Clifton <nickc@redhat.com>
1367
1368 PR target/20150
1369 * msp430-dis.c (msp430dis_read_two_bytes): New function.
1370 (msp430dis_opcode_unsigned): New function.
1371 (msp430dis_opcode_signed): New function.
1372 (msp430_singleoperand): Use the new opcode reading functions.
1373 Only disassenmble bytes if they were successfully read.
1374 (msp430_doubleoperand): Likewise.
1375 (msp430_branchinstr): Likewise.
1376 (msp430x_callx_instr): Likewise.
1377 (print_insn_msp430): Check that it is safe to read bytes before
1378 attempting disassembly. Use the new opcode reading functions.
1379
19dfcc89
PB		 13802016-05-26 Peter Bergner <bergner@vnet.ibm.com>
1381
1382 * ppc-opc.c (CY): New define. Document it.
1383 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1384
f3ad7637
L		 13852016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1386
1387 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1388 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1389 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
1390 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1391 CPU_ANY_AVX_FLAGS.
1392 * i386-init.h: Regenerated.
1393
f1360d58
L		 13942016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1395
1396 PR gas/20141
1397 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1398 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1399 * i386-init.h: Regenerated.
1400
293f5f65
L		 14012016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1402
1403 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1404 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
1405 * i386-init.h: Regenerated.
1406
d9eca1df
CZ		 14072016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1408
1409 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1410 information.
1411 (print_insn_arc): Set insn_type information.
1412 * arc-opc.c (C_CC): Add F_CLASS_COND.
1413 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1414 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1415 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1416 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1417 (brne, brne_s, jeq_s, jne_s): Likewise.
1418
87789e08
CZ		 14192016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1420
1421 * arc-tbl.h (neg): New instruction variant.
1422
c810e0b8
CZ		 14232016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
1424
1425 * arc-dis.c (find_format, find_format, get_auxreg)
1426 (print_insn_arc): Changed.
1427 * arc-ext.h (INSERT_XOP): Likewise.
1428
3d207518
TS		 14292016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1430
1431 * tic54x-dis.c (sprint_mmr): Adjust.
1432 * tic54x-opc.c: Likewise.
1433
514e58b7
AM		 14342016-05-19 Alan Modra <amodra@gmail.com>
1435
1436 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1437
e43de63c
AM		 14382016-05-19 Alan Modra <amodra@gmail.com>
1439
1440 * ppc-opc.c: Formatting.
1441 (NSISIGNOPT): Define.
1442 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1443
1401d2fe
MR		 14442016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1445
1446 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1447 replacing references to `micromips_ase' throughout.
1448 (_print_insn_mips): Don't use file-level microMIPS annotation to
1449 determine the disassembly mode with the symbol table.
1450
1178da44
PB		 14512016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1452
1453 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1454
8f4f9071
MF		 14552016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1456
1457 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1458 mips64r6.
1459 * mips-opc.c (D34): New macro.
1460 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1461
8bc52696
AF		 14622016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1463
1464 * i386-dis.c (prefix_table): Add RDPID instruction.
1465 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1466 (cpu_flags): Add RDPID bitfield.
1467 * i386-opc.h (enum): Add RDPID element.
1468 (i386_cpu_flags): Add RDPID field.
1469 * i386-opc.tbl: Add RDPID instruction.
1470 * i386-init.h: Regenerate.
1471 * i386-tbl.h: Regenerate.
1472
39d911fc
TP		 14732016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1474
1475 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1476 branch type of a symbol.
1477 (print_insn): Likewise.
1478
16a1fa25
TP		 14792016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1480
1481 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1482 Mainline Security Extensions instructions.
1483 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1484 Extensions instructions.
1485 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1486 instructions.
1487 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1488 special registers.
1489
d751b79e
JM		 14902016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1491
1492 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1493
945e0f82
CZ		 14942016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1495
1496 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1497 (arcExtMap_genOpcode): Likewise.
1498 * arc-opc.c (arg_32bit_rc): Define new variable.
1499 (arg_32bit_u6): Likewise.
1500 (arg_32bit_limm): Likewise.
1501
20f55f38
SN		 15022016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1503
1504 * aarch64-gen.c (VERIFIER): Define.
1505 * aarch64-opc.c (VERIFIER): Define.
1506 (verify_ldpsw): Use static linkage.
1507 * aarch64-opc.h (verify_ldpsw): Remove.
1508 * aarch64-tbl.h: Use VERIFIER for verifiers.
1509
4bd13cde
NC		 15102016-04-28 Nick Clifton <nickc@redhat.com>
1511
1512 PR target/19722
1513 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1514 * aarch64-opc.c (verify_ldpsw): New function.
1515 * aarch64-opc.h (verify_ldpsw): New prototype.
1516 * aarch64-tbl.h: Add initialiser for verifier field.
1517 (LDPSW): Set verifier to verify_ldpsw.
1518
c0f92bf9
L		 15192016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1520
1521 PR binutils/19983
1522 PR binutils/19984
1523 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1524 smaller than address size.
1525
e6c7cdec
TS		 15262016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1527
1528 * alpha-dis.c: Regenerate.
1529 * crx-dis.c: Likewise.
1530 * disassemble.c: Likewise.
1531 * epiphany-opc.c: Likewise.
1532 * fr30-opc.c: Likewise.
1533 * frv-opc.c: Likewise.
1534 * ip2k-opc.c: Likewise.
1535 * iq2000-opc.c: Likewise.
1536 * lm32-opc.c: Likewise.
1537 * lm32-opinst.c: Likewise.
1538 * m32c-opc.c: Likewise.
1539 * m32r-opc.c: Likewise.
1540 * m32r-opinst.c: Likewise.
1541 * mep-opc.c: Likewise.
1542 * mt-opc.c: Likewise.
1543 * or1k-opc.c: Likewise.
1544 * or1k-opinst.c: Likewise.
1545 * tic80-opc.c: Likewise.
1546 * xc16x-opc.c: Likewise.
1547 * xstormy16-opc.c: Likewise.
1548
537aefaf
AB		 15492016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1550
1551 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1552 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1553 calcsd, and calcxd instructions.
1554 * arc-opc.c (insert_nps_bitop_size): Delete.
1555 (extract_nps_bitop_size): Delete.
1556 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1557 (extract_nps_qcmp_m3): Define.
1558 (extract_nps_qcmp_m2): Define.
1559 (extract_nps_qcmp_m1): Define.
1560 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1561 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1562 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1563 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1564 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1565 NPS_QCMP_M3.
1566
c8f785f2
AB		 15672016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1568
1569 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1570
6fd8e7c2
L		 15712016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1572
1573 * Makefile.in: Regenerated with automake 1.11.6.
1574 * aclocal.m4: Likewise.
1575
4b0c052e
AB		 15762016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1577
1578 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1579 instructions.
1580 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1581 (extract_nps_cmem_uimm16): New function.
1582 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1583
cb040366
AB		 15842016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1585
1586 * arc-dis.c (arc_insn_length): New function.
1587 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1588 (find_format): Change insnLen parameter to unsigned.
1589
accc0180
NC		 15902016-04-13 Nick Clifton <nickc@redhat.com>
1591
1592 PR target/19937
1593 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1594 the LD.B and LD.BU instructions.
1595
f36e33da
CZ		 15962016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1597
1598 * arc-dis.c (find_format): Check for extension flags.
1599 (print_flags): New function.
1600 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1601 .extAuxRegister.
1602 * arc-ext.c (arcExtMap_coreRegName): Use
1603 LAST_EXTENSION_CORE_REGISTER.
1604 (arcExtMap_coreReadWrite): Likewise.
1605 (dump_ARC_extmap): Update printing.
1606 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1607 (arc_aux_regs): Add cpu field.
1608 * arc-regs.h: Add cpu field, lower case name aux registers.
1609
1c2e355e
CZ		 16102016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1611
1612 * arc-tbl.h: Add rtsc, sleep with no arguments.
1613
b99747ae
CZ		 16142016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1615
1616 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1617 Initialize.
1618 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1619 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1620 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1621 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1622 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1623 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1624 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1625 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1626 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1627 (arc_opcode arc_opcodes): Null terminate the array.
1628 (arc_num_opcodes): Remove.
1629 * arc-ext.h (INSERT_XOP): Define.
1630 (extInstruction_t): Likewise.
1631 (arcExtMap_instName): Delete.
1632 (arcExtMap_insn): New function.
1633 (arcExtMap_genOpcode): Likewise.
1634 * arc-ext.c (ExtInstruction): Remove.
1635 (create_map): Zero initialize instruction fields.
1636 (arcExtMap_instName): Remove.
1637 (arcExtMap_insn): New function.
1638 (dump_ARC_extmap): More info while debuging.
1639 (arcExtMap_genOpcode): New function.
1640 * arc-dis.c (find_format): New function.
1641 (print_insn_arc): Use find_format.
1642 (arc_get_disassembler): Enable dump_ARC_extmap only when
1643 debugging.
1644
92708cec
MR		 16452016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1646
1647 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1648 instruction bits out.
1649
a42a4f84
AB		 16502016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1651
1652 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1653 * arc-opc.c (arc_flag_operands): Add new flags.
1654 (arc_flag_classes): Add new classes.
1655
1328504b
AB		 16562016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1657
1658 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1659
820f03ff
AB		 16602016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1661
1662 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1663 encode1, rflt, crc16, and crc32 instructions.
1664 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1665 (arc_flag_classes): Add C_NPS_R.
1666 (insert_nps_bitop_size_2b): New function.
1667 (extract_nps_bitop_size_2b): Likewise.
1668 (insert_nps_bitop_uimm8): Likewise.
1669 (extract_nps_bitop_uimm8): Likewise.
1670 (arc_operands): Add new operand entries.
1671
8ddf6b2a
CZ		 16722016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1673
b99747ae
CZ		 1674 * arc-regs.h: Add a new subclass field. Add double assist
1675 accumulator register values.
1676 * arc-tbl.h: Use DPA subclass to mark the double assist
1677 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1678 * arc-opc.c (RSP): Define instead of SP.
1679 (arc_aux_regs): Add the subclass field.
8ddf6b2a 1680
589a7d88
JW		 16812016-04-05 Jiong Wang <jiong.wang@arm.com>
1682
1683 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1684
0a191de9 16852016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 1686
1687 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1688 NPS_R_SRC1.
1689
0a106562
AB		 16902016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1691
1692 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1693 issues. No functional changes.
1694
bd05ac5f
CZ		 16952016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1696
b99747ae
CZ		 1697 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1698 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1699 (RTT): Remove duplicate.
1700 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1701 (PCT_CONFIG*): Remove.
1702 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 1703
9885948f
CZ		 17042016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1705
b99747ae 1706 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 1707
f2dd8838
CZ		 17082016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1709
b99747ae
CZ		 1710 * arc-tbl.h (invld07): Remove.
1711 * arc-ext-tbl.h: New file.
1712 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1713 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 1714
0d2f91fe
JK		 17152016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1716
1717 Fix -Wstack-usage warnings.
1718 * aarch64-dis.c (print_operands): Substitute size.
1719 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1720
a6b71f42
JM		 17212016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1722
1723 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1724 to get a proper diagnostic when an invalid ASR register is used.
1725
9780e045
NC		 17262016-03-22 Nick Clifton <nickc@redhat.com>
1727
1728 * configure: Regenerate.
1729
e23e8ebe
AB		 17302016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1731
1732 * arc-nps400-tbl.h: New file.
1733 * arc-opc.c: Add top level comment.
1734 (insert_nps_3bit_dst): New function.
1735 (extract_nps_3bit_dst): New function.
1736 (insert_nps_3bit_src2): New function.
1737 (extract_nps_3bit_src2): New function.
1738 (insert_nps_bitop_size): New function.
1739 (extract_nps_bitop_size): New function.
1740 (arc_flag_operands): Add nps400 entries.
1741 (arc_flag_classes): Add nps400 entries.
1742 (arc_operands): Add nps400 entries.
1743 (arc_opcodes): Add nps400 include.
1744
1ae8ab47
AB		 17452016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1746
1747 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1748 the new class enum values.
1749
8699fc3e
AB		 17502016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1751
1752 * arc-dis.c (print_insn_arc): Handle nps400.
1753
24740d83
AB		 17542016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1755
1756 * arc-opc.c (BASE): Delete.
1757
8678914f
NC		 17582016-03-18 Nick Clifton <nickc@redhat.com>
1759
1760 PR target/19721
1761 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1762 of MOV insn that aliases an ORR insn.
1763
cc933301
JW		 17642016-03-16 Jiong Wang <jiong.wang@arm.com>
1765
1766 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1767
f86f5863
TS		 17682016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1769
1770 * mcore-opc.h: Add const qualifiers.
1771 * microblaze-opc.h (struct op_code_struct): Likewise.
1772 * sh-opc.h: Likewise.
1773 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1774 (tic4x_print_op): Likewise.
1775
62de1c63
AM		 17762016-03-02 Alan Modra <amodra@gmail.com>
1777
d11698cd 1778 * or1k-desc.h: Regenerate.
62de1c63 1779 * fr30-ibld.c: Regenerate.
c697cf0b 1780 * rl78-decode.c: Regenerate.
62de1c63 1781
020efce5
NC		 17822016-03-01 Nick Clifton <nickc@redhat.com>
1783
1784 PR target/19747
1785 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1786
b0c11777
RL		 17872016-02-24 Renlin Li <renlin.li@arm.com>
1788
1789 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1790 (print_insn_coprocessor): Support fp16 instructions.
1791
3e309328
RL		 17922016-02-24 Renlin Li <renlin.li@arm.com>
1793
1794 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1795 vminnm, vrint(mpna).
1796
8afc7bea
RL		 17972016-02-24 Renlin Li <renlin.li@arm.com>
1798
1799 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1800 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1801
4fd7268a
L		 18022016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1803
1804 * i386-dis.c (print_insn): Parenthesize expression to prevent
1805 truncated addresses.
1806 (OP_J): Likewise.
1807
4670103e
CZ		 18082016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1809 Janek van Oirschot <jvanoirs@synopsys.com>
1810
b99747ae
CZ		 1811 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1812 variable.
4670103e 1813
c1d9289f
NC		 18142016-02-04 Nick Clifton <nickc@redhat.com>
1815
1816 PR target/19561
1817 * msp430-dis.c (print_insn_msp430): Add a special case for
1818 decoding an RRC instruction with the ZC bit set in the extension
1819 word.
1820
a143b004
AB		 18212016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1822
1823 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1824 * epiphany-ibld.c: Regenerate.
1825 * fr30-ibld.c: Regenerate.
1826 * frv-ibld.c: Regenerate.
1827 * ip2k-ibld.c: Regenerate.
1828 * iq2000-ibld.c: Regenerate.
1829 * lm32-ibld.c: Regenerate.
1830 * m32c-ibld.c: Regenerate.
1831 * m32r-ibld.c: Regenerate.
1832 * mep-ibld.c: Regenerate.
1833 * mt-ibld.c: Regenerate.
1834 * or1k-ibld.c: Regenerate.
1835 * xc16x-ibld.c: Regenerate.
1836 * xstormy16-ibld.c: Regenerate.
1837
b89807c6
AB		 18382016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1839
1840 * epiphany-dis.c: Regenerated from latest cpu files.
1841
d8c823c8
MM		 18422016-02-01 Michael McConville <mmcco@mykolab.com>
1843
1844 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1845 test bit.
1846
5bc5ae88
RL		 18472016-01-25 Renlin Li <renlin.li@arm.com>
1848
1849 * arm-dis.c (mapping_symbol_for_insn): New function.
1850 (find_ifthen_state): Call mapping_symbol_for_insn().
1851
0bff6e2d
MW		 18522016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1853
1854 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1855 of MSR UAO immediate operand.
1856
100b4f2e
MR		 18572016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1858
1859 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1860 instruction support.
1861
5c14705f
AM		 18622016-01-17 Alan Modra <amodra@gmail.com>
1863
1864 * configure: Regenerate.
1865
4d82fe66
NC		 18662016-01-14 Nick Clifton <nickc@redhat.com>
1867
1868 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1869 instructions that can support stack pointer operations.
1870 * rl78-decode.c: Regenerate.
1871 * rl78-dis.c: Fix display of stack pointer in MOVW based
1872 instructions.
1873
651657fa
MW		 18742016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1875
1876 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1877 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1878 erxtatus_el1 and erxaddr_el1.
1879
105bde57
MW		 18802016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1881
1882 * arm-dis.c (arm_opcodes): Add "esb".
1883 (thumb_opcodes): Likewise.
1884
afa8d405
PB		 18852016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1886
1887 * ppc-opc.c <xscmpnedp>: Delete.
1888 <xvcmpnedp>: Likewise.
1889 <xvcmpnedp.>: Likewise.
1890 <xvcmpnesp>: Likewise.
1891 <xvcmpnesp.>: Likewise.
1892
83c3256e
AS		 18932016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1894
1895 PR gas/13050
1896 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1897 addition to ISA_A.
1898
6f2750fe
AM		 18992016-01-01 Alan Modra <amodra@gmail.com>
1900
1901 Update year range in copyright notice of all files.
1902
3499769a
AM		 1903For older changes see ChangeLog-2015
1904\f
1905Copyright (C) 2016 Free Software Foundation, Inc.
1906
1907Copying and distribution of this file, with or without modification,
1908are permitted in any medium without royalty provided the copyright
1909notice and this notice are preserved.
1910
1911Local Variables:
1912mode: change-log
1913left-margin: 8
1914fill-column: 74
1915version-control: never
1916End:
GDB Binutils - Deliverables
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