projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Add Disp32S to 64bit call.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
00f51a41
L		 12011-08-01 H.J. Lu <hongjiu.lu@intel.com>
2
3 PR gas/13046
4 * i386-opc.tbl: Add Disp32S to 64bit call.
5 * i386-tbl.h: Regenerated.
6
df58fc94
RS		 72011-07-24 Chao-ying Fu <fu@mips.com>
8 Maciej W. Rozycki <macro@codesourcery.com>
9
10 * micromips-opc.c: New file.
11 * mips-dis.c (micromips_to_32_reg_b_map): New array.
12 (micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise.
13 (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise.
14 (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise.
15 (micromips_to_32_reg_q_map): Likewise.
16 (micromips_imm_b_map, micromips_imm_c_map): Likewise.
17 (micromips_ase): New variable.
18 (is_micromips): New function.
19 (set_default_mips_dis_options): Handle microMIPS ASE.
20 (print_insn_micromips): New function.
21 (is_compressed_mode_p): Likewise.
22 (_print_insn_mips): Handle microMIPS instructions.
23 * Makefile.am (CFILES): Add micromips-opc.c.
24 * configure.in (bfd_mips_arch): Add micromips-opc.lo.
25 * Makefile.in: Regenerate.
26 * configure: Regenerate.
27
28 * mips-dis.c (micromips_to_32_reg_h_map): New variable.
29 (micromips_to_32_reg_i_map): Likewise.
30 (micromips_to_32_reg_m_map): Likewise.
31 (micromips_to_32_reg_n_map): New macro.
32
bcd530a7
RS		 332011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
34
35 * mips-opc.c (NODS): New macro.
36 (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
37 (DSP_VOLA): Likewise.
38 (mips_builtin_opcodes): Add NODS annotation to "deret" and
39 "eret". Replace INSN_SYNC with NODS throughout. Use NODS in
40 place of TRAP for "wait", "waiti" and "yield".
41 * mips16-opc.c (NODS): New macro.
42 (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
43 (mips16_opcodes): Use NODS in place of TRAP for "jalrc", "jrc",
44 "restore" and "save".
45
7a9068fe
L		 462011-07-22 H.J. Lu <hongjiu.lu@intel.com>
47
48 * configure.in: Handle bfd_k1om_arch.
49 * configure: Regenerated.
50
51 * disassemble.c (disassembler): Handle bfd_k1om_arch.
52
53 * i386-dis.c (print_insn): Handle bfd_mach_k1om and
54 bfd_mach_k1om_intel_syntax.
55
56 * i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to
57 ~(CpuL1OM|CpuK1OM). Add CPU_K1OM_FLAGS.
58 (cpu_flags): Add CpuK1OM.
59
60 * i386-opc.h (CpuK1OM): New.
61 (i386_cpu_flags): Add cpuk1om.
62
63 * i386-init.h: Regenerated.
64 * i386-tbl.h: Likewise.
65
1b93226d
NC		 662011-07-12 Nick Clifton <nickc@redhat.com>
67
68 * arm-dis.c (print_insn_arm): Revert previous, undocumented,
69 accidental change.
70
5d73b1f1
NC		 712011-07-01 Nick Clifton <nickc@redhat.com>
72
73 PR binutils/12329
74 * avr-dis.c (avr_operand): Fix disassembly of ELPM, LPM and SPM
75 insns using post-increment addressing.
76
182ae480
L		 772011-06-30 H.J. Lu <hongjiu.lu@intel.com>
78
79 * i386-dis.c (vex_len_table): Update rorxS.
80
4cb0953d
L		 812011-06-30 H.J. Lu <hongjiu.lu@intel.com>
82
83 AVX Programming Reference (June, 2011)
84 * i386-dis.c (vex_len_table): Correct rorxS.
85
86 * i386-opc.tbl: Correct rorx.
87 * i386-tbl.h: Regenerated.
88
906efcbc
L		 892011-06-29 H.J. Lu <hongjiu.lu@intel.com>
90
91 * tilegx-opc.c (find_opcode): Replace "index" with "i".
92 * tilepro-opc.c (find_opcode): Likewise.
93
ceb94aa5
RS		 942011-06-29 Richard Sandiford <rdsandiford@googlemail.com>
95
96 * mips16-opc.c (jalrc, jrc): Move earlier in file.
97
f7002f42
L		 982011-06-21 H.J. Lu <hongjiu.lu@intel.com>
99
100 * i386-dis.c (prefix_table): Re-indent PREFIX_VEX_0F388C and
101 PREFIX_VEX_0F388E.
102
56300268
AS		 1032011-06-17 Andreas Schwab <schwab@redhat.com>
104
105 * Makefile.am (MAINTAINERCLEANFILES): Move s390-opc.tab ...
106 (MOSTLYCLEANFILES): ... here.
107 * Makefile.in: Regenerate.
108
bcf2cf9f
AM		 1092011-06-14 Alan Modra <amodra@gmail.com>
110
111 * Makefile.in: Regenerate.
112
aa137e4d
NC		 1132011-06-13 Walter Lee <walt@tilera.com>
114
115 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c,
116 tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c.
117 * Makefile.in: Regenerate.
118 * configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch.
119 * configure: Regenerate.
120 * disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro.
121 * po/POTFILES.in: Regenerate.
122 * tilegx-dis.c: New file.
123 * tilegx-opc.c: New file.
124 * tilepro-dis.c: New file.
125 * tilepro-opc.c: New file.
126
6c30d220
L		 1272011-06-10 H.J. Lu <hongjiu.lu@intel.com>
128
129 AVX Programming Reference (June, 2011)
130 * i386-dis.c (XMGatherQ): New.
131 * i386-dis.c (EXxmm_mb): New.
132 (EXxmm_mb): Likewise.
133 (EXxmm_mw): Likewise.
134 (EXxmm_md): Likewise.
135 (EXxmm_mq): Likewise.
136 (EXxmmdw): Likewise.
137 (EXxmmqd): Likewise.
138 (VexGatherQ): Likewise.
139 (MVexVSIBDWpX): Likewise.
140 (MVexVSIBQWpX): Likewise.
141 (xmm_mb_mode): Likewise.
142 (xmm_mw_mode): Likewise.
143 (xmm_md_mode): Likewise.
144 (xmm_mq_mode): Likewise.
145 (xmmdw_mode): Likewise.
146 (xmmqd_mode): Likewise.
147 (ymmxmm_mode): Likewise.
148 (vex_vsib_d_w_dq_mode): Likewise.
149 (vex_vsib_q_w_dq_mode): Likewise.
150 (MOD_VEX_0F385A_PREFIX_2): Likewise.
151 (MOD_VEX_0F388C_PREFIX_2): Likewise.
152 (MOD_VEX_0F388E_PREFIX_2): Likewise.
153 (PREFIX_0F3882): Likewise.
154 (PREFIX_VEX_0F3816): Likewise.
155 (PREFIX_VEX_0F3836): Likewise.
156 (PREFIX_VEX_0F3845): Likewise.
157 (PREFIX_VEX_0F3846): Likewise.
158 (PREFIX_VEX_0F3847): Likewise.
159 (PREFIX_VEX_0F3858): Likewise.
160 (PREFIX_VEX_0F3859): Likewise.
161 (PREFIX_VEX_0F385A): Likewise.
162 (PREFIX_VEX_0F3878): Likewise.
163 (PREFIX_VEX_0F3879): Likewise.
164 (PREFIX_VEX_0F388C): Likewise.
165 (PREFIX_VEX_0F388E): Likewise.
166 (PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise.
167 (PREFIX_VEX_0F38F5): Likewise.
168 (PREFIX_VEX_0F38F6): Likewise.
169 (PREFIX_VEX_0F3A00): Likewise.
170 (PREFIX_VEX_0F3A01): Likewise.
171 (PREFIX_VEX_0F3A02): Likewise.
172 (PREFIX_VEX_0F3A38): Likewise.
173 (PREFIX_VEX_0F3A39): Likewise.
174 (PREFIX_VEX_0F3A46): Likewise.
175 (PREFIX_VEX_0F3AF0): Likewise.
176 (VEX_LEN_0F3816_P_2): Likewise.
177 (VEX_LEN_0F3819_P_2): Likewise.
178 (VEX_LEN_0F3836_P_2): Likewise.
179 (VEX_LEN_0F385A_P_2_M_0): Likewise.
180 (VEX_LEN_0F38F5_P_0): Likewise.
181 (VEX_LEN_0F38F5_P_1): Likewise.
182 (VEX_LEN_0F38F5_P_3): Likewise.
183 (VEX_LEN_0F38F6_P_3): Likewise.
184 (VEX_LEN_0F38F7_P_1): Likewise.
185 (VEX_LEN_0F38F7_P_2): Likewise.
186 (VEX_LEN_0F38F7_P_3): Likewise.
187 (VEX_LEN_0F3A00_P_2): Likewise.
188 (VEX_LEN_0F3A01_P_2): Likewise.
189 (VEX_LEN_0F3A38_P_2): Likewise.
190 (VEX_LEN_0F3A39_P_2): Likewise.
191 (VEX_LEN_0F3A46_P_2): Likewise.
192 (VEX_LEN_0F3AF0_P_3): Likewise.
193 (VEX_W_0F3816_P_2): Likewise.
194 (VEX_W_0F3818_P_2): Likewise.
195 (VEX_W_0F3819_P_2): Likewise.
196 (VEX_W_0F3836_P_2): Likewise.
197 (VEX_W_0F3846_P_2): Likewise.
198 (VEX_W_0F3858_P_2): Likewise.
199 (VEX_W_0F3859_P_2): Likewise.
200 (VEX_W_0F385A_P_2_M_0): Likewise.
201 (VEX_W_0F3878_P_2): Likewise.
202 (VEX_W_0F3879_P_2): Likewise.
203 (VEX_W_0F3A00_P_2): Likewise.
204 (VEX_W_0F3A01_P_2): Likewise.
205 (VEX_W_0F3A02_P_2): Likewise.
206 (VEX_W_0F3A38_P_2): Likewise.
207 (VEX_W_0F3A39_P_2): Likewise.
208 (VEX_W_0F3A46_P_2): Likewise.
209 (MOD_VEX_0F3818_PREFIX_2): Removed.
210 (MOD_VEX_0F3819_PREFIX_2): Likewise.
211 (VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise.
212 (VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise.
213 (VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise.
214 (VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise.
215 (VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise.
216 (VEX_LEN_0F3A0E_P_2): Likewise.
217 (VEX_LEN_0F3A0F_P_2): Likewise.
218 (VEX_LEN_0F3A42_P_2): Likewise.
219 (VEX_LEN_0F3A4C_P_2): Likewise.
220 (VEX_W_0F3818_P_2_M_0): Likewise.
221 (VEX_W_0F3819_P_2_M_0): Likewise.
222 (prefix_table): Updated.
223 (three_byte_table): Likewise.
224 (vex_table): Likewise.
225 (vex_len_table): Likewise.
226 (vex_w_table): Likewise.
227 (mod_table): Likewise.
228 (putop): Handle "LW".
229 (intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode,
230 xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode,
231 vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode.
232 (OP_EX): Likewise.
233 (OP_E_memory): Handle vex_vsib_d_w_dq_mode and
234 vex_vsib_q_w_dq_mode.
235 (OP_XMM): Handle vex_vsib_q_w_dq_mode.
236 (OP_VEX): Likewise.
237
238 * i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS
239 and CPU_ANY_AVX_FLAGS. Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS,
240 CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS.
241 (cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID.
242 (opcode_modifiers): Add VecSIB.
243
244 * i386-opc.h (CpuAVX2): New.
245 (CpuBMI2): Likewise.
246 (CpuLZCNT): Likewise.
247 (CpuINVPCID): Likewise.
248 (VecSIB128): Likewise.
249 (VecSIB256): Likewise.
250 (VecSIB): Likewise.
251 (i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid.
252 (i386_opcode_modifier): Add vecsib.
253
254 * i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions.
255 * i386-init.h: Regenerated.
256 * i386-tbl.h: Likewise.
257
d535accd
QN		 2582011-06-03 Quentin Neill <quentin.neill@amd.com>
259
260 * i386-gen.c (cpu_flag_init): Add CpuF16C to CPU_BDVER2_FLAGS.
261 * i386-init.h: Regenerated.
262
f8b960bc
NC		 2632011-06-03 Nick Clifton <nickc@redhat.com>
264
265 PR binutils/12752
266 * arm-dis.c (print_insn_coprocessor): Use bfd_vma type for
267 computing address offsets.
268 (print_arm_address): Likewise.
269 (print_insn_arm): Likewise.
270 (print_insn_thumb16): Likewise.
271 (print_insn_thumb32): Likewise.
272
26d97720
NS		 2732011-06-02 Jie Zhang <jie@codesourcery.com>
274 Nathan Sidwell <nathan@codesourcery.com>
275 Maciej Rozycki <macro@codesourcery.com>
276
277 * arm-dis.c (print_insn_coprocessor): Explicitly print #-0
278 as address offset.
279 (print_arm_address): Likewise. Elide positive #0 appropriately.
280 (print_insn_arm): Likewise.
281
f8b960bc
NC		 2822011-06-02 Nick Clifton <nickc@redhat.com>
283
284 PR gas/12752
285 * arm-dis.c (print_insn_thumb32): Do not sign extend addresses
286 passed to print_address_func.
287
cc643b88
NC		 2882011-06-02 Nick Clifton <nickc@redhat.com>
289
290 * arm-dis.c: Fix spelling mistakes.
291 * op/opcodes.pot: Regenerate.
292
c8fa16ed
AK		 2932011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
294
295 * s390-opc.c: Replace S390_OPERAND_REG_EVEN with
296 S390_OPERAND_REG_PAIR. Fix INSTR_RRF_0UFEF instruction type.
297 * s390-opc.txt: Fix cxr instruction type.
298
5e4b319c
AK		 2992011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
300
301 * s390-opc.c: Add new instruction types marking register pair
302 operands.
303 * s390-opc.txt: Match instructions having register pair operands
304 to the new instruction types.
305
fda544a2
NC		 3062011-05-19 Nick Clifton <nickc@redhat.com>
307
308 * v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2
309 operands.
310
4cab4add
QN		 3112011-05-10 Quentin Neill <quentin.neill@amd.com>
312
313 * i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS.
314 * i386-init.h: Regenerated.
315
b4e7b885
NC		 3162011-04-27 Nick Clifton <nickc@redhat.com>
317
318 * po/da.po: Updated Danish translation.
319
2f7f7710
AM		 3202011-04-26 Anton Blanchard <anton@samba.org>
321
322 * ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7.
323
9887672f
DD		 3242011-04-21 DJ Delorie <dj@redhat.com>
325
326 * rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs.
327 * rx-decode.c: Regenerate.
328
3251b375
L		 3292011-04-20 H.J. Lu <hongjiu.lu@intel.com>
330
331 * i386-init.h: Regenerated.
332
b13a3ca6
QN		 3332011-04-19 Quentin Neill <quentin.neill@amd.com>
334
335 * i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits
336 from bdver1 flags.
337
7d063384
NC		 3382011-04-13 Nick Clifton <nickc@redhat.com>
339
340 * v850-dis.c (disassemble): Always print a closing square brace if
341 an opening square brace was printed.
342
32a94698
NC		 3432011-04-12 Nick Clifton <nickc@redhat.com>
344
345 PR binutils/12534
346 * arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn
347 patterns.
348 (print_insn_thumb32): Handle %L.
349
d2cd1205
JB		 3502011-04-11 Julian Brown <julian@codesourcery.com>
351
352 * arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
353 (print_insn_thumb32): Add APSR bitmask support.
354
1fbaefec
PB		 3552011-04-07 Paul Carroll<pcarroll@codesourcery.com>
356
357 * arm-dis.c (print_insn): init vars moved into private_data structure.
358
67171547
MF		 3592011-03-24 Mike Frysinger <vapier@gentoo.org>
360
361 * bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic.
362
8cc66334
EW		 3632011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
364
365 * avr-dis.c (avr_operand): Add opcode_str parameter. Check for
366 post-increment to support LPM Z+ instruction. Add support for 'E'
367 constraint for DES instruction.
368 (print_insn_avr): Adjust calls to avr_operand. Rename variable.
369
34e77a92
RS		 3702011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
371
372 * arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
373
35fc36a8
RS		 3742011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
375
376 * arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
377 Use branch types instead.
378 (print_insn): Likewise.
379
0067d8fc
MR		 3802011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
381
382 * mips-opc.c (mips_builtin_opcodes): Correct register use
383 annotation of "alnv.ps".
384
3eebd5eb
MR		 3852011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
386
387 * mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
388
500cccad
MF		 3892011-02-22 Mike Frysinger <vapier@gentoo.org>
390
391 * bfin-dis.c (OUTS): Remove p NULL check and txt NUL check.
392
f5caf9f4
MF		 3932011-02-22 Mike Frysinger <vapier@gentoo.org>
394
395 * bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS.
396
e5bc4265
MF		 3972011-02-19 Mike Frysinger <vapier@gentoo.org>
398
399 * bfin-dis.c (saved_state): Mark static. Change a[01]x to ax[] and
400 a[01]w to aw[]. Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1,
401 av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts,
402 exception, end_of_registers, msize, memory, bfd_mach.
403 (CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG,
404 LB0REG, LC1REG, LT1REG, LB1REG): Delete
405 (AXREG, AWREG, LCREG, LTREG, LBREG): Define.
406 (get_allreg): Change to new defines. Fallback to abort().
407
602427c4
MF		 4082011-02-14 Mike Frysinger <vapier@gentoo.org>
409
410 * bfin-dis.c: Add whitespace/parenthesis where needed.
411
298c1ec2
MF		 4122011-02-14 Mike Frysinger <vapier@gentoo.org>
413
414 * bfin-dis.c (decode_LoopSetup_0): Return when reg is greater
415 than 7.
416
822ce8ee
RW		 4172011-02-13 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
418
419 * configure: Regenerate.
420
13c02f06
MF		 4212011-02-13 Mike Frysinger <vapier@gentoo.org>
422
423 * bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg.
424
4db66394
MF		 4252011-02-13 Mike Frysinger <vapier@gentoo.org>
426
427 * bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1. Output
428 dregs only when P is set, and dregs_lo otherwise.
429
36f44611
MF		 4302011-02-13 Mike Frysinger <vapier@gentoo.org>
431
432 * bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code.
433
9805c0a5
MF		 4342011-02-12 Mike Frysinger <vapier@gentoo.org>
435
436 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT.
437
43a6aa65
MF		 4382011-02-12 Mike Frysinger <vapier@gentoo.org>
439
440 * bfin-dis.c (machine_registers): Delete REG_GP.
441 (reg_names): Delete "GP".
442 (decode_allregs): Change REG_GP to REG_LASTREG.
443
26bb3ddd
MF		 4442011-02-12 Mike Frysinger <vapier@gentoo.org>
445
89c0d58c
MR		 446 * bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2,
447 M_IH, M_IU): Delete.
26bb3ddd 448
69b8ea4a
MF		 4492011-02-11 Mike Frysinger <vapier@gentoo.org>
450
451 * bfin-dis.c (reg_names): Add const.
452 (decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte,
453 decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs,
454 decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits,
455 decode_counters, decode_allregs): Likewise.
456
42d5f9c6
MS		 4572011-02-09 Michael Snyder <msnyder@vmware.com>
458
56300268 459 * i386-dis.c (OP_J): Parenthesize expression to prevent
42d5f9c6
MS		 460 truncated addresses.
461 (print_insn): Fix indentation off-by-one.
462
4be0c941
NC		 4632011-02-01 Nick Clifton <nickc@redhat.com>
464
465 * po/da.po: Updated Danish translation.
466
6b069ee7
AM		 4672011-01-21 Dave Murphy <davem@devkitpro.org>
468
469 * ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.
470
e3949f17
L		 4712011-01-18 H.J. Lu <hongjiu.lu@intel.com>
472
473 * i386-dis.c (sIbT): New.
474 (b_T_mode): Likewise.
475 (dis386): Replace sIb with sIbT on "pushT".
476 (x86_64_table): Replace sIb with Ib on "aam" and "aad".
477 (OP_sI): Handle b_T_mode. Properly sign-extend byte.
478
752573b2
JK		 4792011-01-18 Jan Kratochvil <jan.kratochvil@redhat.com>
480
481 * i386-init.h: Regenerated.
482 * i386-tbl.h: Regenerated
483
2a2a0f38
QN		 4842011-01-17 Quentin Neill <quentin.neill@amd.com>
485
486 * i386-dis.c (REG_XOP_TBM_01): New.
487 (REG_XOP_TBM_02): New.
488 (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
489 (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
490 entries, and add bextr instruction.
491
492 * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
493 (cpu_flags): Add CpuTBM.
494
495 * i386-opc.h (CpuTBM) New.
496 (i386_cpu_flags): Add bit cputbm.
497
498 * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
499 blcs, blsfill, blsic, t1mskc, and tzmsk.
500
90d6ff62
DD		 5012011-01-12 DJ Delorie <dj@redhat.com>
502
503 * rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.
504
c95354ed
MX		 5052011-01-11 Mingjie Xing <mingjie.xing@gmail.com>
506
507 * mips-dis.c (print_insn_args): Adjust the value to print the real
508 offset for "+c" argument.
509
f7465604
NC		 5102011-01-10 Nick Clifton <nickc@redhat.com>
511
512 * po/da.po: Updated Danish translation.
513
639e30d2
NS		 5142011-01-05 Nathan Sidwell <nathan@codesourcery.com>
515
516 * arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
517
f12dc422
L		 5182011-01-04 H.J. Lu <hongjiu.lu@intel.com>
519
520 * i386-dis.c (REG_VEX_38F3): New.
521 (PREFIX_0FBC): Likewise.
522 (PREFIX_VEX_38F2): Likewise.
523 (PREFIX_VEX_38F3_REG_1): Likewise.
524 (PREFIX_VEX_38F3_REG_2): Likewise.
525 (PREFIX_VEX_38F3_REG_3): Likewise.
526 (PREFIX_VEX_38F7): Likewise.
527 (VEX_LEN_38F2_P_0): Likewise.
528 (VEX_LEN_38F3_R_1_P_0): Likewise.
529 (VEX_LEN_38F3_R_2_P_0): Likewise.
530 (VEX_LEN_38F3_R_3_P_0): Likewise.
531 (VEX_LEN_38F7_P_0): Likewise.
532 (dis386_twobyte): Use PREFIX_0FBC.
533 (reg_table): Add REG_VEX_38F3.
534 (prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2,
535 PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2,
536 PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7.
537 (vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and
538 PREFIX_VEX_38F7.
539 (vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0,
540 VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and
541 VEX_LEN_38F7_P_0.
542
543 * i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS.
544 (cpu_flags): Add CpuBMI.
545
546 * i386-opc.h (CpuBMI): New.
547 (i386_cpu_flags): Add cpubmi.
548
549 * i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt.
550 * i386-init.h: Regenerated.
551 * i386-tbl.h: Likewise.
552
cb21baef
L		 5532011-01-04 H.J. Lu <hongjiu.lu@intel.com>
554
555 * i386-dis.c (VexGdq): New.
556 (OP_VEX): Handle dq_mode.
557
0db46eb4
L		 5582011-01-01 H.J. Lu <hongjiu.lu@intel.com>
559
560 * i386-gen.c (process_copyright): Update copyright to 2011.
561
9e9e0820 562For older changes see ChangeLog-2010
252b5132
RH		 563\f
564Local Variables:
2f6d2f85
NC		 565mode: change-log
566left-margin: 8
567fill-column: 74
252b5132
RH		 568version-control: never
569End:
GDB Binutils - Deliverables
This page took 0.754804 seconds and 4 git commands to generate.