[deliverable/binutils-gdb.git] / opcodes / ChangeLog

2013-02-19  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/15159
	* i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.

	* i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
	(cpu_flags): Add CpuSMAP.

	* i386-opc.h (CpuSMAP): New.
	(i386_cpu_flags): Add cpusmap.

	* i386-opc.tbl: Add clac and stac.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2013-02-15  Markos Chandras  <markos.chandras@imgtec.com>

	* metag-dis.c: Initialize outf->bytes_per_chunk to 4
	which also makes the disassembler output be in little
	endian like it should be.

2013-02-14  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
	fields to NULL.
	(aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.

2013-02-13  Maciej W. Rozycki  <macro@codesourcery.com>

	* mips-dis.c (is_compressed_mode_p): Only match symbols from the
	section disassembled.

2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* arm-dis.c: Update strht pattern.

2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>

	* mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
	single-float.  Disable ll, lld, sc and scd for EE.  Disable the
	trunc.w.s macro for EE.

2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
            Andrew Jenner <andrew@codesourcery.com>

	Based on patches from Altera Corporation.

	* Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
	nios2-opc.c.
	* Makefile.in: Regenerated.
	* configure.in: Add case for bfd_nios2_arch.
	* configure: Regenerated.
	* disassemble.c (ARCH_nios2): Define.
	(disassembler): Add case for bfd_arch_nios2.
	* nios2-dis.c: New file.
	* nios2-opc.c: New file.

2013-02-04  Alan Modra  <amodra@gmail.com>

	* po/POTFILES.in: Regenerate.
	* rl78-decode.c: Regenerate.
	* rx-decode.c: Regenerate.

2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
	ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
	* aarch64-asm.c (convert_xtl_to_shll): New function.
	(convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	calling convert_xtl_to_shll.
	* aarch64-dis.c (convert_shll_to_xtl): New function.
	(convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	calling convert_shll_to_xtl.
	* aarch64-gen.c: Update copyright year.
	* aarch64-asm-2.c: Re-generate.
	* aarch64-dis-2.c: Re-generate.
	* aarch64-opc-2.c: Re-generate.

2013-01-24  Nick Clifton  <nickc@redhat.com>

	* v850-dis.c: Add support for e3v5 architecture.
	* v850-opc.c: Likewise.

2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
	* aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
	* aarch64-opc.c (operand_general_constraint_met_p): For
	AARCH64_MOD_LSL, move the range check on the shift amount before the
	alignment check; change to call set_sft_amount_out_of_range_error
	instead of set_imm_out_of_range_error.
	* aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
	(aarch64_opcode_table): Remove the OP enumerator from the asimdimm
	8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
	SIMD_IMM_SFT.

2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2013-01-15  Nick Clifton  <nickc@redhat.com>

	* v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
	values.
	* v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.

2013-01-14  Will Newton <will.newton@imgtec.com>

	* metag-dis.c (REG_WIDTH): Increase to 64.

2013-01-10  Peter Bergner <bergner@vnet.ibm.com>

	* ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
	* ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
	XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
	(SH6): Update.
	<"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
	"tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
	"treclaim.", "tsr.">: Add POWER8 HTM opcodes.
	<"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.

2013-01-10  Will Newton <will.newton@imgtec.com>

	* Makefile.am: Add Meta.
	* configure.in: Add Meta.
	* disassemble.c: Add Meta support.
	* metag-dis.c: New file.
	* Makefile.in: Regenerate.
	* configure: Regenerate.

2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>

	* cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
	(match_opcode): Rename to cr16_match_opcode.

2013-01-04  Juergen Urban <JuergenUrban@gmx.de>

	* mips-dis.c: Add names for CP0 registers of r5900.
	* mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
	instructions sq and lq.
	Add support for MIPS r5900 CPU.
	Add support for 128 bit MMI (Multimedia Instructions).
	Add support for EE instructions (Emotion Engine).
	Disable unsupported floating point instructions (64 bit and
	undefined compare operations).
	Enable instructions of MIPS ISA IV which are supported by r5900.
	Disable 64 bit co processor instructions.
	Disable 64 bit multiplication and division instructions.
	Disable instructions for co-processor 2 and 3, because these are
	not supported (preparation for later VU0 support (Vector Unit)).
	Disable cvt.w.s because this behaves like trunc.w.s and the
	correct execution can't be ensured on r5900.
	Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
	will confuse less developers and compilers.

2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-opc.c (aarch64_print_operand): Change to print
	AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
	in comment.
	* aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
	from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
	OP_MOV_IMM_WIDE.

2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
	PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.

2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (process_copyright): Update copyright year to 2013.

2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>

	* cr16-dis.c (match_opcode,make_instruction): Remove static
	declaration.
	(dwordU,wordU): Moved typedefs to opcode/cr16.h
	(cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.

For older changes see ChangeLog-2012
\f
Copyright (C) 2013 Free Software Foundation, Inc.

Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.

Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
Commit	Line	Data
5c111e37 L	1	2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
	2
	3	PR gas/15159
	4	* i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
	5
	6	* i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
	7	(cpu_flags): Add CpuSMAP.
	8
	9	* i386-opc.h (CpuSMAP): New.
	10	(i386_cpu_flags): Add cpusmap.
	11
	12	* i386-opc.tbl: Add clac and stac.
	13
	14	* i386-init.h: Regenerated.
	15	* i386-tbl.h: Likewise.
	16
9d1df426 NC	17	2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
	18
	19	* metag-dis.c: Initialize outf->bytes_per_chunk to 4
	20	which also makes the disassembler output be in little
	21	endian like it should be.
	22
a1ccaec9 YZ	23	2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
	24
	25	* aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
	26	fields to NULL.
	27	(aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
	28
ef068ef4	29	2013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
5417f71e MR	30
	31	* mips-dis.c (is_compressed_mode_p): Only match symbols from the
	32	section disassembled.
	33
6fe6ded9 RE	34	2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
	35
	36	* arm-dis.c: Update strht pattern.
	37
0aa27725 RS	38	2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
	39
	40	* mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
	41	single-float. Disable ll, lld, sc and scd for EE. Disable the
	42	trunc.w.s macro for EE.
	43
36591ba1 SL	44	2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
	45	Andrew Jenner <andrew@codesourcery.com>
	46
	47	Based on patches from Altera Corporation.
	48
	49	* Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
	50	nios2-opc.c.
	51	* Makefile.in: Regenerated.
	52	* configure.in: Add case for bfd_nios2_arch.
	53	* configure: Regenerated.
	54	* disassemble.c (ARCH_nios2): Define.
	55	(disassembler): Add case for bfd_arch_nios2.
	56	* nios2-dis.c: New file.
	57	* nios2-opc.c: New file.
	58
545093a4 AM	59	2013-02-04 Alan Modra <amodra@gmail.com>
	60
	61	* po/POTFILES.in: Regenerate.
	62	* rl78-decode.c: Regenerate.
	63	* rx-decode.c: Regenerate.
	64
e30181a5 YZ	65	2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
	66
	67	* aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
	68	ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
	69	* aarch64-asm.c (convert_xtl_to_shll): New function.
	70	(convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	71	calling convert_xtl_to_shll.
	72	* aarch64-dis.c (convert_shll_to_xtl): New function.
	73	(convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	74	calling convert_shll_to_xtl.
	75	* aarch64-gen.c: Update copyright year.
	76	* aarch64-asm-2.c: Re-generate.
	77	* aarch64-dis-2.c: Re-generate.
	78	* aarch64-opc-2.c: Re-generate.
	79
78c8d46c NC	80	2013-01-24 Nick Clifton <nickc@redhat.com>
	81
	82	* v850-dis.c: Add support for e3v5 architecture.
	83	* v850-opc.c: Likewise.
	84
f5555712 YZ	85	2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
	86
	87	* aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
	88	* aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
	89	* aarch64-opc.c (operand_general_constraint_met_p): For
78c8d46c	90	AARCH64_MOD_LSL, move the range check on the shift amount before the
f5555712 YZ	91	alignment check; change to call set_sft_amount_out_of_range_error
	92	instead of set_imm_out_of_range_error.
	93	* aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
	94	(aarch64_opcode_table): Remove the OP enumerator from the asimdimm
	95	8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
	96	SIMD_IMM_SFT.
	97
2f81ff92 L	98	2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
	99
	100	* i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
	101
	102	* i386-init.h: Regenerated.
	103	* i386-tbl.h: Likewise.
	104
dd42f060 NC	105	2013-01-15 Nick Clifton <nickc@redhat.com>
	106
	107	* v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
	108	values.
	109	* v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
	110
a4533ed8 NC	111	2013-01-14 Will Newton <will.newton@imgtec.com>
	112
	113	* metag-dis.c (REG_WIDTH): Increase to 64.
	114
5817ffd1 PB	115	2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
	116
	117	* ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
	118	* ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
	119	XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
	120	(SH6): Update.
	121	<"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
	122	"tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
	123	"treclaim.", "tsr.">: Add POWER8 HTM opcodes.
	124	<"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
	125
a3c62988 NC	126	2013-01-10 Will Newton <will.newton@imgtec.com>
	127
	128	* Makefile.am: Add Meta.
	129	* configure.in: Add Meta.
	130	* disassemble.c: Add Meta support.
	131	* metag-dis.c: New file.
	132	* Makefile.in: Regenerate.
	133	* configure: Regenerate.
	134
73335eae NC	135	2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
	136
	137	* cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
	138	(match_opcode): Rename to cr16_match_opcode.
	139
e407c74b NC	140	2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
	141
	142	* mips-dis.c: Add names for CP0 registers of r5900.
	143	* mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
	144	instructions sq and lq.
	145	Add support for MIPS r5900 CPU.
	146	Add support for 128 bit MMI (Multimedia Instructions).
	147	Add support for EE instructions (Emotion Engine).
	148	Disable unsupported floating point instructions (64 bit and
	149	undefined compare operations).
	150	Enable instructions of MIPS ISA IV which are supported by r5900.
	151	Disable 64 bit co processor instructions.
	152	Disable 64 bit multiplication and division instructions.
	153	Disable instructions for co-processor 2 and 3, because these are
	154	not supported (preparation for later VU0 support (Vector Unit)).
	155	Disable cvt.w.s because this behaves like trunc.w.s and the
	156	correct execution can't be ensured on r5900.
	157	Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
	158	will confuse less developers and compilers.
	159
a32c3ff8 NC	160	2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
a32c3ff8 NC	161
fb098a1e YZ	162	* aarch64-opc.c (aarch64_print_operand): Change to print
	163	AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
	164	in comment.
	165	* aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
	166	from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
	167	OP_MOV_IMM_WIDE.
	168
	169	2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
	170
	171	* aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
	172	PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
a32c3ff8	173
62658407 L	174	2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
	175
	176	* i386-gen.c (process_copyright): Update copyright year to 2013.
	177
bab4becb	178	2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
5bf135a7	179
bab4becb NC	180	* cr16-dis.c (match_opcode,make_instruction): Remove static
	181	declaration.
	182	(dwordU,wordU): Moved typedefs to opcode/cr16.h
	183	(cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
5bf135a7	184
bab4becb	185	For older changes see ChangeLog-2012
252b5132	186	\f
bab4becb	187	Copyright (C) 2013 Free Software Foundation, Inc.
752937aa NC	188
	189	Copying and distribution of this file, with or without modification,
	190	are permitted in any medium without royalty provided the copyright
	191	notice and this notice are preserved.
	192
252b5132	193	Local Variables:
2f6d2f85 NC	194	mode: change-log
	195	left-margin: 8
	196	fill-column: 74
252b5132 RH	197	version-control: never
252b5132 RH	198	End: