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btrace: fix void return
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
875880c6
YQ		 12015-10-07 Yao Qi <yao.qi@linaro.org>
2
3 * aarch64-dis.c (aarch64_ext_sysins_op): Access field
4 'name' rather than 'template'.
5 * aarch64-opc.c (aarch64_print_operand): Likewise.
6
886a2506
NC		 72015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
8
9 * arc-dis.c: Revamped file for ARC support
10 * arc-dis.h: Likewise.
11 * arc-ext.c: Likewise.
12 * arc-ext.h: Likewise.
13 * arc-opc.c: Likewise.
14 * arc-fxi.h: New file.
15 * arc-regs.h: Likewise.
16 * arc-tbl.h: Likewise.
17
36f4aab1
YQ		 182015-10-02 Yao Qi <yao.qi@linaro.org>
19
20 * aarch64-dis.c (disas_aarch64_insn): Remove static. Change
21 argument insn type to aarch64_insn. Rename to ...
22 (aarch64_decode_insn): ... it.
23 (print_insn_aarch64_word): Caller updated.
24
7232d389
YQ		 252015-10-02 Yao Qi <yao.qi@linaro.org>
26
27 * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
28 (print_insn_aarch64_word): Caller updated.
29
7ecc513a
DV		 302015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
31
32 * s390-mkopc.c (main): Parse htm and vx flag.
33 * s390-opc.txt: Mark instructions from the hardware transactional
34 memory and vector facilities with the "htm"/"vx" flag.
35
b08b78e7
NC		 362015-09-28 Nick Clifton <nickc@redhat.com>
37
38 * po/de.po: Updated German translation.
39
36f7a941
TR		 402015-09-28 Tom Rix <tom@bumblecow.com>
41
42 * ppc-opc.c (PPC500): Mark some opcodes as invalid
43
b6518b38
NC		 442015-09-23 Nick Clifton <nickc@redhat.com>
45
46 * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
47 function.
48 * tic30-dis.c (print_branch): Likewise.
49 * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
50 value before left shifting.
51 * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
52 * hppa-dis.c (print_insn_hppa): Likewise.
53 * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
54 array.
55 * msp430-dis.c (msp430_singleoperand): Likewise.
56 (msp430_doubleoperand): Likewise.
57 (print_insn_msp430): Likewise.
58 * nds32-asm.c (parse_operand): Likewise.
59 * sh-opc.h (MASK): Likewise.
60 * v850-dis.c (get_operand_value): Likewise.
61
f04265ec
NC		 622015-09-22 Nick Clifton <nickc@redhat.com>
63
64 * rx-decode.opc (bwl): Use RX_Bad_Size.
65 (sbwl): Likewise.
66 (ubwl): Likewise. Rename to ubw.
67 (uBWL): Rename to uBW.
68 Replace all references to uBWL with uBW.
69 * rx-decode.c: Regenerate.
70 * rx-dis.c (size_names): Add entry for RX_Bad_Size.
71 (opsize_names): Likewise.
72 (print_insn_rx): Detect and report RX_Bad_Size.
73
6dca4fd1
AB		 742015-09-22 Anton Blanchard <anton@samba.org>
75
76 * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
77
38074311
JM		 782015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
79
80 * sparc-dis.c (print_insn_sparc): Handle the privileged register
81 %pmcdper.
82
5f40e14d
JS		 832015-08-24 Jan Stancek <jstancek@redhat.com>
84
85 * i386-dis.c (print_insn): Fix decoding of three byte operands.
86
ab4e4ed5
AF		 872015-08-21 Alexander Fomin <alexander.fomin@intel.com>
88
89 PR binutils/18257
90 * i386-dis.c: Use MOD_TABLE for most of mask instructions.
91 (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
92 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
93 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
94 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
95 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
96 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
97 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
98 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
99 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
100 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
101 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
102 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
103 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
104 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
105 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
106 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
107 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
108 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
109 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
110 MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
111 MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
112 MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
113 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
114 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
115 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
116 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
117 MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
118 MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
119 MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
120 MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
121 (vex_w_table): Replace terminals with MOD_TABLE entries for
122 most of mask instructions.
123
919b75f7
AM		 1242015-08-17 Alan Modra <amodra@gmail.com>
125
126 * cgen.sh: Trim trailing space from cgen output.
127 * ia64-gen.c (print_dependency_table): Don't generate trailing space.
128 (print_dis_table): Likewise.
129 * opc2c.c (dump_lines): Likewise.
130 (orig_filename): Warning fix.
131 * ia64-asmtab.c: Regenerate.
132
4ab90a7a
AV		 1332015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
134
135 * arm-dis.c (print_insn_arm): Disassembling for all targets V6
136 and higher with ARM instruction set will now mark the 26-bit
137 versions of teq,tst,cmn and cmp as UNPREDICTABLE.
138 (arm_opcodes): Fix for unpredictable nop being recognized as a
139 teq.
140
40fc1451
SD		 1412015-08-12 Simon Dardis <simon.dardis@imgtec.com>
142
143 * micromips-opc.c (micromips_opcodes): Re-order table so that move
144 based on 'or' is first.
145 * mips-opc.c (mips_builtin_opcodes): Ditto.
146
922c5db5
NC		 1472015-08-11 Nick Clifton <nickc@redhat.com>
148
149 PR 18800
150 * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
151 instruction.
152
75fb7498
RS		 1532015-08-10 Robert Suchanek <robert.suchanek@imgtec.com>
154
155 * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
156
36aed29d
AP		 1572015-08-07 Amit Pawar <Amit.Pawar@amd.com>
158
159 * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
160 * i386-init.h: Regenerated.
161
a8484f96
L		 1622015-07-30 H.J. Lu <hongjiu.lu@intel.com>
163
164 PR binutils/13571
165 * i386-dis.c (MOD_0FC3): New.
166 (PREFIX_0FC3): Renamed to ...
167 (PREFIX_MOD_0_0FC3): This.
168 (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
169 (prefix_table): Replace Ma with Ev on movntiS.
170 (mod_table): Add MOD_0FC3.
171
37a42ee9
L		 1722015-07-27 H.J. Lu <hongjiu.lu@intel.com>
173
174 * configure: Regenerated.
175
070fe95d
AM		 1762015-07-23 Alan Modra <amodra@gmail.com>
177
178 PR 18708
179 * i386-dis.c (get64): Avoid signed integer overflow.
180
20c2a615
L		 1812015-07-22 Alexander Fomin <alexander.fomin@intel.com>
182
183 PR binutils/18631
184 * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
185 "EXEvexHalfBcstXmmq" for the second operand.
186 (EVEX_W_0F79_P_2): Likewise.
187 (EVEX_W_0F7A_P_2): Likewise.
188 (EVEX_W_0F7B_P_2): Likewise.
189
6f1c2142
AM		 1902015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
191
192 * arm-dis.c (print_insn_coprocessor): Added support for quarter
193 float bitfield format.
194 (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
195 quarter float bitfield format.
196
8a643cc3
L		 1972015-07-14 H.J. Lu <hongjiu.lu@intel.com>
198
199 * configure: Regenerated.
200
ef5a96d5
AM		 2012015-07-03 Alan Modra <amodra@gmail.com>
202
203 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
204 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
205 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
206
c8c8175b
SL		 2072015-07-01 Sandra Loosemore <sandra@codesourcery.com>
208 Cesar Philippidis <cesar@codesourcery.com>
209
210 * nios2-dis.c (nios2_extract_opcode): New.
211 (nios2_disassembler_state): New.
212 (nios2_find_opcode_hash): Use mach parameter to select correct
213 disassembler state.
214 (nios2_print_insn_arg): Extend to support new R2 argument letters
215 and formats.
216 (print_insn_nios2): Check for 16-bit instruction at end of memory.
217 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
218 (NIOS2_NUM_OPCODES): Rename to...
219 (NIOS2_NUM_R1_OPCODES): This.
220 (nios2_r2_opcodes): New.
221 (NIOS2_NUM_R2_OPCODES): New.
222 (nios2_num_r2_opcodes): New.
223 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
224 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
225 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
226 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
227 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
228
9916071f
AP		 2292015-06-30 Amit Pawar <Amit.Pawar@amd.com>
230
231 * i386-dis.c (OP_Mwaitx): New.
232 (rm_table): Add monitorx/mwaitx.
233 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
234 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
235 (operand_type_init): Add CpuMWAITX.
236 * i386-opc.h (CpuMWAITX): New.
237 (i386_cpu_flags): Add cpumwaitx.
238 * i386-opc.tbl: Add monitorx and mwaitx.
239 * i386-init.h: Regenerated.
240 * i386-tbl.h: Likewise.
241
7b934113
PB		 2422015-06-22 Peter Bergner <bergner@vnet.ibm.com>
243
244 * ppc-opc.c (insert_ls): Test for invalid LS operands.
245 (insert_esync): New function.
246 (LS, WC): Use insert_ls.
247 (ESYNC): Use insert_esync.
248
bdc4de1b
NC		 2492015-06-22 Nick Clifton <nickc@redhat.com>
250
251 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
252 requested region lies beyond it.
253 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
254 looking for 32-bit insns.
255 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
256 data.
257 * sh-dis.c (print_insn_sh): Likewise.
258 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
259 blocks of instructions.
260 * vax-dis.c (print_insn_vax): Check that the requested address
261 does not clash with the stop_vma.
262
11a0cf2e
PB		 2632015-06-19 Peter Bergner <bergner@vnet.ibm.com>
264
070fe95d 265 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
11a0cf2e
PB		 266 * ppc-opc.c (FXM4): Add non-zero optional value.
267 (TBR): Likewise.
268 (SXL): Likewise.
269 (insert_fxm): Handle new default operand value.
270 (extract_fxm): Likewise.
271 (insert_tbr): Likewise.
272 (extract_tbr): Likewise.
273
bdfa8b95
MW		 2742015-06-16 Matthew Wahab <matthew.wahab@arm.com>
275
276 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
277
24b4cf66
SN		 2782015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
279
280 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
281
99a2c561
PB		 2822015-06-12 Peter Bergner <bergner@vnet.ibm.com>
283
284 * ppc-opc.c: Add comment accidentally removed by old commit.
285 (MTMSRD_L): Delete.
286
40f77f82
AM		 2872015-06-04 Peter Bergner <bergner@vnet.ibm.com>
288
289 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
290
13be46a2
NC		 2912015-06-04 Nick Clifton <nickc@redhat.com>
292
293 PR 18474
294 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
295
ddfded2f
MW		 2962015-06-02 Matthew Wahab <matthew.wahab@arm.com>
297
298 * arm-dis.c (arm_opcodes): Add "setpan".
299 (thumb_opcodes): Add "setpan".
300
1af1dd51
MW		 3012015-06-02 Matthew Wahab <matthew.wahab@arm.com>
302
303 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
304 macros.
305
9e1f0fa7
MW		 3062015-06-02 Matthew Wahab <matthew.wahab@arm.com>
307
308 * aarch64-tbl.h (aarch64_feature_rdma): New.
309 (RDMA): New.
310 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
311 * aarch64-asm-2.c: Regenerate.
312 * aarch64-dis-2.c: Regenerate.
313 * aarch64-opc-2.c: Regenerate.
314
290806fd
MW		 3152015-06-02 Matthew Wahab <matthew.wahab@arm.com>
316
317 * aarch64-tbl.h (aarch64_feature_lor): New.
318 (LOR): New.
319 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
320 "stllrb", "stllrh".
321 * aarch64-asm-2.c: Regenerate.
322 * aarch64-dis-2.c: Regenerate.
323 * aarch64-opc-2.c: Regenerate.
324
f21cce2c
MW		 3252015-06-01 Matthew Wahab <matthew.wahab@arm.com>
326
327 * aarch64-opc.c (F_ARCHEXT): New.
328 (aarch64_sys_regs): Add "pan".
329 (aarch64_sys_reg_supported_p): New.
330 (aarch64_pstatefields): Add "pan".
331 (aarch64_pstatefield_supported_p): New.
332
d194d186
JB		 3332015-06-01 Jan Beulich <jbeulich@suse.com>
334
335 * i386-tbl.h: Regenerate.
336
3a8547d2
JB		 3372015-06-01 Jan Beulich <jbeulich@suse.com>
338
339 * i386-dis.c (print_insn): Swap rounding mode specifier and
340 general purpose register in Intel mode.
341
015c54d5
JB		 3422015-06-01 Jan Beulich <jbeulich@suse.com>
343
344 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
345 * i386-tbl.h: Regenerate.
346
071f0063
L		 3472015-05-18 H.J. Lu <hongjiu.lu@intel.com>
348
349 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
350 * i386-init.h: Regenerated.
351
5db04b09
L		 3522015-05-15 H.J. Lu <hongjiu.lu@intel.com>
353
354 PR binutis/18386
355 * i386-dis.c: Add comments for '@'.
356 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
357 (enum x86_64_isa): New.
358 (isa64): Likewise.
359 (print_i386_disassembler_options): Add amd64 and intel64.
360 (print_insn): Handle amd64 and intel64.
361 (putop): Handle '@'.
362 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
363 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
364 * i386-opc.h (AMD64): New.
365 (CpuIntel64): Likewise.
366 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
367 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
368 Mark direct call/jmp without Disp16|Disp32 as Intel64.
369 * i386-init.h: Regenerated.
370 * i386-tbl.h: Likewise.
371
4bc0608a
PB		 3722015-05-14 Peter Bergner <bergner@vnet.ibm.com>
373
374 * ppc-opc.c (IH) New define.
375 (powerpc_opcodes) <wait>: Do not enable for POWER7.
376 <tlbie>: Add RS operand for POWER7.
377 <slbia>: Add IH operand for POWER6.
378
70cead07
L		 3792015-05-11 H.J. Lu <hongjiu.lu@intel.com>
380
381 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
382 direct branch.
383 (jmp): Likewise.
384 * i386-tbl.h: Regenerated.
385
7b6d09fb
L		 3862015-05-11 H.J. Lu <hongjiu.lu@intel.com>
387
388 * configure.ac: Support bfd_iamcu_arch.
389 * disassemble.c (disassembler): Support bfd_iamcu_arch.
390 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
391 CPU_IAMCU_COMPAT_FLAGS.
392 (cpu_flags): Add CpuIAMCU.
393 * i386-opc.h (CpuIAMCU): New.
394 (i386_cpu_flags): Add cpuiamcu.
395 * configure: Regenerated.
396 * i386-init.h: Likewise.
397 * i386-tbl.h: Likewise.
398
31955f99
L		 3992015-05-08 H.J. Lu <hongjiu.lu@intel.com>
400
401 PR binutis/18386
402 * i386-dis.c (X86_64_E8): New.
403 (X86_64_E9): Likewise.
404 Update comments on 'T', 'U', 'V'. Add comments for '^'.
405 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
406 (x86_64_table): Add X86_64_E8 and X86_64_E9.
407 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
408 (putop): Handle '^'.
409 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
410 REX_W.
411
0952813b
DD		 4122015-04-30 DJ Delorie <dj@redhat.com>
413
414 * disassemble.c (disassembler): Choose suitable disassembler based
415 on E_ABI.
416 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
417 it to decode mul/div insns.
418 * rl78-decode.c: Regenerate.
419 * rl78-dis.c (print_insn_rl78): Rename to...
420 (print_insn_rl78_common): ...this, take ISA parameter.
421 (print_insn_rl78): New.
422 (print_insn_rl78_g10): New.
423 (print_insn_rl78_g13): New.
424 (print_insn_rl78_g14): New.
425 (rl78_get_disassembler): New.
426
f9d3ecaa
NC		 4272015-04-29 Nick Clifton <nickc@redhat.com>
428
429 * po/fr.po: Updated French translation.
430
4fff86c5
PB		 4312015-04-27 Peter Bergner <bergner@vnet.ibm.com>
432
433 * ppc-opc.c (DCBT_EO): New define.
434 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
435 <lharx>: Likewise.
436 <stbcx.>: Likewise.
437 <sthcx.>: Likewise.
438 <waitrsv>: Do not enable for POWER7 and later.
439 <waitimpl>: Likewise.
440 <dcbt>: Default to the two operand form of the instruction for all
441 "old" cpus. For "new" cpus, use the operand ordering that matches
442 whether the cpu is server or embedded.
443 <dcbtst>: Likewise.
444
3b78cfe1
AK		 4452015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
446
447 * s390-opc.c: New instruction type VV0UU2.
448 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
449 and WFC.
450
04d824a4
JB		 4512015-04-23 Jan Beulich <jbeulich@suse.com>
452
453 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
454 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
455 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
456 (vfpclasspd, vfpclassps): Add %XZ.
457
09708981
L		 4582015-04-15 H.J. Lu <hongjiu.lu@intel.com>
459
460 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
461 (PREFIX_UD_REPZ): Likewise.
462 (PREFIX_UD_REPNZ): Likewise.
463 (PREFIX_UD_DATA): Likewise.
464 (PREFIX_UD_ADDR): Likewise.
465 (PREFIX_UD_LOCK): Likewise.
466
3888916d
L		 4672015-04-15 H.J. Lu <hongjiu.lu@intel.com>
468
469 * i386-dis.c (prefix_requirement): Removed.
470 (print_insn): Don't set prefix_requirement. Check
471 dp->prefix_requirement instead of prefix_requirement.
472
f24bcbaa
L		 4732015-04-15 H.J. Lu <hongjiu.lu@intel.com>
474
475 PR binutils/17898
476 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
477 (PREFIX_MOD_0_0FC7_REG_6): This.
478 (PREFIX_MOD_3_0FC7_REG_6): New.
479 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
480 (prefix_table): Replace PREFIX_0FC7_REG_6 with
481 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
482 PREFIX_MOD_3_0FC7_REG_7.
483 (mod_table): Replace PREFIX_0FC7_REG_6 with
484 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
485 PREFIX_MOD_3_0FC7_REG_7.
486
507bd325
L		 4872015-04-15 H.J. Lu <hongjiu.lu@intel.com>
488
489 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
490 (PREFIX_MANDATORY_REPNZ): Likewise.
491 (PREFIX_MANDATORY_DATA): Likewise.
492 (PREFIX_MANDATORY_ADDR): Likewise.
493 (PREFIX_MANDATORY_LOCK): Likewise.
494 (PREFIX_MANDATORY): Likewise.
495 (PREFIX_UD_SHIFT): Set to 8
496 (PREFIX_UD_REPZ): Updated.
497 (PREFIX_UD_REPNZ): Likewise.
498 (PREFIX_UD_DATA): Likewise.
499 (PREFIX_UD_ADDR): Likewise.
500 (PREFIX_UD_LOCK): Likewise.
501 (PREFIX_IGNORED_SHIFT): New.
502 (PREFIX_IGNORED_REPZ): Likewise.
503 (PREFIX_IGNORED_REPNZ): Likewise.
504 (PREFIX_IGNORED_DATA): Likewise.
505 (PREFIX_IGNORED_ADDR): Likewise.
506 (PREFIX_IGNORED_LOCK): Likewise.
507 (PREFIX_OPCODE): Likewise.
508 (PREFIX_IGNORED): Likewise.
509 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
510 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
511 (three_byte_table): Likewise.
512 (mod_table): Likewise.
513 (mandatory_prefix): Renamed to ...
514 (prefix_requirement): This.
515 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
516 Update PREFIX_90 entry.
517 (get_valid_dis386): Check prefix_requirement to see if a prefix
518 should be ignored.
519 (print_insn): Replace mandatory_prefix with prefix_requirement.
520
f0fba320
RL		 5212015-04-15 Renlin Li <renlin.li@arm.com>
522
523 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
524 use it for ssat and ssat16.
525 (print_insn_thumb32): Add handle case for 'D' control code.
526
bf890a93
IT		 5272015-04-06 Ilya Tocar <ilya.tocar@intel.com>
528 H.J. Lu <hongjiu.lu@intel.com>
529
530 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
531 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
532 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
533 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
534 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
535 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
536 Fill prefix_requirement field.
537 (struct dis386): Add prefix_requirement field.
538 (dis386): Fill prefix_requirement field.
539 (dis386_twobyte): Ditto.
540 (twobyte_has_mandatory_prefix_: Remove.
541 (reg_table): Fill prefix_requirement field.
542 (prefix_table): Ditto.
543 (x86_64_table): Ditto.
544 (three_byte_table): Ditto.
545 (xop_table): Ditto.
546 (vex_table): Ditto.
547 (vex_len_table): Ditto.
548 (vex_w_table): Ditto.
549 (mod_table): Ditto.
550 (bad_opcode): Ditto.
551 (print_insn): Use prefix_requirement.
552 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
553 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
554 (float_reg): Ditto.
555
2f783c1f
MF		 5562015-03-30 Mike Frysinger <vapier@gentoo.org>
557
558 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
559
b9d94d62
L		 5602015-03-29 H.J. Lu <hongjiu.lu@intel.com>
561
562 * Makefile.in: Regenerated.
563
27c49e9a
AB		 5642015-03-25 Anton Blanchard <anton@samba.org>
565
566 * ppc-dis.c (disassemble_init_powerpc): Only initialise
567 powerpc_opcd_indices and vle_opcd_indices once.
568
c4e676f1
AB		 5692015-03-25 Anton Blanchard <anton@samba.org>
570
571 * ppc-opc.c (powerpc_opcodes): Add slbfee.
572
823d2571
TG		 5732015-03-24 Terry Guo <terry.guo@arm.com>
574
575 * arm-dis.c (opcode32): Updated to use new arm feature struct.
576 (opcode16): Likewise.
577 (coprocessor_opcodes): Replace bit with feature struct.
578 (neon_opcodes): Likewise.
579 (arm_opcodes): Likewise.
580 (thumb_opcodes): Likewise.
581 (thumb32_opcodes): Likewise.
582 (print_insn_coprocessor): Likewise.
583 (print_insn_arm): Likewise.
584 (select_arm_features): Follow new feature struct.
585
029f3522
GG		 5862015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
587
588 * i386-dis.c (rm_table): Add clzero.
589 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
590 Add CPU_CLZERO_FLAGS.
591 (cpu_flags): Add CpuCLZERO.
592 * i386-opc.h: Add CpuCLZERO.
593 * i386-opc.tbl: Add clzero.
594 * i386-init.h: Re-generated.
595 * i386-tbl.h: Re-generated.
596
6914869a
AB		 5972015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
598
599 * mips-opc.c (decode_mips_operand): Fix constraint issues
600 with u and y operands.
601
21e20815
AB		 6022015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
603
604 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
605
6b1d7593
AK		 6062015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
607
608 * s390-opc.c: Add new IBM z13 instructions.
609 * s390-opc.txt: Likewise.
610
c8f89a34
JW		 6112015-03-10 Renlin Li <renlin.li@arm.com>
612
613 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
614 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
615 related alias.
616 * aarch64-asm-2.c: Regenerate.
617 * aarch64-dis-2.c: Likewise.
618 * aarch64-opc-2.c: Likewise.
619
d8282f0e
JW		 6202015-03-03 Jiong Wang <jiong.wang@arm.com>
621
622 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
623
ac994365
OE		 6242015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
625
626 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
627 arch_sh_up.
628 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
629 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
630
fd63f640
V		 6312015-02-23 Vinay <Vinay.G@kpit.com>
632
633 * rl78-decode.opc (MOV): Added space between two operands for
634 'mov' instruction in index addressing mode.
635 * rl78-decode.c: Regenerate.
636
f63c1776
PA		 6372015-02-19 Pedro Alves <palves@redhat.com>
638
639 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
640
07774fcc
PA		 6412015-02-10 Pedro Alves <palves@redhat.com>
642 Tom Tromey <tromey@redhat.com>
643
644 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
645 microblaze_and, microblaze_xor.
646 * microblaze-opc.h (opcodes): Adjust.
647
3f8107ab
AM		 6482015-01-28 James Bowman <james.bowman@ftdichip.com>
649
650 * Makefile.am: Add FT32 files.
651 * configure.ac: Handle FT32.
652 * disassemble.c (disassembler): Call print_insn_ft32.
653 * ft32-dis.c: New file.
654 * ft32-opc.c: New file.
655 * Makefile.in: Regenerate.
656 * configure: Regenerate.
657 * po/POTFILES.in: Regenerate.
658
e5fe4957
KLC		 6592015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
660
661 * nds32-asm.c (keyword_sr): Add new system registers.
662
1e2e8c52
AK		 6632015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
664
665 * s390-dis.c (s390_extract_operand): Support vector register
666 operands.
667 (s390_print_insn_with_opcode): Support new operands types and add
668 new handling of optional operands.
669 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
670 and include opcode/s390.h instead.
671 (struct op_struct): New field `flags'.
672 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
673 (dumpTable): Dump flags.
674 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
675 string.
676 * s390-opc.c: Add new operands types, instruction formats, and
677 instruction masks.
678 (s390_opformats): Add new formats for .insn.
679 * s390-opc.txt: Add new instructions.
680
b90efa5b 6812015-01-01 Alan Modra <amodra@gmail.com>
bffb6004 682
b90efa5b 683 Update year range in copyright notice of all files.
bffb6004 684
b90efa5b 685For older changes see ChangeLog-2014
252b5132 686\f
b90efa5b 687Copyright (C) 2015 Free Software Foundation, Inc.
752937aa
NC		 688
689Copying and distribution of this file, with or without modification,
690are permitted in any medium without royalty provided the copyright
691notice and this notice are preserved.
692
252b5132 693Local Variables:
2f6d2f85
NC		 694mode: change-log
695left-margin: 8
696fill-column: 74
252b5132
RH		 697version-control: never
698End:
GDB Binutils - Deliverables
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