projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
x86: merge/move logic determining the EVEX disp8 shift
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
059edf8b
JB		 12020-07-14 Jan Beulich <jbeulich@suse.com>
2
3 * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
4 dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
5 d_scalar_swap_mode case handling. Move shift adjsutment into
6 the case its applicable to.
7
4726e9a4
JB		 82020-07-14 Jan Beulich <jbeulich@suse.com>
9
10 * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
11 (EXbScalar, EXwScalar): Fold to ...
12 (EXbwUnit): ... this.
13 (b_scalar_mode, w_scalar_mode): Fold to ...
14 (bw_unit_mode): ... this.
15 (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
16 w_scalar_mode handling by bw_unit_mode one.
17 * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
18 ...
19 * i386-dis-evex-prefix.h: ... here.
20
b24d668c
JB		 212020-07-14 Jan Beulich <jbeulich@suse.com>
22
23 * i386-dis.c (PCMPESTR_Fixup): Delete.
24 (dis386): Adjust "LQ" description.
25 (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
26 cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
27 PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
28 vpcmpestrm, and vpcmpestri.
29 (putop): Honor "cond" when handling LQ.
30 * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
31 vcvtsi2ss and vcvtusi2ss.
32 * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
33 vcvtsi2sd and vcvtusi2sd.
34
c4de7606
JB		 352020-07-14 Jan Beulich <jbeulich@suse.com>
36
37 * i386-dis.c (VCMP_Fixup, VCMP): Delete.
38 (simd_cmp_op): Add const.
39 (vex_cmp_op): Move up and drop initial 8 entries. Add const.
40 (CMP_Fixup): Handle VEX case.
41 (prefix_table): Replace VCMP by CMP.
42 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
43
9ab00b61
JB		 442020-07-14 Jan Beulich <jbeulich@suse.com>
45
46 * i386-dis.c (MOVBE_Fixup): Delete.
47 (Mv): Define.
48 (prefix_table): Use Mv for movbe entries.
49
2875b28a
JB		 502020-07-14 Jan Beulich <jbeulich@suse.com>
51
52 * i386-dis.c (CRC32_Fixup): Delete.
53 (prefix_table): Use Eb/Ev for crc32 entries.
54
e184e611
JB		 552020-07-14 Jan Beulich <jbeulich@suse.com>
56
57 * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
58 Conditionalize invocations of "USED_REX (0)".
59
e8b5d5f9
JB		 602020-07-14 Jan Beulich <jbeulich@suse.com>
61
62 * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
63 CH, DH, BH, AX, DX): Delete.
64 (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
65 eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
66 dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
67
260cd341
LC		 682020-07-10 Lili Cui <lili.cui@intel.com>
69
70 * i386-dis.c (TMM): New.
71 (EXtmm): Likewise.
72 (VexTmm): Likewise.
73 (MVexSIBMEM): Likewise.
74 (tmm_mode): Likewise.
75 (vex_sibmem_mode): Likewise.
76 (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
77 (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
78 (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
79 (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
80 (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
81 (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
82 (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
83 (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
84 (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
85 (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
86 (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
87 (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
88 (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
89 (PREFIX_VEX_0F3849_X86_64): Likewise.
90 (PREFIX_VEX_0F384B_X86_64): Likewise.
91 (PREFIX_VEX_0F385C_X86_64): Likewise.
92 (PREFIX_VEX_0F385E_X86_64): Likewise.
93 (X86_64_VEX_0F3849): Likewise.
94 (X86_64_VEX_0F384B): Likewise.
95 (X86_64_VEX_0F385C): Likewise.
96 (X86_64_VEX_0F385E): Likewise.
97 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
98 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
99 (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
100 (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
101 (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
102 (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
103 (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
104 (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
105 (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
106 (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
107 (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
108 (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
109 (VEX_W_0F3849_X86_64_P_0): Likewise.
110 (VEX_W_0F3849_X86_64_P_2): Likewise.
111 (VEX_W_0F3849_X86_64_P_3): Likewise.
112 (VEX_W_0F384B_X86_64_P_1): Likewise.
113 (VEX_W_0F384B_X86_64_P_2): Likewise.
114 (VEX_W_0F384B_X86_64_P_3): Likewise.
115 (VEX_W_0F385C_X86_64_P_1): Likewise.
116 (VEX_W_0F385E_X86_64_P_0): Likewise.
117 (VEX_W_0F385E_X86_64_P_1): Likewise.
118 (VEX_W_0F385E_X86_64_P_2): Likewise.
119 (VEX_W_0F385E_X86_64_P_3): Likewise.
120 (names_tmm): Likewise.
121 (att_names_tmm): Likewise.
122 (intel_operand_size): Handle void_mode.
123 (OP_XMM): Handle tmm_mode.
124 (OP_EX): Likewise.
125 (OP_VEX): Likewise.
126 * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
127 CpuAMX_BF16 and CpuAMX_TILE.
128 (operand_type_shorthands): Add RegTMM.
129 (operand_type_init): Likewise.
130 (operand_types): Add Tmmword.
131 (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
132 (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
133 * i386-opc.h (CpuAMX_INT8): New.
134 (CpuAMX_BF16): Likewise.
135 (CpuAMX_TILE): Likewise.
136 (SIBMEM): Likewise.
137 (Tmmword): Likewise.
138 (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
139 (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
140 (i386_operand_type): Add tmmword.
141 * i386-opc.tbl: Add AMX instructions.
142 * i386-reg.tbl: Add AMX registers.
143 * i386-init.h: Regenerated.
144 * i386-tbl.h: Likewise.
145
467bbef0
JB		 1462020-07-08 Jan Beulich <jbeulich@suse.com>
147
148 * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
149 (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
150 Rename to ...
151 (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
152 REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
153 respectively.
154 (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
155 VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
156 VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
157 VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
158 VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
159 VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
160 VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
161 VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
162 VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
163 VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
164 VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
165 VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
166 VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
167 VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
168 VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
169 VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
170 VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
171 VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
172 VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
173 VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
174 VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
175 VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
176 VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
177 VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
178 VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
179 VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
180 VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
181 VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
182 VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
183 VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
184 VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
185 VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
186 VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
187 VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
188 VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
189 VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
190 (reg_table): Re-order XOP entries. Adjust their operands.
191 (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
192 08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
193 08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
194 09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
195 09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
196 09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
197 entries by references ...
198 (vex_len_table): ... to resepctive new entries here. For several
199 new and existing entries reference ...
200 (vex_w_table): ... new entries here.
201 (mod_table): New MOD_VEX_0FXOP_09_12 entry.
202
6384fd9e
JB		 2032020-07-08 Jan Beulich <jbeulich@suse.com>
204
205 * i386-dis.c (XMVexScalarI4): Define.
206 (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
207 VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
208 VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
209 (vex_len_table): Move scalar FMA4 entries ...
210 (prefix_table): ... here.
211 (OP_REG_VexI4): Handle scalar_mode.
212 * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
213 * i386-tbl.h: Re-generate.
214
e6123d0c
JB		 2152020-07-08 Jan Beulich <jbeulich@suse.com>
216
217 * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
218 Vex_2src_2): Delete.
219 (OP_VexW, VexW): New.
220 (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
221 for shifts and rotates by register.
222
93abb146
JB		 2232020-07-08 Jan Beulich <jbeulich@suse.com>
224
225 * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
226 VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
227 OP_EX_VexReg): Delete.
228 (OP_VexI4, VexI4): New.
229 (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
230 (prefix_table): ... here.
231 (print_insn): Drop setting of vex_w_done.
232
b13b1bc0
JB		 2332020-07-08 Jan Beulich <jbeulich@suse.com>
234
235 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
236 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
237 (xop_table): Replace operands of 4-operand insns.
238 (OP_REG_VexI4): Move VEX.W based operand swaping here.
239
f337259f
CZ		 2402020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
241
242 * arc-opc.c (insert_rbd): New function.
243 (RBD): Define.
244 (RBDdup): Likewise.
245 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
246 instructions.
247
931452b6
JB		 2482020-07-07 Jan Beulich <jbeulich@suse.com>
249
250 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
251 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
252 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
253 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
254 Delete.
255 (putop): Handle "BW".
256 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
257 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
258 and 0F3A3F ...
259 * i386-dis-evex-prefix.h: ... here.
260
b5b098c2
JB		 2612020-07-06 Jan Beulich <jbeulich@suse.com>
262
263 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
264 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
265 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
266 VEX_W_0FXOP_09_83): New enumerators.
267 (xop_table): Reference the above.
268 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
269 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
270 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
271 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
272
21a3faeb
JB		 2732020-07-06 Jan Beulich <jbeulich@suse.com>
274
275 * i386-dis.c (EVEX_W_0F3838_P_1,
276 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
277 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
278 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
279 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
280 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
281 (putop): Centralize management of last[]. Delete SAVE_LAST.
282 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
283 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
284 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
285 * i386-dis-evex-prefix.h: here.
286
bc152a17
JB		 2872020-07-06 Jan Beulich <jbeulich@suse.com>
288
289 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
290 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
291 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
292 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
293 enumerators.
294 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
295 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
296 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
297 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
298 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
299 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
300 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
301 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
302 these, respectively.
303 * i386-dis-evex-len.h: Adjust comments.
304 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
305 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
306 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
307 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
308 MOD_EVEX_0F385B_P_2_W_1 table entries.
309 * i386-dis-evex-w.h: Reference mod_table[] for
310 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
311 EVEX_W_0F385B_P_2.
312
c82a99a0
JB		 3132020-07-06 Jan Beulich <jbeulich@suse.com>
314
315 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
316 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
317 EXymm.
318 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
319 Likewise. Mark 256-bit entries invalid.
320
fedfb81e
JB		 3212020-07-06 Jan Beulich <jbeulich@suse.com>
322
323 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
324 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
325 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
326 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
327 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
328 PREFIX_EVEX_0F382B): Delete.
329 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
330 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
331 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
332 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
333 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
334 to ...
335 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
336 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
337 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
338 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
339 respectively.
340 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
341 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
342 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
343 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
344 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
345 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
346 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
347 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
348 PREFIX_EVEX_0F382B): Remove table entries.
349 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
350 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
351 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
352
3a57774c
JB		 3532020-07-06 Jan Beulich <jbeulich@suse.com>
354
355 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
356 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
357 enumerators.
358 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
359 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
360 EVEX_LEN_0F3A01_P_2_W_1 table entries.
361 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
362 entries.
363
e74d9fa9
JB		 3642020-07-06 Jan Beulich <jbeulich@suse.com>
365
366 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
367 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
368 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
369 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
370 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
371 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
372 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
373 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
374 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
375 entries.
376
6431c801
JB		 3772020-07-06 Jan Beulich <jbeulich@suse.com>
378
379 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
380 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
381 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
382 respectively.
383 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
384 entries.
385 * i386-dis-evex.h (evex_table): Reference VEX table entry for
386 opcode 0F3A1D.
387 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
388 entry.
389 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
390
6df22cf6
JB		 3912020-07-06 Jan Beulich <jbeulich@suse.com>
392
393 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
394 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
395 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
396 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
397 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
398 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
399 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
400 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
401 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
402 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
403 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
404 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
405 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
406 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
407 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
408 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
409 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
410 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
411 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
412 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
413 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
414 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
415 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
416 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
417 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
418 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
419 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
420 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
421 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
422 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
423 (prefix_table): Add EXxEVexR to FMA table entries.
424 (OP_Rounding): Move abort() invocation.
425 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
426 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
427 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
428 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
429 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
430 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
431 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
432 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
433 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
434 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
435 0F3ACE, 0F3ACF.
436 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
437 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
438 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
439 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
440 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
441 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
442 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
443 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
444 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
445 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
446 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
447 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
448 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
449 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
450 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
451 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
452 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
453 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
454 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
455 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
456 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
457 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
458 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
459 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
460 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
461 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
462 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
463 Delete table entries.
464 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
465 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
466 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
467 Likewise.
468
39e0f456
JB		 4692020-07-06 Jan Beulich <jbeulich@suse.com>
470
471 * i386-dis.c (EXqScalarS): Delete.
472 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
473 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
474
5b872f7d
JB		 4752020-07-06 Jan Beulich <jbeulich@suse.com>
476
477 * i386-dis.c (safe-ctype.h): Include.
478 (EXdScalar, EXqScalar): Delete.
479 (d_scalar_mode, q_scalar_mode): Delete.
480 (prefix_table, vex_len_table): Use EXxmm_md in place of
481 EXdScalar and EXxmm_mq in place of EXqScalar.
482 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
483 d_scalar_mode and q_scalar_mode.
484 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
485 (vmovsd): Use EXxmm_mq.
486
ddc73fa9
NC		 4872020-07-06 Yuri Chornoivan <yurchor@ukr.net>
488
489 PR 26204
490 * arc-dis.c: Fix spelling mistake.
491 * po/opcodes.pot: Regenerate.
492
17550be7
NC		 4932020-07-06 Nick Clifton <nickc@redhat.com>
494
495 * po/pt_BR.po: Updated Brazilian Portugugese translation.
496 * po/uk.po: Updated Ukranian translation.
497
b19d852d
NC		 4982020-07-04 Nick Clifton <nickc@redhat.com>
499
500 * configure: Regenerate.
501 * po/opcodes.pot: Regenerate.
502
b115b9fd
NC		 5032020-07-04 Nick Clifton <nickc@redhat.com>
504
505 Binutils 2.35 branch created.
506
c2ecccb3
L		 5072020-07-02 H.J. Lu <hongjiu.lu@intel.com>
508
509 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
510 * i386-opc.h (VexSwapSources): New.
511 (i386_opcode_modifier): Add vexswapsources.
512 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
513 with two source operands swapped.
514 * i386-tbl.h: Regenerated.
515
08ccfccf
NC		 5162020-06-30 Nelson Chu <nelson.chu@sifive.com>
517
518 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
519 unprivileged CSR can also be initialized.
520
279edac5
AM		 5212020-06-29 Alan Modra <amodra@gmail.com>
522
523 * arm-dis.c: Use C style comments.
524 * cr16-opc.c: Likewise.
525 * ft32-dis.c: Likewise.
526 * moxie-opc.c: Likewise.
527 * tic54x-dis.c: Likewise.
528 * s12z-opc.c: Remove useless comment.
529 * xgate-dis.c: Likewise.
530
e978ad62
L		 5312020-06-26 H.J. Lu <hongjiu.lu@intel.com>
532
533 * i386-opc.tbl: Add a blank line.
534
63112cd6
L		 5352020-06-26 H.J. Lu <hongjiu.lu@intel.com>
536
537 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
538 (VecSIB128): Renamed to ...
539 (VECSIB128): This.
540 (VecSIB256): Renamed to ...
541 (VECSIB256): This.
542 (VecSIB512): Renamed to ...
543 (VECSIB512): This.
544 (VecSIB): Renamed to ...
545 (SIB): This.
546 (i386_opcode_modifier): Replace vecsib with sib.
79b32e73 547 * i386-opc.tbl (VecSIB128): New.
63112cd6
L		 548 (VecSIB256): Likewise.
549 (VecSIB512): Likewise.
79b32e73 550 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
63112cd6
L		 551 and VecSIB512, respectively.
552
d1c36125
JB		 5532020-06-26 Jan Beulich <jbeulich@suse.com>
554
555 * i386-dis.c: Adjust description of I macro.
556 (x86_64_table): Drop use of I.
557 (float_mem): Replace use of I.
558 (putop): Remove handling of I. Adjust setting/clearing of "alt".
559
2a1bb84c
JB		 5602020-06-26 Jan Beulich <jbeulich@suse.com>
561
562 * i386-dis.c: (print_insn): Avoid straight assignment to
563 priv.orig_sizeflag when processing -M sub-options.
564
8f570d62
JB		 5652020-06-25 Jan Beulich <jbeulich@suse.com>
566
567 * i386-dis.c: Adjust description of J macro.
568 (dis386, x86_64_table, mod_table): Replace J.
569 (putop): Remove handling of J.
570
464dc4af
JB		 5712020-06-25 Jan Beulich <jbeulich@suse.com>
572
573 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
574
589958d6
JB		 5752020-06-25 Jan Beulich <jbeulich@suse.com>
576
577 * i386-dis.c: Adjust description of "LQ" macro.
578 (dis386_twobyte): Use LQ for sysret.
579 (putop): Adjust handling of LQ.
580
39ff0b81
NC		 5812020-06-22 Nelson Chu <nelson.chu@sifive.com>
582
583 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
584 * riscv-dis.c: Include elfxx-riscv.h.
585
d27c357a
JB		 5862020-06-18 H.J. Lu <hongjiu.lu@intel.com>
587
588 * i386-dis.c (prefix_table): Revert the last vmgexit change.
589
6fde587f
CL		 5902020-06-17 Lili Cui <lili.cui@intel.com>
591
592 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
593
efe30057
L		 5942020-06-14 H.J. Lu <hongjiu.lu@intel.com>
595
596 PR gas/26115
597 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
598 * i386-opc.tbl: Likewise.
599 * i386-tbl.h: Regenerated.
600
d8af286f
NC		 6012020-06-12 Nelson Chu <nelson.chu@sifive.com>
602
603 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
604
14962256
AC		 6052020-06-11 Alex Coplan <alex.coplan@arm.com>
606
607 * aarch64-opc.c (SYSREG): New macro for describing system registers.
608 (SR_CORE): Likewise.
609 (SR_FEAT): Likewise.
610 (SR_RNG): Likewise.
611 (SR_V8_1): Likewise.
612 (SR_V8_2): Likewise.
613 (SR_V8_3): Likewise.
614 (SR_V8_4): Likewise.
615 (SR_PAN): Likewise.
616 (SR_RAS): Likewise.
617 (SR_SSBS): Likewise.
618 (SR_SVE): Likewise.
619 (SR_ID_PFR2): Likewise.
620 (SR_PROFILE): Likewise.
621 (SR_MEMTAG): Likewise.
622 (SR_SCXTNUM): Likewise.
623 (aarch64_sys_regs): Refactor to store feature information in the table.
624 (aarch64_sys_reg_supported_p): Collapse logic for system registers
625 that now describe their own features.
626 (aarch64_pstatefield_supported_p): Likewise.
627
f9630fa6
L		 6282020-06-09 H.J. Lu <hongjiu.lu@intel.com>
629
630 * i386-dis.c (prefix_table): Fix a typo in comments.
631
73239888
JB		 6322020-06-09 Jan Beulich <jbeulich@suse.com>
633
634 * i386-dis.c (rex_ignored): Delete.
635 (ckprefix): Drop rex_ignored initialization.
636 (get_valid_dis386): Drop setting of rex_ignored.
637 (print_insn): Drop checking of rex_ignored. Don't record data
638 size prefix as used with VEX-and-alike encodings.
639
18897deb
JB		 6402020-06-09 Jan Beulich <jbeulich@suse.com>
641
642 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
643 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
644 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
645 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
646 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
647 VEX_0F12, and VEX_0F16.
648 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
649 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
650 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
651 from movlps and movhlps. New MOD_0F12_PREFIX_2,
652 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
653 MOD_VEX_0F16_PREFIX_2 entries.
654
97e6786a
JB		 6552020-06-09 Jan Beulich <jbeulich@suse.com>
656
657 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
658 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
659 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
660 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
661 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
662 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
663 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
664 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
665 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
666 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
667 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
668 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
669 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
670 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
671 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
672 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
673 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
674 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
675 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
676 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
677 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
678 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
679 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
680 EVEX_W_0FC6_P_2): Delete.
681 (print_insn): Add EVEX.W vs embedded prefix consistency check
682 to prefix validation.
683 * i386-dis-evex.h (evex_table): Don't further descend for
684 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
685 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
686 and 0F2B.
687 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
688 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
689 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
690 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
691 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
692 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
693 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
694 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
695 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
696 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
697 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
698 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
699 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
700 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
701 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
702 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
703 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
704 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
705 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
706 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
707 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
708 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
709 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
710 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
711 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
712 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
713 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
714
bf926894
JB		 7152020-06-09 Jan Beulich <jbeulich@suse.com>
716
717 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
718 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
719 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
720 vmovmskpX.
721 (print_insn): Drop pointless check against bad_opcode. Split
722 prefix validation into legacy and VEX-and-alike parts.
723 (putop): Re-work 'X' macro handling.
724
a5aaedb9
JB		 7252020-06-09 Jan Beulich <jbeulich@suse.com>
726
727 * i386-dis.c (MOD_0F51): Rename to ...
728 (MOD_0F50): ... this.
729
26417f19
AC		 7302020-06-08 Alex Coplan <alex.coplan@arm.com>
731
732 * arm-dis.c (arm_opcodes): Add dfb.
733 (thumb32_opcodes): Add dfb.
734
8a6fb3f9
JB		 7352020-06-08 Jan Beulich <jbeulich@suse.com>
736
737 * i386-opc.h (reg_entry): Const-qualify reg_name field.
738
1424c35d
AM		 7392020-06-06 Alan Modra <amodra@gmail.com>
740
741 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
742
d3d1cc7b
AM		 7432020-06-05 Alan Modra <amodra@gmail.com>
744
745 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
746 size is large enough.
747
d8740be1
JM		 7482020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
749
750 * disassemble.c (disassemble_init_for_target): Set endian_code for
751 bpf targets.
752 * bpf-desc.c: Regenerate.
753 * bpf-opc.c: Likewise.
754 * bpf-dis.c: Likewise.
755
e9bffec9
JM		 7562020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
757
758 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
759 (cgen_put_insn_value): Likewise.
760 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
761 * cgen-dis.in (print_insn): Likewise.
762 * cgen-ibld.in (insert_1): Likewise.
763 (insert_1): Likewise.
764 (insert_insn_normal): Likewise.
765 (extract_1): Likewise.
766 * bpf-dis.c: Regenerate.
767 * bpf-ibld.c: Likewise.
768 * bpf-ibld.c: Likewise.
769 * cgen-dis.in: Likewise.
770 * cgen-ibld.in: Likewise.
771 * cgen-opc.c: Likewise.
772 * epiphany-dis.c: Likewise.
773 * epiphany-ibld.c: Likewise.
774 * fr30-dis.c: Likewise.
775 * fr30-ibld.c: Likewise.
776 * frv-dis.c: Likewise.
777 * frv-ibld.c: Likewise.
778 * ip2k-dis.c: Likewise.
779 * ip2k-ibld.c: Likewise.
780 * iq2000-dis.c: Likewise.
781 * iq2000-ibld.c: Likewise.
782 * lm32-dis.c: Likewise.
783 * lm32-ibld.c: Likewise.
784 * m32c-dis.c: Likewise.
785 * m32c-ibld.c: Likewise.
786 * m32r-dis.c: Likewise.
787 * m32r-ibld.c: Likewise.
788 * mep-dis.c: Likewise.
789 * mep-ibld.c: Likewise.
790 * mt-dis.c: Likewise.
791 * mt-ibld.c: Likewise.
792 * or1k-dis.c: Likewise.
793 * or1k-ibld.c: Likewise.
794 * xc16x-dis.c: Likewise.
795 * xc16x-ibld.c: Likewise.
796 * xstormy16-dis.c: Likewise.
797 * xstormy16-ibld.c: Likewise.
798
b3db6d07
JM		 7992020-06-04 Jose E. Marchesi <jemarch@gnu.org>
800
801 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
802 (print_insn_): Handle instruction endian.
803 * bpf-dis.c: Regenerate.
804 * bpf-desc.c: Regenerate.
805 * epiphany-dis.c: Likewise.
806 * epiphany-desc.c: Likewise.
807 * fr30-dis.c: Likewise.
808 * fr30-desc.c: Likewise.
809 * frv-dis.c: Likewise.
810 * frv-desc.c: Likewise.
811 * ip2k-dis.c: Likewise.
812 * ip2k-desc.c: Likewise.
813 * iq2000-dis.c: Likewise.
814 * iq2000-desc.c: Likewise.
815 * lm32-dis.c: Likewise.
816 * lm32-desc.c: Likewise.
817 * m32c-dis.c: Likewise.
818 * m32c-desc.c: Likewise.
819 * m32r-dis.c: Likewise.
820 * m32r-desc.c: Likewise.
821 * mep-dis.c: Likewise.
822 * mep-desc.c: Likewise.
823 * mt-dis.c: Likewise.
824 * mt-desc.c: Likewise.
825 * or1k-dis.c: Likewise.
826 * or1k-desc.c: Likewise.
827 * xc16x-dis.c: Likewise.
828 * xc16x-desc.c: Likewise.
829 * xstormy16-dis.c: Likewise.
830 * xstormy16-desc.c: Likewise.
831
4ee4189f
NC		 8322020-06-03 Nick Clifton <nickc@redhat.com>
833
834 * po/sr.po: Updated Serbian translation.
835
44730156
NC		 8362020-06-03 Nelson Chu <nelson.chu@sifive.com>
837
838 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
839 (riscv_get_priv_spec_class): Likewise.
840
3c3d0376
AM		 8412020-06-01 Alan Modra <amodra@gmail.com>
842
843 * bpf-desc.c: Regenerate.
844
78c1c354
JM		 8452020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
846 David Faust <david.faust@oracle.com>
847
848 * bpf-desc.c: Regenerate.
849 * bpf-opc.h: Likewise.
850 * bpf-opc.c: Likewise.
851 * bpf-dis.c: Likewise.
852
efcf5fb5
AM		 8532020-05-28 Alan Modra <amodra@gmail.com>
854
855 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
856 values.
857
ab382d64
AM		 8582020-05-28 Alan Modra <amodra@gmail.com>
859
860 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
861 immediates.
862 (print_insn_ns32k): Revert last change.
863
151f5de4
NC		 8642020-05-28 Nick Clifton <nickc@redhat.com>
865
866 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
867 static.
868
25e1eca8
SL		 8692020-05-26 Sandra Loosemore <sandra@codesourcery.com>
870
871 Fix extraction of signed constants in nios2 disassembler (again).
872
873 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
874 extractions of signed fields.
875
57b17940
SSF		 8762020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
877
878 * s390-opc.txt: Relocate vector load/store instructions with
879 additional alignment parameter and change architecture level
880 constraint from z14 to z13.
881
d96bf37b
AM		 8822020-05-21 Alan Modra <amodra@gmail.com>
883
884 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
885 * sparc-dis.c: Likewise.
886 * tic4x-dis.c: Likewise.
887 * xtensa-dis.c: Likewise.
888 * bpf-desc.c: Regenerate.
889 * epiphany-desc.c: Regenerate.
890 * fr30-desc.c: Regenerate.
891 * frv-desc.c: Regenerate.
892 * ip2k-desc.c: Regenerate.
893 * iq2000-desc.c: Regenerate.
894 * lm32-desc.c: Regenerate.
895 * m32c-desc.c: Regenerate.
896 * m32r-desc.c: Regenerate.
897 * mep-asm.c: Regenerate.
898 * mep-desc.c: Regenerate.
899 * mt-desc.c: Regenerate.
900 * or1k-desc.c: Regenerate.
901 * xc16x-desc.c: Regenerate.
902 * xstormy16-desc.c: Regenerate.
903
8f595e9b
NC		 9042020-05-20 Nelson Chu <nelson.chu@sifive.com>
905
906 * riscv-opc.c (riscv_ext_version_table): The table used to store
907 all information about the supported spec and the corresponding ISA
908 versions. Currently, only Zicsr is supported to verify the
909 correctness of Z sub extension settings. Others will be supported
910 in the future patches.
911 (struct isa_spec_t, isa_specs): List for all supported ISA spec
912 classes and the corresponding strings.
913 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
914 spec class by giving a ISA spec string.
915 * riscv-opc.c (struct priv_spec_t): New structure.
916 (struct priv_spec_t priv_specs): List for all supported privilege spec
917 classes and the corresponding strings.
918 (riscv_get_priv_spec_class): New function. Get the corresponding
919 privilege spec class by giving a spec string.
920 (riscv_get_priv_spec_name): New function. Get the corresponding
921 privilege spec string by giving a CSR version class.
922 * riscv-dis.c: Updated since DECLARE_CSR is changed.
923 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
924 according to the chosen version. Build a hash table riscv_csr_hash to
925 store the valid CSR for the chosen pirv verison. Dump the direct
926 CSR address rather than it's name if it is invalid.
927 (parse_riscv_dis_option_without_args): New function. Parse the options
928 without arguments.
929 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
930 parse the options without arguments first, and then handle the options
931 with arguments. Add the new option -Mpriv-spec, which has argument.
932 * riscv-dis.c (print_riscv_disassembler_options): Add description
933 about the new OBJDUMP option.
934
3d205eb4
PB		 9352020-05-19 Peter Bergner <bergner@linux.ibm.com>
936
937 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
938 WC values on POWER10 sync, dcbf and wait instructions.
939 (insert_pl, extract_pl): New functions.
940 (L2OPT, LS, WC): Use insert_ls and extract_ls.
941 (LS3): New , 3-bit L for sync.
942 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
943 (SC2, PL): New, 2-bit SC and PL for sync and wait.
944 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
945 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
946 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
947 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
948 <wait>: Enable PL operand on POWER10.
949 <dcbf>: Enable L3OPT operand on POWER10.
950 <sync>: Enable SC2 operand on POWER10.
951
a501eb44
SH		 9522020-05-19 Stafford Horne <shorne@gmail.com>
953
954 PR 25184
955 * or1k-asm.c: Regenerate.
956 * or1k-desc.c: Regenerate.
957 * or1k-desc.h: Regenerate.
958 * or1k-dis.c: Regenerate.
959 * or1k-ibld.c: Regenerate.
960 * or1k-opc.c: Regenerate.
961 * or1k-opc.h: Regenerate.
962 * or1k-opinst.c: Regenerate.
963
3b646889
AM		 9642020-05-11 Alan Modra <amodra@gmail.com>
965
966 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
967 xsmaxcqp, xsmincqp.
968
9cc4ce88
AM		 9692020-05-11 Alan Modra <amodra@gmail.com>
970
971 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
972 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
973
5d57bc3f
AM		 9742020-05-11 Alan Modra <amodra@gmail.com>
975
976 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
977
66ef5847
AM		 9782020-05-11 Alan Modra <amodra@gmail.com>
979
980 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
981 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
982
4f3e9537
PB		 9832020-05-11 Peter Bergner <bergner@linux.ibm.com>
984
985 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
986 mnemonics.
987
ec40e91c
AM		 9882020-05-11 Alan Modra <amodra@gmail.com>
989
990 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
991 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
992 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
993 (prefix_opcodes): Add xxeval.
994
d7e97a76
AM		 9952020-05-11 Alan Modra <amodra@gmail.com>
996
997 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
998 xxgenpcvwm, xxgenpcvdm.
999
fdefed7c
AM		 10002020-05-11 Alan Modra <amodra@gmail.com>
1001
1002 * ppc-opc.c (MP, VXVAM_MASK): Define.
1003 (VXVAPS_MASK): Use VXVA_MASK.
1004 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
1005 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
1006 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
1007 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
1008
aa3c112f
AM		 10092020-05-11 Alan Modra <amodra@gmail.com>
1010 Peter Bergner <bergner@linux.ibm.com>
1011
1012 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
1013 New functions.
1014 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
1015 YMSK2, XA6a, XA6ap, XB6a entries.
1016 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
1017 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
1018 (PPCVSX4): Define.
1019 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
1020 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
1021 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
1022 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
1023 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
1024 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
1025 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
1026 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
1027 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
1028 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
1029 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
1030 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
1031 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
1032 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
1033
6edbfd3b
AM		 10342020-05-11 Alan Modra <amodra@gmail.com>
1035
1036 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
1037 (insert_xts, extract_xts): New functions.
1038 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
1039 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
1040 (VXRC_MASK, VXSH_MASK): Define.
1041 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
1042 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
1043 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
1044 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
1045 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
1046 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
1047 xxblendvh, xxblendvw, xxblendvd, xxpermx.
1048
c7d7aea2
AM		 10492020-05-11 Alan Modra <amodra@gmail.com>
1050
1051 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
1052 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
1053 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
1054 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
1055 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
1056
94ba9882
AM		 10572020-05-11 Alan Modra <amodra@gmail.com>
1058
1059 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
1060 (XTP, DQXP, DQXP_MASK): Define.
1061 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
1062 (prefix_opcodes): Add plxvp and pstxvp.
1063
f4791f1a
AM		 10642020-05-11 Alan Modra <amodra@gmail.com>
1065
1066 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
1067 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
1068 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
1069
3ff0a5ba
PB		 10702020-05-11 Peter Bergner <bergner@linux.ibm.com>
1071
1072 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
1073
afef4fe9
PB		 10742020-05-11 Peter Bergner <bergner@linux.ibm.com>
1075
1076 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
1077 (L1OPT): Define.
1078 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
1079
1224c05d
PB		 10802020-05-11 Peter Bergner <bergner@linux.ibm.com>
1081
1082 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
1083
6bbb0c05
AM		 10842020-05-11 Alan Modra <amodra@gmail.com>
1085
1086 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
1087
7c1f4227
AM		 10882020-05-11 Alan Modra <amodra@gmail.com>
1089
1090 * ppc-dis.c (ppc_opts): Add "power10" entry.
1091 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
1092 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
1093
73199c2b
NC		 10942020-05-11 Nick Clifton <nickc@redhat.com>
1095
1096 * po/fr.po: Updated French translation.
1097
09c1e68a
AC		 10982020-04-30 Alex Coplan <alex.coplan@arm.com>
1099
1100 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
1101 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
1102 (operand_general_constraint_met_p): validate
1103 AARCH64_OPND_UNDEFINED.
1104 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
1105 for FLD_imm16_2.
1106 * aarch64-asm-2.c: Regenerated.
1107 * aarch64-dis-2.c: Regenerated.
1108 * aarch64-opc-2.c: Regenerated.
1109
9654d51a
NC		 11102020-04-29 Nick Clifton <nickc@redhat.com>
1111
1112 PR 22699
1113 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
1114 and SETRC insns.
1115
c2e71e57
NC		 11162020-04-29 Nick Clifton <nickc@redhat.com>
1117
1118 * po/sv.po: Updated Swedish translation.
1119
5c936ef5
NC		 11202020-04-29 Nick Clifton <nickc@redhat.com>
1121
1122 PR 22699
1123 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
1124 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
1125 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
1126 IMM0_8U case.
1127
bb2a1453
AS		 11282020-04-21 Andreas Schwab <schwab@linux-m68k.org>
1129
1130 PR 25848
1131 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
1132 cmpi only on m68020up and cpu32.
1133
c2e5c986
SD		 11342020-04-20 Sudakshina Das <sudi.das@arm.com>
1135
1136 * aarch64-asm.c (aarch64_ins_none): New.
1137 * aarch64-asm.h (ins_none): New declaration.
1138 * aarch64-dis.c (aarch64_ext_none): New.
1139 * aarch64-dis.h (ext_none): New declaration.
1140 * aarch64-opc.c (aarch64_print_operand): Update case for
1141 AARCH64_OPND_BARRIER_PSB.
1142 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
1143 (AARCH64_OPERANDS): Update inserter/extracter for
1144 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
1145 * aarch64-asm-2.c: Regenerated.
1146 * aarch64-dis-2.c: Regenerated.
1147 * aarch64-opc-2.c: Regenerated.
1148
8a6e1d1d
SD		 11492020-04-20 Sudakshina Das <sudi.das@arm.com>
1150
1151 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
1152 (aarch64_feature_ras, RAS): Likewise.
1153 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
1154 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
1155 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
1156 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
1157 * aarch64-asm-2.c: Regenerated.
1158 * aarch64-dis-2.c: Regenerated.
1159 * aarch64-opc-2.c: Regenerated.
1160
e409955d
FS		 11612020-04-17 Fredrik Strupe <fredrik@strupe.net>
1162
1163 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
1164 (print_insn_neon): Support disassembly of conditional
1165 instructions.
1166
c54a9b56
DF		 11672020-02-16 David Faust <david.faust@oracle.com>
1168
1169 * bpf-desc.c: Regenerate.
1170 * bpf-desc.h: Likewise.
1171 * bpf-opc.c: Regenerate.
1172 * bpf-opc.h: Likewise.
1173
bb651e8b
CL		 11742020-04-07 Lili Cui <lili.cui@intel.com>
1175
1176 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
1177 (prefix_table): New instructions (see prefixes above).
1178 (rm_table): Likewise
1179 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
1180 CPU_ANY_TSXLDTRK_FLAGS.
1181 (cpu_flags): Add CpuTSXLDTRK.
1182 * i386-opc.h (enum): Add CpuTSXLDTRK.
1183 (i386_cpu_flags): Add cputsxldtrk.
1184 * i386-opc.tbl: Add XSUSPLDTRK insns.
1185 * i386-init.h: Regenerate.
1186 * i386-tbl.h: Likewise.
1187
4b27d27c
L		 11882020-04-02 Lili Cui <lili.cui@intel.com>
1189
1190 * i386-dis.c (prefix_table): New instructions serialize.
1191 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
1192 CPU_ANY_SERIALIZE_FLAGS.
1193 (cpu_flags): Add CpuSERIALIZE.
1194 * i386-opc.h (enum): Add CpuSERIALIZE.
1195 (i386_cpu_flags): Add cpuserialize.
1196 * i386-opc.tbl: Add SERIALIZE insns.
1197 * i386-init.h: Regenerate.
1198 * i386-tbl.h: Likewise.
1199
832a5807
AM		 12002020-03-26 Alan Modra <amodra@gmail.com>
1201
1202 * disassemble.h (opcodes_assert): Declare.
1203 (OPCODES_ASSERT): Define.
1204 * disassemble.c: Don't include assert.h. Include opintl.h.
1205 (opcodes_assert): New function.
1206 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
1207 (bfd_h8_disassemble): Reduce size of data array. Correctly
1208 calculate maxlen. Omit insn decoding when insn length exceeds
1209 maxlen. Exit from nibble loop when looking for E, before
1210 accessing next data byte. Move processing of E outside loop.
1211 Replace tests of maxlen in loop with assertions.
1212
4c4addbe
AM		 12132020-03-26 Alan Modra <amodra@gmail.com>
1214
1215 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
1216
a18cd0ca
AM		 12172020-03-25 Alan Modra <amodra@gmail.com>
1218
1219 * z80-dis.c (suffix): Init mybuf.
1220
57cb32b3
AM		 12212020-03-22 Alan Modra <amodra@gmail.com>
1222
1223 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
1224 successflly read from section.
1225
beea5cc1
AM		 12262020-03-22 Alan Modra <amodra@gmail.com>
1227
1228 * arc-dis.c (find_format): Use ISO C string concatenation rather
1229 than line continuation within a string. Don't access needs_limm
1230 before testing opcode != NULL.
1231
03704c77
AM		 12322020-03-22 Alan Modra <amodra@gmail.com>
1233
1234 * ns32k-dis.c (print_insn_arg): Update comment.
1235 (print_insn_ns32k): Reduce size of index_offset array, and
1236 initialize, passing -1 to print_insn_arg for args that are not
1237 an index. Don't exit arg loop early. Abort on bad arg number.
1238
d1023b5d
AM		 12392020-03-22 Alan Modra <amodra@gmail.com>
1240
1241 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
1242 * s12z-opc.c: Formatting.
1243 (operands_f): Return an int.
1244 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
1245 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
1246 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
1247 (exg_sex_discrim): Likewise.
1248 (create_immediate_operand, create_bitfield_operand),
1249 (create_register_operand_with_size, create_register_all_operand),
1250 (create_register_all16_operand, create_simple_memory_operand),
1251 (create_memory_operand, create_memory_auto_operand): Don't
1252 segfault on malloc failure.
1253 (z_ext24_decode): Return an int status, negative on fail, zero
1254 on success.
1255 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
1256 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
1257 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
1258 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
1259 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
1260 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
1261 (loop_primitive_decode, shift_decode, psh_pul_decode),
1262 (bit_field_decode): Similarly.
1263 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
1264 to return value, update callers.
1265 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
1266 Don't segfault on NULL operand.
1267 (decode_operation): Return OP_INVALID on first fail.
1268 (decode_s12z): Check all reads, returning -1 on fail.
1269
340f3ac8
AM		 12702020-03-20 Alan Modra <amodra@gmail.com>
1271
1272 * metag-dis.c (print_insn_metag): Don't ignore status from
1273 read_memory_func.
1274
fe90ae8a
AM		 12752020-03-20 Alan Modra <amodra@gmail.com>
1276
1277 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
1278 Initialize parts of buffer not written when handling a possible
1279 2-byte insn at end of section. Don't attempt decoding of such
1280 an insn by the 4-byte machinery.
1281
833d919c
AM		 12822020-03-20 Alan Modra <amodra@gmail.com>
1283
1284 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
1285 partially filled buffer. Prevent lookup of 4-byte insns when
1286 only VLE 2-byte insns are possible due to section size. Print
1287 ".word" rather than ".long" for 2-byte leftovers.
1288
327ef784
NC		 12892020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
1290
1291 PR 25641
1292 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
1293
1673df32
JB		 12942020-03-13 Jan Beulich <jbeulich@suse.com>
1295
1296 * i386-dis.c (X86_64_0D): Rename to ...
1297 (X86_64_0E): ... this.
1298
384f3689
L		 12992020-03-09 H.J. Lu <hongjiu.lu@intel.com>
1300
1301 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
1302 * Makefile.in: Regenerated.
1303
865e2027
JB		 13042020-03-09 Jan Beulich <jbeulich@suse.com>
1305
1306 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
1307 3-operand pseudos.
1308 * i386-tbl.h: Re-generate.
1309
2f13234b
JB		 13102020-03-09 Jan Beulich <jbeulich@suse.com>
1311
1312 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
1313 vprot*, vpsha*, and vpshl*.
1314 * i386-tbl.h: Re-generate.
1315
3fabc179
JB		 13162020-03-09 Jan Beulich <jbeulich@suse.com>
1317
1318 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
1319 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
1320 * i386-tbl.h: Re-generate.
1321
3677e4c1
JB		 13222020-03-09 Jan Beulich <jbeulich@suse.com>
1323
1324 * i386-gen.c (set_bitfield): Ignore zero-length field names.
1325 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
1326 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
1327 * i386-tbl.h: Re-generate.
1328
4c4898e8
JB		 13292020-03-09 Jan Beulich <jbeulich@suse.com>
1330
1331 * i386-gen.c (struct template_arg, struct template_instance,
1332 struct template_param, struct template, templates,
1333 parse_template, expand_templates): New.
1334 (process_i386_opcodes): Various local variables moved to
1335 expand_templates. Call parse_template and expand_templates.
1336 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
1337 * i386-tbl.h: Re-generate.
1338
bc49bfd8
JB		 13392020-03-06 Jan Beulich <jbeulich@suse.com>
1340
1341 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
1342 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
1343 register and memory source templates. Replace VexW= by VexW*
1344 where applicable.
1345 * i386-tbl.h: Re-generate.
1346
4873e243
JB		 13472020-03-06 Jan Beulich <jbeulich@suse.com>
1348
1349 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
1350 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
1351 * i386-tbl.h: Re-generate.
1352
672a349b
JB		 13532020-03-06 Jan Beulich <jbeulich@suse.com>
1354
1355 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
1356 * i386-tbl.h: Re-generate.
1357
4ed21b58
JB		 13582020-03-06 Jan Beulich <jbeulich@suse.com>
1359
1360 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
1361 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
1362 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
1363 VexW0 on SSE2AVX variants.
1364 (vmovq): Drop NoRex64 from XMM/XMM variants.
1365 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
1366 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
1367 applicable use VexW0.
1368 * i386-tbl.h: Re-generate.
1369
643bb870
JB		 13702020-03-06 Jan Beulich <jbeulich@suse.com>
1371
1372 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
1373 * i386-opc.h (Rex64): Delete.
1374 (struct i386_opcode_modifier): Remove rex64 field.
1375 * i386-opc.tbl (crc32): Drop Rex64.
1376 Replace Rex64 with Size64 everywhere else.
1377 * i386-tbl.h: Re-generate.
1378
a23b33b3
JB		 13792020-03-06 Jan Beulich <jbeulich@suse.com>
1380
1381 * i386-dis.c (OP_E_memory): Exclude recording of used address
1382 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
1383 addressed memory operands for MPX insns.
1384
a0497384
JB		 13852020-03-06 Jan Beulich <jbeulich@suse.com>
1386
1387 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
1388 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
1389 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
1390 (ptwrite): Split into non-64-bit and 64-bit forms.
1391 * i386-tbl.h: Re-generate.
1392
b630c145
JB		 13932020-03-06 Jan Beulich <jbeulich@suse.com>
1394
1395 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
1396 template.
1397 * i386-tbl.h: Re-generate.
1398
a847e322
JB		 13992020-03-04 Jan Beulich <jbeulich@suse.com>
1400
1401 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
1402 (prefix_table): Move vmmcall here. Add vmgexit.
1403 (rm_table): Replace vmmcall entry by prefix_table[] escape.
1404 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
1405 (cpu_flags): Add CpuSEV_ES entry.
1406 * i386-opc.h (CpuSEV_ES): New.
1407 (union i386_cpu_flags): Add cpusev_es field.
1408 * i386-opc.tbl (vmgexit): New.
1409 * i386-init.h, i386-tbl.h: Re-generate.
1410
3cd7f3e3
L		 14112020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1412
1413 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
1414 with MnemonicSize.
1415 * i386-opc.h (IGNORESIZE): New.
1416 (DEFAULTSIZE): Likewise.
1417 (IgnoreSize): Removed.
1418 (DefaultSize): Likewise.
1419 (MnemonicSize): New.
1420 (i386_opcode_modifier): Replace ignoresize/defaultsize with
1421 mnemonicsize.
1422 * i386-opc.tbl (IgnoreSize): New.
1423 (DefaultSize): Likewise.
1424 * i386-tbl.h: Regenerated.
1425
b8ba1385
SB		 14262020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1427
1428 PR 25627
1429 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
1430 instructions.
1431
10d97a0f
L		 14322020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1433
1434 PR gas/25622
1435 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
1436 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
1437 * i386-tbl.h: Regenerated.
1438
dc1e8a47
AM		 14392020-02-26 Alan Modra <amodra@gmail.com>
1440
1441 * aarch64-asm.c: Indent labels correctly.
1442 * aarch64-dis.c: Likewise.
1443 * aarch64-gen.c: Likewise.
1444 * aarch64-opc.c: Likewise.
1445 * alpha-dis.c: Likewise.
1446 * i386-dis.c: Likewise.
1447 * nds32-asm.c: Likewise.
1448 * nfp-dis.c: Likewise.
1449 * visium-dis.c: Likewise.
1450
265b4673
CZ		 14512020-02-25 Claudiu Zissulescu <claziss@gmail.com>
1452
1453 * arc-regs.h (int_vector_base): Make it available for all ARC
1454 CPUs.
1455
bd0cf5a6
NC		 14562020-02-20 Nelson Chu <nelson.chu@sifive.com>
1457
1458 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
1459 changed.
1460
fa164239
JW		 14612020-02-19 Nelson Chu <nelson.chu@sifive.com>
1462
1463 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
1464 c.mv/c.li if rs1 is zero.
1465
272a84b1
L		 14662020-02-17 H.J. Lu <hongjiu.lu@intel.com>
1467
1468 * i386-gen.c (cpu_flag_init): Replace CpuABM with
1469 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
1470 CPU_POPCNT_FLAGS.
1471 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
1472 * i386-opc.h (CpuABM): Removed.
1473 (CpuPOPCNT): New.
1474 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
1475 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
1476 popcnt. Remove CpuABM from lzcnt.
1477 * i386-init.h: Regenerated.
1478 * i386-tbl.h: Likewise.
1479
1f730c46
JB		 14802020-02-17 Jan Beulich <jbeulich@suse.com>
1481
1482 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
1483 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
1484 VexW1 instead of open-coding them.
1485 * i386-tbl.h: Re-generate.
1486
c8f8eebc
JB		 14872020-02-17 Jan Beulich <jbeulich@suse.com>
1488
1489 * i386-opc.tbl (AddrPrefixOpReg): Define.
1490 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
1491 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
1492 templates. Drop NoRex64.
1493 * i386-tbl.h: Re-generate.
1494
b9915cbc
JB		 14952020-02-17 Jan Beulich <jbeulich@suse.com>
1496
1497 PR gas/6518
1498 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1499 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
1500 into Intel syntax instance (with Unpsecified) and AT&T one
1501 (without).
1502 (vcvtneps2bf16): Likewise, along with folding the two so far
1503 separate ones.
1504 * i386-tbl.h: Re-generate.
1505
ce504911
L		 15062020-02-16 H.J. Lu <hongjiu.lu@intel.com>
1507
1508 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
1509 CPU_ANY_SSE4A_FLAGS.
1510
dabec65d
AM		 15112020-02-17 Alan Modra <amodra@gmail.com>
1512
1513 * i386-gen.c (cpu_flag_init): Correct last change.
1514
af5c13b0
L		 15152020-02-16 H.J. Lu <hongjiu.lu@intel.com>
1516
1517 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
1518 CPU_ANY_SSE4_FLAGS.
1519
6867aac0
L		 15202020-02-14 H.J. Lu <hongjiu.lu@intel.com>
1521
1522 * i386-opc.tbl (movsx): Remove Intel syntax comments.
1523 (movzx): Likewise.
1524
65fca059
JB		 15252020-02-14 Jan Beulich <jbeulich@suse.com>
1526
1527 PR gas/25438
1528 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
1529 destination for Cpu64-only variant.
1530 (movzx): Fold patterns.
1531 * i386-tbl.h: Re-generate.
1532
7deea9aa
JB		 15332020-02-13 Jan Beulich <jbeulich@suse.com>
1534
1535 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
1536 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
1537 CPU_ANY_SSE4_FLAGS entry.
1538 * i386-init.h: Re-generate.
1539
6c0946d0
JB		 15402020-02-12 Jan Beulich <jbeulich@suse.com>
1541
1542 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
1543 with Unspecified, making the present one AT&T syntax only.
1544 * i386-tbl.h: Re-generate.
1545
ddb56fe6
JB		 15462020-02-12 Jan Beulich <jbeulich@suse.com>
1547
1548 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
1549 * i386-tbl.h: Re-generate.
1550
5990e377
JB		 15512020-02-12 Jan Beulich <jbeulich@suse.com>
1552
1553 PR gas/24546
1554 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
1555 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
1556 Amd64 and Intel64 templates.
1557 (call, jmp): Likewise for far indirect variants. Dro
1558 Unspecified.
1559 * i386-tbl.h: Re-generate.
1560
50128d0c
JB		 15612020-02-11 Jan Beulich <jbeulich@suse.com>
1562
1563 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
1564 * i386-opc.h (ShortForm): Delete.
1565 (struct i386_opcode_modifier): Remove shortform field.
1566 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
1567 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
1568 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
1569 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
1570 Drop ShortForm.
1571 * i386-tbl.h: Re-generate.
1572
1e05b5c4
JB		 15732020-02-11 Jan Beulich <jbeulich@suse.com>
1574
1575 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
1576 fucompi): Drop ShortForm from operand-less templates.
1577 * i386-tbl.h: Re-generate.
1578
2f5dd314
AM		 15792020-02-11 Alan Modra <amodra@gmail.com>
1580
1581 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
1582 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
1583 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
1584 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
1585 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
1586
5aae9ae9
MM		 15872020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
1588
1589 * arm-dis.c (print_insn_cde): Define 'V' parse character.
1590 (cde_opcodes): Add VCX* instructions.
1591
4934a27c
MM		 15922020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
1593 Matthew Malcomson <matthew.malcomson@arm.com>
1594
1595 * arm-dis.c (struct cdeopcode32): New.
1596 (CDE_OPCODE): New macro.
1597 (cde_opcodes): New disassembly table.
1598 (regnames): New option to table.
1599 (cde_coprocs): New global variable.
1600 (print_insn_cde): New
1601 (print_insn_thumb32): Use print_insn_cde.
1602 (parse_arm_disassembler_options): Parse coprocN args.
1603
4b5aaf5f
L		 16042020-02-10 H.J. Lu <hongjiu.lu@intel.com>
1605
1606 PR gas/25516
1607 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
1608 with ISA64.
1609 * i386-opc.h (AMD64): Removed.
1610 (Intel64): Likewose.
1611 (AMD64): New.
1612 (INTEL64): Likewise.
1613 (INTEL64ONLY): Likewise.
1614 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
1615 * i386-opc.tbl (Amd64): New.
1616 (Intel64): Likewise.
1617 (Intel64Only): Likewise.
1618 Replace AMD64 with Amd64. Update sysenter/sysenter with
1619 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
1620 * i386-tbl.h: Regenerated.
1621
9fc0b501
SB		 16222020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
1623
1624 PR 25469
1625 * z80-dis.c: Add support for GBZ80 opcodes.
1626
c5d7be0c
AM		 16272020-02-04 Alan Modra <amodra@gmail.com>
1628
1629 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
1630
44e4546f
AM		 16312020-02-03 Alan Modra <amodra@gmail.com>
1632
1633 * m32c-ibld.c: Regenerate.
1634
b2b1453a
AM		 16352020-02-01 Alan Modra <amodra@gmail.com>
1636
1637 * frv-ibld.c: Regenerate.
1638
4102be5c
JB		 16392020-01-31 Jan Beulich <jbeulich@suse.com>
1640
1641 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
1642 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
1643 (OP_E_memory): Replace xmm_mdq_mode case label by
1644 vex_scalar_w_dq_mode one.
1645 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
1646
825bd36c
JB		 16472020-01-31 Jan Beulich <jbeulich@suse.com>
1648
1649 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
1650 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
1651 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
1652 (intel_operand_size): Drop vex_w_dq_mode case label.
1653
c3036ed0
RS		 16542020-01-31 Richard Sandiford <richard.sandiford@arm.com>
1655
1656 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
1657 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
1658
0c115f84
AM		 16592020-01-30 Alan Modra <amodra@gmail.com>
1660
1661 * m32c-ibld.c: Regenerate.
1662
bd434cc4
JM		 16632020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
1664
1665 * bpf-opc.c: Regenerate.
1666
aeab2b26
JB		 16672020-01-30 Jan Beulich <jbeulich@suse.com>
1668
1669 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
1670 (dis386): Use them to replace C2/C3 table entries.
1671 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
1672 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
1673 ones. Use Size64 instead of DefaultSize on Intel64 ones.
1674 * i386-tbl.h: Re-generate.
1675
62b3f548
JB		 16762020-01-30 Jan Beulich <jbeulich@suse.com>
1677
1678 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
1679 forms.
1680 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
1681 DefaultSize.
1682 * i386-tbl.h: Re-generate.
1683
1bd8ae10
AM		 16842020-01-30 Alan Modra <amodra@gmail.com>
1685
1686 * tic4x-dis.c (tic4x_dp): Make unsigned.
1687
bc31405e
L		 16882020-01-27 H.J. Lu <hongjiu.lu@intel.com>
1689 Jan Beulich <jbeulich@suse.com>
1690
1691 PR binutils/25445
1692 * i386-dis.c (MOVSXD_Fixup): New function.
1693 (movsxd_mode): New enum.
1694 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
1695 (intel_operand_size): Handle movsxd_mode.
1696 (OP_E_register): Likewise.
1697 (OP_G): Likewise.
1698 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
1699 register on movsxd. Add movsxd with 16-bit destination register
1700 for AMD64 and Intel64 ISAs.
1701 * i386-tbl.h: Regenerated.
1702
7568c93b
TC		 17032020-01-27 Tamar Christina <tamar.christina@arm.com>
1704
1705 PR 25403
1706 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
1707 * aarch64-asm-2.c: Regenerate
1708 * aarch64-dis-2.c: Likewise.
1709 * aarch64-opc-2.c: Likewise.
1710
c006a730
JB		 17112020-01-21 Jan Beulich <jbeulich@suse.com>
1712
1713 * i386-opc.tbl (sysret): Drop DefaultSize.
1714 * i386-tbl.h: Re-generate.
1715
c906a69a
JB		 17162020-01-21 Jan Beulich <jbeulich@suse.com>
1717
1718 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
1719 Dword.
1720 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
1721 * i386-tbl.h: Re-generate.
1722
26916852
NC		 17232020-01-20 Nick Clifton <nickc@redhat.com>
1724
1725 * po/de.po: Updated German translation.
1726 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1727 * po/uk.po: Updated Ukranian translation.
1728
4d6cbb64
AM		 17292020-01-20 Alan Modra <amodra@gmail.com>
1730
1731 * hppa-dis.c (fput_const): Remove useless cast.
1732
2bddb71a
AM		 17332020-01-20 Alan Modra <amodra@gmail.com>
1734
1735 * arm-dis.c (print_insn_arm): Wrap 'T' value.
1736
1b1bb2c6
NC		 17372020-01-18 Nick Clifton <nickc@redhat.com>
1738
1739 * configure: Regenerate.
1740 * po/opcodes.pot: Regenerate.
1741
ae774686
NC		 17422020-01-18 Nick Clifton <nickc@redhat.com>
1743
1744 Binutils 2.34 branch created.
1745
07f1f3aa
CB		 17462020-01-17 Christian Biesinger <cbiesinger@google.com>
1747
1748 * opintl.h: Fix spelling error (seperate).
1749
42e04b36
L		 17502020-01-17 H.J. Lu <hongjiu.lu@intel.com>
1751
1752 * i386-opc.tbl: Add {vex} pseudo prefix.
1753 * i386-tbl.h: Regenerated.
1754
2da2eaf4
AV		 17552020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1756
1757 PR 25376
1758 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
1759 (neon_opcodes): Likewise.
1760 (select_arm_features): Make sure we enable MVE bits when selecting
1761 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
1762 any architecture.
1763
d0849eed
JB		 17642020-01-16 Jan Beulich <jbeulich@suse.com>
1765
1766 * i386-opc.tbl: Drop stale comment from XOP section.
1767
9cf70a44
JB		 17682020-01-16 Jan Beulich <jbeulich@suse.com>
1769
1770 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
1771 (extractps): Add VexWIG to SSE2AVX forms.
1772 * i386-tbl.h: Re-generate.
1773
4814632e
JB		 17742020-01-16 Jan Beulich <jbeulich@suse.com>
1775
1776 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
1777 Size64 from and use VexW1 on SSE2AVX forms.
1778 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
1779 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
1780 * i386-tbl.h: Re-generate.
1781
aad09917
AM		 17822020-01-15 Alan Modra <amodra@gmail.com>
1783
1784 * tic4x-dis.c (tic4x_version): Make unsigned long.
1785 (optab, optab_special, registernames): New file scope vars.
1786 (tic4x_print_register): Set up registernames rather than
1787 malloc'd registertable.
1788 (tic4x_disassemble): Delete optable and optable_special. Use
1789 optab and optab_special instead. Throw away old optab,
1790 optab_special and registernames when info->mach changes.
1791
7a6bf3be
SB		 17922020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
1793
1794 PR 25377
1795 * z80-dis.c (suffix): Use .db instruction to generate double
1796 prefix.
1797
ca1eaac0
AM		 17982020-01-14 Alan Modra <amodra@gmail.com>
1799
1800 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
1801 values to unsigned before shifting.
1802
1d67fe3b
TT		 18032020-01-13 Thomas Troeger <tstroege@gmx.de>
1804
1805 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1806 flow instructions.
1807 (print_insn_thumb16, print_insn_thumb32): Likewise.
1808 (print_insn): Initialize the insn info.
1809 * i386-dis.c (print_insn): Initialize the insn info fields, and
1810 detect jumps.
1811
5e4f7e05
CZ		 18122012-01-13 Claudiu Zissulescu <claziss@gmail.com>
1813
1814 * arc-opc.c (C_NE): Make it required.
1815
b9fe6b8a
CZ		 18162012-01-13 Claudiu Zissulescu <claziss@gmail.com>
1817
1818 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1819 reserved register name.
1820
90dee485
AM		 18212020-01-13 Alan Modra <amodra@gmail.com>
1822
1823 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1824 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1825
febda64f
AM		 18262020-01-13 Alan Modra <amodra@gmail.com>
1827
1828 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
1829 result of wasm_read_leb128 in a uint64_t and check that bits
1830 are not lost when copying to other locals. Use uint32_t for
1831 most locals. Use PRId64 when printing int64_t.
1832
df08b588
AM		 18332020-01-13 Alan Modra <amodra@gmail.com>
1834
1835 * score-dis.c: Formatting.
1836 * score7-dis.c: Formatting.
1837
b2c759ce
AM		 18382020-01-13 Alan Modra <amodra@gmail.com>
1839
1840 * score-dis.c (print_insn_score48): Use unsigned variables for
1841 unsigned values. Don't left shift negative values.
1842 (print_insn_score32): Likewise.
1843 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1844
5496abe1
AM		 18452020-01-13 Alan Modra <amodra@gmail.com>
1846
1847 * tic4x-dis.c (tic4x_print_register): Remove dead code.
1848
202e762b
AM		 18492020-01-13 Alan Modra <amodra@gmail.com>
1850
1851 * fr30-ibld.c: Regenerate.
1852
7ef412cf
AM		 18532020-01-13 Alan Modra <amodra@gmail.com>
1854
1855 * xgate-dis.c (print_insn): Don't left shift signed value.
1856 (ripBits): Formatting, use 1u.
1857
7f578b95
AM		 18582020-01-10 Alan Modra <amodra@gmail.com>
1859
1860 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1861 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
1862
441af85b
AM		 18632020-01-10 Alan Modra <amodra@gmail.com>
1864
1865 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1866 and XRREG value earlier to avoid a shift with negative exponent.
1867 * m10200-dis.c (disassemble): Similarly.
1868
bce58db4
NC		 18692020-01-09 Nick Clifton <nickc@redhat.com>
1870
1871 PR 25224
1872 * z80-dis.c (ld_ii_ii): Use correct cast.
1873
40c75bc8
SB		 18742020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1875
1876 PR 25224
1877 * z80-dis.c (ld_ii_ii): Use character constant when checking
1878 opcode byte value.
1879
d835a58b
JB		 18802020-01-09 Jan Beulich <jbeulich@suse.com>
1881
1882 * i386-dis.c (SEP_Fixup): New.
1883 (SEP): Define.
1884 (dis386_twobyte): Use it for sysenter/sysexit.
1885 (enum x86_64_isa): Change amd64 enumerator to value 1.
1886 (OP_J): Compare isa64 against intel64 instead of amd64.
1887 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1888 forms.
1889 * i386-tbl.h: Re-generate.
1890
030a2e78
AM		 18912020-01-08 Alan Modra <amodra@gmail.com>
1892
1893 * z8k-dis.c: Include libiberty.h
1894 (instr_data_s): Make max_fetched unsigned.
1895 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1896 Don't exceed byte_info bounds.
1897 (output_instr): Make num_bytes unsigned.
1898 (unpack_instr): Likewise for nibl_count and loop.
1899 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1900 idx unsigned.
1901 * z8k-opc.h: Regenerate.
1902
bb82aefe
SV		 19032020-01-07 Shahab Vahedi <shahab@synopsys.com>
1904
1905 * arc-tbl.h (llock): Use 'LLOCK' as class.
1906 (llockd): Likewise.
1907 (scond): Use 'SCOND' as class.
1908 (scondd): Likewise.
1909 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1910 (scondd): Likewise.
1911
cc6aa1a6
AM		 19122020-01-06 Alan Modra <amodra@gmail.com>
1913
1914 * m32c-ibld.c: Regenerate.
1915
660e62b1
AM		 19162020-01-06 Alan Modra <amodra@gmail.com>
1917
1918 PR 25344
1919 * z80-dis.c (suffix): Don't use a local struct buffer copy.
1920 Peek at next byte to prevent recursion on repeated prefix bytes.
1921 Ensure uninitialised "mybuf" is not accessed.
1922 (print_insn_z80): Don't zero n_fetch and n_used here,..
1923 (print_insn_z80_buf): ..do it here instead.
1924
c9ae58fe
AM		 19252020-01-04 Alan Modra <amodra@gmail.com>
1926
1927 * m32r-ibld.c: Regenerate.
1928
5f57d4ec
AM		 19292020-01-04 Alan Modra <amodra@gmail.com>
1930
1931 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1932
2c5c1196
AM		 19332020-01-04 Alan Modra <amodra@gmail.com>
1934
1935 * crx-dis.c (match_opcode): Avoid shift left of signed value.
1936
2e98c6c5
AM		 19372020-01-04 Alan Modra <amodra@gmail.com>
1938
1939 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1940
567dfba2
JB		 19412020-01-03 Jan Beulich <jbeulich@suse.com>
1942
5437a02a
JB		 1943 * aarch64-tbl.h (aarch64_opcode_table): Use
1944 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1945
19462020-01-03 Jan Beulich <jbeulich@suse.com>
1947
1948 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB		 1949 forms of SUDOT and USDOT.
1950
8c45011a
JB		 19512020-01-03 Jan Beulich <jbeulich@suse.com>
1952
5437a02a 1953 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a
JB		 1954 uzip{1,2}.
1955 * opcodes/aarch64-dis-2.c: Re-generate.
1956
f4950f76
JB		 19572020-01-03 Jan Beulich <jbeulich@suse.com>
1958
5437a02a 1959 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
JB		 1960 FMMLA encoding.
1961 * opcodes/aarch64-dis-2.c: Re-generate.
1962
6655dba2
SB		 19632020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
1964
1965 * z80-dis.c: Add support for eZ80 and Z80 instructions.
1966
b14ce8bf
AM		 19672020-01-01 Alan Modra <amodra@gmail.com>
1968
1969 Update year range in copyright notice of all files.
1970
0b114740 1971For older changes see ChangeLog-2019
3499769a 1972\f
0b114740 1973Copyright (C) 2020 Free Software Foundation, Inc.
3499769a
AM		 1974
1975Copying and distribution of this file, with or without modification,
1976are permitted in any medium without royalty provided the copyright
1977notice and this notice are preserved.
1978
1979Local Variables:
1980mode: change-log
1981left-margin: 8
1982fill-column: 74
1983version-control: never
1984End:
GDB Binutils - Deliverables
This page took 0.803796 seconds and 4 git commands to generate.