projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Regenerate .pot files
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
06647dfd
AM		 12005-03-05 Alan Modra <amodra@bigpond.net.au>
2
3 * po/opcodes.pot: Regenerate.
4
82b829a7
RR		 52005-03-03 Ramana Radhakrishnan <ramana.radhakrishnan@codito.com>
6
06647dfd
AM		 7 * opcodes/arc-dis.c: Add enum a4_decoding_class.
8 (dsmOneArcInst): Use the enum values for the decoding class.
9 Remove redundant case in the switch for decodingClass value 11.
82b829a7 10
c4a530c5
JB		 112005-03-02 Jan Beulich <jbeulich@novell.com>
12
13 * i386-dis.c (print_insn): Suppress lock prefix printing for cr8...15
14 accesses.
15 (OP_C): Consider lock prefix in non-64-bit modes.
16
47d8304e
AM		 172005-02-24 Alan Modra <amodra@bigpond.net.au>
18
19 * cris-dis.c (format_hex): Remove ineffective warning fix.
20 * crx-dis.c (make_instruction): Warning fix.
21 * frv-asm.c: Regenerate.
22
ec36c4a4
NC		 232005-02-23 Nick Clifton <nickc@redhat.com>
24
33b71eeb
NC		 25 * cgen-dis.in: Use bfd_byte for buffers that are passed to
26 read_memory.
06647dfd 27
33b71eeb 28 * ia64-opc.c (locate_opcode_ent): Initialise opval array.
06647dfd 29
ec36c4a4
NC		 30 * crx-dis.c (make_instruction): Move argument structure into inner
31 scope and ensure that all of its fields are initialised before
32 they are used.
33
33b71eeb
NC		 34 * fr30-asm.c: Regenerate.
35 * fr30-dis.c: Regenerate.
36 * frv-asm.c: Regenerate.
37 * frv-dis.c: Regenerate.
38 * ip2k-asm.c: Regenerate.
39 * ip2k-dis.c: Regenerate.
40 * iq2000-asm.c: Regenerate.
41 * iq2000-dis.c: Regenerate.
42 * m32r-asm.c: Regenerate.
43 * m32r-dis.c: Regenerate.
44 * openrisc-asm.c: Regenerate.
45 * openrisc-dis.c: Regenerate.
46 * xstormy16-asm.c: Regenerate.
47 * xstormy16-dis.c: Regenerate.
48
53c9ebc5
AM		 492005-02-22 Alan Modra <amodra@bigpond.net.au>
50
51 * arc-ext.c: Warning fixes.
52 * arc-ext.h: Likewise.
53 * cgen-opc.c: Likewise.
54 * ia64-gen.c: Likewise.
55 * maxq-dis.c: Likewise.
56 * ns32k-dis.c: Likewise.
57 * w65-dis.c: Likewise.
58 * ia64-asmtab.c: Regenerate.
59
610ad19b
AM		 602005-02-22 Alan Modra <amodra@bigpond.net.au>
61
62 * fr30-desc.c: Regenerate.
63 * fr30-desc.h: Regenerate.
64 * fr30-opc.c: Regenerate.
65 * fr30-opc.h: Regenerate.
66 * frv-desc.c: Regenerate.
67 * frv-desc.h: Regenerate.
68 * frv-opc.c: Regenerate.
69 * frv-opc.h: Regenerate.
70 * ip2k-desc.c: Regenerate.
71 * ip2k-desc.h: Regenerate.
72 * ip2k-opc.c: Regenerate.
73 * ip2k-opc.h: Regenerate.
74 * iq2000-desc.c: Regenerate.
75 * iq2000-desc.h: Regenerate.
76 * iq2000-opc.c: Regenerate.
77 * iq2000-opc.h: Regenerate.
78 * m32r-desc.c: Regenerate.
79 * m32r-desc.h: Regenerate.
80 * m32r-opc.c: Regenerate.
81 * m32r-opc.h: Regenerate.
82 * m32r-opinst.c: Regenerate.
83 * openrisc-desc.c: Regenerate.
84 * openrisc-desc.h: Regenerate.
85 * openrisc-opc.c: Regenerate.
86 * openrisc-opc.h: Regenerate.
87 * xstormy16-desc.c: Regenerate.
88 * xstormy16-desc.h: Regenerate.
89 * xstormy16-opc.c: Regenerate.
90 * xstormy16-opc.h: Regenerate.
91
db9db6f2
AM		 922005-02-21 Alan Modra <amodra@bigpond.net.au>
93
94 * Makefile.am: Run "make dep-am"
95 * Makefile.in: Regenerate.
96
bf143b25
NC		 972005-02-15 Nick Clifton <nickc@redhat.com>
98
99 * cgen-dis.in (print_address): Add an ATTRIBUTE_UNUSED to prevent
100 compile time warnings.
101 (print_keyword): Likewise.
102 (default_print_insn): Likewise.
103
104 * fr30-desc.c: Regenerated.
105 * fr30-desc.h: Regenerated.
106 * fr30-dis.c: Regenerated.
107 * fr30-opc.c: Regenerated.
108 * fr30-opc.h: Regenerated.
109 * frv-desc.c: Regenerated.
110 * frv-dis.c: Regenerated.
111 * frv-opc.c: Regenerated.
112 * ip2k-asm.c: Regenerated.
113 * ip2k-desc.c: Regenerated.
114 * ip2k-desc.h: Regenerated.
115 * ip2k-dis.c: Regenerated.
116 * ip2k-opc.c: Regenerated.
117 * ip2k-opc.h: Regenerated.
118 * iq2000-desc.c: Regenerated.
119 * iq2000-dis.c: Regenerated.
120 * iq2000-opc.c: Regenerated.
121 * m32r-asm.c: Regenerated.
122 * m32r-desc.c: Regenerated.
123 * m32r-desc.h: Regenerated.
124 * m32r-dis.c: Regenerated.
125 * m32r-opc.c: Regenerated.
126 * m32r-opc.h: Regenerated.
127 * m32r-opinst.c: Regenerated.
128 * openrisc-desc.c: Regenerated.
129 * openrisc-desc.h: Regenerated.
130 * openrisc-dis.c: Regenerated.
131 * openrisc-opc.c: Regenerated.
132 * openrisc-opc.h: Regenerated.
133 * xstormy16-desc.c: Regenerated.
134 * xstormy16-desc.h: Regenerated.
135 * xstormy16-dis.c: Regenerated.
136 * xstormy16-opc.c: Regenerated.
137 * xstormy16-opc.h: Regenerated.
138
d6098898
L		 1392005-02-14 H.J. Lu <hongjiu.lu@intel.com>
140
141 * dis-buf.c (perror_memory): Use sprintf_vma to print out
142 address.
143
5a84f3e0
NC		 1442005-02-11 Nick Clifton <nickc@redhat.com>
145
bc18c937
NC		 146 * iq2000-asm.c: Regenerate.
147
5a84f3e0
NC		 148 * frv-dis.c: Regenerate.
149
0a40490e
JB		 1502005-02-07 Jim Blandy <jimb@redhat.com>
151
152 * Makefile.am (CGEN): Load guile.scm before calling the main
153 application script.
154 * Makefile.in: Regenerated.
155 * cgen.sh: Be prepared for the 'cgen' argument to contain spaces.
156 Simply pass the cgen-opc.scm path to ${cgen} as its first
157 argument; ${cgen} itself now contains the '-s', or whatever is
158 appropriate for the Scheme being used.
159
c46f8c51
AC		 1602005-01-31 Andrew Cagney <cagney@gnu.org>
161
162 * configure: Regenerate to track ../gettext.m4.
163
60b9a617
JB		 1642005-01-31 Jan Beulich <jbeulich@novell.com>
165
166 * ia64-gen.c (NELEMS): Define.
167 (shrink): Generate alias with missing second predicate register when
168 opcode has two outputs and these are both predicates.
169 * ia64-opc-i.c (FULL17): Define.
170 (ia64_opcodes_i): Add mov-to-pr alias without second input. Use FULL17
171 here to generate output template.
172 (TBITCM, TNATCM): Undefine after use.
173 * ia64-opc-m.c (ia64_opcodes_i): Add alloc alias without ar.pfs as
174 first input. Add ld16 aliases without ar.csd as second output. Add
175 st16 aliases without ar.csd as second input. Add cmpxchg aliases
176 without ar.ccv as third input. Add cmp8xchg16 aliases without ar.csd/
177 ar.ccv as third/fourth inputs. Consolidate through...
178 (CMPXCHG_acq, CMPXCHG_rel, CMPXCHG_1, CMPXCHG_2, CMPXCHG_4, CMPXCHG_8,
179 CMPXCHGn, CMP8XCHG16, CMPXCHG_ALL): Define.
180 * ia64-asmtab.c: Regenerate.
181
a53bf506
AC		 1822005-01-27 Andrew Cagney <cagney@gnu.org>
183
184 * configure: Regenerate to track ../gettext.m4 change.
185
90219bd0
AO		 1862005-01-25 Alexandre Oliva <aoliva@redhat.com>
187
188 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
189 * frv-asm.c: Rebuilt.
190 * frv-desc.c: Rebuilt.
191 * frv-desc.h: Rebuilt.
192 * frv-dis.c: Rebuilt.
193 * frv-ibld.c: Rebuilt.
194 * frv-opc.c: Rebuilt.
195 * frv-opc.h: Rebuilt.
196
45181ed1
AC		 1972005-01-24 Andrew Cagney <cagney@gnu.org>
198
199 * configure: Regenerate, ../gettext.m4 was updated.
200
9e836e3d
FF		 2012005-01-21 Fred Fish <fnf@specifixinc.com>
202
203 * mips-opc.c: Change INSN_ALIAS to INSN2_ALIAS.
204 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
205 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
206 * mips-dis.c: Ditto.
207
5e8cb021
AM		 2082005-01-20 Alan Modra <amodra@bigpond.net.au>
209
210 * ppc-opc.c (powerpc_opcodes): Add optional 'l' arg to tlbiel.
211
986e18a5
FF		 2122005-01-19 Fred Fish <fnf@specifixinc.com>
213
214 * mips-dis.c (no_aliases): New disassembly option flag.
215 (set_default_mips_dis_options): Init no_aliases to zero.
216 (parse_mips_dis_option): Handle no-aliases option.
217 (print_insn_mips): Ignore table entries that are aliases
218 if no_aliases is set.
219 (print_insn_mips16): Ditto.
220 * mips-opc.c (mips_builtin_opcodes): Add initializer column for
221 new pinfo2 member and add INSN_ALIAS initializers as needed. Also
222 move WR_MACC and RD_MACC initializers from pinfo to pinfo2.
223 * mips16-opc.c (mips16_opcodes): Ditto.
224
e38bc3b5
NC		 2252005-01-17 Andrew Stubbs <andrew.stubbs@st.com>
226
227 * sh-opc.h (arch_sh2a_or_sh3e,arch_sh2a_or_sh4): Correct definition.
228 (inheritance diagram): Add missing edge.
229 (arch_sh1_up): Rename arch_sh_up to match external name to make life
230 easier for the testsuite.
231 (arch_sh4_nofp_up): Likewise, rename arch_sh4_nofpu_up.
232 (arch_sh4a_nofp_up): Likewise, rename arch_sh4a_nofpu_up.
610ad19b 233 (arch_sh2a_nofpu_or_sh4_nommu_nofpu_up): Add missing
e38bc3b5
NC		 234 arch_sh2a_or_sh4_up child.
235 (sh_table): Do renaming as above.
236 Correct comment for ldc.l for gas testsuite to read.
237 Remove rogue mul.l from sh1 (duplicate of the one for sh2).
238 Correct comments for movy.w and movy.l for gas testsuite to read.
239 Correct comments for fmov.d and fmov.s for gas testsuite to read.
240
9df48ba9
L		 2412005-01-12 H.J. Lu <hongjiu.lu@intel.com>
242
243 * i386-dis.c (OP_E): Don't ignore scale in SIB for 64 bit mode.
244
2033b4b9
L		 2452005-01-12 H.J. Lu <hongjiu.lu@intel.com>
246
247 * i386-dis.c (OP_E): Ignore scale when index == 0x4 in SIB.
248
0bcb06d2
AS		 2492005-01-10 Andreas Schwab <schwab@suse.de>
250
251 * disassemble.c (disassemble_init_for_target) <case
252 bfd_arch_ia64>: Set skip_zeroes to 16.
253 <case bfd_arch_tic4x>: Set skip_zeroes to 32.
254
47add74d
TL		 2552004-12-23 Tomer Levi <Tomer.Levi@nsc.com>
256
257 * crx-opc.c: Mark 'bcop' instruction as RELAXABLE.
258
246f4c05
SS		 2592004-12-14 Svein E. Seldal <Svein.Seldal@solidas.com>
260
261 * avr-dis.c: Prettyprint. Added printing of symbol names in all
262 memory references. Convert avr_operand() to C90 formatting.
263
0e1200e5
TL		 2642004-12-05 Tomer Levi <Tomer.Levi@nsc.com>
265
266 * crx-dis.c (print_arg): Use 'info->print_address_func' for address printing.
267
89a649f7
TL		 2682004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
269
270 * crx-opc.c (crx_optab): Mark all rbase_disps* operands as signed.
271 (no_op_insn): Initialize array with instructions that have no
272 operands.
273 * crx-dis.c (make_instruction): Get rid of COP_BRANCH_INS operand swapping.
274
6255809c
RE		 2752004-11-29 Richard Earnshaw <rearnsha@arm.com>
276
277 * arm-dis.c: Correct top-level comment.
278
2fbad815
RE		 2792004-11-27 Richard Earnshaw <rearnsha@arm.com>
280
281 * arm-opc.h (arm_opcode, thumb_opcode): Add extra field for the
282 architecuture defining the insn.
283 (arm_opcodes, thumb_opcodes): Delete. Move to ...
6b8725b9
RE		 284 * arm-dis.c (arm_opcodes, thumb_opcodes): Here. Add architecutre
285 field.
2fbad815
RE		 286 Also include opcode/arm.h.
287 * Makefile.am (arm-dis.lo): Update dependency list.
288 * Makefile.in: Regenerate.
289
d81acc42
NC		 2902004-11-22 Ravi Ramaseshan <ravi.ramaseshan@codito.com>
291
292 * opcode/arc-opc.c (insert_base): Modify ls_operand[LS_OFFSET] to
293 reflect the change to the short immediate syntax.
294
ca4f2377
AM		 2952004-11-19 Alan Modra <amodra@bigpond.net.au>
296
5da8bf1b
AM		 297 * or32-opc.c (debug): Warning fix.
298 * po/POTFILES.in: Regenerate.
299
ca4f2377
AM		 300 * maxq-dis.c: Formatting.
301 (print_insn): Warning fix.
302
b7693d02
DJ		 3032004-11-17 Daniel Jacobowitz <dan@codesourcery.com>
304
305 * arm-dis.c (WORD_ADDRESS): Define.
306 (print_insn): Use it. Correct big-endian end-of-section handling.
307
300dac7e
NC		 3082004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
309 Vineet Sharma <vineets@noida.hcltech.com>
310
311 * maxq-dis.c: New file.
312 * disassemble.c (ARCH_maxq): Define.
610ad19b 313 (disassembler): Add 'print_insn_maxq_little' for handling maxq
300dac7e
NC		 314 instructions..
315 * configure.in: Add case for bfd_maxq_arch.
316 * configure: Regenerate.
317 * Makefile.am: Add support for maxq-dis.c
318 * Makefile.in: Regenerate.
319 * aclocal.m4: Regenerate.
320
42048ee7
TL		 3212004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
322
323 * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
324 mode.
325 * crx-dis.c: Likewise.
326
bd21e58e
HPN		 3272004-11-04 Hans-Peter Nilsson <hp@axis.com>
328
329 Generally, handle CRISv32.
330 * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
331 (struct cris_disasm_data): New type.
332 (format_reg, format_hex, cris_constraint, print_flags)
333 (get_opcode_entry): Add struct cris_disasm_data * parameter. All
334 callers changed.
335 (format_sup_reg, print_insn_crisv32_with_register_prefix)
336 (print_insn_crisv32_without_register_prefix)
337 (print_insn_crisv10_v32_with_register_prefix)
338 (print_insn_crisv10_v32_without_register_prefix)
339 (cris_parse_disassembler_options): New functions.
340 (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
341 parameter. All callers changed.
342 (get_opcode_entry): Call malloc, not xmalloc. Return NULL on
343 failure.
344 (cris_constraint) <case 'Y', 'U'>: New cases.
345 (bytes_to_skip): Handle 'Y' and 'N' as 's'. Skip size is 4 bytes
346 for constraint 'n'.
347 (print_with_operands) <case 'Y'>: New case.
348 (print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
349 <case 'N', 'Y', 'Q'>: New cases.
350 (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
351 (print_insn_cris_with_register_prefix)
352 (print_insn_cris_without_register_prefix): Call
353 cris_parse_disassembler_options.
354 * cris-opc.c (cris_spec_regs): Mention that this table isn't used
355 for CRISv32 and the size of immediate operands. New v32-only
356 entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
357 spc. Add v32-only 4-byte entries for p2, p3, p5 and p6. Change
358 ccr, ibr, irp to be v0..v10. Change bar, dccr to be v8..v10.
359 Change brp to be v3..v10.
360 (cris_support_regs): New vector.
361 (cris_opcodes): Update head comment. New format characters '[',
362 ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
363 Add new opcodes for v32 and adjust existing opcodes to accommodate
364 differences to earlier variants.
365 (cris_cond15s): New vector.
366
9306ca4a
JB		 3672004-11-04 Jan Beulich <jbeulich@novell.com>
368
369 * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
370 (indirEb): Remove.
371 (Mp): Use f_mode rather than none at all.
372 (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
373 replaces what previously was x_mode; x_mode now means 128-bit SSE
374 operands.
375 (dis386): Make far jumps and calls have an 'l' prefix only in AT&T
376 mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
377 pinsrw's second operand is Edqw.
378 (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
379 operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
380 fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
381 mode when an operand size override is present or always suffixing.
382 More instructions will need to be added to this group.
383 (putop): Handle new macro chars 'C' (short/long suffix selector),
384 'I' (Intel mode override for following macro char), and 'J' (for
385 adding the 'l' prefix to far branches in AT&T mode). When an
386 alternative was specified in the template, honor macro character when
387 specified for Intel mode.
388 (OP_E): Handle new *_mode values. Correct pointer specifications for
389 memory operands. Consolidate output of index register.
390 (OP_G): Handle new *_mode values.
391 (OP_I): Handle const_1_mode.
392 (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
393 respective opcode prefix bits have been consumed.
394 (OP_EM, OP_EX): Provide some default handling for generating pointer
395 specifications.
396
f39c96a9
TL		 3972004-10-28 Tomer Levi <Tomer.Levi@nsc.com>
398
399 * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
400 COP_INST macro.
401
812337be
TL		 4022004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
403
404 * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
405 (getregliststring): Support HI/LO and user registers.
610ad19b 406 * crx-opc.c (crx_instruction): Update data structure according to the
812337be
TL		 407 rearrangement done in CRX opcode header file.
408 (crx_regtab): Likewise.
409 (crx_optab): Likewise.
610ad19b 410 (crx_instruction): Reorder load/stor instructions, remove unsupported
812337be
TL		 411 formats.
412 support new Co-Processor instruction 'cpi'.
413
4030fa5a
NC		 4142004-10-27 Nick Clifton <nickc@redhat.com>
415
416 * opcodes/iq2000-asm.c: Regenerate.
417 * opcodes/iq2000-desc.c: Regenerate.
418 * opcodes/iq2000-desc.h: Regenerate.
419 * opcodes/iq2000-dis.c: Regenerate.
420 * opcodes/iq2000-ibld.c: Regenerate.
421 * opcodes/iq2000-opc.c: Regenerate.
422 * opcodes/iq2000-opc.h: Regenerate.
423
fc3d45e8
TL		 4242004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
425
426 * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
427 us4, us5 (respectively).
428 Remove unsupported 'popa' instruction.
429 Reverse operands order in store co-processor instructions.
430
3c55da70
AM		 4312004-10-15 Alan Modra <amodra@bigpond.net.au>
432
433 * Makefile.am: Run "make dep-am"
434 * Makefile.in: Regenerate.
435
7fa3d080
BW		 4362004-10-12 Bob Wilson <bob.wilson@acm.org>
437
438 * xtensa-dis.c: Use ISO C90 formatting.
439
e612bb4d
AM		 4402004-10-09 Alan Modra <amodra@bigpond.net.au>
441
442 * ppc-opc.c: Revert 2004-09-09 change.
443
43cd72b9
BW		 4442004-10-07 Bob Wilson <bob.wilson@acm.org>
445
446 * xtensa-dis.c (state_names): Delete.
447 (fetch_data): Use xtensa_isa_maxlength.
448 (print_xtensa_operand): Replace operand parameter with opcode/operand
449 pair. Remove print_sr_name parameter. Use new xtensa-isa.h functions.
450 (print_insn_xtensa): Use new xtensa-isa.h functions. Handle multislot
451 instruction bundles. Use xmalloc instead of malloc.
452
bbac1f2a
NC		 4532004-10-07 David Gibson <david@gibson.dropbear.id.au>
454
455 * ppc-opc.c: Replace literal "0"s with NULLs in pointer
456 initializers.
457
48c9f030
NC		 4582004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
459
460 * crx-opc.c (crx_instruction): Support Co-processor insns.
461 * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
462 (getregliststring): Change function to use the above enum.
463 (print_arg): Handle CO-Processor insns.
464 (crx_cinvs): Add 'b' option to invalidate the branch-target
465 cache.
466
12c64a4e
AH		 4672004-10-06 Aldy Hernandez <aldyh@redhat.com>
468
469 * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
470 efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
471 efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
472 efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
473 efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
474
14127cc4
NC		 4752004-10-01 Bill Farmer <Bill@the-farmers.freeserve.co.uk>
476
477 * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
478 rather than add it.
479
0dd132b6
NC		 4802004-09-30 Paul Brook <paul@codesourcery.com>
481
482 * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
483 * arm-opc.h: Document %e. Add ARMv6ZK instructions.
484
3f85e526
L		 4852004-09-17 H.J. Lu <hongjiu.lu@intel.com>
486
487 * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
488 (CONFIG_STATUS_DEPENDENCIES): New.
489 (Makefile): Removed.
490 (config.status): Likewise.
491 * Makefile.in: Regenerated.
492
8ae85421
AM		 4932004-09-17 Alan Modra <amodra@bigpond.net.au>
494
495 * Makefile.am: Run "make dep-am".
496 * Makefile.in: Regenerate.
497 * aclocal.m4: Regenerate.
498 * configure: Regenerate.
499 * po/POTFILES.in: Regenerate.
500 * po/opcodes.pot: Regenerate.
501
24443139
AS		 5022004-09-11 Andreas Schwab <schwab@suse.de>
503
504 * configure: Rebuild.
505
2a309db0
AM		 5062004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
507
508 * ppc-opc.c (L): Make this field not optional.
509
42851540
NC		 5102004-09-03 Tomer Levi <Tomer.Levi@nsc.com>
511
512 * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
513 Fix parameter to 'm[t|f]csr' insns.
514
979273e3
NN		 5152004-08-30 Nathanael Nerode <neroden@gcc.gnu.org>
516
517 * configure.in: Autoupdate to autoconf 2.59.
518 * aclocal.m4: Rebuild with aclocal 1.4p6.
519 * configure: Rebuild with autoconf 2.59.
520 * Makefile.in: Rebuild with automake 1.4p6 (picking up
521 bfd changes for autoconf 2.59 on the way).
522 * config.in: Rebuild with autoheader 2.59.
523
ac28a1cb
RS		 5242004-08-27 Richard Sandiford <rsandifo@redhat.com>
525
526 * frv-desc.[ch], frv-opc.[ch]: Regenerated.
527
30d1c836
ML		 5282004-07-30 Michal Ludvig <mludvig@suse.cz>
529
530 * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
531 (GRPPADLCK2): New define.
532 (twobyte_has_modrm): True for 0xA6.
533 (grps): GRPPADLCK2 for opcode 0xA6.
534
0b0ac059
AO		 5352004-07-29 Alexandre Oliva <aoliva@redhat.com>
536
537 Introduce SH2a support.
538 * sh-opc.h (arch_sh2a_base): Renumber.
539 (arch_sh2a_nofpu_base): Remove.
540 (arch_sh_base_mask): Adjust.
541 (arch_opann_mask): New.
542 (arch_sh2a, arch_sh2a_nofpu): Adjust.
543 (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
544 (sh_table): Adjust whitespace.
545 2004-02-24 Corinna Vinschen <vinschen@redhat.com>
546 * sh-opc.h (arch_sh2a_nofpu_up): New. Use instead of arch_sh2a_up in
547 instruction list throughout.
548 (arch_sh2a_up): Redefine to include fpu instruction set. Use instead
549 of arch_sh2a in instruction list throughout.
550 (arch_sh2e_up): Accomodate above changes.
551 (arch_sh2_up): Ditto.
552 2004-02-20 Corinna Vinschen <vinschen@redhat.com>
553 * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
554 2004-02-18 Corinna Vinschen <vinschen@redhat.com>
555 * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
556 * sh-opc.h (arch_sh2a_nofpu): New.
557 (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
558 (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
559 instruction.
560 2004-01-20 DJ Delorie <dj@redhat.com>
561 * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
562 2003-12-29 DJ Delorie <dj@redhat.com>
563 * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
564 sh_opcode_info, sh_table): Add sh2a support.
565 (arch_op32): New, to tag 32-bit opcodes.
566 * sh-dis.c (print_insn_sh): Support sh2a opcodes.
567 2003-12-02 Michael Snyder <msnyder@redhat.com>
568 * sh-opc.h (arch_sh2a): Add.
569 * sh-dis.c (arch_sh2a): Handle.
570 * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
571
670ec21d
NC		 5722004-07-27 Tomer Levi <Tomer.Levi@nsc.com>
573
574 * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
575
ed049af3
NC		 5762004-07-22 Nick Clifton <nickc@redhat.com>
577
578 PR/280
579 * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
580 insns - this is done by objdump itself.
581 * h8500-dis.c (print_insn_h8500): Likewise.
582
20f0a1fc
NC		 5832004-07-21 Jan Beulich <jbeulich@novell.com>
584
585 * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
586 regardless of address size prefix in effect.
587 (ptr_reg): Size or address registers does not depend on rex64, but
588 on the presence of an address size override.
589 (OP_MMX): Use rex.x only for xmm registers.
590 (OP_EM): Use rex.z only for xmm registers.
591
6f14957b
MR		 5922004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
593
594 * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
595 move/branch operations to the bottom so that VR5400 multimedia
596 instructions take precedence in disassembly.
597
1586d91e
MR		 5982004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
599
600 * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
601 ISA-specific "break" encoding.
602
982de27a
NC		 6032004-07-13 Elvis Chiang <elvisfb@gmail.com>
604
605 * arm-opc.h: Fix typo in comment.
606
4300ab10
AS		 6072004-07-11 Andreas Schwab <schwab@suse.de>
608
609 * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
610
8577e690
AS		 6112004-07-09 Andreas Schwab <schwab@suse.de>
612
613 * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
614
1fe1f39c
NC		 6152004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
616
617 * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
618 (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
619 (crx-dis.lo): New target.
620 (crx-opc.lo): Likewise.
621 * Makefile.in: Regenerate.
622 * configure.in: Handle bfd_crx_arch.
623 * configure: Regenerate.
624 * crx-dis.c: New file.
625 * crx-opc.c: New file.
626 * disassemble.c (ARCH_crx): Define.
627 (disassembler): Handle ARCH_crx.
628
7a33b495
JW		 6292004-06-29 James E Wilson <wilson@specifixinc.com>
630
631 * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
632 * ia64-asmtab.c: Regnerate.
633
98e69875
AM		 6342004-06-28 Alan Modra <amodra@bigpond.net.au>
635
636 * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
637 (extract_fxm): Don't test dialect.
638 (XFXFXM_MASK): Include the power4 bit.
639 (XFXM): Add p4 param.
640 (powerpc_opcodes): Add mfocrf and mtocrf. Adjust mtcr.
641
a53b85e2
AO		 6422004-06-27 Alexandre Oliva <aoliva@redhat.com>
643
644 2003-07-21 Richard Sandiford <rsandifo@redhat.com>
645 * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
646
d0618d1c
AM		 6472004-06-26 Alan Modra <amodra@bigpond.net.au>
648
649 * ppc-opc.c (BH, XLBH_MASK): Define.
650 (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
651
1d9f512f
AM		 6522004-06-24 Alan Modra <amodra@bigpond.net.au>
653
654 * i386-dis.c (x_mode): Comment.
655 (two_source_ops): File scope.
656 (float_mem): Correct fisttpll and fistpll.
657 (float_mem_mode): New table.
658 (dofloat): Use it.
659 (OP_E): Correct intel mode PTR output.
660 (ptr_reg): Use open_char and close_char.
661 (PNI_Fixup): Handle possible suffix on sidt. Use op1out etc. for
662 operands. Set two_source_ops.
663
52886d70
AM		 6642004-06-15 Alan Modra <amodra@bigpond.net.au>
665
666 * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
667 instead of _raw_size.
668
bad9ceea
JJ		 6692004-06-08 Jakub Jelinek <jakub@redhat.com>
670
671 * ia64-gen.c (in_iclass): Handle more postinc st
672 and ld variants.
673 * ia64-asmtab.c: Rebuilt.
674
0451f5df
MS		 6752004-06-01 Martin Schwidefsky <schwidefsky@de.ibm.com>
676
677 * s390-opc.txt: Correct architecture mask for some opcodes.
678 lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
679 in the esa mode as well.
680
f6f9408f
JR		 6812004-05-28 Andrew Stubbs <andrew.stubbs@superh.com>
682
683 * sh-dis.c (target_arch): Make unsigned.
684 (print_insn_sh): Replace (most of) switch with a call to
685 sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
686 * sh-opc.h: Redefine architecture flags values.
687 Add sh3-nommu architecture.
688 Reorganise <arch>_up macros so they make more visual sense.
689 (SH_MERGE_ARCH_SET): Define new macro.
690 (SH_VALID_BASE_ARCH_SET): Likewise.
691 (SH_VALID_MMU_ARCH_SET): Likewise.
692 (SH_VALID_CO_ARCH_SET): Likewise.
693 (SH_VALID_ARCH_SET): Likewise.
694 (SH_MERGE_ARCH_SET_VALID): Likewise.
695 (SH_ARCH_SET_HAS_FPU): Likewise.
696 (SH_ARCH_SET_HAS_DSP): Likewise.
697 (SH_ARCH_UNKNOWN_ARCH): Likewise.
698 (sh_get_arch_from_bfd_mach): Add prototype.
699 (sh_get_arch_up_from_bfd_mach): Likewise.
700 (sh_get_bfd_mach_from_arch_set): Likewise.
701 (sh_merge_bfd_arc): Likewise.
702
be8c092b
NC		 7032004-05-24 Peter Barada <peter@the-baradas.com>
704
705 * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
610ad19b
AM		 706 into new match_insn_m68k function. Loop over canidate
707 matches and select first that completely matches.
be8c092b
NC		 708 * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
709 * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
610ad19b 710 to verify addressing for MAC/EMAC.
be8c092b
NC		 711 * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
712 reigster halves since 'fpu' and 'spl' look misleading.
713 * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
714 * m68k-opc.c: Rearragne mac/emac cases to use longest for
715 first, tighten up match masks.
716 * m68k-opc.c: Add 'size' field to struct m68k_opcode. Produce
717 'size' from special case code in print_insn_m68k to
718 determine decode size of insns.
719
a30e9cc4
AM		 7202004-05-19 Alan Modra <amodra@bigpond.net.au>
721
722 * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
723 well as when -mpower4.
724
9598fbe5
NC		 7252004-05-13 Nick Clifton <nickc@redhat.com>
726
727 * po/fr.po: Updated French translation.
728
6b6e92f4
NC		 7292004-05-05 Peter Barada <peter@the-baradas.com>
730
731 * m68k-dis.c(print_insn_m68k): Add new chips, use core
732 variants in arch_mask. Only set m68881/68851 for 68k chips.
733 * m68k-op.c: Switch from ColdFire chips to core variants.
734
a404d431
AM		 7352004-05-05 Alan Modra <amodra@bigpond.net.au>
736
a30e9cc4 737 PR 147.
a404d431
AM		 738 * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
739
f3806e43
BE		 7402004-04-29 Ben Elliston <bje@au.ibm.com>
741
520ceea4
BE		 742 * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
743 (powerpc_opcodes): Add "dbczl" instruction for PPC970.
f3806e43 744
1f1799d5
KK		 7452004-04-22 Kaz Kojima <kkojima@rr.iij4u.or.jp>
746
747 * sh-dis.c (print_insn_sh): Print the value in constant pool
748 as a symbol if it looks like a symbol.
749
fd99574b
NC		 7502004-04-22 Peter Barada <peter@the-baradas.com>
751
752 * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
753 appropriate ColdFire architectures.
754 (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
755 mask addressing.
756 Add EMAC instructions, fix MAC instructions. Remove
757 macmw/macml/msacmw/msacml instructions since mask addressing now
758 supported.
759
b4781d44
JJ		 7602004-04-20 Jakub Jelinek <jakub@redhat.com>
761
762 * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
763 (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
764 suffix. Use fmov*x macros, create all 3 fpsize variants in one
765 macro. Adjust all users.
766
91809fda 7672004-04-15 Anil Paranjpe <anilp1@kpitcummins.com>
610ad19b 768
91809fda
NC		 769 * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
770 separately.
771
f4453dfa
NC		 7722004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
773
774 * m32r-asm.c: Regenerate.
775
9b0de91a
SS		 7762004-03-29 Stan Shebs <shebs@apple.com>
777
778 * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
779 used.
780
e20c0b3d
AM		 7812004-03-19 Alan Modra <amodra@bigpond.net.au>
782
783 * aclocal.m4: Regenerate.
784 * config.in: Regenerate.
785 * configure: Regenerate.
786 * po/POTFILES.in: Regenerate.
787 * po/opcodes.pot: Regenerate.
788
fdd12ef3
AM		 7892004-03-16 Alan Modra <amodra@bigpond.net.au>
790
791 * ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
792 PPC_OPERANDS_GPR_0.
793 * ppc-opc.c (RA0): Define.
794 (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
795 (RAOPT): Rename from RAO. Update all uses.
a9c3619e 796 (powerpc_opcodes): Use RA0 as appropriate.
fdd12ef3 797
2dc111b3 7982004-03-15 Aldy Hernandez <aldyh@redhat.com>
fdd12ef3
AM		 799
800 * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
2dc111b3 801
7bfeee7b
AM		 8022004-03-15 Alan Modra <amodra@bigpond.net.au>
803
804 * sparc-dis.c (print_insn_sparc): Update getword prototype.
805
7ffdda93
ML		 8062004-03-12 Michal Ludvig <mludvig@suse.cz>
807
808 * i386-dis.c (GRPPLOCK): Delete.
7bfeee7b 809 (grps): Delete GRPPLOCK entry.
7ffdda93 810
cc0ec051
AM		 8112004-03-12 Alan Modra <amodra@bigpond.net.au>
812
813 * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
814 (M, Mp): Use OP_M.
815 (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
816 (GRPPADLCK): Define.
817 (dis386): Use NOP_Fixup on "nop".
818 (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
819 (twobyte_has_modrm): Set for 0xa7.
820 (padlock_table): Delete. Move to..
821 (grps): ..here, using OP_0f07. Use OP_Ofae on lfence, mfence
822 and clflush.
823 (print_insn): Revert PADLOCK_SPECIAL code.
824 (OP_E): Delete sfence, lfence, mfence checks.
825
4fd61dcb
JJ		 8262004-03-12 Jakub Jelinek <jakub@redhat.com>
827
828 * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
829 (INVLPG_Fixup): New function.
830 (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
831
0f10071e
ML		 8322004-03-12 Michal Ludvig <mludvig@suse.cz>
833
834 * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
835 (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
836 (padlock_table): New struct with PadLock instructions.
837 (print_insn): Handle PADLOCK_SPECIAL.
838
c02908d2
AM		 8392004-03-12 Alan Modra <amodra@bigpond.net.au>
840
841 * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
842 (OP_E): Twiddle clflush to sfence here.
843
d5bb7600
NC		 8442004-03-08 Nick Clifton <nickc@redhat.com>
845
846 * po/de.po: Updated German translation.
847
ae51a426
JR		 8482003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>
849
850 * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
851 nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu.
852 * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
853 accordingly.
854
676a64f4
RS		 8552004-03-01 Richard Sandiford <rsandifo@redhat.com>
856
857 * frv-asm.c: Regenerate.
858 * frv-desc.c: Regenerate.
859 * frv-desc.h: Regenerate.
860 * frv-dis.c: Regenerate.
861 * frv-ibld.c: Regenerate.
862 * frv-opc.c: Regenerate.
863 * frv-opc.h: Regenerate.
864
c7a48b9a
RS		 8652004-03-01 Richard Sandiford <rsandifo@redhat.com>
866
867 * frv-desc.c, frv-opc.c: Regenerate.
868
8ae0baa2
RS		 8692004-03-01 Richard Sandiford <rsandifo@redhat.com>
870
871 * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
872
ce11586c
JR		 8732004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
874
875 * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
876 Also correct mistake in the comment.
877
6a5709a5
JR		 8782004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
879
880 * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
881 ensure that double registers have even numbers.
882 Add REG_N_B01 for nn01 (binary 01) nibble to ensure
883 that reserved instruction 0xfffd does not decode the same
884 as 0xfdfd (ftrv).
885 * sh-opc.h: Add REG_N_D nibble type and use it whereever
886 REG_N refers to a double register.
887 Add REG_N_B01 nibble type and use it instead of REG_NM
888 in ftrv.
889 Adjust the bit patterns in a few comments.
890
e5d2b64f 8912004-02-25 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 892
893 * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
e5d2b64f 894
1f04b05f
AH		 8952004-02-20 Aldy Hernandez <aldyh@redhat.com>
896
897 * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
898
2f3b8700
AH		 8992004-02-20 Aldy Hernandez <aldyh@redhat.com>
900
901 * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
902
f0b26da6 9032004-02-20 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 904
905 * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
906 mtivor32, mtivor33, mtivor34.
f0b26da6 907
23d59c56 9082004-02-19 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 909
910 * ppc-opc.c (powerpc_opcodes): Add mfmcar.
23d59c56 911
34920d91
NC		 9122004-02-10 Petko Manolov <petkan@nucleusys.com>
913
914 * arm-opc.h Maverick accumulator register opcode fixes.
915
44d86481
BE		 9162004-02-13 Ben Elliston <bje@wasabisystems.com>
917
918 * m32r-dis.c: Regenerate.
919
17707c23
MS		 9202004-01-27 Michael Snyder <msnyder@redhat.com>
921
922 * sh-opc.h (sh_table): "fsrra", not "fssra".
923
fe3a9bc4
NC		 9242004-01-23 Andrew Over <andrew.over@cs.anu.edu.au>
925
926 * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
927 contraints.
928
ff24f124
JJ		 9292004-01-19 Andrew Over <andrew.over@cs.anu.edu.au>
930
931 * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
932
a02a862a
AM		 9332004-01-19 Alan Modra <amodra@bigpond.net.au>
934
935 * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
936 1. Don't print scale factor on AT&T mode when index missing.
937
d164ea7f
AO		 9382004-01-16 Alexandre Oliva <aoliva@redhat.com>
939
940 * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
941 when loaded into XR registers.
942
cb10e79a
RS		 9432004-01-14 Richard Sandiford <rsandifo@redhat.com>
944
945 * frv-desc.h: Regenerate.
946 * frv-desc.c: Regenerate.
947 * frv-opc.c: Regenerate.
948
f532f3fa
MS		 9492004-01-13 Michael Snyder <msnyder@redhat.com>
950
951 * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
952
e45d0630
PB		 9532004-01-09 Paul Brook <paul@codesourcery.com>
954
955 * arm-opc.h (arm_opcodes): Move generic mcrr after known
956 specific opcodes.
957
3ba7a1aa
DJ		 9582004-01-07 Daniel Jacobowitz <drow@mvista.com>
959
960 * Makefile.am (libopcodes_la_DEPENDENCIES)
961 (libopcodes_la_LIBADD): Revert 2003-05-17 change. Add explanatory
962 comment about the problem.
963 * Makefile.in: Regenerate.
964
ba2d3f07
AO		 9652004-01-06 Alexandre Oliva <aoliva@redhat.com>
966
967 2003-12-19 Alexandre Oliva <aoliva@redhat.com>
968 * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
969 cut&paste errors in shifting/truncating numerical operands.
970 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
971 * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
972 (parse_uslo16): Likewise.
973 (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
974 (parse_d12): Parse gotoff12 and gotofffuncdesc12.
975 (parse_s12): Likewise.
976 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
977 * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
978 (parse_uslo16): Likewise.
979 (parse_uhi16): Parse gothi and gotfuncdeschi.
980 (parse_d12): Parse got12 and gotfuncdesc12.
981 (parse_s12): Likewise.
982
3ab48931
NC		 9832004-01-02 Albert Bartoszko <albar@nt.kegel.com.pl>
984
985 * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
986 instruction which looks similar to an 'rla' instruction.
a0bd404e 987
c9e214e5 988For older changes see ChangeLog-0203
252b5132
RH		 989\f
990Local Variables:
2f6d2f85
NC		 991mode: change-log
992left-margin: 8
993fill-column: 74
252b5132
RH		 994version-control: never
995End:
GDB Binutils - Deliverables
This page took 0.319092 seconds and 4 git commands to generate.