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Modify the ARM encoding and decoding of SQRSHRL and UQRSHLL MVE instructions.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
08132bdd
SP		 12019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
2
3 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
4 cases MVE_SQRSHRL and MVE_UQRSHLL.
5 (print_insn_mve): Add case for specifier 'k' to check
6 specific bit of the instruction.
7
d88bdcb4
PA		 82019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
9
10 PR 24854
11 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
12 encountering an unknown machine type.
13 (print_insn_arc): Handle arc_insn_length returning 0. In error
14 cases return -1 rather than calling abort.
15
bc750500
JB		 162019-08-07 Jan Beulich <jbeulich@suse.com>
17
18 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
19 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
20 IgnoreSize.
21 * i386-tbl.h: Re-generate.
22
23d188c7
BW		 232019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
24
25 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
26 instructions.
27
c0d6f62f
JW		 282019-07-30 Mel Chen <mel.chen@sifive.com>
29
30 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
31 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
32
33 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
34 fscsr.
35
0f3f7167
CZ		 362019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
37
38 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
39 and MPY class instructions.
40 (parse_option): Add nps400 option.
41 (print_arc_disassembler_options): Add nps400 info.
42
7e126ba3
CZ		 432019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
44
45 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
46 (bspop): Likewise.
47 (modapp): Likewise.
48 * arc-opc.c (RAD_CHK): Add.
49 * arc-tbl.h: Regenerate.
50
a028026d
KT		 512019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
52
53 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
54 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
55
ac79ff9e
NC		 562019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
57
58 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
59 instructions as UNPREDICTABLE.
60
231097b0
JM		 612019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
62
63 * bpf-desc.c: Regenerated.
64
1d942ae9
JB		 652019-07-17 Jan Beulich <jbeulich@suse.com>
66
67 * i386-gen.c (static_assert): Define.
68 (main): Use it.
69 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
70 (Opcode_Modifier_Num): ... this.
71 (Mem): Delete.
72
dfd69174
JB		 732019-07-16 Jan Beulich <jbeulich@suse.com>
74
75 * i386-gen.c (operand_types): Move RegMem ...
76 (opcode_modifiers): ... here.
77 * i386-opc.h (RegMem): Move to opcode modifer enum.
78 (union i386_operand_type): Move regmem field ...
79 (struct i386_opcode_modifier): ... here.
80 * i386-opc.tbl (RegMem): Define.
81 (mov, movq): Move RegMem on segment, control, debug, and test
82 register flavors.
83 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
84 to non-SSE2AVX flavor.
85 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
86 Move RegMem on register only flavors. Drop IgnoreSize from
87 legacy encoding flavors.
88 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
89 flavors.
90 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
91 register only flavors.
92 (vmovd): Move RegMem and drop IgnoreSize on register only
93 flavor. Change opcode and operand order to store form.
94 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
95
21df382b
JB		 962019-07-16 Jan Beulich <jbeulich@suse.com>
97
98 * i386-gen.c (operand_type_init, operand_types): Replace SReg
99 entries.
100 * i386-opc.h (SReg2, SReg3): Replace by ...
101 (SReg): ... this.
102 (union i386_operand_type): Replace sreg fields.
103 * i386-opc.tbl (mov, ): Use SReg.
104 (push, pop): Likewies. Drop i386 and x86-64 specific segment
105 register flavors.
106 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
107 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
108
3719fd55
JM		 1092019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
110
111 * bpf-desc.c: Regenerate.
112 * bpf-opc.c: Likewise.
113 * bpf-opc.h: Likewise.
114
92434a14
JM		 1152019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
116
117 * bpf-desc.c: Regenerate.
118 * bpf-opc.c: Likewise.
119
43dd7626
HPN		 1202019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
121
122 * arm-dis.c (print_insn_coprocessor): Rename index to
123 index_operand.
124
98602811
JW		 1252019-07-05 Kito Cheng <kito.cheng@sifive.com>
126
127 * riscv-opc.c (riscv_insn_types): Add r4 type.
128
129 * riscv-opc.c (riscv_insn_types): Add b and j type.
130
131 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
132 format for sb type and correct s type.
133
01c1ee4a
RS		 1342019-07-02 Richard Sandiford <richard.sandiford@arm.com>
135
136 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
137 SVE FMOV alias of FCPY.
138
83adff69
RS		 1392019-07-02 Richard Sandiford <richard.sandiford@arm.com>
140
141 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
142 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
143
89418844
RS		 1442019-07-02 Richard Sandiford <richard.sandiford@arm.com>
145
146 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
147 registers in an instruction prefixed by MOVPRFX.
148
41be57ca
MM		 1492019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
150
151 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
152 sve_size_13 icode to account for variant behaviour of
153 pmull{t,b}.
154 * aarch64-dis-2.c: Regenerate.
155 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
156 sve_size_13 icode to account for variant behaviour of
157 pmull{t,b}.
158 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
159 (OP_SVE_VVV_Q_D): Add new qualifier.
160 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
161 (struct aarch64_opcode): Split pmull{t,b} into those requiring
162 AES and those not.
163
9d3bf266
JB		 1642019-07-01 Jan Beulich <jbeulich@suse.com>
165
166 * opcodes/i386-gen.c (operand_type_init): Remove
167 OPERAND_TYPE_VEC_IMM4 entry.
168 (operand_types): Remove Vec_Imm4.
169 * opcodes/i386-opc.h (Vec_Imm4): Delete.
170 (union i386_operand_type): Remove vec_imm4.
171 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
172 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
173
c3949f43
JB		 1742019-07-01 Jan Beulich <jbeulich@suse.com>
175
176 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
177 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
178 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
179 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
180 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
181 monitorx, mwaitx): Drop ImmExt from operand-less forms.
182 * i386-tbl.h: Re-generate.
183
5641ec01
JB		 1842019-07-01 Jan Beulich <jbeulich@suse.com>
185
186 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
187 register operands.
188 * i386-tbl.h: Re-generate.
189
79dec6b7
JB		 1902019-07-01 Jan Beulich <jbeulich@suse.com>
191
192 * i386-opc.tbl (C): New.
193 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
194 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
195 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
196 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
197 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
198 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
199 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
200 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
201 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
202 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
203 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
204 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
205 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
206 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
207 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
208 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
209 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
210 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
211 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
212 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
213 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
214 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
215 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
216 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
217 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
218 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
219 flavors.
220 * i386-tbl.h: Re-generate.
221
a0a1771e
JB		 2222019-07-01 Jan Beulich <jbeulich@suse.com>
223
224 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
225 register operands.
226 * i386-tbl.h: Re-generate.
227
cd546e7b
JB		 2282019-07-01 Jan Beulich <jbeulich@suse.com>
229
230 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
231 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
232 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
233 * i386-tbl.h: Re-generate.
234
e3bba3fc
JB		 2352019-07-01 Jan Beulich <jbeulich@suse.com>
236
237 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
238 Disp8MemShift from register only templates.
239 * i386-tbl.h: Re-generate.
240
36cc073e
JB		 2412019-07-01 Jan Beulich <jbeulich@suse.com>
242
243 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
244 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
245 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
246 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
247 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
248 EVEX_W_0F11_P_3_M_1): Delete.
249 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
250 EVEX_W_0F11_P_3): New.
251 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
252 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
253 MOD_EVEX_0F11_PREFIX_3 table entries.
254 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
255 PREFIX_EVEX_0F11 table entries.
256 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
257 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
258 EVEX_W_0F11_P_3_M_{0,1} table entries.
259
219920a7
JB		 2602019-07-01 Jan Beulich <jbeulich@suse.com>
261
262 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
263 Delete.
264
e395f487
L		 2652019-06-27 H.J. Lu <hongjiu.lu@intel.com>
266
267 PR binutils/24719
268 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
269 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
270 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
271 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
272 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
273 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
274 EVEX_LEN_0F38C7_R_6_P_2_W_1.
275 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
276 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
277 PREFIX_EVEX_0F38C6_REG_6 entries.
278 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
279 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
280 EVEX_W_0F38C7_R_6_P_2 entries.
281 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
282 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
283 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
284 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
285 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
286 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
287 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
288
2b7bcc87
JB		 2892019-06-27 Jan Beulich <jbeulich@suse.com>
290
291 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
292 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
293 VEX_LEN_0F2D_P_3): Delete.
294 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
295 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
296 (prefix_table): ... here.
297
c1dc7af5
JB		 2982019-06-27 Jan Beulich <jbeulich@suse.com>
299
300 * i386-dis.c (Iq): Delete.
301 (Id): New.
302 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
303 TBM insns.
304 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
305 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
306 (OP_E_memory): Also honor needindex when deciding whether an
307 address size prefix needs printing.
308 (OP_I): Remove handling of q_mode. Add handling of d_mode.
309
d7560e2d
JW		 3102019-06-26 Jim Wilson <jimw@sifive.com>
311
312 PR binutils/24739
313 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
314 Set info->display_endian to info->endian_code.
315
2c703856
JB		 3162019-06-25 Jan Beulich <jbeulich@suse.com>
317
318 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
319 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
320 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
321 OPERAND_TYPE_ACC64 entries.
322 * i386-init.h: Re-generate.
323
54fbadc0
JB		 3242019-06-25 Jan Beulich <jbeulich@suse.com>
325
326 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
327 Delete.
328 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
329 of dqa_mode.
330 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
331 entries here.
332 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
333 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
334
a280ab8e
JB		 3352019-06-25 Jan Beulich <jbeulich@suse.com>
336
337 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
338 variables.
339
e1a1babd
JB		 3402019-06-25 Jan Beulich <jbeulich@suse.com>
341
342 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
343 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
344 movnti.
d7560e2d 345 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 346 * i386-tbl.h: Re-generate.
347
b8364fa7
JB		 3482019-06-25 Jan Beulich <jbeulich@suse.com>
349
350 * i386-opc.tbl (and): Mark Imm8S form for optimization.
351 * i386-tbl.h: Re-generate.
352
ad692897
L		 3532019-06-21 H.J. Lu <hongjiu.lu@intel.com>
354
355 * i386-dis-evex.h: Break into ...
356 * i386-dis-evex-len.h: New file.
357 * i386-dis-evex-mod.h: Likewise.
358 * i386-dis-evex-prefix.h: Likewise.
359 * i386-dis-evex-reg.h: Likewise.
360 * i386-dis-evex-w.h: Likewise.
361 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
362 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
363 i386-dis-evex-mod.h.
364
f0a6222e
L		 3652019-06-19 H.J. Lu <hongjiu.lu@intel.com>
366
367 PR binutils/24700
368 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
369 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
370 EVEX_W_0F385B_P_2.
371 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
372 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
373 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
374 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
375 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
376 EVEX_LEN_0F385B_P_2_W_1.
377 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
378 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
379 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
380 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
381 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
382 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
383 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
384 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
385 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
386 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
387
6e1c90b7
L		 3882019-06-17 H.J. Lu <hongjiu.lu@intel.com>
389
390 PR binutils/24691
391 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
392 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
393 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
394 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
395 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
396 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
397 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
398 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
399 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
400 EVEX_LEN_0F3A43_P_2_W_1.
401 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
402 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
403 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
404 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
405 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
406 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
407 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
408 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
409 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
410 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
411 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
412 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
413
bcc5a6eb
NC		 4142019-06-14 Nick Clifton <nickc@redhat.com>
415
416 * po/fr.po; Updated French translation.
417
e4c4ac46
SH		 4182019-06-13 Stafford Horne <shorne@gmail.com>
419
420 * or1k-asm.c: Regenerated.
421 * or1k-desc.c: Regenerated.
422 * or1k-desc.h: Regenerated.
423 * or1k-dis.c: Regenerated.
424 * or1k-ibld.c: Regenerated.
425 * or1k-opc.c: Regenerated.
426 * or1k-opc.h: Regenerated.
427 * or1k-opinst.c: Regenerated.
428
a0e44ef5
PB		 4292019-06-12 Peter Bergner <bergner@linux.ibm.com>
430
431 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
432
12efd68d
L		 4332019-06-05 H.J. Lu <hongjiu.lu@intel.com>
434
435 PR binutils/24633
436 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
437 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
438 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
439 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
440 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
441 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
442 EVEX_LEN_0F3A1B_P_2_W_1.
443 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
444 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
445 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
446 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
447 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
448 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
449 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
450 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
451
63c6fc6c
L		 4522019-06-04 H.J. Lu <hongjiu.lu@intel.com>
453
454 PR binutils/24626
455 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
456 EVEX.vvvv when disassembling VEX and EVEX instructions.
457 (OP_VEX): Set vex.register_specifier to 0 after readding
458 vex.register_specifier.
459 (OP_Vex_2src_1): Likewise.
460 (OP_Vex_2src_2): Likewise.
461 (OP_LWP_E): Likewise.
462 (OP_EX_Vex): Don't check vex.register_specifier.
463 (OP_XMM_Vex): Likewise.
464
9186c494
L		 4652019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
466 Lili Cui <lili.cui@intel.com>
467
468 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
469 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
470 instructions.
471 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
472 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
473 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
474 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
475 (i386_cpu_flags): Add cpuavx512_vp2intersect.
476 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
477 * i386-init.h: Regenerated.
478 * i386-tbl.h: Likewise.
479
5d79adc4
L		 4802019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
481 Lili Cui <lili.cui@intel.com>
482
483 * doc/c-i386.texi: Document enqcmd.
484 * testsuite/gas/i386/enqcmd-intel.d: New file.
485 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
486 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
487 * testsuite/gas/i386/enqcmd.d: Likewise.
488 * testsuite/gas/i386/enqcmd.s: Likewise.
489 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
490 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
491 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
492 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
493 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
494 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
495 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
496 and x86-64-enqcmd.
497
a9d96ab9
AH		 4982019-06-04 Alan Hayward <alan.hayward@arm.com>
499
500 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
501
4f6d070a
AM		 5022019-06-03 Alan Modra <amodra@gmail.com>
503
504 * ppc-dis.c (prefix_opcd_indices): Correct size.
505
a2f4b66c
L		 5062019-05-28 H.J. Lu <hongjiu.lu@intel.com>
507
508 PR gas/24625
509 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
510 Disp8ShiftVL.
511 * i386-tbl.h: Regenerated.
512
405b5bd8
AM		 5132019-05-24 Alan Modra <amodra@gmail.com>
514
515 * po/POTFILES.in: Regenerate.
516
8acf1435
PB		 5172019-05-24 Peter Bergner <bergner@linux.ibm.com>
518 Alan Modra <amodra@gmail.com>
519
520 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
521 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
522 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
523 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
524 XTOP>): Define and add entries.
525 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
526 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
527 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
528 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
529
dd7efa79
PB		 5302019-05-24 Peter Bergner <bergner@linux.ibm.com>
531 Alan Modra <amodra@gmail.com>
532
533 * ppc-dis.c (ppc_opts): Add "future" entry.
534 (PREFIX_OPCD_SEGS): Define.
535 (prefix_opcd_indices): New array.
536 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
537 (lookup_prefix): New function.
538 (print_insn_powerpc): Handle 64-bit prefix instructions.
539 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
540 (PMRR, POWERXX): Define.
541 (prefix_opcodes): New instruction table.
542 (prefix_num_opcodes): New constant.
543
79472b45
JM		 5442019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
545
546 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
547 * configure: Regenerated.
548 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
549 and cpu/bpf.opc.
550 (HFILES): Add bpf-desc.h and bpf-opc.h.
551 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
552 bpf-ibld.c and bpf-opc.c.
553 (BPF_DEPS): Define.
554 * Makefile.in: Regenerated.
555 * disassemble.c (ARCH_bpf): Define.
556 (disassembler): Add case for bfd_arch_bpf.
557 (disassemble_init_for_target): Likewise.
558 (enum epbf_isa_attr): Define.
559 * disassemble.h: extern print_insn_bpf.
560 * bpf-asm.c: Generated.
561 * bpf-opc.h: Likewise.
562 * bpf-opc.c: Likewise.
563 * bpf-ibld.c: Likewise.
564 * bpf-dis.c: Likewise.
565 * bpf-desc.h: Likewise.
566 * bpf-desc.c: Likewise.
567
ba6cd17f
SD		 5682019-05-21 Sudakshina Das <sudi.das@arm.com>
569
570 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
571 and VMSR with the new operands.
572
e39c1607
SD		 5732019-05-21 Sudakshina Das <sudi.das@arm.com>
574
575 * arm-dis.c (enum mve_instructions): New enum
576 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
577 and cneg.
578 (mve_opcodes): New instructions as above.
579 (is_mve_encoding_conflict): Add cases for csinc, csinv,
580 csneg and csel.
581 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
582
23d00a41
SD		 5832019-05-21 Sudakshina Das <sudi.das@arm.com>
584
585 * arm-dis.c (emun mve_instructions): Updated for new instructions.
586 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
587 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
588 uqshl, urshrl and urshr.
589 (is_mve_okay_in_it): Add new instructions to TRUE list.
590 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
591 (print_insn_mve): Updated to accept new %j,
592 %<bitfield>m and %<bitfield>n patterns.
593
cd4797ee
FS		 5942019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
595
596 * mips-opc.c (mips_builtin_opcodes): Change source register
597 constraint for DAUI.
598
999b073b
NC		 5992019-05-20 Nick Clifton <nickc@redhat.com>
600
601 * po/fr.po: Updated French translation.
602
14b456f2
AV		 6032019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
604 Michael Collison <michael.collison@arm.com>
605
606 * arm-dis.c (thumb32_opcodes): Add new instructions.
607 (enum mve_instructions): Likewise.
608 (enum mve_undefined): Add new reasons.
609 (is_mve_encoding_conflict): Handle new instructions.
610 (is_mve_undefined): Likewise.
611 (is_mve_unpredictable): Likewise.
612 (print_mve_undefined): Likewise.
613 (print_mve_size): Likewise.
614
f49bb598
AV		 6152019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
616 Michael Collison <michael.collison@arm.com>
617
618 * arm-dis.c (thumb32_opcodes): Add new instructions.
619 (enum mve_instructions): Likewise.
620 (is_mve_encoding_conflict): Handle new instructions.
621 (is_mve_undefined): Likewise.
622 (is_mve_unpredictable): Likewise.
623 (print_mve_size): Likewise.
624
56858bea
AV		 6252019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
626 Michael Collison <michael.collison@arm.com>
627
628 * arm-dis.c (thumb32_opcodes): Add new instructions.
629 (enum mve_instructions): Likewise.
630 (is_mve_encoding_conflict): Likewise.
631 (is_mve_unpredictable): Likewise.
632 (print_mve_size): Likewise.
633
e523f101
AV		 6342019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
635 Michael Collison <michael.collison@arm.com>
636
637 * arm-dis.c (thumb32_opcodes): Add new instructions.
638 (enum mve_instructions): Likewise.
639 (is_mve_encoding_conflict): Handle new instructions.
640 (is_mve_undefined): Likewise.
641 (is_mve_unpredictable): Likewise.
642 (print_mve_size): Likewise.
643
66dcaa5d
AV		 6442019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
645 Michael Collison <michael.collison@arm.com>
646
647 * arm-dis.c (thumb32_opcodes): Add new instructions.
648 (enum mve_instructions): Likewise.
649 (is_mve_encoding_conflict): Handle new instructions.
650 (is_mve_undefined): Likewise.
651 (is_mve_unpredictable): Likewise.
652 (print_mve_size): Likewise.
653 (print_insn_mve): Likewise.
654
d052b9b7
AV		 6552019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
656 Michael Collison <michael.collison@arm.com>
657
658 * arm-dis.c (thumb32_opcodes): Add new instructions.
659 (print_insn_thumb32): Handle new instructions.
660
ed63aa17
AV		 6612019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
662 Michael Collison <michael.collison@arm.com>
663
664 * arm-dis.c (enum mve_instructions): Add new instructions.
665 (enum mve_undefined): Add new reasons.
666 (is_mve_encoding_conflict): Handle new instructions.
667 (is_mve_undefined): Likewise.
668 (is_mve_unpredictable): Likewise.
669 (print_mve_undefined): Likewise.
670 (print_mve_size): Likewise.
671 (print_mve_shift_n): Likewise.
672 (print_insn_mve): Likewise.
673
897b9bbc
AV		 6742019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
675 Michael Collison <michael.collison@arm.com>
676
677 * arm-dis.c (enum mve_instructions): Add new instructions.
678 (is_mve_encoding_conflict): Handle new instructions.
679 (is_mve_unpredictable): Likewise.
680 (print_mve_rotate): Likewise.
681 (print_mve_size): Likewise.
682 (print_insn_mve): Likewise.
683
1c8f2df8
AV		 6842019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
685 Michael Collison <michael.collison@arm.com>
686
687 * arm-dis.c (enum mve_instructions): Add new instructions.
688 (is_mve_encoding_conflict): Handle new instructions.
689 (is_mve_unpredictable): Likewise.
690 (print_mve_size): Likewise.
691 (print_insn_mve): Likewise.
692
d3b63143
AV		 6932019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
694 Michael Collison <michael.collison@arm.com>
695
696 * arm-dis.c (enum mve_instructions): Add new instructions.
697 (enum mve_undefined): Add new reasons.
698 (is_mve_encoding_conflict): Handle new instructions.
699 (is_mve_undefined): Likewise.
700 (is_mve_unpredictable): Likewise.
701 (print_mve_undefined): Likewise.
702 (print_mve_size): Likewise.
703 (print_insn_mve): Likewise.
704
14925797
AV		 7052019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
706 Michael Collison <michael.collison@arm.com>
707
708 * arm-dis.c (enum mve_instructions): Add new instructions.
709 (is_mve_encoding_conflict): Handle new instructions.
710 (is_mve_undefined): Likewise.
711 (is_mve_unpredictable): Likewise.
712 (print_mve_size): Likewise.
713 (print_insn_mve): Likewise.
714
c507f10b
AV		 7152019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
716 Michael Collison <michael.collison@arm.com>
717
718 * arm-dis.c (enum mve_instructions): Add new instructions.
719 (enum mve_unpredictable): Add new reasons.
720 (enum mve_undefined): Likewise.
721 (is_mve_okay_in_it): Handle new isntructions.
722 (is_mve_encoding_conflict): Likewise.
723 (is_mve_undefined): Likewise.
724 (is_mve_unpredictable): Likewise.
725 (print_mve_vmov_index): Likewise.
726 (print_simd_imm8): Likewise.
727 (print_mve_undefined): Likewise.
728 (print_mve_unpredictable): Likewise.
729 (print_mve_size): Likewise.
730 (print_insn_mve): Likewise.
731
bf0b396d
AV		 7322019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
733 Michael Collison <michael.collison@arm.com>
734
735 * arm-dis.c (enum mve_instructions): Add new instructions.
736 (enum mve_unpredictable): Add new reasons.
737 (enum mve_undefined): Likewise.
738 (is_mve_encoding_conflict): Handle new instructions.
739 (is_mve_undefined): Likewise.
740 (is_mve_unpredictable): Likewise.
741 (print_mve_undefined): Likewise.
742 (print_mve_unpredictable): Likewise.
743 (print_mve_rounding_mode): Likewise.
744 (print_mve_vcvt_size): Likewise.
745 (print_mve_size): Likewise.
746 (print_insn_mve): Likewise.
747
ef1576a1
AV		 7482019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
749 Michael Collison <michael.collison@arm.com>
750
751 * arm-dis.c (enum mve_instructions): Add new instructions.
752 (enum mve_unpredictable): Add new reasons.
753 (enum mve_undefined): Likewise.
754 (is_mve_undefined): Handle new instructions.
755 (is_mve_unpredictable): Likewise.
756 (print_mve_undefined): Likewise.
757 (print_mve_unpredictable): Likewise.
758 (print_mve_size): Likewise.
759 (print_insn_mve): Likewise.
760
aef6d006
AV		 7612019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
762 Michael Collison <michael.collison@arm.com>
763
764 * arm-dis.c (enum mve_instructions): Add new instructions.
765 (enum mve_undefined): Add new reasons.
766 (insns): Add new instructions.
767 (is_mve_encoding_conflict):
768 (print_mve_vld_str_addr): New print function.
769 (is_mve_undefined): Handle new instructions.
770 (is_mve_unpredictable): Likewise.
771 (print_mve_undefined): Likewise.
772 (print_mve_size): Likewise.
773 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
774 (print_insn_mve): Handle new operands.
775
04d54ace
AV		 7762019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
777 Michael Collison <michael.collison@arm.com>
778
779 * arm-dis.c (enum mve_instructions): Add new instructions.
780 (enum mve_unpredictable): Add new reasons.
781 (is_mve_encoding_conflict): Handle new instructions.
782 (is_mve_unpredictable): Likewise.
783 (mve_opcodes): Add new instructions.
784 (print_mve_unpredictable): Handle new reasons.
785 (print_mve_register_blocks): New print function.
786 (print_mve_size): Handle new instructions.
787 (print_insn_mve): Likewise.
788
9743db03
AV		 7892019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
790 Michael Collison <michael.collison@arm.com>
791
792 * arm-dis.c (enum mve_instructions): Add new instructions.
793 (enum mve_unpredictable): Add new reasons.
794 (enum mve_undefined): Likewise.
795 (is_mve_encoding_conflict): Handle new instructions.
796 (is_mve_undefined): Likewise.
797 (is_mve_unpredictable): Likewise.
798 (coprocessor_opcodes): Move NEON VDUP from here...
799 (neon_opcodes): ... to here.
800 (mve_opcodes): Add new instructions.
801 (print_mve_undefined): Handle new reasons.
802 (print_mve_unpredictable): Likewise.
803 (print_mve_size): Handle new instructions.
804 (print_insn_neon): Handle vdup.
805 (print_insn_mve): Handle new operands.
806
143275ea
AV		 8072019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
808 Michael Collison <michael.collison@arm.com>
809
810 * arm-dis.c (enum mve_instructions): Add new instructions.
811 (enum mve_unpredictable): Add new values.
812 (mve_opcodes): Add new instructions.
813 (vec_condnames): New array with vector conditions.
814 (mve_predicatenames): New array with predicate suffixes.
815 (mve_vec_sizename): New array with vector sizes.
816 (enum vpt_pred_state): New enum with vector predication states.
817 (struct vpt_block): New struct type for vpt blocks.
818 (vpt_block_state): Global struct to keep track of state.
819 (mve_extract_pred_mask): New helper function.
820 (num_instructions_vpt_block): Likewise.
821 (mark_outside_vpt_block): Likewise.
822 (mark_inside_vpt_block): Likewise.
823 (invert_next_predicate_state): Likewise.
824 (update_next_predicate_state): Likewise.
825 (update_vpt_block_state): Likewise.
826 (is_vpt_instruction): Likewise.
827 (is_mve_encoding_conflict): Add entries for new instructions.
828 (is_mve_unpredictable): Likewise.
829 (print_mve_unpredictable): Handle new cases.
830 (print_instruction_predicate): Likewise.
831 (print_mve_size): New function.
832 (print_vec_condition): New function.
833 (print_insn_mve): Handle vpt blocks and new print operands.
834
f08d8ce3
AV		 8352019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
836
837 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
838 8, 14 and 15 for Armv8.1-M Mainline.
839
73cd51e5
AV		 8402019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
841 Michael Collison <michael.collison@arm.com>
842
843 * arm-dis.c (enum mve_instructions): New enum.
844 (enum mve_unpredictable): Likewise.
845 (enum mve_undefined): Likewise.
846 (struct mopcode32): New struct.
847 (is_mve_okay_in_it): New function.
848 (is_mve_architecture): Likewise.
849 (arm_decode_field): Likewise.
850 (arm_decode_field_multiple): Likewise.
851 (is_mve_encoding_conflict): Likewise.
852 (is_mve_undefined): Likewise.
853 (is_mve_unpredictable): Likewise.
854 (print_mve_undefined): Likewise.
855 (print_mve_unpredictable): Likewise.
856 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
857 (print_insn_mve): New function.
858 (print_insn_thumb32): Handle MVE architecture.
859 (select_arm_features): Force thumb for Armv8.1-m Mainline.
860
3076e594
NC		 8612019-05-10 Nick Clifton <nickc@redhat.com>
862
863 PR 24538
864 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
865 end of the table prematurely.
866
387e7624
FS		 8672019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
868
869 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
870 macros for R6.
871
0067be51
AM		 8722019-05-11 Alan Modra <amodra@gmail.com>
873
874 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
875 when -Mraw is in effect.
876
42e6288f
MM		 8772019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
878
879 * aarch64-dis-2.c: Regenerate.
880 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
881 (OP_SVE_BBB): New variant set.
882 (OP_SVE_DDDD): New variant set.
883 (OP_SVE_HHH): New variant set.
884 (OP_SVE_HHHU): New variant set.
885 (OP_SVE_SSS): New variant set.
886 (OP_SVE_SSSU): New variant set.
887 (OP_SVE_SHH): New variant set.
888 (OP_SVE_SBBU): New variant set.
889 (OP_SVE_DSS): New variant set.
890 (OP_SVE_DHHU): New variant set.
891 (OP_SVE_VMV_HSD_BHS): New variant set.
892 (OP_SVE_VVU_HSD_BHS): New variant set.
893 (OP_SVE_VVVU_SD_BH): New variant set.
894 (OP_SVE_VVVU_BHSD): New variant set.
895 (OP_SVE_VVV_QHD_DBS): New variant set.
896 (OP_SVE_VVV_HSD_BHS): New variant set.
897 (OP_SVE_VVV_HSD_BHS2): New variant set.
898 (OP_SVE_VVV_BHS_HSD): New variant set.
899 (OP_SVE_VV_BHS_HSD): New variant set.
900 (OP_SVE_VVV_SD): New variant set.
901 (OP_SVE_VVU_BHS_HSD): New variant set.
902 (OP_SVE_VZVV_SD): New variant set.
903 (OP_SVE_VZVV_BH): New variant set.
904 (OP_SVE_VZV_SD): New variant set.
905 (aarch64_opcode_table): Add sve2 instructions.
906
28ed815a
MM		 9072019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
908
909 * aarch64-asm-2.c: Regenerated.
910 * aarch64-dis-2.c: Regenerated.
911 * aarch64-opc-2.c: Regenerated.
912 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
913 for SVE_SHLIMM_UNPRED_22.
914 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
915 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
916 operand.
917
fd1dc4a0
MM		 9182019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
919
920 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
921 sve_size_tsz_bhs iclass encode.
922 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
923 sve_size_tsz_bhs iclass decode.
924
31e36ab3
MM		 9252019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
926
927 * aarch64-asm-2.c: Regenerated.
928 * aarch64-dis-2.c: Regenerated.
929 * aarch64-opc-2.c: Regenerated.
930 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
931 for SVE_Zm4_11_INDEX.
932 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
933 (fields): Handle SVE_i2h field.
934 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
935 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
936
1be5f94f
MM		 9372019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
938
939 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
940 sve_shift_tsz_bhsd iclass encode.
941 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
942 sve_shift_tsz_bhsd iclass decode.
943
3c17238b
MM		 9442019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
945
946 * aarch64-asm-2.c: Regenerated.
947 * aarch64-dis-2.c: Regenerated.
948 * aarch64-opc-2.c: Regenerated.
949 * aarch64-asm.c (aarch64_ins_sve_shrimm):
950 (aarch64_encode_variant_using_iclass): Handle
951 sve_shift_tsz_hsd iclass encode.
952 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
953 sve_shift_tsz_hsd iclass decode.
954 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
955 for SVE_SHRIMM_UNPRED_22.
956 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
957 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
958 operand.
959
cd50a87a
MM		 9602019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
961
962 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
963 sve_size_013 iclass encode.
964 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
965 sve_size_013 iclass decode.
966
3c705960
MM		 9672019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
968
969 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
970 sve_size_bh iclass encode.
971 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
972 sve_size_bh iclass decode.
973
0a57e14f
MM		 9742019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
975
976 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
977 sve_size_sd2 iclass encode.
978 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
979 sve_size_sd2 iclass decode.
980 * aarch64-opc.c (fields): Handle SVE_sz2 field.
981 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
982
c469c864
MM		 9832019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
984
985 * aarch64-asm-2.c: Regenerated.
986 * aarch64-dis-2.c: Regenerated.
987 * aarch64-opc-2.c: Regenerated.
988 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
989 for SVE_ADDR_ZX.
990 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
991 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
992
116adc27
MM		 9932019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
994
995 * aarch64-asm-2.c: Regenerated.
996 * aarch64-dis-2.c: Regenerated.
997 * aarch64-opc-2.c: Regenerated.
998 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
999 for SVE_Zm3_11_INDEX.
1000 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1001 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1002 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1003 fields.
1004 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1005
3bd82c86
MM		 10062019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1007
1008 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1009 sve_size_hsd2 iclass encode.
1010 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1011 sve_size_hsd2 iclass decode.
1012 * aarch64-opc.c (fields): Handle SVE_size field.
1013 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1014
adccc507
MM		 10152019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1016
1017 * aarch64-asm-2.c: Regenerated.
1018 * aarch64-dis-2.c: Regenerated.
1019 * aarch64-opc-2.c: Regenerated.
1020 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1021 for SVE_IMM_ROT3.
1022 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1023 (fields): Handle SVE_rot3 field.
1024 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1025 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1026
5cd99750
MM		 10272019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1028
1029 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1030 instructions.
1031
7ce2460a
MM		 10322019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1033
1034 * aarch64-tbl.h
1035 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1036 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1037 aarch64_feature_sve2bitperm): New feature sets.
1038 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1039 for feature set addresses.
1040 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1041 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1042
41cee089
FS		 10432019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1044 Faraz Shahbazker <fshahbazker@wavecomp.com>
1045
1046 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1047 argument and set ASE_EVA_R6 appropriately.
1048 (set_default_mips_dis_options): Pass ISA to above.
1049 (parse_mips_dis_option): Likewise.
1050 * mips-opc.c (EVAR6): New macro.
1051 (mips_builtin_opcodes): Add llwpe, scwpe.
1052
b83b4b13
SD		 10532019-05-01 Sudakshina Das <sudi.das@arm.com>
1054
1055 * aarch64-asm-2.c: Regenerated.
1056 * aarch64-dis-2.c: Regenerated.
1057 * aarch64-opc-2.c: Regenerated.
1058 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1059 AARCH64_OPND_TME_UIMM16.
1060 (aarch64_print_operand): Likewise.
1061 * aarch64-tbl.h (QL_IMM_NIL): New.
1062 (TME): New.
1063 (_TME_INSN): New.
1064 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1065
4a90ce95
JD		 10662019-04-29 John Darrington <john@darrington.wattle.id.au>
1067
1068 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1069
a45328b9
AB		 10702019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1071 Faraz Shahbazker <fshahbazker@wavecomp.com>
1072
1073 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1074
d10be0cb
JD		 10752019-04-24 John Darrington <john@darrington.wattle.id.au>
1076
1077 * s12z-opc.h: Add extern "C" bracketing to help
1078 users who wish to use this interface in c++ code.
1079
a679f24e
JD		 10802019-04-24 John Darrington <john@darrington.wattle.id.au>
1081
1082 * s12z-opc.c (bm_decode): Handle bit map operations with the
1083 "reserved0" mode.
1084
32c36c3c
AV		 10852019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1086
1087 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1088 specifier. Add entries for VLDR and VSTR of system registers.
1089 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1090 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1091 of %J and %K format specifier.
1092
efd6b359
AV		 10932019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1094
1095 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1096 Add new entries for VSCCLRM instruction.
1097 (print_insn_coprocessor): Handle new %C format control code.
1098
6b0dd094
AV		 10992019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1100
1101 * arm-dis.c (enum isa): New enum.
1102 (struct sopcode32): New structure.
1103 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1104 set isa field of all current entries to ANY.
1105 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1106 Only match an entry if its isa field allows the current mode.
1107
4b5a202f
AV		 11082019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1109
1110 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1111 CLRM.
1112 (print_insn_thumb32): Add logic to print %n CLRM register list.
1113
60f993ce
AV		 11142019-04-15 Sudakshina Das <sudi.das@arm.com>
1115
1116 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1117 and %Q patterns.
1118
f6b2b12d
AV		 11192019-04-15 Sudakshina Das <sudi.das@arm.com>
1120
1121 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1122 (print_insn_thumb32): Edit the switch case for %Z.
1123
1889da70
AV		 11242019-04-15 Sudakshina Das <sudi.das@arm.com>
1125
1126 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1127
65d1bc05
AV		 11282019-04-15 Sudakshina Das <sudi.das@arm.com>
1129
1130 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1131
1caf72a5
AV		 11322019-04-15 Sudakshina Das <sudi.das@arm.com>
1133
1134 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1135
f1c7f421
AV		 11362019-04-15 Sudakshina Das <sudi.das@arm.com>
1137
1138 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1139 Arm register with r13 and r15 unpredictable.
1140 (thumb32_opcodes): New instructions for bfx and bflx.
1141
4389b29a
AV		 11422019-04-15 Sudakshina Das <sudi.das@arm.com>
1143
1144 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1145
e5d6e09e
AV		 11462019-04-15 Sudakshina Das <sudi.das@arm.com>
1147
1148 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1149
e12437dc
AV		 11502019-04-15 Sudakshina Das <sudi.das@arm.com>
1151
1152 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1153
031254f2
AV		 11542019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1155
1156 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1157
e5a557ac
JD		 11582019-04-12 John Darrington <john@darrington.wattle.id.au>
1159
1160 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1161 "optr". ("operator" is a reserved word in c++).
1162
bd7ceb8d
SD		 11632019-04-11 Sudakshina Das <sudi.das@arm.com>
1164
1165 * aarch64-opc.c (aarch64_print_operand): Add case for
1166 AARCH64_OPND_Rt_SP.
1167 (verify_constraints): Likewise.
1168 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1169 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1170 to accept Rt|SP as first operand.
1171 (AARCH64_OPERANDS): Add new Rt_SP.
1172 * aarch64-asm-2.c: Regenerated.
1173 * aarch64-dis-2.c: Regenerated.
1174 * aarch64-opc-2.c: Regenerated.
1175
e54010f1
SD		 11762019-04-11 Sudakshina Das <sudi.das@arm.com>
1177
1178 * aarch64-asm-2.c: Regenerated.
1179 * aarch64-dis-2.c: Likewise.
1180 * aarch64-opc-2.c: Likewise.
1181 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1182
7e96e219
RS		 11832019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1184
1185 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1186
6f2791d5
L		 11872019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1188
1189 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1190 * i386-init.h: Regenerated.
1191
e392bad3
AM		 11922019-04-07 Alan Modra <amodra@gmail.com>
1193
1194 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1195 op_separator to control printing of spaces, comma and parens
1196 rather than need_comma, need_paren and spaces vars.
1197
dffaa15c
AM		 11982019-04-07 Alan Modra <amodra@gmail.com>
1199
1200 PR 24421
1201 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1202 (print_insn_neon, print_insn_arm): Likewise.
1203
d6aab7a1
XG		 12042019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1205
1206 * i386-dis-evex.h (evex_table): Updated to support BF16
1207 instructions.
1208 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1209 and EVEX_W_0F3872_P_3.
1210 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1211 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1212 * i386-opc.h (enum): Add CpuAVX512_BF16.
1213 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1214 * i386-opc.tbl: Add AVX512 BF16 instructions.
1215 * i386-init.h: Regenerated.
1216 * i386-tbl.h: Likewise.
1217
66e85460
AM		 12182019-04-05 Alan Modra <amodra@gmail.com>
1219
1220 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1221 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1222 to favour printing of "-" branch hint when using the "y" bit.
1223 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1224
c2b1c275
AM		 12252019-04-05 Alan Modra <amodra@gmail.com>
1226
1227 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1228 opcode until first operand is output.
1229
aae9718e
PB		 12302019-04-04 Peter Bergner <bergner@linux.ibm.com>
1231
1232 PR gas/24349
1233 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1234 (valid_bo_post_v2): Add support for 'at' branch hints.
1235 (insert_bo): Only error on branch on ctr.
1236 (get_bo_hint_mask): New function.
1237 (insert_boe): Add new 'branch_taken' formal argument. Add support
1238 for inserting 'at' branch hints.
1239 (extract_boe): Add new 'branch_taken' formal argument. Add support
1240 for extracting 'at' branch hints.
1241 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1242 (BOE): Delete operand.
1243 (BOM, BOP): New operands.
1244 (RM): Update value.
1245 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1246 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1247 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1248 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1249 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1250 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1251 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1252 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1253 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1254 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1255 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1256 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1257 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1258 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1259 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1260 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1261 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1262 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1263 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1264 bttarl+>: New extended mnemonics.
1265
96a86c01
AM		 12662019-03-28 Alan Modra <amodra@gmail.com>
1267
1268 PR 24390
1269 * ppc-opc.c (BTF): Define.
1270 (powerpc_opcodes): Use for mtfsb*.
1271 * ppc-dis.c (print_insn_powerpc): Print fields with both
1272 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1273
796d6298
TC		 12742019-03-25 Tamar Christina <tamar.christina@arm.com>
1275
1276 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1277 (mapping_symbol_for_insn): Implement new algorithm.
1278 (print_insn): Remove duplicate code.
1279
60df3720
TC		 12802019-03-25 Tamar Christina <tamar.christina@arm.com>
1281
1282 * aarch64-dis.c (print_insn_aarch64):
1283 Implement override.
1284
51457761
TC		 12852019-03-25 Tamar Christina <tamar.christina@arm.com>
1286
1287 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1288 order.
1289
53b2f36b
TC		 12902019-03-25 Tamar Christina <tamar.christina@arm.com>
1291
1292 * aarch64-dis.c (last_stop_offset): New.
1293 (print_insn_aarch64): Use stop_offset.
1294
89199bb5
L		 12952019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1296
1297 PR gas/24359
1298 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1299 CPU_ANY_AVX2_FLAGS.
1300 * i386-init.h: Regenerated.
1301
97ed31ae
L		 13022019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1303
1304 PR gas/24348
1305 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1306 vmovdqu16, vmovdqu32 and vmovdqu64.
1307 * i386-tbl.h: Regenerated.
1308
0919bfe9
AK		 13092019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1310
1311 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1312 from vstrszb, vstrszh, and vstrszf.
1313
13142019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1315
1316 * s390-opc.txt: Add instruction descriptions.
1317
21820ebe
JW		 13182019-02-08 Jim Wilson <jimw@sifive.com>
1319
1320 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1321 <bne>: Likewise.
1322
f7dd2fb2
TC		 13232019-02-07 Tamar Christina <tamar.christina@arm.com>
1324
1325 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1326
6456d318
TC		 13272019-02-07 Tamar Christina <tamar.christina@arm.com>
1328
1329 PR binutils/23212
1330 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1331 * aarch64-opc.c (verify_elem_sd): New.
1332 (fields): Add FLD_sz entr.
1333 * aarch64-tbl.h (_SIMD_INSN): New.
1334 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1335 fmulx scalar and vector by element isns.
1336
4a83b610
NC		 13372019-02-07 Nick Clifton <nickc@redhat.com>
1338
1339 * po/sv.po: Updated Swedish translation.
1340
fc60b8c8
AK		 13412019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1342
1343 * s390-mkopc.c (main): Accept arch13 as cpu string.
1344 * s390-opc.c: Add new instruction formats and instruction opcode
1345 masks.
1346 * s390-opc.txt: Add new arch13 instructions.
1347
e10620d3
TC		 13482019-01-25 Sudakshina Das <sudi.das@arm.com>
1349
1350 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1351 (aarch64_opcode): Change encoding for stg, stzg
1352 st2g and st2zg.
1353 * aarch64-asm-2.c: Regenerated.
1354 * aarch64-dis-2.c: Regenerated.
1355 * aarch64-opc-2.c: Regenerated.
1356
20a4ca55
SD		 13572019-01-25 Sudakshina Das <sudi.das@arm.com>
1358
1359 * aarch64-asm-2.c: Regenerated.
1360 * aarch64-dis-2.c: Likewise.
1361 * aarch64-opc-2.c: Likewise.
1362 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1363
550fd7bf
SD		 13642019-01-25 Sudakshina Das <sudi.das@arm.com>
1365 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1366
1367 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1368 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1369 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1370 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1371 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1372 case for ldstgv_indexed.
1373 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1374 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1375 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1376 * aarch64-asm-2.c: Regenerated.
1377 * aarch64-dis-2.c: Regenerated.
1378 * aarch64-opc-2.c: Regenerated.
1379
d9938630
NC		 13802019-01-23 Nick Clifton <nickc@redhat.com>
1381
1382 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1383
375cd423
NC		 13842019-01-21 Nick Clifton <nickc@redhat.com>
1385
1386 * po/de.po: Updated German translation.
1387 * po/uk.po: Updated Ukranian translation.
1388
57299f48
CX		 13892019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1390 * mips-dis.c (mips_arch_choices): Fix typo in
1391 gs464, gs464e and gs264e descriptors.
1392
f48dfe41
NC		 13932019-01-19 Nick Clifton <nickc@redhat.com>
1394
1395 * configure: Regenerate.
1396 * po/opcodes.pot: Regenerate.
1397
f974f26c
NC		 13982018-06-24 Nick Clifton <nickc@redhat.com>
1399
1400 2.32 branch created.
1401
39f286cd
JD		 14022019-01-09 John Darrington <john@darrington.wattle.id.au>
1403
448b8ca8
JD		 1404 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
1405 if it is null.
1406 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 1407 zero.
1408
3107326d
AP		 14092019-01-09 Andrew Paprocki <andrew@ishiboo.com>
1410
1411 * configure: Regenerate.
1412
7e9ca91e
AM		 14132019-01-07 Alan Modra <amodra@gmail.com>
1414
1415 * configure: Regenerate.
1416 * po/POTFILES.in: Regenerate.
1417
ef1ad42b
JD		 14182019-01-03 John Darrington <john@darrington.wattle.id.au>
1419
1420 * s12z-opc.c: New file.
1421 * s12z-opc.h: New file.
1422 * s12z-dis.c: Removed all code not directly related to display
1423 of instructions. Used the interface provided by the new files
1424 instead.
1425 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 1426 * Makefile.in: Regenerate.
ef1ad42b 1427 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 1428 * configure: Regenerate.
ef1ad42b 1429
82704155
AM		 14302019-01-01 Alan Modra <amodra@gmail.com>
1431
1432 Update year range in copyright notice of all files.
1433
d5c04e1b 1434For older changes see ChangeLog-2018
3499769a 1435\f
d5c04e1b 1436Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 1437
1438Copying and distribution of this file, with or without modification,
1439are permitted in any medium without royalty provided the copyright
1440notice and this notice are preserved.
1441
1442Local Variables:
1443mode: change-log
1444left-margin: 8
1445fill-column: 74
1446version-control: never
1447End:
GDB Binutils - Deliverables
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