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PR gprof/13325
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
c3732716
JB		 12011-10-24 Julian Brown <julian@codesourcery.com>
2
3 * m68k-opc.c (m68k_opcodes): Fix entries for ColdFire moveml.
4
9cae27dc
AK		 52011-10-21 Jan Glauber <jang@linux.vnet.ibm.com>
6
7 * s390-opc.txt: Add CPUMF instructions.
8
a415b1cd
JB		 92011-10-18 Jie Zhang <jie@codesourcery.com>
10 Julian Brown <julian@codesourcery.com>
11
12 * arm-dis.c (print_insn_arm): Explicitly specify rotation if needed.
13
d5698657
NC		 142011-10-10 Nick Clifton <nickc@redhat.com>
15
16 * po/es.po: Updated Spanish translation.
17 * po/fi.po: Updated Finnish translation.
18
989993d8
JB		 192011-09-28 Jan Beulich <jbeulich@suse.com>
20
21 * ppc-opc.c (insert_nbi, insert_rbx, FRAp, FRBp, FRSp, FRTp, NBI, RAX,
22 RBX): New.
23 (insert_bo, insert_boe): Reject bcctr with bit 2 in bo unset.
24 (powerpc_opcodes): Use RAX for second and RBXC for third operand of
25 lswx. Use NBI for third operand of lswi. Use FRTp for first operand of
26 lfdp and lfdpx. Use FRSp for first operand of stfdp and stfdpx, and
27 mark them as invalid on POWER7. Use FRTp, FRAp, and FRBp repsectively
28 on DFP quad instructions.
29
92a7795b
DM		 302011-09-27 David S. Miller <davem@davemloft.net>
31
32 * sparc-opc.c (sparc_opcodes): Fix random instruction to write
33 to a float instead of an integer register.
34
e91d1076
DM		 352011-09-26 David S. Miller <davem@davemloft.net>
36
37 * sparc-opc.c (sparc_opcodes): Add integer multiply-add
38 instructions.
39
9e8c70f9
DM		 402011-09-21 David S. Miller <davem@davemloft.net>
41
42 * sparc-opc.c (sparc_opcodes): Annotate table with HWCAP flag
43 bits. Fix "fchksm16" mnemonic.
44
9bf29d72
DM		 452011-09-08 Mark Fortescue <mark@mtfhpc.demon.co.uk>
46
47 The changes below bring 'mov' and 'ticc' instructions into line
48 with the V8 SPARC Architecture Manual.
49 * sparc-opc.c (sparc_opcodes): Add entry for 'ticc imm + regrs1'.
50 * sparc-opc.c (sparc_opcodes): Add alias entries for
51 'mov regrs2,%asrX'; 'mov regrs2,%y'; 'mov regrs2,%prs';
52 'mov regrs2,%wim' and 'mov regrs2,%tbr'.
53 * sparc-opc.c (sparc_opcodes): Move/Change entries for
54 'mov imm,%asrX'; 'mov imm,%y'; 'mov imm,%prs'; 'mov imm,%wim'
55 and 'mov imm,%tbr'.
56 * sparc-opc.c (sparc_opcodes): Add wr alias entries to match above
57 mov aliases.
58
8dbb9eb3
DM		 59 * sparc-opc.c (sparc_opcodes): Add entry for 'save simm13,regrs1,regrd'
60 This has been reported as being accepted by the Sun assmebler.
61
cdf49201
DM		 622011-09-08 David S. Miller <davem@davemloft.net>
63
64 * sparc-opc.c (pdistn): Destination is integer not float register.
65
96e67898
AS		 662011-09-07 Andreas Schwab <schwab@linux-m68k.org>
67
b2ea1829 68 PR gas/13145
96e67898
AS		 69 * m68k-opc.c: Use "y" in moveml pattern for mcfisa_a.
70
7cf80422
NC		 712011-08-26 Nick Clifton <nickc@redhat.com>
72
73 * po/es.po: Updated Spanish translation.
74
dc15e575
NC		 752011-08-22 Nick Clifton <nickc@redhat.com>
76
77 * Makefile.am (CPUDIR): Redfine to point to top level cpu
78 directory.
79 (stamp-frv): Use CPUDIR.
80 (stamp-iq2000): Likewise.
81 (stamp-lm32): Likewise.
82 (stamp-m32c): Likewise.
83 (stamp-mt): Likewise.
84 (stamp-xc16x): Likewise.
85 * Makefile.in: Regenerate.
86
dec0624d
MR		 872011-08-09 Chao-ying Fu <fu@mips.com>
88 Maciej W. Rozycki <macro@codesourcery.com>
89
90 * mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2"
91 and "mips64r2".
92 (print_insn_args, print_insn_micromips): Handle MCU.
93 * micromips-opc.c (MC): New macro.
94 (micromips_opcodes): Add "aclr", "aset" and "iret".
95 * mips-opc.c (MC): New macro.
96 (mips_builtin_opcodes): Add "aclr", "aset" and "iret".
97
2b0c8b40
MR		 982011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
99
100 * micromips-opc.c (MOD_mb, MOD_mc, MOD_md): Remove macros.
101 (MOD_me, MOD_mf, MOD_mg, MOD_mhi, MOD_mj, MOD_ml): Likewise.
102 (MOD_mm, MOD_mn, MOD_mp, MOD_mq, MOD_sp): Likewise.
103 (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf): New macros.
104 (RD_mg, WR_mhi, RD_mj, WR_mj, RD_ml, RD_mmn): Likewise.
105 (RD_mp, WR_mp, RD_mq, RD_sp, WR_sp): Likewise.
106 (WR_s): Update macro.
107 (micromips_opcodes): Update register use flags of: "addiu",
108 "addiupc", "addiur1sp", "addiur2", "addius5", "addiusp", "addu",
109 "and", "andi", "beq", "beqz", "bne", "bnez", "di", "ei", "j",
110 "jalr", "jalrs", "jr", "jraddiusp", "jrc", "lbu", "lhu", "li",
111 "lui", "lw", "lwm", "mfhi", "mflo", "move", "movep", "not",
112 "nor", "or", "ori", "sb", "sh", "sll", "srl", "subu", "sw",
113 "swm" and "xor" instructions.
114
ea783ef3
DM		 1152011-08-05 David S. Miller <davem@davemloft.net>
116
117 * sparc-dis.c (v9a_ast_reg_names): Add "cps".
118 (X_RS3): New macro.
119 (print_insn_sparc): Handle '4', '5', and '(' format codes.
120 Accept %asr numbers below 28.
121 * sparc-opc.c (sparc_opcodes): Add entries for HPC and VIS3
122 instructions.
123
3929df09
QN		 1242011-08-02 Quentin Neill <quentin.neill@amd.com>
125
126 * i386-dis.c (xop_table): Remove spurious bextr insn.
127
d7921315
L		 1282011-08-01 H.J. Lu <hongjiu.lu@intel.com>
129
130 PR ld/13048
131 * i386-dis.c (print_insn): Optimize info->mach check.
132
00f51a41
L		 1332011-08-01 H.J. Lu <hongjiu.lu@intel.com>
134
135 PR gas/13046
136 * i386-opc.tbl: Add Disp32S to 64bit call.
137 * i386-tbl.h: Regenerated.
138
df58fc94
RS		 1392011-07-24 Chao-ying Fu <fu@mips.com>
140 Maciej W. Rozycki <macro@codesourcery.com>
141
142 * micromips-opc.c: New file.
143 * mips-dis.c (micromips_to_32_reg_b_map): New array.
144 (micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise.
145 (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise.
146 (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise.
147 (micromips_to_32_reg_q_map): Likewise.
148 (micromips_imm_b_map, micromips_imm_c_map): Likewise.
149 (micromips_ase): New variable.
150 (is_micromips): New function.
151 (set_default_mips_dis_options): Handle microMIPS ASE.
152 (print_insn_micromips): New function.
153 (is_compressed_mode_p): Likewise.
154 (_print_insn_mips): Handle microMIPS instructions.
155 * Makefile.am (CFILES): Add micromips-opc.c.
156 * configure.in (bfd_mips_arch): Add micromips-opc.lo.
157 * Makefile.in: Regenerate.
158 * configure: Regenerate.
159
160 * mips-dis.c (micromips_to_32_reg_h_map): New variable.
161 (micromips_to_32_reg_i_map): Likewise.
162 (micromips_to_32_reg_m_map): Likewise.
163 (micromips_to_32_reg_n_map): New macro.
164
bcd530a7
RS		 1652011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
166
167 * mips-opc.c (NODS): New macro.
168 (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
169 (DSP_VOLA): Likewise.
170 (mips_builtin_opcodes): Add NODS annotation to "deret" and
171 "eret". Replace INSN_SYNC with NODS throughout. Use NODS in
172 place of TRAP for "wait", "waiti" and "yield".
173 * mips16-opc.c (NODS): New macro.
174 (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
175 (mips16_opcodes): Use NODS in place of TRAP for "jalrc", "jrc",
176 "restore" and "save".
177
7a9068fe
L		 1782011-07-22 H.J. Lu <hongjiu.lu@intel.com>
179
180 * configure.in: Handle bfd_k1om_arch.
181 * configure: Regenerated.
182
183 * disassemble.c (disassembler): Handle bfd_k1om_arch.
184
185 * i386-dis.c (print_insn): Handle bfd_mach_k1om and
186 bfd_mach_k1om_intel_syntax.
187
188 * i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to
189 ~(CpuL1OM|CpuK1OM). Add CPU_K1OM_FLAGS.
190 (cpu_flags): Add CpuK1OM.
191
192 * i386-opc.h (CpuK1OM): New.
193 (i386_cpu_flags): Add cpuk1om.
194
195 * i386-init.h: Regenerated.
196 * i386-tbl.h: Likewise.
197
1b93226d
NC		 1982011-07-12 Nick Clifton <nickc@redhat.com>
199
200 * arm-dis.c (print_insn_arm): Revert previous, undocumented,
201 accidental change.
202
5d73b1f1
NC		 2032011-07-01 Nick Clifton <nickc@redhat.com>
204
205 PR binutils/12329
206 * avr-dis.c (avr_operand): Fix disassembly of ELPM, LPM and SPM
207 insns using post-increment addressing.
208
182ae480
L		 2092011-06-30 H.J. Lu <hongjiu.lu@intel.com>
210
211 * i386-dis.c (vex_len_table): Update rorxS.
212
4cb0953d
L		 2132011-06-30 H.J. Lu <hongjiu.lu@intel.com>
214
215 AVX Programming Reference (June, 2011)
216 * i386-dis.c (vex_len_table): Correct rorxS.
217
218 * i386-opc.tbl: Correct rorx.
219 * i386-tbl.h: Regenerated.
220
906efcbc
L		 2212011-06-29 H.J. Lu <hongjiu.lu@intel.com>
222
223 * tilegx-opc.c (find_opcode): Replace "index" with "i".
224 * tilepro-opc.c (find_opcode): Likewise.
225
ceb94aa5
RS		 2262011-06-29 Richard Sandiford <rdsandiford@googlemail.com>
227
228 * mips16-opc.c (jalrc, jrc): Move earlier in file.
229
f7002f42
L		 2302011-06-21 H.J. Lu <hongjiu.lu@intel.com>
231
232 * i386-dis.c (prefix_table): Re-indent PREFIX_VEX_0F388C and
233 PREFIX_VEX_0F388E.
234
56300268
AS		 2352011-06-17 Andreas Schwab <schwab@redhat.com>
236
237 * Makefile.am (MAINTAINERCLEANFILES): Move s390-opc.tab ...
238 (MOSTLYCLEANFILES): ... here.
239 * Makefile.in: Regenerate.
240
bcf2cf9f
AM		 2412011-06-14 Alan Modra <amodra@gmail.com>
242
243 * Makefile.in: Regenerate.
244
aa137e4d
NC		 2452011-06-13 Walter Lee <walt@tilera.com>
246
247 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c,
248 tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c.
249 * Makefile.in: Regenerate.
250 * configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch.
251 * configure: Regenerate.
252 * disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro.
253 * po/POTFILES.in: Regenerate.
254 * tilegx-dis.c: New file.
255 * tilegx-opc.c: New file.
256 * tilepro-dis.c: New file.
257 * tilepro-opc.c: New file.
258
6c30d220
L		 2592011-06-10 H.J. Lu <hongjiu.lu@intel.com>
260
261 AVX Programming Reference (June, 2011)
262 * i386-dis.c (XMGatherQ): New.
263 * i386-dis.c (EXxmm_mb): New.
264 (EXxmm_mb): Likewise.
265 (EXxmm_mw): Likewise.
266 (EXxmm_md): Likewise.
267 (EXxmm_mq): Likewise.
268 (EXxmmdw): Likewise.
269 (EXxmmqd): Likewise.
270 (VexGatherQ): Likewise.
271 (MVexVSIBDWpX): Likewise.
272 (MVexVSIBQWpX): Likewise.
273 (xmm_mb_mode): Likewise.
274 (xmm_mw_mode): Likewise.
275 (xmm_md_mode): Likewise.
276 (xmm_mq_mode): Likewise.
277 (xmmdw_mode): Likewise.
278 (xmmqd_mode): Likewise.
279 (ymmxmm_mode): Likewise.
280 (vex_vsib_d_w_dq_mode): Likewise.
281 (vex_vsib_q_w_dq_mode): Likewise.
282 (MOD_VEX_0F385A_PREFIX_2): Likewise.
283 (MOD_VEX_0F388C_PREFIX_2): Likewise.
284 (MOD_VEX_0F388E_PREFIX_2): Likewise.
285 (PREFIX_0F3882): Likewise.
286 (PREFIX_VEX_0F3816): Likewise.
287 (PREFIX_VEX_0F3836): Likewise.
288 (PREFIX_VEX_0F3845): Likewise.
289 (PREFIX_VEX_0F3846): Likewise.
290 (PREFIX_VEX_0F3847): Likewise.
291 (PREFIX_VEX_0F3858): Likewise.
292 (PREFIX_VEX_0F3859): Likewise.
293 (PREFIX_VEX_0F385A): Likewise.
294 (PREFIX_VEX_0F3878): Likewise.
295 (PREFIX_VEX_0F3879): Likewise.
296 (PREFIX_VEX_0F388C): Likewise.
297 (PREFIX_VEX_0F388E): Likewise.
298 (PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise.
299 (PREFIX_VEX_0F38F5): Likewise.
300 (PREFIX_VEX_0F38F6): Likewise.
301 (PREFIX_VEX_0F3A00): Likewise.
302 (PREFIX_VEX_0F3A01): Likewise.
303 (PREFIX_VEX_0F3A02): Likewise.
304 (PREFIX_VEX_0F3A38): Likewise.
305 (PREFIX_VEX_0F3A39): Likewise.
306 (PREFIX_VEX_0F3A46): Likewise.
307 (PREFIX_VEX_0F3AF0): Likewise.
308 (VEX_LEN_0F3816_P_2): Likewise.
309 (VEX_LEN_0F3819_P_2): Likewise.
310 (VEX_LEN_0F3836_P_2): Likewise.
311 (VEX_LEN_0F385A_P_2_M_0): Likewise.
312 (VEX_LEN_0F38F5_P_0): Likewise.
313 (VEX_LEN_0F38F5_P_1): Likewise.
314 (VEX_LEN_0F38F5_P_3): Likewise.
315 (VEX_LEN_0F38F6_P_3): Likewise.
316 (VEX_LEN_0F38F7_P_1): Likewise.
317 (VEX_LEN_0F38F7_P_2): Likewise.
318 (VEX_LEN_0F38F7_P_3): Likewise.
319 (VEX_LEN_0F3A00_P_2): Likewise.
320 (VEX_LEN_0F3A01_P_2): Likewise.
321 (VEX_LEN_0F3A38_P_2): Likewise.
322 (VEX_LEN_0F3A39_P_2): Likewise.
323 (VEX_LEN_0F3A46_P_2): Likewise.
324 (VEX_LEN_0F3AF0_P_3): Likewise.
325 (VEX_W_0F3816_P_2): Likewise.
326 (VEX_W_0F3818_P_2): Likewise.
327 (VEX_W_0F3819_P_2): Likewise.
328 (VEX_W_0F3836_P_2): Likewise.
329 (VEX_W_0F3846_P_2): Likewise.
330 (VEX_W_0F3858_P_2): Likewise.
331 (VEX_W_0F3859_P_2): Likewise.
332 (VEX_W_0F385A_P_2_M_0): Likewise.
333 (VEX_W_0F3878_P_2): Likewise.
334 (VEX_W_0F3879_P_2): Likewise.
335 (VEX_W_0F3A00_P_2): Likewise.
336 (VEX_W_0F3A01_P_2): Likewise.
337 (VEX_W_0F3A02_P_2): Likewise.
338 (VEX_W_0F3A38_P_2): Likewise.
339 (VEX_W_0F3A39_P_2): Likewise.
340 (VEX_W_0F3A46_P_2): Likewise.
341 (MOD_VEX_0F3818_PREFIX_2): Removed.
342 (MOD_VEX_0F3819_PREFIX_2): Likewise.
343 (VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise.
344 (VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise.
345 (VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise.
346 (VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise.
347 (VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise.
348 (VEX_LEN_0F3A0E_P_2): Likewise.
349 (VEX_LEN_0F3A0F_P_2): Likewise.
350 (VEX_LEN_0F3A42_P_2): Likewise.
351 (VEX_LEN_0F3A4C_P_2): Likewise.
352 (VEX_W_0F3818_P_2_M_0): Likewise.
353 (VEX_W_0F3819_P_2_M_0): Likewise.
354 (prefix_table): Updated.
355 (three_byte_table): Likewise.
356 (vex_table): Likewise.
357 (vex_len_table): Likewise.
358 (vex_w_table): Likewise.
359 (mod_table): Likewise.
360 (putop): Handle "LW".
361 (intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode,
362 xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode,
363 vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode.
364 (OP_EX): Likewise.
365 (OP_E_memory): Handle vex_vsib_d_w_dq_mode and
366 vex_vsib_q_w_dq_mode.
367 (OP_XMM): Handle vex_vsib_q_w_dq_mode.
368 (OP_VEX): Likewise.
369
370 * i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS
371 and CPU_ANY_AVX_FLAGS. Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS,
372 CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS.
373 (cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID.
374 (opcode_modifiers): Add VecSIB.
375
376 * i386-opc.h (CpuAVX2): New.
377 (CpuBMI2): Likewise.
378 (CpuLZCNT): Likewise.
379 (CpuINVPCID): Likewise.
380 (VecSIB128): Likewise.
381 (VecSIB256): Likewise.
382 (VecSIB): Likewise.
383 (i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid.
384 (i386_opcode_modifier): Add vecsib.
385
386 * i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions.
387 * i386-init.h: Regenerated.
388 * i386-tbl.h: Likewise.
389
d535accd
QN		 3902011-06-03 Quentin Neill <quentin.neill@amd.com>
391
392 * i386-gen.c (cpu_flag_init): Add CpuF16C to CPU_BDVER2_FLAGS.
393 * i386-init.h: Regenerated.
394
f8b960bc
NC		 3952011-06-03 Nick Clifton <nickc@redhat.com>
396
397 PR binutils/12752
398 * arm-dis.c (print_insn_coprocessor): Use bfd_vma type for
399 computing address offsets.
400 (print_arm_address): Likewise.
401 (print_insn_arm): Likewise.
402 (print_insn_thumb16): Likewise.
403 (print_insn_thumb32): Likewise.
404
26d97720
NS		 4052011-06-02 Jie Zhang <jie@codesourcery.com>
406 Nathan Sidwell <nathan@codesourcery.com>
407 Maciej Rozycki <macro@codesourcery.com>
408
409 * arm-dis.c (print_insn_coprocessor): Explicitly print #-0
410 as address offset.
411 (print_arm_address): Likewise. Elide positive #0 appropriately.
412 (print_insn_arm): Likewise.
413
f8b960bc
NC		 4142011-06-02 Nick Clifton <nickc@redhat.com>
415
416 PR gas/12752
417 * arm-dis.c (print_insn_thumb32): Do not sign extend addresses
418 passed to print_address_func.
419
cc643b88
NC		 4202011-06-02 Nick Clifton <nickc@redhat.com>
421
422 * arm-dis.c: Fix spelling mistakes.
423 * op/opcodes.pot: Regenerate.
424
c8fa16ed
AK		 4252011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
426
427 * s390-opc.c: Replace S390_OPERAND_REG_EVEN with
428 S390_OPERAND_REG_PAIR. Fix INSTR_RRF_0UFEF instruction type.
429 * s390-opc.txt: Fix cxr instruction type.
430
5e4b319c
AK		 4312011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
432
433 * s390-opc.c: Add new instruction types marking register pair
434 operands.
435 * s390-opc.txt: Match instructions having register pair operands
436 to the new instruction types.
437
fda544a2
NC		 4382011-05-19 Nick Clifton <nickc@redhat.com>
439
440 * v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2
441 operands.
442
4cab4add
QN		 4432011-05-10 Quentin Neill <quentin.neill@amd.com>
444
445 * i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS.
446 * i386-init.h: Regenerated.
447
b4e7b885
NC		 4482011-04-27 Nick Clifton <nickc@redhat.com>
449
450 * po/da.po: Updated Danish translation.
451
2f7f7710
AM		 4522011-04-26 Anton Blanchard <anton@samba.org>
453
454 * ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7.
455
9887672f
DD		 4562011-04-21 DJ Delorie <dj@redhat.com>
457
458 * rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs.
459 * rx-decode.c: Regenerate.
460
3251b375
L		 4612011-04-20 H.J. Lu <hongjiu.lu@intel.com>
462
463 * i386-init.h: Regenerated.
464
b13a3ca6
QN		 4652011-04-19 Quentin Neill <quentin.neill@amd.com>
466
467 * i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits
468 from bdver1 flags.
469
7d063384
NC		 4702011-04-13 Nick Clifton <nickc@redhat.com>
471
472 * v850-dis.c (disassemble): Always print a closing square brace if
473 an opening square brace was printed.
474
32a94698
NC		 4752011-04-12 Nick Clifton <nickc@redhat.com>
476
477 PR binutils/12534
478 * arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn
479 patterns.
480 (print_insn_thumb32): Handle %L.
481
d2cd1205
JB		 4822011-04-11 Julian Brown <julian@codesourcery.com>
483
484 * arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
485 (print_insn_thumb32): Add APSR bitmask support.
486
1fbaefec
PB		 4872011-04-07 Paul Carroll<pcarroll@codesourcery.com>
488
489 * arm-dis.c (print_insn): init vars moved into private_data structure.
490
67171547
MF		 4912011-03-24 Mike Frysinger <vapier@gentoo.org>
492
493 * bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic.
494
8cc66334
EW		 4952011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
496
497 * avr-dis.c (avr_operand): Add opcode_str parameter. Check for
498 post-increment to support LPM Z+ instruction. Add support for 'E'
499 constraint for DES instruction.
500 (print_insn_avr): Adjust calls to avr_operand. Rename variable.
501
34e77a92
RS		 5022011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
503
504 * arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
505
35fc36a8
RS		 5062011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
507
508 * arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
509 Use branch types instead.
510 (print_insn): Likewise.
511
0067d8fc
MR		 5122011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
513
514 * mips-opc.c (mips_builtin_opcodes): Correct register use
515 annotation of "alnv.ps".
516
3eebd5eb
MR		 5172011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
518
519 * mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
520
500cccad
MF		 5212011-02-22 Mike Frysinger <vapier@gentoo.org>
522
523 * bfin-dis.c (OUTS): Remove p NULL check and txt NUL check.
524
f5caf9f4
MF		 5252011-02-22 Mike Frysinger <vapier@gentoo.org>
526
527 * bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS.
528
e5bc4265
MF		 5292011-02-19 Mike Frysinger <vapier@gentoo.org>
530
531 * bfin-dis.c (saved_state): Mark static. Change a[01]x to ax[] and
532 a[01]w to aw[]. Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1,
533 av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts,
534 exception, end_of_registers, msize, memory, bfd_mach.
535 (CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG,
536 LB0REG, LC1REG, LT1REG, LB1REG): Delete
537 (AXREG, AWREG, LCREG, LTREG, LBREG): Define.
538 (get_allreg): Change to new defines. Fallback to abort().
539
602427c4
MF		 5402011-02-14 Mike Frysinger <vapier@gentoo.org>
541
542 * bfin-dis.c: Add whitespace/parenthesis where needed.
543
298c1ec2
MF		 5442011-02-14 Mike Frysinger <vapier@gentoo.org>
545
546 * bfin-dis.c (decode_LoopSetup_0): Return when reg is greater
547 than 7.
548
822ce8ee
RW		 5492011-02-13 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
550
551 * configure: Regenerate.
552
13c02f06
MF		 5532011-02-13 Mike Frysinger <vapier@gentoo.org>
554
555 * bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg.
556
4db66394
MF		 5572011-02-13 Mike Frysinger <vapier@gentoo.org>
558
559 * bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1. Output
560 dregs only when P is set, and dregs_lo otherwise.
561
36f44611
MF		 5622011-02-13 Mike Frysinger <vapier@gentoo.org>
563
564 * bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code.
565
9805c0a5
MF		 5662011-02-12 Mike Frysinger <vapier@gentoo.org>
567
568 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT.
569
43a6aa65
MF		 5702011-02-12 Mike Frysinger <vapier@gentoo.org>
571
572 * bfin-dis.c (machine_registers): Delete REG_GP.
573 (reg_names): Delete "GP".
574 (decode_allregs): Change REG_GP to REG_LASTREG.
575
26bb3ddd
MF		 5762011-02-12 Mike Frysinger <vapier@gentoo.org>
577
89c0d58c
MR		 578 * bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2,
579 M_IH, M_IU): Delete.
26bb3ddd 580
69b8ea4a
MF		 5812011-02-11 Mike Frysinger <vapier@gentoo.org>
582
583 * bfin-dis.c (reg_names): Add const.
584 (decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte,
585 decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs,
586 decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits,
587 decode_counters, decode_allregs): Likewise.
588
42d5f9c6
MS		 5892011-02-09 Michael Snyder <msnyder@vmware.com>
590
56300268 591 * i386-dis.c (OP_J): Parenthesize expression to prevent
42d5f9c6
MS		 592 truncated addresses.
593 (print_insn): Fix indentation off-by-one.
594
4be0c941
NC		 5952011-02-01 Nick Clifton <nickc@redhat.com>
596
597 * po/da.po: Updated Danish translation.
598
6b069ee7
AM		 5992011-01-21 Dave Murphy <davem@devkitpro.org>
600
601 * ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.
602
e3949f17
L		 6032011-01-18 H.J. Lu <hongjiu.lu@intel.com>
604
605 * i386-dis.c (sIbT): New.
606 (b_T_mode): Likewise.
607 (dis386): Replace sIb with sIbT on "pushT".
608 (x86_64_table): Replace sIb with Ib on "aam" and "aad".
609 (OP_sI): Handle b_T_mode. Properly sign-extend byte.
610
752573b2
JK		 6112011-01-18 Jan Kratochvil <jan.kratochvil@redhat.com>
612
613 * i386-init.h: Regenerated.
614 * i386-tbl.h: Regenerated
615
2a2a0f38
QN		 6162011-01-17 Quentin Neill <quentin.neill@amd.com>
617
618 * i386-dis.c (REG_XOP_TBM_01): New.
619 (REG_XOP_TBM_02): New.
620 (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
621 (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
622 entries, and add bextr instruction.
623
624 * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
625 (cpu_flags): Add CpuTBM.
626
627 * i386-opc.h (CpuTBM) New.
628 (i386_cpu_flags): Add bit cputbm.
629
630 * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
631 blcs, blsfill, blsic, t1mskc, and tzmsk.
632
90d6ff62
DD		 6332011-01-12 DJ Delorie <dj@redhat.com>
634
635 * rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.
636
c95354ed
MX		 6372011-01-11 Mingjie Xing <mingjie.xing@gmail.com>
638
639 * mips-dis.c (print_insn_args): Adjust the value to print the real
640 offset for "+c" argument.
641
f7465604
NC		 6422011-01-10 Nick Clifton <nickc@redhat.com>
643
644 * po/da.po: Updated Danish translation.
645
639e30d2
NS		 6462011-01-05 Nathan Sidwell <nathan@codesourcery.com>
647
648 * arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
649
f12dc422
L		 6502011-01-04 H.J. Lu <hongjiu.lu@intel.com>
651
652 * i386-dis.c (REG_VEX_38F3): New.
653 (PREFIX_0FBC): Likewise.
654 (PREFIX_VEX_38F2): Likewise.
655 (PREFIX_VEX_38F3_REG_1): Likewise.
656 (PREFIX_VEX_38F3_REG_2): Likewise.
657 (PREFIX_VEX_38F3_REG_3): Likewise.
658 (PREFIX_VEX_38F7): Likewise.
659 (VEX_LEN_38F2_P_0): Likewise.
660 (VEX_LEN_38F3_R_1_P_0): Likewise.
661 (VEX_LEN_38F3_R_2_P_0): Likewise.
662 (VEX_LEN_38F3_R_3_P_0): Likewise.
663 (VEX_LEN_38F7_P_0): Likewise.
664 (dis386_twobyte): Use PREFIX_0FBC.
665 (reg_table): Add REG_VEX_38F3.
666 (prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2,
667 PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2,
668 PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7.
669 (vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and
670 PREFIX_VEX_38F7.
671 (vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0,
672 VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and
673 VEX_LEN_38F7_P_0.
674
675 * i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS.
676 (cpu_flags): Add CpuBMI.
677
678 * i386-opc.h (CpuBMI): New.
679 (i386_cpu_flags): Add cpubmi.
680
681 * i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt.
682 * i386-init.h: Regenerated.
683 * i386-tbl.h: Likewise.
684
cb21baef
L		 6852011-01-04 H.J. Lu <hongjiu.lu@intel.com>
686
687 * i386-dis.c (VexGdq): New.
688 (OP_VEX): Handle dq_mode.
689
0db46eb4
L		 6902011-01-01 H.J. Lu <hongjiu.lu@intel.com>
691
692 * i386-gen.c (process_copyright): Update copyright to 2011.
693
9e9e0820 694For older changes see ChangeLog-2010
252b5132
RH		 695\f
696Local Variables:
2f6d2f85
NC		 697mode: change-log
698left-margin: 8
699fill-column: 74
252b5132
RH		 700version-control: never
701End:
GDB Binutils - Deliverables
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