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* mips-dis.c (print_insn_micromips): Rename local variable iprintf
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
0c7533d3
PM		 12011-11-25 Pierre Muller <muller@ics.u-strasbg.fr>
2
3 * mips-dis.c (print_insn_micromips): Rename local variable iprintf
4 to infprintf to avoid shadow warning.
5
eda81062
NC		 62011-11-25 Nick Clifton <nickc@redhat.com>
7
8 * po/it.po: Updated Italian translation.
9
514f48bb
MR		 102011-11-16 Maciej W. Rozycki <macro@codesourcery.com>
11
12 * micromips-opc.c (micromips_opcodes): Use NODS rather than TRAP
13 for "alnv.ps".
14
207d428d
NC		 152011-11-02 Nick Clifton <nickc@redhat.com>
16
17 * po/it.po: New Italian translation.
18 * configure.in (ALL_LINGUAS): Add it.
19 * configure: Regenerate.
20 * po/opcodes.pot: Regenerate.
21
99c513f6
DD		 222011-11-01 DJ Delorie <dj@redhat.com>
23
24 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add rl78-decode.c and
25 rl78-dis.c.
26 (MAINTAINERCLEANFILES): Add rl78-decode.c.
27 (rl78-decode.c): New rule, built from rl78-decode.opc and opc2c.
28 * Makefile.in: Regenerate.
29 * configure.in: Add bfd_rl78_arch case.
30 * configure: Regenerate.
31 * disassemble.c: Define ARCH_rl78.
32 (disassembler): Add ARCH_rl78 case.
33 * rl78-decode.c: New file.
34 * rl78-decode.opc: New file.
35 * rl78-dis.c: New file.
36
a08fc942
PB		 372011-10-27 Peter Bergner <bergner@vnet.ibm.com>
38
39 * ppc-opc.c (powerpc_opcodes) <drrndq, drrndq., dtstexq, dctqpq,
40 dctqpq., dctfixq, dctfixq., dxexq, dxexq., dtstsfq, dcffixq, dcffixq.,
41 diexq, diexq.>: Use FRT, FRA, FRB and FRBp repsectively on DFP quad
42 instructions.
43
f6dd4781
NC		 442011-10-26 Nick Clifton <nickc@redhat.com>
45
46 PR binutils/13348
47 * i386-dis.c (print_insn): Fix testing of array subscript.
48
56b13185
JR		 492011-10-26 Joern Rennecke <joern.rennecke@embecosm.com>
50
51 * disassemble.c (ARCH_epiphany): Move into alphasorted spot.
fd936b4c
JR		 52 * epiphany-asm.c, epiphany-opc.h: Regenerate.
53
cfb8c092
NC		 542011-10-25 Joern Rennecke <joern.rennecke@embecosm.com>
55
56 * Makefile.am (HFILES): Add epiphany-desc.h and epiphany-opc.h .
57 (TARGET_LIBOPCODES_CFILES): Add epiphany-asm.c, epiphany-desc.c,
58 epiphany-dis.c, epiphany-ibld.c and epiphany-opc.c .
59 (CLEANFILES): Add stamp-epiphany.
60 (EPIPHANY_DEPS): Set. Make CGEN-generated Epiphany files depend on it.
61 (stamp-epiphany): New rule.
62 * configure.in: Handle bfd_epiphany_arch.
63 * disassemble.c (ARCH_epiphany): Define.
64 (disassembler): Handle bfd_arch_epiphany.
65 * epiphany-asm.c: New file.
66 * epiphany-desc.c: New file.
67 * epiphany-desc.h: New file.
68 * epiphany-dis.c: New file.
69 * epiphany-ibld.c: New file.
70 * epiphany-opc.c: New file.
71 * epiphany-opc.h: New file.
72 * Makefile.in: Regenerate.
73 * configure: Regenerate.
74 * po/POTFILES.in: Regenerate.
75 * po/opcodes.pot: Regenerate.
76
c3732716
JB		 772011-10-24 Julian Brown <julian@codesourcery.com>
78
79 * m68k-opc.c (m68k_opcodes): Fix entries for ColdFire moveml.
80
9cae27dc
AK		 812011-10-21 Jan Glauber <jang@linux.vnet.ibm.com>
82
83 * s390-opc.txt: Add CPUMF instructions.
84
a415b1cd
JB		 852011-10-18 Jie Zhang <jie@codesourcery.com>
86 Julian Brown <julian@codesourcery.com>
87
88 * arm-dis.c (print_insn_arm): Explicitly specify rotation if needed.
89
d5698657
NC		 902011-10-10 Nick Clifton <nickc@redhat.com>
91
92 * po/es.po: Updated Spanish translation.
93 * po/fi.po: Updated Finnish translation.
94
989993d8
JB		 952011-09-28 Jan Beulich <jbeulich@suse.com>
96
97 * ppc-opc.c (insert_nbi, insert_rbx, FRAp, FRBp, FRSp, FRTp, NBI, RAX,
98 RBX): New.
99 (insert_bo, insert_boe): Reject bcctr with bit 2 in bo unset.
100 (powerpc_opcodes): Use RAX for second and RBXC for third operand of
101 lswx. Use NBI for third operand of lswi. Use FRTp for first operand of
102 lfdp and lfdpx. Use FRSp for first operand of stfdp and stfdpx, and
103 mark them as invalid on POWER7. Use FRTp, FRAp, and FRBp repsectively
104 on DFP quad instructions.
105
92a7795b
DM		 1062011-09-27 David S. Miller <davem@davemloft.net>
107
108 * sparc-opc.c (sparc_opcodes): Fix random instruction to write
109 to a float instead of an integer register.
110
e91d1076
DM		 1112011-09-26 David S. Miller <davem@davemloft.net>
112
113 * sparc-opc.c (sparc_opcodes): Add integer multiply-add
114 instructions.
115
9e8c70f9
DM		 1162011-09-21 David S. Miller <davem@davemloft.net>
117
118 * sparc-opc.c (sparc_opcodes): Annotate table with HWCAP flag
119 bits. Fix "fchksm16" mnemonic.
120
9bf29d72
DM		 1212011-09-08 Mark Fortescue <mark@mtfhpc.demon.co.uk>
122
123 The changes below bring 'mov' and 'ticc' instructions into line
124 with the V8 SPARC Architecture Manual.
125 * sparc-opc.c (sparc_opcodes): Add entry for 'ticc imm + regrs1'.
126 * sparc-opc.c (sparc_opcodes): Add alias entries for
127 'mov regrs2,%asrX'; 'mov regrs2,%y'; 'mov regrs2,%prs';
128 'mov regrs2,%wim' and 'mov regrs2,%tbr'.
129 * sparc-opc.c (sparc_opcodes): Move/Change entries for
130 'mov imm,%asrX'; 'mov imm,%y'; 'mov imm,%prs'; 'mov imm,%wim'
131 and 'mov imm,%tbr'.
132 * sparc-opc.c (sparc_opcodes): Add wr alias entries to match above
133 mov aliases.
134
8dbb9eb3
DM		 135 * sparc-opc.c (sparc_opcodes): Add entry for 'save simm13,regrs1,regrd'
136 This has been reported as being accepted by the Sun assmebler.
137
cdf49201
DM		 1382011-09-08 David S. Miller <davem@davemloft.net>
139
140 * sparc-opc.c (pdistn): Destination is integer not float register.
141
96e67898
AS		 1422011-09-07 Andreas Schwab <schwab@linux-m68k.org>
143
b2ea1829 144 PR gas/13145
96e67898
AS		 145 * m68k-opc.c: Use "y" in moveml pattern for mcfisa_a.
146
7cf80422
NC		 1472011-08-26 Nick Clifton <nickc@redhat.com>
148
149 * po/es.po: Updated Spanish translation.
150
dc15e575
NC		 1512011-08-22 Nick Clifton <nickc@redhat.com>
152
153 * Makefile.am (CPUDIR): Redfine to point to top level cpu
154 directory.
155 (stamp-frv): Use CPUDIR.
156 (stamp-iq2000): Likewise.
157 (stamp-lm32): Likewise.
158 (stamp-m32c): Likewise.
159 (stamp-mt): Likewise.
160 (stamp-xc16x): Likewise.
161 * Makefile.in: Regenerate.
162
dec0624d
MR		 1632011-08-09 Chao-ying Fu <fu@mips.com>
164 Maciej W. Rozycki <macro@codesourcery.com>
165
166 * mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2"
167 and "mips64r2".
168 (print_insn_args, print_insn_micromips): Handle MCU.
169 * micromips-opc.c (MC): New macro.
170 (micromips_opcodes): Add "aclr", "aset" and "iret".
171 * mips-opc.c (MC): New macro.
172 (mips_builtin_opcodes): Add "aclr", "aset" and "iret".
173
2b0c8b40
MR		 1742011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
175
176 * micromips-opc.c (MOD_mb, MOD_mc, MOD_md): Remove macros.
177 (MOD_me, MOD_mf, MOD_mg, MOD_mhi, MOD_mj, MOD_ml): Likewise.
178 (MOD_mm, MOD_mn, MOD_mp, MOD_mq, MOD_sp): Likewise.
179 (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf): New macros.
180 (RD_mg, WR_mhi, RD_mj, WR_mj, RD_ml, RD_mmn): Likewise.
181 (RD_mp, WR_mp, RD_mq, RD_sp, WR_sp): Likewise.
182 (WR_s): Update macro.
183 (micromips_opcodes): Update register use flags of: "addiu",
184 "addiupc", "addiur1sp", "addiur2", "addius5", "addiusp", "addu",
185 "and", "andi", "beq", "beqz", "bne", "bnez", "di", "ei", "j",
186 "jalr", "jalrs", "jr", "jraddiusp", "jrc", "lbu", "lhu", "li",
187 "lui", "lw", "lwm", "mfhi", "mflo", "move", "movep", "not",
188 "nor", "or", "ori", "sb", "sh", "sll", "srl", "subu", "sw",
189 "swm" and "xor" instructions.
190
ea783ef3
DM		 1912011-08-05 David S. Miller <davem@davemloft.net>
192
193 * sparc-dis.c (v9a_ast_reg_names): Add "cps".
194 (X_RS3): New macro.
195 (print_insn_sparc): Handle '4', '5', and '(' format codes.
196 Accept %asr numbers below 28.
197 * sparc-opc.c (sparc_opcodes): Add entries for HPC and VIS3
198 instructions.
199
3929df09
QN		 2002011-08-02 Quentin Neill <quentin.neill@amd.com>
201
202 * i386-dis.c (xop_table): Remove spurious bextr insn.
203
d7921315
L		 2042011-08-01 H.J. Lu <hongjiu.lu@intel.com>
205
206 PR ld/13048
207 * i386-dis.c (print_insn): Optimize info->mach check.
208
00f51a41
L		 2092011-08-01 H.J. Lu <hongjiu.lu@intel.com>
210
211 PR gas/13046
212 * i386-opc.tbl: Add Disp32S to 64bit call.
213 * i386-tbl.h: Regenerated.
214
df58fc94
RS		 2152011-07-24 Chao-ying Fu <fu@mips.com>
216 Maciej W. Rozycki <macro@codesourcery.com>
217
218 * micromips-opc.c: New file.
219 * mips-dis.c (micromips_to_32_reg_b_map): New array.
220 (micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise.
221 (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise.
222 (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise.
223 (micromips_to_32_reg_q_map): Likewise.
224 (micromips_imm_b_map, micromips_imm_c_map): Likewise.
225 (micromips_ase): New variable.
226 (is_micromips): New function.
227 (set_default_mips_dis_options): Handle microMIPS ASE.
228 (print_insn_micromips): New function.
229 (is_compressed_mode_p): Likewise.
230 (_print_insn_mips): Handle microMIPS instructions.
231 * Makefile.am (CFILES): Add micromips-opc.c.
232 * configure.in (bfd_mips_arch): Add micromips-opc.lo.
233 * Makefile.in: Regenerate.
234 * configure: Regenerate.
235
236 * mips-dis.c (micromips_to_32_reg_h_map): New variable.
237 (micromips_to_32_reg_i_map): Likewise.
238 (micromips_to_32_reg_m_map): Likewise.
239 (micromips_to_32_reg_n_map): New macro.
240
bcd530a7
RS		 2412011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
242
243 * mips-opc.c (NODS): New macro.
244 (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
245 (DSP_VOLA): Likewise.
246 (mips_builtin_opcodes): Add NODS annotation to "deret" and
247 "eret". Replace INSN_SYNC with NODS throughout. Use NODS in
248 place of TRAP for "wait", "waiti" and "yield".
249 * mips16-opc.c (NODS): New macro.
250 (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
251 (mips16_opcodes): Use NODS in place of TRAP for "jalrc", "jrc",
252 "restore" and "save".
253
7a9068fe
L		 2542011-07-22 H.J. Lu <hongjiu.lu@intel.com>
255
256 * configure.in: Handle bfd_k1om_arch.
257 * configure: Regenerated.
258
259 * disassemble.c (disassembler): Handle bfd_k1om_arch.
260
261 * i386-dis.c (print_insn): Handle bfd_mach_k1om and
262 bfd_mach_k1om_intel_syntax.
263
264 * i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to
265 ~(CpuL1OM|CpuK1OM). Add CPU_K1OM_FLAGS.
266 (cpu_flags): Add CpuK1OM.
267
268 * i386-opc.h (CpuK1OM): New.
269 (i386_cpu_flags): Add cpuk1om.
270
271 * i386-init.h: Regenerated.
272 * i386-tbl.h: Likewise.
273
1b93226d
NC		 2742011-07-12 Nick Clifton <nickc@redhat.com>
275
276 * arm-dis.c (print_insn_arm): Revert previous, undocumented,
277 accidental change.
278
5d73b1f1
NC		 2792011-07-01 Nick Clifton <nickc@redhat.com>
280
281 PR binutils/12329
282 * avr-dis.c (avr_operand): Fix disassembly of ELPM, LPM and SPM
283 insns using post-increment addressing.
284
182ae480
L		 2852011-06-30 H.J. Lu <hongjiu.lu@intel.com>
286
287 * i386-dis.c (vex_len_table): Update rorxS.
288
4cb0953d
L		 2892011-06-30 H.J. Lu <hongjiu.lu@intel.com>
290
291 AVX Programming Reference (June, 2011)
292 * i386-dis.c (vex_len_table): Correct rorxS.
293
294 * i386-opc.tbl: Correct rorx.
295 * i386-tbl.h: Regenerated.
296
906efcbc
L		 2972011-06-29 H.J. Lu <hongjiu.lu@intel.com>
298
299 * tilegx-opc.c (find_opcode): Replace "index" with "i".
300 * tilepro-opc.c (find_opcode): Likewise.
301
ceb94aa5
RS		 3022011-06-29 Richard Sandiford <rdsandiford@googlemail.com>
303
304 * mips16-opc.c (jalrc, jrc): Move earlier in file.
305
f7002f42
L		 3062011-06-21 H.J. Lu <hongjiu.lu@intel.com>
307
308 * i386-dis.c (prefix_table): Re-indent PREFIX_VEX_0F388C and
309 PREFIX_VEX_0F388E.
310
56300268
AS		 3112011-06-17 Andreas Schwab <schwab@redhat.com>
312
313 * Makefile.am (MAINTAINERCLEANFILES): Move s390-opc.tab ...
314 (MOSTLYCLEANFILES): ... here.
315 * Makefile.in: Regenerate.
316
bcf2cf9f
AM		 3172011-06-14 Alan Modra <amodra@gmail.com>
318
319 * Makefile.in: Regenerate.
320
aa137e4d
NC		 3212011-06-13 Walter Lee <walt@tilera.com>
322
323 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c,
324 tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c.
325 * Makefile.in: Regenerate.
326 * configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch.
327 * configure: Regenerate.
328 * disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro.
329 * po/POTFILES.in: Regenerate.
330 * tilegx-dis.c: New file.
331 * tilegx-opc.c: New file.
332 * tilepro-dis.c: New file.
333 * tilepro-opc.c: New file.
334
6c30d220
L		 3352011-06-10 H.J. Lu <hongjiu.lu@intel.com>
336
337 AVX Programming Reference (June, 2011)
338 * i386-dis.c (XMGatherQ): New.
339 * i386-dis.c (EXxmm_mb): New.
340 (EXxmm_mb): Likewise.
341 (EXxmm_mw): Likewise.
342 (EXxmm_md): Likewise.
343 (EXxmm_mq): Likewise.
344 (EXxmmdw): Likewise.
345 (EXxmmqd): Likewise.
346 (VexGatherQ): Likewise.
347 (MVexVSIBDWpX): Likewise.
348 (MVexVSIBQWpX): Likewise.
349 (xmm_mb_mode): Likewise.
350 (xmm_mw_mode): Likewise.
351 (xmm_md_mode): Likewise.
352 (xmm_mq_mode): Likewise.
353 (xmmdw_mode): Likewise.
354 (xmmqd_mode): Likewise.
355 (ymmxmm_mode): Likewise.
356 (vex_vsib_d_w_dq_mode): Likewise.
357 (vex_vsib_q_w_dq_mode): Likewise.
358 (MOD_VEX_0F385A_PREFIX_2): Likewise.
359 (MOD_VEX_0F388C_PREFIX_2): Likewise.
360 (MOD_VEX_0F388E_PREFIX_2): Likewise.
361 (PREFIX_0F3882): Likewise.
362 (PREFIX_VEX_0F3816): Likewise.
363 (PREFIX_VEX_0F3836): Likewise.
364 (PREFIX_VEX_0F3845): Likewise.
365 (PREFIX_VEX_0F3846): Likewise.
366 (PREFIX_VEX_0F3847): Likewise.
367 (PREFIX_VEX_0F3858): Likewise.
368 (PREFIX_VEX_0F3859): Likewise.
369 (PREFIX_VEX_0F385A): Likewise.
370 (PREFIX_VEX_0F3878): Likewise.
371 (PREFIX_VEX_0F3879): Likewise.
372 (PREFIX_VEX_0F388C): Likewise.
373 (PREFIX_VEX_0F388E): Likewise.
374 (PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise.
375 (PREFIX_VEX_0F38F5): Likewise.
376 (PREFIX_VEX_0F38F6): Likewise.
377 (PREFIX_VEX_0F3A00): Likewise.
378 (PREFIX_VEX_0F3A01): Likewise.
379 (PREFIX_VEX_0F3A02): Likewise.
380 (PREFIX_VEX_0F3A38): Likewise.
381 (PREFIX_VEX_0F3A39): Likewise.
382 (PREFIX_VEX_0F3A46): Likewise.
383 (PREFIX_VEX_0F3AF0): Likewise.
384 (VEX_LEN_0F3816_P_2): Likewise.
385 (VEX_LEN_0F3819_P_2): Likewise.
386 (VEX_LEN_0F3836_P_2): Likewise.
387 (VEX_LEN_0F385A_P_2_M_0): Likewise.
388 (VEX_LEN_0F38F5_P_0): Likewise.
389 (VEX_LEN_0F38F5_P_1): Likewise.
390 (VEX_LEN_0F38F5_P_3): Likewise.
391 (VEX_LEN_0F38F6_P_3): Likewise.
392 (VEX_LEN_0F38F7_P_1): Likewise.
393 (VEX_LEN_0F38F7_P_2): Likewise.
394 (VEX_LEN_0F38F7_P_3): Likewise.
395 (VEX_LEN_0F3A00_P_2): Likewise.
396 (VEX_LEN_0F3A01_P_2): Likewise.
397 (VEX_LEN_0F3A38_P_2): Likewise.
398 (VEX_LEN_0F3A39_P_2): Likewise.
399 (VEX_LEN_0F3A46_P_2): Likewise.
400 (VEX_LEN_0F3AF0_P_3): Likewise.
401 (VEX_W_0F3816_P_2): Likewise.
402 (VEX_W_0F3818_P_2): Likewise.
403 (VEX_W_0F3819_P_2): Likewise.
404 (VEX_W_0F3836_P_2): Likewise.
405 (VEX_W_0F3846_P_2): Likewise.
406 (VEX_W_0F3858_P_2): Likewise.
407 (VEX_W_0F3859_P_2): Likewise.
408 (VEX_W_0F385A_P_2_M_0): Likewise.
409 (VEX_W_0F3878_P_2): Likewise.
410 (VEX_W_0F3879_P_2): Likewise.
411 (VEX_W_0F3A00_P_2): Likewise.
412 (VEX_W_0F3A01_P_2): Likewise.
413 (VEX_W_0F3A02_P_2): Likewise.
414 (VEX_W_0F3A38_P_2): Likewise.
415 (VEX_W_0F3A39_P_2): Likewise.
416 (VEX_W_0F3A46_P_2): Likewise.
417 (MOD_VEX_0F3818_PREFIX_2): Removed.
418 (MOD_VEX_0F3819_PREFIX_2): Likewise.
419 (VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise.
420 (VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise.
421 (VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise.
422 (VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise.
423 (VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise.
424 (VEX_LEN_0F3A0E_P_2): Likewise.
425 (VEX_LEN_0F3A0F_P_2): Likewise.
426 (VEX_LEN_0F3A42_P_2): Likewise.
427 (VEX_LEN_0F3A4C_P_2): Likewise.
428 (VEX_W_0F3818_P_2_M_0): Likewise.
429 (VEX_W_0F3819_P_2_M_0): Likewise.
430 (prefix_table): Updated.
431 (three_byte_table): Likewise.
432 (vex_table): Likewise.
433 (vex_len_table): Likewise.
434 (vex_w_table): Likewise.
435 (mod_table): Likewise.
436 (putop): Handle "LW".
437 (intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode,
438 xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode,
439 vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode.
440 (OP_EX): Likewise.
441 (OP_E_memory): Handle vex_vsib_d_w_dq_mode and
442 vex_vsib_q_w_dq_mode.
443 (OP_XMM): Handle vex_vsib_q_w_dq_mode.
444 (OP_VEX): Likewise.
445
446 * i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS
447 and CPU_ANY_AVX_FLAGS. Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS,
448 CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS.
449 (cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID.
450 (opcode_modifiers): Add VecSIB.
451
452 * i386-opc.h (CpuAVX2): New.
453 (CpuBMI2): Likewise.
454 (CpuLZCNT): Likewise.
455 (CpuINVPCID): Likewise.
456 (VecSIB128): Likewise.
457 (VecSIB256): Likewise.
458 (VecSIB): Likewise.
459 (i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid.
460 (i386_opcode_modifier): Add vecsib.
461
462 * i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions.
463 * i386-init.h: Regenerated.
464 * i386-tbl.h: Likewise.
465
d535accd
QN		 4662011-06-03 Quentin Neill <quentin.neill@amd.com>
467
468 * i386-gen.c (cpu_flag_init): Add CpuF16C to CPU_BDVER2_FLAGS.
469 * i386-init.h: Regenerated.
470
f8b960bc
NC		 4712011-06-03 Nick Clifton <nickc@redhat.com>
472
473 PR binutils/12752
474 * arm-dis.c (print_insn_coprocessor): Use bfd_vma type for
475 computing address offsets.
476 (print_arm_address): Likewise.
477 (print_insn_arm): Likewise.
478 (print_insn_thumb16): Likewise.
479 (print_insn_thumb32): Likewise.
480
26d97720
NS		 4812011-06-02 Jie Zhang <jie@codesourcery.com>
482 Nathan Sidwell <nathan@codesourcery.com>
483 Maciej Rozycki <macro@codesourcery.com>
484
485 * arm-dis.c (print_insn_coprocessor): Explicitly print #-0
486 as address offset.
487 (print_arm_address): Likewise. Elide positive #0 appropriately.
488 (print_insn_arm): Likewise.
489
f8b960bc
NC		 4902011-06-02 Nick Clifton <nickc@redhat.com>
491
492 PR gas/12752
493 * arm-dis.c (print_insn_thumb32): Do not sign extend addresses
494 passed to print_address_func.
495
cc643b88
NC		 4962011-06-02 Nick Clifton <nickc@redhat.com>
497
498 * arm-dis.c: Fix spelling mistakes.
499 * op/opcodes.pot: Regenerate.
500
c8fa16ed
AK		 5012011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
502
503 * s390-opc.c: Replace S390_OPERAND_REG_EVEN with
504 S390_OPERAND_REG_PAIR. Fix INSTR_RRF_0UFEF instruction type.
505 * s390-opc.txt: Fix cxr instruction type.
506
5e4b319c
AK		 5072011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
508
509 * s390-opc.c: Add new instruction types marking register pair
510 operands.
511 * s390-opc.txt: Match instructions having register pair operands
512 to the new instruction types.
513
fda544a2
NC		 5142011-05-19 Nick Clifton <nickc@redhat.com>
515
516 * v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2
517 operands.
518
4cab4add
QN		 5192011-05-10 Quentin Neill <quentin.neill@amd.com>
520
521 * i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS.
522 * i386-init.h: Regenerated.
523
b4e7b885
NC		 5242011-04-27 Nick Clifton <nickc@redhat.com>
525
526 * po/da.po: Updated Danish translation.
527
2f7f7710
AM		 5282011-04-26 Anton Blanchard <anton@samba.org>
529
530 * ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7.
531
9887672f
DD		 5322011-04-21 DJ Delorie <dj@redhat.com>
533
534 * rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs.
535 * rx-decode.c: Regenerate.
536
3251b375
L		 5372011-04-20 H.J. Lu <hongjiu.lu@intel.com>
538
539 * i386-init.h: Regenerated.
540
b13a3ca6
QN		 5412011-04-19 Quentin Neill <quentin.neill@amd.com>
542
543 * i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits
544 from bdver1 flags.
545
7d063384
NC		 5462011-04-13 Nick Clifton <nickc@redhat.com>
547
548 * v850-dis.c (disassemble): Always print a closing square brace if
549 an opening square brace was printed.
550
32a94698
NC		 5512011-04-12 Nick Clifton <nickc@redhat.com>
552
553 PR binutils/12534
554 * arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn
555 patterns.
556 (print_insn_thumb32): Handle %L.
557
d2cd1205
JB		 5582011-04-11 Julian Brown <julian@codesourcery.com>
559
560 * arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
561 (print_insn_thumb32): Add APSR bitmask support.
562
1fbaefec
PB		 5632011-04-07 Paul Carroll<pcarroll@codesourcery.com>
564
565 * arm-dis.c (print_insn): init vars moved into private_data structure.
566
67171547
MF		 5672011-03-24 Mike Frysinger <vapier@gentoo.org>
568
569 * bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic.
570
8cc66334
EW		 5712011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
572
573 * avr-dis.c (avr_operand): Add opcode_str parameter. Check for
574 post-increment to support LPM Z+ instruction. Add support for 'E'
575 constraint for DES instruction.
576 (print_insn_avr): Adjust calls to avr_operand. Rename variable.
577
34e77a92
RS		 5782011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
579
580 * arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
581
35fc36a8
RS		 5822011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
583
584 * arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
585 Use branch types instead.
586 (print_insn): Likewise.
587
0067d8fc
MR		 5882011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
589
590 * mips-opc.c (mips_builtin_opcodes): Correct register use
591 annotation of "alnv.ps".
592
3eebd5eb
MR		 5932011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
594
595 * mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
596
500cccad
MF		 5972011-02-22 Mike Frysinger <vapier@gentoo.org>
598
599 * bfin-dis.c (OUTS): Remove p NULL check and txt NUL check.
600
f5caf9f4
MF		 6012011-02-22 Mike Frysinger <vapier@gentoo.org>
602
603 * bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS.
604
e5bc4265
MF		 6052011-02-19 Mike Frysinger <vapier@gentoo.org>
606
607 * bfin-dis.c (saved_state): Mark static. Change a[01]x to ax[] and
608 a[01]w to aw[]. Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1,
609 av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts,
610 exception, end_of_registers, msize, memory, bfd_mach.
611 (CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG,
612 LB0REG, LC1REG, LT1REG, LB1REG): Delete
613 (AXREG, AWREG, LCREG, LTREG, LBREG): Define.
614 (get_allreg): Change to new defines. Fallback to abort().
615
602427c4
MF		 6162011-02-14 Mike Frysinger <vapier@gentoo.org>
617
618 * bfin-dis.c: Add whitespace/parenthesis where needed.
619
298c1ec2
MF		 6202011-02-14 Mike Frysinger <vapier@gentoo.org>
621
622 * bfin-dis.c (decode_LoopSetup_0): Return when reg is greater
623 than 7.
624
822ce8ee
RW		 6252011-02-13 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
626
627 * configure: Regenerate.
628
13c02f06
MF		 6292011-02-13 Mike Frysinger <vapier@gentoo.org>
630
631 * bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg.
632
4db66394
MF		 6332011-02-13 Mike Frysinger <vapier@gentoo.org>
634
635 * bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1. Output
636 dregs only when P is set, and dregs_lo otherwise.
637
36f44611
MF		 6382011-02-13 Mike Frysinger <vapier@gentoo.org>
639
640 * bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code.
641
9805c0a5
MF		 6422011-02-12 Mike Frysinger <vapier@gentoo.org>
643
644 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT.
645
43a6aa65
MF		 6462011-02-12 Mike Frysinger <vapier@gentoo.org>
647
648 * bfin-dis.c (machine_registers): Delete REG_GP.
649 (reg_names): Delete "GP".
650 (decode_allregs): Change REG_GP to REG_LASTREG.
651
26bb3ddd
MF		 6522011-02-12 Mike Frysinger <vapier@gentoo.org>
653
89c0d58c
MR		 654 * bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2,
655 M_IH, M_IU): Delete.
26bb3ddd 656
69b8ea4a
MF		 6572011-02-11 Mike Frysinger <vapier@gentoo.org>
658
659 * bfin-dis.c (reg_names): Add const.
660 (decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte,
661 decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs,
662 decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits,
663 decode_counters, decode_allregs): Likewise.
664
42d5f9c6
MS		 6652011-02-09 Michael Snyder <msnyder@vmware.com>
666
56300268 667 * i386-dis.c (OP_J): Parenthesize expression to prevent
42d5f9c6
MS		 668 truncated addresses.
669 (print_insn): Fix indentation off-by-one.
670
4be0c941
NC		 6712011-02-01 Nick Clifton <nickc@redhat.com>
672
673 * po/da.po: Updated Danish translation.
674
6b069ee7
AM		 6752011-01-21 Dave Murphy <davem@devkitpro.org>
676
677 * ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.
678
e3949f17
L		 6792011-01-18 H.J. Lu <hongjiu.lu@intel.com>
680
681 * i386-dis.c (sIbT): New.
682 (b_T_mode): Likewise.
683 (dis386): Replace sIb with sIbT on "pushT".
684 (x86_64_table): Replace sIb with Ib on "aam" and "aad".
685 (OP_sI): Handle b_T_mode. Properly sign-extend byte.
686
752573b2
JK		 6872011-01-18 Jan Kratochvil <jan.kratochvil@redhat.com>
688
689 * i386-init.h: Regenerated.
690 * i386-tbl.h: Regenerated
691
2a2a0f38
QN		 6922011-01-17 Quentin Neill <quentin.neill@amd.com>
693
694 * i386-dis.c (REG_XOP_TBM_01): New.
695 (REG_XOP_TBM_02): New.
696 (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
697 (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
698 entries, and add bextr instruction.
699
700 * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
701 (cpu_flags): Add CpuTBM.
702
703 * i386-opc.h (CpuTBM) New.
704 (i386_cpu_flags): Add bit cputbm.
705
706 * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
707 blcs, blsfill, blsic, t1mskc, and tzmsk.
708
90d6ff62
DD		 7092011-01-12 DJ Delorie <dj@redhat.com>
710
711 * rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.
712
c95354ed
MX		 7132011-01-11 Mingjie Xing <mingjie.xing@gmail.com>
714
715 * mips-dis.c (print_insn_args): Adjust the value to print the real
716 offset for "+c" argument.
717
f7465604
NC		 7182011-01-10 Nick Clifton <nickc@redhat.com>
719
720 * po/da.po: Updated Danish translation.
721
639e30d2
NS		 7222011-01-05 Nathan Sidwell <nathan@codesourcery.com>
723
724 * arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
725
f12dc422
L		 7262011-01-04 H.J. Lu <hongjiu.lu@intel.com>
727
728 * i386-dis.c (REG_VEX_38F3): New.
729 (PREFIX_0FBC): Likewise.
730 (PREFIX_VEX_38F2): Likewise.
731 (PREFIX_VEX_38F3_REG_1): Likewise.
732 (PREFIX_VEX_38F3_REG_2): Likewise.
733 (PREFIX_VEX_38F3_REG_3): Likewise.
734 (PREFIX_VEX_38F7): Likewise.
735 (VEX_LEN_38F2_P_0): Likewise.
736 (VEX_LEN_38F3_R_1_P_0): Likewise.
737 (VEX_LEN_38F3_R_2_P_0): Likewise.
738 (VEX_LEN_38F3_R_3_P_0): Likewise.
739 (VEX_LEN_38F7_P_0): Likewise.
740 (dis386_twobyte): Use PREFIX_0FBC.
741 (reg_table): Add REG_VEX_38F3.
742 (prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2,
743 PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2,
744 PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7.
745 (vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and
746 PREFIX_VEX_38F7.
747 (vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0,
748 VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and
749 VEX_LEN_38F7_P_0.
750
751 * i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS.
752 (cpu_flags): Add CpuBMI.
753
754 * i386-opc.h (CpuBMI): New.
755 (i386_cpu_flags): Add cpubmi.
756
757 * i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt.
758 * i386-init.h: Regenerated.
759 * i386-tbl.h: Likewise.
760
cb21baef
L		 7612011-01-04 H.J. Lu <hongjiu.lu@intel.com>
762
763 * i386-dis.c (VexGdq): New.
764 (OP_VEX): Handle dq_mode.
765
0db46eb4
L		 7662011-01-01 H.J. Lu <hongjiu.lu@intel.com>
767
768 * i386-gen.c (process_copyright): Update copyright to 2011.
769
9e9e0820 770For older changes see ChangeLog-2010
252b5132
RH		 771\f
772Local Variables:
2f6d2f85
NC		 773mode: change-log
774left-margin: 8
775fill-column: 74
252b5132
RH		 776version-control: never
777End:
GDB Binutils - Deliverables
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