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2005-11-02 Andrew Stubbs <andrew.stubbs@st.com>
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
9a2ff3f5
AM		 12005-10-31 Alan Modra <amodra@bigpond.net.au>
2
3 * arm-dis.c (print_insn): Warning fix.
4
9e5169a8
L		 52005-10-30 H.J. Lu <hongjiu.lu@intel.com>
6
7 * Makefile.am: Run "make dep-am".
8 * Makefile.in: Regenerated.
9
10 * dep-in.sed: Replace " ./" with " ".
11
fb53f5a8
DB		 122005-10-28 Dave Brolley <brolley@redhat.com>
13
14 * All CGEN-generated sources: Regenerate.
15
16 Contribute the following changes:
17 2005-09-19 Dave Brolley <brolley@redhat.com>
18
19 * disassemble.c (disassemble_init_for_target): Add 'break' to case for
20 bfd_arch_tic4x. Use cgen_bitset_create and cgen_bitset_set for
21 bfd_arch_m32c case.
22
23 2005-02-16 Dave Brolley <brolley@redhat.com>
24
25 * cgen-dis.in: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
26 cgen_isa_mask_* to cgen_bitset_*.
27 * cgen-opc.c: Likewise.
28
29 2003-11-28 Richard Sandiford <rsandifo@redhat.com>
30
31 * cgen-dis.in (print_insn_@arch@): Fix comparison with cached isas.
32 * *-dis.c: Regenerate.
33
34 2003-06-05 DJ Delorie <dj@redhat.com>
35
36 * cgen-dis.in (print_insn_@arch@): Copy prev_isas, don't assign
37 it, as it may point to a reused buffer. Set prev_isas when we
38 change cpus.
39
40 2002-12-13 Dave Brolley <brolley@redhat.com>
41
42 * cgen-opc.c (cgen_isa_mask_create): New support function for
43 CGEN_ISA_MASK.
44 (cgen_isa_mask_init): Ditto.
45 (cgen_isa_mask_clear): Ditto.
46 (cgen_isa_mask_add): Ditto.
47 (cgen_isa_mask_set): Ditto.
48 (cgen_isa_supported): Ditto.
49 (cgen_isa_mask_compare): Ditto.
50 (cgen_isa_mask_intersection): Ditto.
51 (cgen_isa_mask_copy): Ditto.
52 (cgen_isa_mask_combine): Ditto.
53 * cgen-dis.in (libiberty.h): #include it.
54 (isas): Renamed from 'isa' and now (CGEN_ISA_MASK *).
55 (print_insn_@arch@): Use CGEN_ISA_MASK and support functions.
56 * Makefile.am (CGENDEPS): Add utils-cgen.scm and attrs.scm.
57 * Makefile.in: Regenerated.
58
c6552317
DD		 592005-10-27 DJ Delorie <dj@redhat.com>
60
61 * m32c-asm.c: Regenerate.
62 * m32c-desc.c: Regenerate.
63 * m32c-desc.h: Regenerate.
64 * m32c-dis.c: Regenerate.
65 * m32c-ibld.c: Regenerate.
66 * m32c-opc.c: Regenerate.
67 * m32c-opc.h: Regenerate.
68
f75eb1c0
DD		 692005-10-26 DJ Delorie <dj@redhat.com>
70
71 * m32c-asm.c: Regenerate.
72 * m32c-desc.c: Regenerate.
73 * m32c-desc.h: Regenerate.
74 * m32c-dis.c: Regenerate.
75 * m32c-ibld.c: Regenerate.
76 * m32c-opc.c: Regenerate.
77 * m32c-opc.h: Regenerate.
78
f1022c90
PB		 792005-10-26 Paul Brook <paul@codesourcery.com>
80
81 * arm-dis.c (arm_opcodes): Correct "sel" entry.
82
e277c00b
AM		 832005-10-26 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
84
85 * m32r-asm.c: Regenerate.
86
92e0a941
DD		 872005-10-25 DJ Delorie <dj@redhat.com>
88
89 * m32c-asm.c: Regenerate.
90 * m32c-desc.c: Regenerate.
91 * m32c-desc.h: Regenerate.
92 * m32c-dis.c: Regenerate.
93 * m32c-ibld.c: Regenerate.
94 * m32c-opc.c: Regenerate.
95 * m32c-opc.h: Regenerate.
96
3c9b82ba
NC		 972005-10-25 Arnold Metselaar <arnold.metselaar@planet.nl>
98
99 * configure.in: Add target architecture bfd_arch_z80.
100 * configure: Regenerated.
101 * disassemble.c (disassembler)<ARCH_z80>: Add case
102 bfd_arch_z80.
103 * z80-dis.c: New file.
104
3caac5b8
AM		 1052005-10-25 Alan Modra <amodra@bigpond.net.au>
106
107 * po/POTFILES.in: Regenerate.
108 * po/opcodes.pot: Regenerate.
109
6a2375c6
JB		 1102005-10-24 Jan Beulich <jbeulich@novell.com>
111
112 * ia64-asmtab.c: Regenerate.
113
a1a280bb
DD		 1142005-10-21 DJ Delorie <dj@redhat.com>
115
116 * m32c-asm.c: Regenerate.
117 * m32c-desc.c: Regenerate.
118 * m32c-desc.h: Regenerate.
119 * m32c-dis.c: Regenerate.
120 * m32c-ibld.c: Regenerate.
121 * m32c-opc.c: Regenerate.
122 * m32c-opc.h: Regenerate.
123
b7d48530
NC		 1242005-10-21 Nick Clifton <nickc@redhat.com>
125
126 * bfin-dis.c: Tidy up code, removing redundant constructs.
127
8dd744b6
MS		 1282005-10-19 Martin Schwidefsky <schwidefsky@de.ibm.com>
129
130 * s390-opc.txt: Add unnormalized hfp multiply and multiply-and-add
131 instructions.
132
e74eb924
NC		 1332005-10-18 Nick Clifton <nickc@redhat.com>
134
135 * m32r-asm.c: Regenerate after updating m32r.opc.
136
471e4e36
JZ		 1372005-10-18 Jie Zhang <jie.zhang@analog.com>
138
139 * bfin-dis.c (print_insn_bfin): Do proper endian transform when
140 reading instruction from memory.
141
5e03663f
NC		 1422005-10-18 Nick Clifton <nickc@redhat.com>
143
144 * m32r-asm.c: Regenerate after updating m32r.opc.
145
ab7c9a26
NC		 1462005-10-14 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
147
148 * m32r-asm.c: Regenerate after updating m32r.opc.
149
19590ef7
RE		 1502005-10-08 James Lemke <jim@wasabisystems.com>
151
152 * arm-dis.c (coprocessor_opcodes): Fix mask for various Maverick CDP
153 operations.
154
6edfbbad
DJ		 1552005-10-06 Daniel Jacobowitz <dan@codesourcery.com>
156
157 * ppc-dis.c (struct dis_private): Remove.
158 (powerpc_dialect): Avoid aliasing warnings.
159 (print_insn_big_powerpc, print_insn_little_powerpc): Likewise.
160
095f2843
NC		 1612005-09-30 Nick Clifton <nickc@redhat.com>
162
163 * po/ga.po: New Irish translation.
164 * configure.in (ALL_LINGUAS): Add "ga".
165 * configure: Regenerate.
166
fdd3b9b3
L		 1672005-09-30 H.J. Lu <hongjiu.lu@intel.com>
168
169 * Makefile.am: Run "make dep-am".
170 * Makefile.in: Regenerated.
171 * aclocal.m4: Likewise.
172 * configure: Likewise.
173
4b7f6baa
CM		 1742005-09-30 Catherine Moore <clm@cm00re.com>
175
176 * Makefile.am: Bfin support.
177 * Makefile.in: Regenerated.
178 * aclocal.m4: Regenerated.
179 * bfin-dis.c: New file.
180 * configure.in: Bfin support.
181 * configure: Regenerated.
182 * disassemble.c (ARCH_bfin): Define.
183 (disassembler): Add case for bfd_arch_bfin.
184
1a114b12
JB		 1852005-09-28 Jan Beulich <jbeulich@novell.com>
186
187 * i386-dis.c (stack_v_mode): Renamed from branch_v_mode.
188 (indirEv): Use it.
189 (stackEv): New.
190 (Ob64, Ov64): Rename to Ob, Ov. Delete unused original definitions.
191 (dis386): Document and use new 'V' meta character. Use it for
192 single-byte push/pop opcode forms. Use stackEv for mod-r/m push/pop
193 opcode forms. Correct typo in 'pop ss'. Replace Ob64/Ov64 by Ob/Ov.
194 (putop): 'q' suffix for 'T' and 'U' meta depends on DFLAG. Mark
195 data prefix as used whenever DFLAG was examined. Handle 'V'.
196 (intel_operand_size): Use stack_v_mode.
197 (OP_E): Use stack_v_mode, but handle only the special case of
198 64-bit mode without operand size override here; fall through to
199 v_mode case otherwise.
200 (OP_REG): Special case rAX_reg ... rDI_reg only when 64-bit mode
201 and no operand size override is present.
202 (OP_J): Use get32s for obtaining the displacement also when rex64
203 is present.
204
3eb17e6b
PB		 2052005-09-08 Paul Brook <paul@codesourcery.com>
206
207 * arm-dis.c (arm_opcodes, thumb32_opcodes): Rename smi to smc.
208
61cc0267
CF		 2092005-09-06 Chao-ying Fu <fu@mips.com>
210
211 * mips-opc.c (MT32): New define.
212 (mips_builtin_opcodes): Move "bc0f", "bc0fl", "bc0t", "bc0tl" to the
213 bottom to avoid opcode collision with "mftr" and "mttr".
214 Add MT instructions.
215 * mips-dis.c (mips_arch_choices): Enable INSN_MT for mips32r2.
216 (print_insn_args): Add supports for +t, +T, !, $, *, &, g operand
217 formats.
218
b13dd07a
PB		 2192005-09-02 Paul Brook <paul@codesourcery.com>
220
221 * arm-dis.c (coprocessor_opcodes): Add null terminator.
222
8f06b2d8
PB		 2232005-09-02 Paul Brook <paul@codesourcery.com>
224
225 * arm-dis.c (coprocessor_opcodes): New.
226 (arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
227 (print_insn_coprocessor): New function.
228 (print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
229 format characters.
230 (print_insn_thumb32): Use print_insn_coprocessor.
231
a2dfd01f
PB		 2322005-08-30 Paul Brook <paul@codesourcery.com>
233
234 * arm-dis.c (thumb_opcodes): Disassemble sub(3) as subs.
235
3f31e633
JB		 2362005-08-26 Jan Beulich <jbeulich@novell.com>
237
238 * i386-dis.c (intel_operand_size): New, broken out from OP_E for
239 re-use.
240 (OP_E): Call intel_operand_size, move call site out of mode
241 dependent code.
242 (OP_OFF): Call intel_operand_size if suffix_always. Remove
243 ATTRIBUTE_UNUSED from parameters.
244 (OP_OFF64): Likewise.
245 (OP_ESreg): Call intel_operand_size.
246 (OP_DSreg): Likewise.
247 (OP_DIR): Use colon rather than semicolon as separator of far
248 jump/call operands.
249
fd25c5a9
CF		 2502005-08-25 Chao-ying Fu <fu@mips.com>
251
252 * mips-opc.c (WR_a, RD_a, MOD_a, DSP_VOLA, D32): New define.
253 (mips_builtin_opcodes): Add DSP instructions.
254 * mips-dis.c (mips_arch_choices): Enable INSN_DSP for mips32, mips32r2,
255 mips64, mips64r2.
256 (print_insn_args): Add supports for 3, 4, 5, 6, 7, 8, 9, 0, :, ', @
257 operand formats.
258
dd8b7c22
DU		 2592005-08-23 David Ung <davidu@mips.com>
260
261 * mips16-opc.c (mips16_opcodes): Add the MIPS16e jalrc/jrc
262 instructions to the table.
263
c17ae8a2
AM		 2642005-08-18 Alan Modra <amodra@bigpond.net.au>
265
848cf006 266 * a29k-dis.c: Delete.
c17ae8a2
AM		 267 * Makefile.am: Remove a29k support.
268 * configure.in: Likewise.
269 * disassemble.c: Likewise.
270 * Makefile.in: Regenerate.
271 * configure: Regenerate.
272 * po/POTFILES.in: Regenerate.
273
36ae0db3
DJ		 2742005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
275
276 * ppc-dis.c (powerpc_dialect): Handle e300.
277 (print_ppc_disassembler_options): Likewise.
278 * ppc-opc.c (PPCE300): Define.
279 (powerpc_opcodes): Mark icbt as available for the e300.
280
63a3357b
DA		 2812005-08-13 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
282
283 * hppa-dis.c (print_insn_hppa): Don't print '%' before register names.
284 Use "rp" instead of "%r2" in "b,l" insns.
285
ad101263
MS		 2862005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
287
288 * s390-dis.c (print_insn_s390): Print unsigned operands with %u.
289 * s390-mkopc.c (s390_opcode_cpu_val): Add support for cpu type z9-109.
290 (main): Likewise.
291 * s390-opc.c (I32_16, U32_16, M_16): Add defines 32 bit immediates
292 and 4 bit optional masks.
293 (INSTR_RIL_RI, INSTR_RIL_RU, INSTR_RRF_M0RR, INSTR_RSE_CCRD,
294 INSTR_RSY_CCRD, INSTR_SSF_RRDRD): Add new instruction formats.
295 (MASK_RIL_RI, MASK_RIL_RU, MASK_RRF_M0RR, MASK_RSE_CCRD,
296 MASK_RSY_CCRD, MASK_SSF_RRDRD): Likewise.
297 (s390_opformats): Likewise.
298 * s390-opc.txt: Add new instructions for cpu type z9-109.
299
f1fa1093
DA		 3002005-08-05 John David Anglin <dave.anglin@nrc-crnc.gc.ca>
301
302 * hppa-dis.c (print_insn_hppa): Prefix 21-bit values with "L%".
303
e9f89963
PB		 3042005-07-29 Paul Brook <paul@codesourcery.com>
305
306 * arm-dis.c: Fix disassebly of thumb2 writeback addressing modes.
307
92e90b6e
PB		 3082005-07-29 Paul Brook <paul@codesourcery.com>
309
310 * arm-dis.c (thumb32_opc): Fix addressing mode for tbh.
311 (print_insn_thumb32): Fix decoding of thumb2 'I' operands.
312
fd54057a
DD		 3132005-07-25 DJ Delorie <dj@redhat.com>
314
315 * m32c-asm.c Regenerate.
316 * m32c-dis.c Regenerate.
317
760c0f6a
DD		 3182005-07-20 DJ Delorie <dj@redhat.com>
319
320 * disassemble.c (disassemble_init_for_target): M32C ISAs are
321 enums, so convert them to bit masks, which attributes are.
322
85da3a56
NC		 3232005-07-18 Nick Clifton <nickc@redhat.com>
324
325 * configure.in: Restore alpha ordering to list of arches.
326 * configure: Regenerate.
327 * disassemble.c: Restore alpha ordering to list of arches.
328
3292005-07-18 Nick Clifton <nickc@redhat.com>
330
331 * m32c-asm.c: Regenerate.
332 * m32c-desc.c: Regenerate.
333 * m32c-desc.h: Regenerate.
334 * m32c-dis.c: Regenerate.
335 * m32c-ibld.h: Regenerate.
336 * m32c-opc.c: Regenerate.
337 * m32c-opc.h: Regenerate.
338
22cbf2e7
L		 3392005-07-18 H.J. Lu <hongjiu.lu@intel.com>
340
341 * i386-dis.c (PNI_Fixup): Update comment.
342 (VMX_Fixup): Properly handle the suffix check.
343
0aea0460
DA		 3442005-07-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
345
346 * hppa-dis.c (print_insn_hppa): Add space after 'w' in wide-mode
347 mfctl disassembly.
348
0f82ff91
AM		 3492005-07-16 Alan Modra <amodra@bigpond.net.au>
350
351 * Makefile.am: Run "make dep-am".
352 (stamp-m32c): Fix cpu dependencies.
353 * Makefile.in: Regenerate.
354 * ip2k-dis.c: Regenerate.
355
90700ea2
L		 3562007-07-15 H.J. Lu <hongjiu.lu@intel.com>
357
358 * i386-dis.c (OP_VMX): New. Handle Intel VMX Instructions.
359 (VMX_Fixup): New. Fix up Intel VMX Instructions.
360 (Em): New.
361 (Gm): New.
362 (VM): New.
363 (dis386_twobyte): Updated entries 0x78 and 0x79.
364 (twobyte_has_modrm): Likewise.
365 (grps): Use OP_VMX in the "sgdtIQ" entry. Updated GRP9.
366 (OP_G): Handle m_mode.
367
49f58d10
JB		 3682005-07-14 Jim Blandy <jimb@redhat.com>
369
370 Add support for the Renesas M32C and M16C.
371 * m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c, m32c-opc.c: New.
372 * m32c-desc.h, m32c-opc.h: New.
373 * Makefile.am (HFILES): List m32c-desc.h and m32c-opc.h.
374 (CFILES): List m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c,
375 m32c-opc.c.
376 (ALL_MACHINES): List m32c-asm.lo, m32c-desc.lo, m32c-dis.lo,
377 m32c-ibld.lo, m32c-opc.lo.
378 (CLEANFILES): List stamp-m32c.
379 (M32C_DEPS): List stamp-m32c, if CGEN_MAINT.
380 (CGEN_CPUS): Add m32c.
381 (m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c, m32c-opc.c)
382 (m32c-desc.h, m32c-opc.h): Depend on M32C_DEPS.
383 (m32c_opc_h): New variable.
384 (stamp-m32c, m32c-asm.lo, m32c-desc.lo, m32c-dis.lo, m32c-ibld.lo)
385 (m32c-opc.lo): New rules.
386 * Makefile.in: Regenerated.
387 * configure.in: Add case for bfd_m32c_arch.
388 * configure: Regenerated.
389 * disassemble.c (ARCH_m32c): New.
390 [ARCH_m32c]: #include "m32c-desc.h".
391 (disassembler) [ARCH_m32c]: Add case for bfd_arch_m32c.
392 (disassemble_init_for_target) [ARCH_m32c]: Same.
393
394 * cgen-ops.h, cgen-types.h: New files.
395 * Makefile.am (HFILES): List them.
396 * Makefile.in: Regenerated.
397
0fd3a477
JW		 3982005-07-07 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
399
400 * arc-dis.c, arm-dis.c, cris-dis.c, crx-dis.c, d10v-dis.c,
401 d30v-dis.c, fr30-dis.c, h8300-dis.c, h8500-dis.c, i860-dis.c,
402 ia64-dis.c, ip2k-dis.c, m10200-dis.c, m10300-dis.c,
403 m88k-dis.c, mcore-dis.c, mips-dis.c, ms1-dis.c, or32-dis.c,
404 ppc-dis.c, sh64-dis.c, sparc-dis.c, tic4x-dis.c, tic80-dis.c,
405 v850-dis.c: Fix format bugs.
406 * ia64-gen.c (fail, warn): Add format attribute.
407 * or32-opc.c (debug): Likewise.
408
22f8fcbd
NC		 4092005-07-07 Khem Raj <kraj@mvista.com>
410
411 * arm-dis.c (opcode32 arm_opcodes): Fix ARM VFP fadds instruction
412 disassembly pattern.
413
d125c27b
AM		 4142005-07-06 Alan Modra <amodra@bigpond.net.au>
415
416 * Makefile.am (stamp-m32r): Fix path to cpu files.
417 (stamp-m32r, stamp-iq2000): Likewise.
418 * Makefile.in: Regenerate.
419 * m32r-asm.c: Regenerate.
420 * po/POTFILES.in: Remove arm-opc.h. Add ms1-asm.c, ms1-desc.c,
421 ms1-desc.h, ms1-dis.c, ms1-ibld.c, ms1-opc.c, ms1-opc.h.
422
3ec2b351
NC		 4232005-07-05 Nick Clifton <nickc@redhat.com>
424
425 * iq2000-asm.c: Regenerate.
426 * ms1-asm.c: Regenerate.
427
30123838
JB		 4282005-07-05 Jan Beulich <jbeulich@novell.com>
429
430 * i386-dis.c (SVME_Fixup): New.
431 (grps): Use it for the lidt entry.
432 (PNI_Fixup): Call OP_M rather than OP_E.
433 (INVLPG_Fixup): Likewise.
434
b0eec63e
L		 4352005-07-04 H.J. Lu <hongjiu.lu@intel.com>
436
437 * tic30-dis.c (cnvt_tmsfloat_ieee): Use HUGE_VALF if defined.
438
47b0e7ad
NC		 4392005-07-01 Nick Clifton <nickc@redhat.com>
440
441 * a29k-dis.c: Update to ISO C90 style function declarations and
442 fix formatting.
443 * alpha-opc.c: Likewise.
444 * arc-dis.c: Likewise.
445 * arc-opc.c: Likewise.
446 * avr-dis.c: Likewise.
447 * cgen-asm.in: Likewise.
448 * cgen-dis.in: Likewise.
449 * cgen-ibld.in: Likewise.
450 * cgen-opc.c: Likewise.
451 * cris-dis.c: Likewise.
452 * d10v-dis.c: Likewise.
453 * d30v-dis.c: Likewise.
454 * d30v-opc.c: Likewise.
455 * dis-buf.c: Likewise.
456 * dlx-dis.c: Likewise.
457 * h8300-dis.c: Likewise.
458 * h8500-dis.c: Likewise.
459 * hppa-dis.c: Likewise.
460 * i370-dis.c: Likewise.
461 * i370-opc.c: Likewise.
462 * m10200-dis.c: Likewise.
463 * m10300-dis.c: Likewise.
464 * m68k-dis.c: Likewise.
465 * m88k-dis.c: Likewise.
466 * mips-dis.c: Likewise.
467 * mmix-dis.c: Likewise.
468 * msp430-dis.c: Likewise.
469 * ns32k-dis.c: Likewise.
470 * or32-dis.c: Likewise.
471 * or32-opc.c: Likewise.
472 * pdp11-dis.c: Likewise.
473 * pj-dis.c: Likewise.
474 * s390-dis.c: Likewise.
475 * sh-dis.c: Likewise.
476 * sh64-dis.c: Likewise.
477 * sparc-dis.c: Likewise.
478 * sparc-opc.c: Likewise.
479 * sysdep.h: Likewise.
480 * tic30-dis.c: Likewise.
481 * tic4x-dis.c: Likewise.
482 * tic80-dis.c: Likewise.
483 * v850-dis.c: Likewise.
484 * v850-opc.c: Likewise.
485 * vax-dis.c: Likewise.
486 * w65-dis.c: Likewise.
487 * z8kgen.c: Likewise.
488
489 * fr30-*: Regenerate.
490 * frv-*: Regenerate.
491 * ip2k-*: Regenerate.
492 * iq2000-*: Regenerate.
493 * m32r-*: Regenerate.
494 * ms1-*: Regenerate.
495 * openrisc-*: Regenerate.
496 * xstormy16-*: Regenerate.
497
cc16ba8c
BE		 4982005-06-23 Ben Elliston <bje@gnu.org>
499
500 * m68k-dis.c: Use ISC C90.
501 * m68k-opc.c: Formatting fixes.
502
4b185e97
DU		 5032005-06-16 David Ung <davidu@mips.com>
504
505 * mips16-opc.c (mips16_opcodes): Add the following MIPS16e
506 instructions to the table; seb/seh/sew/zeb/zeh/zew.
507
ac188222
DB		 5082005-06-15 Dave Brolley <brolley@redhat.com>
509
510 Contribute Morpho ms1 on behalf of Red Hat
511 * ms1-asm.c, ms1-desc.c, ms1-dis.c, ms1-ibld.c, ms1-opc.c,
512 ms1-opc.h: New files, Morpho ms1 target.
513
514 2004-05-14 Stan Cox <scox@redhat.com>
515
516 * disassemble.c (ARCH_ms1): Define.
517 (disassembler): Handle bfd_arch_ms1
518
519 2004-05-13 Michael Snyder <msnyder@redhat.com>
520
521 * Makefile.am, Makefile.in: Add ms1 target.
522 * configure.in: Ditto.
523
6b5d3a4d
ZW		 5242005-06-08 Zack Weinberg <zack@codesourcery.com>
525
526 * arm-opc.h: Delete; fold contents into ...
527 * arm-dis.c: ... here. Move includes of internal COFF headers
528 next to includes of internal ELF headers.
529 (streq, WORD_ADDRESS, BDISP, BDISP23): Delete, unused.
530 (struct arm_opcode): Rename struct opcode32. Make 'assembler' const.
531 (struct thumb_opcode): Rename struct opcode16. Make 'assembler' const.
532 (arm_conditional, arm_fp_const, arm_shift, arm_regname, regnames)
533 (iwmmxt_wwnames, iwmmxt_wwssnames):
534 Make const.
535 (regnames): Remove iWMMXt coprocessor register sets.
536 (iwmmxt_regnames, iwmmxt_cregnames): New statics.
537 (get_arm_regnames): Adjust fourth argument to match above changes.
538 (set_iwmmxt_regnames): Delete.
539 (print_insn_arm): Constify 'c'. Use ISO syntax for function
540 pointer calls. Expand sole use of BDISP. Use iwmmxt_regnames
541 and iwmmxt_cregnames, not set_iwmmxt_regnames.
542 (print_insn_thumb16, print_insn_thumb32): Constify 'c'. Use
543 ISO syntax for function pointer calls.
544
4a5329c6
ZW		 5452005-06-07 Zack Weinberg <zack@codesourcery.com>
546
547 * arm-dis.c: Split up the comments describing the format codes, so
548 that the ARM and 16-bit Thumb opcode tables each have comments
549 preceding them that describe all the codes, and only the codes,
550 valid in those tables. (32-bit Thumb table is already like this.)
551 Reorder the lists in all three comments to match the order in
552 which the codes are implemented.
553 Remove all forward declarations of static functions. Convert all
554 function definitions to ISO C format.
555 (print_insn_arm, print_insn_thumb16, print_insn_thumb32):
556 Return nothing.
557 (print_insn_thumb16): Remove unused case 'I'.
558 (print_insn): Update for changed calling convention of subroutines.
559
3d456fa1
JB		 5602005-05-25 Jan Beulich <jbeulich@novell.com>
561
562 * i386-dis.c (OP_E): In Intel mode, display 32-bit displacements in
563 hex (but retain it being displayed as signed). Remove redundant
564 checks. Add handling of displacements for 16-bit addressing in Intel
565 mode.
566
2888cb7a
JB		 5672005-05-25 Jan Beulich <jbeulich@novell.com>
568
569 * i386-dis.c (prefix_name): Remove pointless mode_64bit check.
570 (OP_E): Remove redundant REX_EXTZ handling. Remove pointless
571 masking of 'rm' in 16-bit memory address handling.
572
1ed8e1e4
AM		 5732005-05-19 Anton Blanchard <anton@samba.org>
574
575 * ppc-dis.c (powerpc_dialect): Handle "-Mpower5".
576 (print_ppc_disassembler_options): Document it.
577 * ppc-opc.c (SVC_LEV): Define.
578 (LEV): Allow optional operand.
579 (POWER5): Define.
580 (powerpc_opcodes): Extend "sc". Adjust "svc" and "svcl". Add
581 "hrfid", "popcntb", "fsqrtes", "fsqrtes.", "fre" and "fre.".
582
49cc2e69
KC		 5832005-05-19 Kelley Cook <kcook@gcc.gnu.org>
584
585 * Makefile.in: Regenerate.
586
c19d1205
ZW		 5872005-05-17 Zack Weinberg <zack@codesourcery.com>
588
589 * arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
590 instructions. Adjust disassembly of some opcodes to match
591 unified syntax.
592 (thumb32_opcodes): New table.
593 (print_insn_thumb): Rename print_insn_thumb16; don't handle
594 two-halfword branches here.
595 (print_insn_thumb32): New function.
596 (print_insn): Choose among print_insn_arm, print_insn_thumb16,
597 and print_insn_thumb32. Be consistent about order of
598 halfwords when printing 32-bit instructions.
599
003519a7
L		 6002005-05-07 H.J. Lu <hongjiu.lu@intel.com>
601
602 PR 843
603 * i386-dis.c (branch_v_mode): New.
604 (indirEv): Use branch_v_mode instead of v_mode.
605 (OP_E): Handle branch_v_mode.
606
920a34a7
L		 6072005-05-07 H.J. Lu <hongjiu.lu@intel.com>
608
609 * d10v-dis.c (dis_2_short): Support 64bit host.
610
5de773c1
NC		 6112005-05-07 Nick Clifton <nickc@redhat.com>
612
613 * po/nl.po: Updated translation.
614
f4321104
NC		 6152005-05-07 Nick Clifton <nickc@redhat.com>
616
617 * Update the address and phone number of the FSF organization in
618 the GPL notices in the following files:
619 a29k-dis.c, aclocal.m4, alpha-dis.c, alpha-opc.c, arc-dis.c,
620 arc-dis.h, arc-ext.c, arc-ext.h, arc-opc.c, arm-dis.c, arm-opc.h,
621 avr-dis.c, cgen-asm.c, cgen-asm.in, cgen-dis.c, cgen-dis.in,
622 cgen-ibld.in, cgen-opc.c, cgen.sh, cris-dis.c, cris-opc.c,
623 crx-dis.c, crx-opc.c, d10v-dis.c, d10v-opc.c, d30v-dis.c,
624 d30v-opc.c, dis-buf.c, dis-init.c, disassemble.c, dlx-dis.c,
625 fr30-asm.c, fr30-desc.c, fr30-desc.h, fr30-dis.c, fr30-ibld.c,
626 fr30-opc.c, fr30-opc.h, frv-asm.c, frv-desc.c, frv-desc.h,
627 frv-dis.c, frv-ibld.c, frv-opc.c, frv-opc.h, h8300-dis.c,
628 h8500-dis.c, h8500-opc.h, hppa-dis.c, i370-dis.c, i370-opc.c,
629 i386-dis.c, i860-dis.c, i960-dis.c, ia64-asmtab.h, ia64-dis.c,
630 ia64-gen.c, ia64-opc-a.c, ia64-opc-b.c, ia64-opc-d.c,
631 ia64-opc-f.c, ia64-opc-i.c, ia64-opc-m.c, ia64-opc-x.c,
632 ia64-opc.c, ia64-opc.h, ip2k-asm.c, ip2k-desc.c, ip2k-desc.h,
633 ip2k-dis.c, ip2k-ibld.c, ip2k-opc.c, ip2k-opc.h, iq2000-asm.c,
634 iq2000-desc.c, iq2000-desc.h, iq2000-dis.c, iq2000-ibld.c,
635 iq2000-opc.c, iq2000-opc.h, m10200-dis.c, m10200-opc.c,
636 m10300-dis.c, m10300-opc.c, m32r-asm.c, m32r-desc.c, m32r-desc.h,
637 m32r-dis.c, m32r-ibld.c, m32r-opc.c, m32r-opc.h, m32r-opinst.c,
638 m68hc11-dis.c, m68hc11-opc.c, m68k-dis.c, m68k-opc.c, m88k-dis.c,
639 maxq-dis.c, mcore-dis.c, mcore-opc.h, mips-dis.c, mips-opc.c,
640 mips16-opc.c, mmix-dis.c, mmix-opc.c, msp430-dis.c, ns32k-dis.c,
641 openrisc-asm.c, openrisc-desc.c, openrisc-desc.h, openrisc-dis.c,
642 openrisc-ibld.c, openrisc-opc.c, openrisc-opc.h, opintl.h,
643 or32-dis.c, or32-opc.c, pdp11-dis.c, pdp11-opc.c, pj-dis.c,
644 pj-opc.c, ppc-dis.c, ppc-opc.c, s390-dis.c, s390-mkopc.c,
645 s390-opc.c, sh-dis.c, sh-opc.h, sh64-dis.c, sh64-opc.c,
646 sh64-opc.h, sparc-dis.c, sparc-opc.c, sysdep.h, tic30-dis.c,
647 tic4x-dis.c, tic54x-dis.c, tic54x-opc.c, tic80-dis.c, tic80-opc.c,
648 v850-dis.c, v850-opc.c, vax-dis.c, w65-dis.c, w65-opc.h,
649 xstormy16-asm.c, xstormy16-desc.c, xstormy16-desc.h,
650 xstormy16-dis.c, xstormy16-ibld.c, xstormy16-opc.c,
651 xstormy16-opc.h, xtensa-dis.c, z8k-dis.c, z8kgen.c
652
10b076a2
JW		 6532005-05-05 James E Wilson <wilson@specifixinc.com>
654
655 * ia64-opc.c: Include sysdep.h before libiberty.h.
656
022716b6
NC		 6572005-05-05 Nick Clifton <nickc@redhat.com>
658
659 * configure.in (ALL_LINGUAS): Add vi.
660 * configure: Regenerate.
661 * po/vi.po: New.
662
db5152b4
JG		 6632005-04-26 Jerome Guitton <guitton@gnat.com>
664
665 * configure.in: Fix the check for basename declaration.
666 * configure: Regenerate.
667
eed0d89a
AM		 6682005-04-19 Alan Modra <amodra@bigpond.net.au>
669
670 * ppc-opc.c (RTO): Define.
671 (powerpc_opcodes <tlbsx, tlbsx., tlbre>): Combine PPC403 and BOOKE
672 entries to suit PPC440.
673
791fe849
MK		 6742005-04-18 Mark Kettenis <kettenis@gnu.org>
675
676 * i386-dis.c: Insert hyphens into selected VIA PadLock extensions.
677 Add xcrypt-ctr.
678
ffe58f7c
NC		 6792005-04-14 Nick Clifton <nickc@redhat.com>
680
681 * po/fi.po: New translation: Finnish.
682 * configure.in (ALL_LINGUAS): Add fi.
683 * configure: Regenerate.
684
9e9b66a9
AM		 6852005-04-14 Alan Modra <amodra@bigpond.net.au>
686
687 * Makefile.am (NO_WERROR): Define.
688 * configure.in: Invoke AM_BINUTILS_WARNINGS.
689 * Makefile.in: Regenerate.
690 * aclocal.m4: Regenerate.
691 * configure: Regenerate.
692
9494d739
NC		 6932005-04-04 Nick Clifton <nickc@redhat.com>
694
695 * fr30-asm.c: Regenerate.
696 * frv-asm.c: Regenerate.
697 * iq2000-asm.c: Regenerate.
698 * m32r-asm.c: Regenerate.
699 * openrisc-asm.c: Regenerate.
700
6128c599
JB		 7012005-04-01 Jan Beulich <jbeulich@novell.com>
702
703 * i386-dis.c (PNI_Fixup): Neither mwait nor monitor have any
704 visible operands in Intel mode. The first operand of monitor is
705 %rax in 64-bit mode.
706
373ff435
JB		 7072005-04-01 Jan Beulich <jbeulich@novell.com>
708
709 * i386-dis.c (INVLPG_Fixup): Decode rdtscp; change code to allow for
710 easier future additions.
711
4bd60896
JG		 7122005-03-31 Jerome Guitton <guitton@gnat.com>
713
714 * configure.in: Check for basename.
715 * configure: Regenerate.
716 * config.in: Ditto.
717
4cc91dba
L		 7182005-03-29 H.J. Lu <hongjiu.lu@intel.com>
719
720 * i386-dis.c (SEG_Fixup): New.
721 (Sv): New.
722 (dis386): Use "Sv" for 0x8c and 0x8e.
723
ec72cfe5
NC		 7242005-03-21 Jan-Benedict Glaw <jbglaw@lug-owl.de>
725 Nick Clifton <nickc@redhat.com>
c19d1205 726
ec72cfe5
NC		 727 * vax-dis.c: (entry_addr): New varible: An array of user supplied
728 function entry mask addresses.
729 (entry_addr_occupied_slots): New variable: The number of occupied
c19d1205 730 elements in entry_addr.
ec72cfe5
NC		 731 (entry_addr_total_slots): New variable: The total number of
732 elements in entry_addr.
733 (parse_disassembler_options): New function. Fills in the entry_addr
734 array.
735 (free_entry_array): New function. Release the memory used by the
736 entry addr array. Suppressed because there is no way to call it.
737 (is_function_entry): Check if a given address is a function's
738 start address by looking at supplied entry mask addresses and
739 symbol information, if available.
740 (print_insn_vax): Use parse_disassembler_options and is_function_entry.
741
85064c79
L		 7422005-03-23 H.J. Lu <hongjiu.lu@intel.com>
743
744 * cris-dis.c (print_with_operands): Use ~31L for long instead
745 of ~31.
746
de7141c7
L		 7472005-03-20 H.J. Lu <hongjiu.lu@intel.com>
748
749 * mmix-opc.c (O): Revert the last change.
750 (Z): Likewise.
751
e493ab45
L		 7522005-03-19 H.J. Lu <hongjiu.lu@intel.com>
753
754 * mmix-opc.c (O): Use 24UL instead of 24 for unsigned long.
755 (Z): Likewise.
756
d8d7c459
HPN		 7572005-03-19 Hans-Peter Nilsson <hp@bitrange.com>
758
759 * mmix-opc.c (O, Z): Force expression as unsigned long.
760
ebdb0383
NC		 7612005-03-18 Nick Clifton <nickc@redhat.com>
762
763 * ip2k-asm.c: Regenerate.
764 * op/opcodes.pot: Regenerate.
765
1ad12f97
NC		 7662005-03-16 Nick Clifton <nickc@redhat.com>
767 Ben Elliston <bje@au.ibm.com>
768
569acd2c 769 * configure.in (werror): New switch: Add -Werror to the
1ad12f97 770 compiler command line. Enabled by default. Disable via
569acd2c 771 --disable-werror.
1ad12f97
NC		 772 * configure: Regenerate.
773
4eb30afc
AM		 7742005-03-16 Alan Modra <amodra@bigpond.net.au>
775
776 * ppc-dis.c (powerpc_dialect): Don't set PPC_OPCODE_ALTIVEC when
777 BOOKE.
778
ea8409f7
AM		 7792005-03-15 Alan Modra <amodra@bigpond.net.au>
780
729ae8d2
AM		 781 * po/es.po: Commit new Spanish translation.
782
ea8409f7
AM		 783 * po/fr.po: Commit new French translation.
784
4f495e61
NC		 7852005-03-14 Jan-Benedict Glaw <jbglaw@lug-owl.de>
786
787 * vax-dis.c: Fix spelling error
788 (print_insn_vax): Use ".word 0x0012 # Entry mask: r1 r2 >" instead
789 of just "Entry mask: < r1 ... >"
790
0a003adc
ZW		 7912005-03-12 Zack Weinberg <zack@codesourcery.com>
792
793 * arm-dis.c (arm_opcodes): Document %E and %V.
794 Add entries for v6T2 ARM instructions:
795 bfc bfi mls strht ldrht ldrsht ldrsbt movw movt rbit ubfx sbfx.
796 (print_insn_arm): Add support for %E and %V.
885fc257 797 (thumb_opcodes): Add ARMv6K instructions nop, sev, wfe, wfi, yield.
0a003adc 798
da99ee72
AM		 7992005-03-10 Jeff Baker <jbaker@qnx.com>
800 Alan Modra <amodra@bigpond.net.au>
801
802 * ppc-opc.c (insert_sprg, extract_sprg): New Functions.
803 (powerpc_operands <SPRG>): Call the above. Bit field is 5 bits.
804 (SPRG_MASK): Delete.
805 (XSPRG_MASK): Mask off extra bits now part of sprg field.
0a003adc 806 (powerpc_opcodes): Asjust mfsprg and mtsprg to suit new mask. Move
da99ee72
AM		 807 mfsprg4..7 after msprg and consolidate.
808
220abb21
AM		 8092005-03-09 Jan-Benedict Glaw <jbglaw@lug-owl.de>
810
811 * vax-dis.c (entry_mask_bit): New array.
812 (print_insn_vax): Decode function entry mask.
813
0e06657a
AH		 8142005-03-07 Aldy Hernandez <aldyh@redhat.com>
815
816 * ppc-opc.c (powerpc_opcodes): Fix encoding of efscfd.
817
06647dfd
AM		 8182005-03-05 Alan Modra <amodra@bigpond.net.au>
819
820 * po/opcodes.pot: Regenerate.
821
82b829a7
RR		 8222005-03-03 Ramana Radhakrishnan <ramana.radhakrishnan@codito.com>
823
220abb21 824 * arc-dis.c (a4_decoding_class): New enum.
06647dfd
AM		 825 (dsmOneArcInst): Use the enum values for the decoding class.
826 Remove redundant case in the switch for decodingClass value 11.
82b829a7 827
c4a530c5
JB		 8282005-03-02 Jan Beulich <jbeulich@novell.com>
829
830 * i386-dis.c (print_insn): Suppress lock prefix printing for cr8...15
831 accesses.
832 (OP_C): Consider lock prefix in non-64-bit modes.
833
47d8304e
AM		 8342005-02-24 Alan Modra <amodra@bigpond.net.au>
835
836 * cris-dis.c (format_hex): Remove ineffective warning fix.
837 * crx-dis.c (make_instruction): Warning fix.
838 * frv-asm.c: Regenerate.
839
ec36c4a4
NC		 8402005-02-23 Nick Clifton <nickc@redhat.com>
841
33b71eeb
NC		 842 * cgen-dis.in: Use bfd_byte for buffers that are passed to
843 read_memory.
06647dfd 844
33b71eeb 845 * ia64-opc.c (locate_opcode_ent): Initialise opval array.
06647dfd 846
ec36c4a4
NC		 847 * crx-dis.c (make_instruction): Move argument structure into inner
848 scope and ensure that all of its fields are initialised before
849 they are used.
850
33b71eeb
NC		 851 * fr30-asm.c: Regenerate.
852 * fr30-dis.c: Regenerate.
853 * frv-asm.c: Regenerate.
854 * frv-dis.c: Regenerate.
855 * ip2k-asm.c: Regenerate.
856 * ip2k-dis.c: Regenerate.
857 * iq2000-asm.c: Regenerate.
858 * iq2000-dis.c: Regenerate.
859 * m32r-asm.c: Regenerate.
860 * m32r-dis.c: Regenerate.
861 * openrisc-asm.c: Regenerate.
862 * openrisc-dis.c: Regenerate.
863 * xstormy16-asm.c: Regenerate.
864 * xstormy16-dis.c: Regenerate.
865
53c9ebc5
AM		 8662005-02-22 Alan Modra <amodra@bigpond.net.au>
867
868 * arc-ext.c: Warning fixes.
869 * arc-ext.h: Likewise.
870 * cgen-opc.c: Likewise.
871 * ia64-gen.c: Likewise.
872 * maxq-dis.c: Likewise.
873 * ns32k-dis.c: Likewise.
874 * w65-dis.c: Likewise.
875 * ia64-asmtab.c: Regenerate.
876
610ad19b
AM		 8772005-02-22 Alan Modra <amodra@bigpond.net.au>
878
879 * fr30-desc.c: Regenerate.
880 * fr30-desc.h: Regenerate.
881 * fr30-opc.c: Regenerate.
882 * fr30-opc.h: Regenerate.
883 * frv-desc.c: Regenerate.
884 * frv-desc.h: Regenerate.
885 * frv-opc.c: Regenerate.
886 * frv-opc.h: Regenerate.
887 * ip2k-desc.c: Regenerate.
888 * ip2k-desc.h: Regenerate.
889 * ip2k-opc.c: Regenerate.
890 * ip2k-opc.h: Regenerate.
891 * iq2000-desc.c: Regenerate.
892 * iq2000-desc.h: Regenerate.
893 * iq2000-opc.c: Regenerate.
894 * iq2000-opc.h: Regenerate.
895 * m32r-desc.c: Regenerate.
896 * m32r-desc.h: Regenerate.
897 * m32r-opc.c: Regenerate.
898 * m32r-opc.h: Regenerate.
899 * m32r-opinst.c: Regenerate.
900 * openrisc-desc.c: Regenerate.
901 * openrisc-desc.h: Regenerate.
902 * openrisc-opc.c: Regenerate.
903 * openrisc-opc.h: Regenerate.
904 * xstormy16-desc.c: Regenerate.
905 * xstormy16-desc.h: Regenerate.
906 * xstormy16-opc.c: Regenerate.
907 * xstormy16-opc.h: Regenerate.
908
db9db6f2
AM		 9092005-02-21 Alan Modra <amodra@bigpond.net.au>
910
911 * Makefile.am: Run "make dep-am"
912 * Makefile.in: Regenerate.
913
bf143b25
NC		 9142005-02-15 Nick Clifton <nickc@redhat.com>
915
916 * cgen-dis.in (print_address): Add an ATTRIBUTE_UNUSED to prevent
917 compile time warnings.
918 (print_keyword): Likewise.
919 (default_print_insn): Likewise.
920
921 * fr30-desc.c: Regenerated.
922 * fr30-desc.h: Regenerated.
923 * fr30-dis.c: Regenerated.
924 * fr30-opc.c: Regenerated.
925 * fr30-opc.h: Regenerated.
926 * frv-desc.c: Regenerated.
927 * frv-dis.c: Regenerated.
928 * frv-opc.c: Regenerated.
929 * ip2k-asm.c: Regenerated.
930 * ip2k-desc.c: Regenerated.
931 * ip2k-desc.h: Regenerated.
932 * ip2k-dis.c: Regenerated.
933 * ip2k-opc.c: Regenerated.
934 * ip2k-opc.h: Regenerated.
935 * iq2000-desc.c: Regenerated.
936 * iq2000-dis.c: Regenerated.
937 * iq2000-opc.c: Regenerated.
938 * m32r-asm.c: Regenerated.
939 * m32r-desc.c: Regenerated.
940 * m32r-desc.h: Regenerated.
941 * m32r-dis.c: Regenerated.
942 * m32r-opc.c: Regenerated.
943 * m32r-opc.h: Regenerated.
944 * m32r-opinst.c: Regenerated.
945 * openrisc-desc.c: Regenerated.
946 * openrisc-desc.h: Regenerated.
947 * openrisc-dis.c: Regenerated.
948 * openrisc-opc.c: Regenerated.
949 * openrisc-opc.h: Regenerated.
950 * xstormy16-desc.c: Regenerated.
951 * xstormy16-desc.h: Regenerated.
952 * xstormy16-dis.c: Regenerated.
953 * xstormy16-opc.c: Regenerated.
954 * xstormy16-opc.h: Regenerated.
955
d6098898
L		 9562005-02-14 H.J. Lu <hongjiu.lu@intel.com>
957
958 * dis-buf.c (perror_memory): Use sprintf_vma to print out
959 address.
960
5a84f3e0
NC		 9612005-02-11 Nick Clifton <nickc@redhat.com>
962
bc18c937
NC		 963 * iq2000-asm.c: Regenerate.
964
5a84f3e0
NC		 965 * frv-dis.c: Regenerate.
966
0a40490e
JB		 9672005-02-07 Jim Blandy <jimb@redhat.com>
968
969 * Makefile.am (CGEN): Load guile.scm before calling the main
970 application script.
971 * Makefile.in: Regenerated.
972 * cgen.sh: Be prepared for the 'cgen' argument to contain spaces.
973 Simply pass the cgen-opc.scm path to ${cgen} as its first
974 argument; ${cgen} itself now contains the '-s', or whatever is
975 appropriate for the Scheme being used.
976
c46f8c51
AC		 9772005-01-31 Andrew Cagney <cagney@gnu.org>
978
979 * configure: Regenerate to track ../gettext.m4.
980
60b9a617
JB		 9812005-01-31 Jan Beulich <jbeulich@novell.com>
982
983 * ia64-gen.c (NELEMS): Define.
984 (shrink): Generate alias with missing second predicate register when
985 opcode has two outputs and these are both predicates.
986 * ia64-opc-i.c (FULL17): Define.
987 (ia64_opcodes_i): Add mov-to-pr alias without second input. Use FULL17
988 here to generate output template.
989 (TBITCM, TNATCM): Undefine after use.
990 * ia64-opc-m.c (ia64_opcodes_i): Add alloc alias without ar.pfs as
991 first input. Add ld16 aliases without ar.csd as second output. Add
992 st16 aliases without ar.csd as second input. Add cmpxchg aliases
993 without ar.ccv as third input. Add cmp8xchg16 aliases without ar.csd/
994 ar.ccv as third/fourth inputs. Consolidate through...
995 (CMPXCHG_acq, CMPXCHG_rel, CMPXCHG_1, CMPXCHG_2, CMPXCHG_4, CMPXCHG_8,
996 CMPXCHGn, CMP8XCHG16, CMPXCHG_ALL): Define.
997 * ia64-asmtab.c: Regenerate.
998
a53bf506
AC		 9992005-01-27 Andrew Cagney <cagney@gnu.org>
1000
1001 * configure: Regenerate to track ../gettext.m4 change.
1002
90219bd0
AO		 10032005-01-25 Alexandre Oliva <aoliva@redhat.com>
1004
1005 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1006 * frv-asm.c: Rebuilt.
1007 * frv-desc.c: Rebuilt.
1008 * frv-desc.h: Rebuilt.
1009 * frv-dis.c: Rebuilt.
1010 * frv-ibld.c: Rebuilt.
1011 * frv-opc.c: Rebuilt.
1012 * frv-opc.h: Rebuilt.
1013
45181ed1
AC		 10142005-01-24 Andrew Cagney <cagney@gnu.org>
1015
1016 * configure: Regenerate, ../gettext.m4 was updated.
1017
9e836e3d
FF		 10182005-01-21 Fred Fish <fnf@specifixinc.com>
1019
1020 * mips-opc.c: Change INSN_ALIAS to INSN2_ALIAS.
1021 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1022 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1023 * mips-dis.c: Ditto.
1024
5e8cb021
AM		 10252005-01-20 Alan Modra <amodra@bigpond.net.au>
1026
1027 * ppc-opc.c (powerpc_opcodes): Add optional 'l' arg to tlbiel.
1028
986e18a5
FF		 10292005-01-19 Fred Fish <fnf@specifixinc.com>
1030
1031 * mips-dis.c (no_aliases): New disassembly option flag.
1032 (set_default_mips_dis_options): Init no_aliases to zero.
1033 (parse_mips_dis_option): Handle no-aliases option.
1034 (print_insn_mips): Ignore table entries that are aliases
1035 if no_aliases is set.
1036 (print_insn_mips16): Ditto.
1037 * mips-opc.c (mips_builtin_opcodes): Add initializer column for
1038 new pinfo2 member and add INSN_ALIAS initializers as needed. Also
1039 move WR_MACC and RD_MACC initializers from pinfo to pinfo2.
1040 * mips16-opc.c (mips16_opcodes): Ditto.
1041
e38bc3b5
NC		 10422005-01-17 Andrew Stubbs <andrew.stubbs@st.com>
1043
1044 * sh-opc.h (arch_sh2a_or_sh3e,arch_sh2a_or_sh4): Correct definition.
1045 (inheritance diagram): Add missing edge.
1046 (arch_sh1_up): Rename arch_sh_up to match external name to make life
1047 easier for the testsuite.
1048 (arch_sh4_nofp_up): Likewise, rename arch_sh4_nofpu_up.
1049 (arch_sh4a_nofp_up): Likewise, rename arch_sh4a_nofpu_up.
610ad19b 1050 (arch_sh2a_nofpu_or_sh4_nommu_nofpu_up): Add missing
e38bc3b5
NC		 1051 arch_sh2a_or_sh4_up child.
1052 (sh_table): Do renaming as above.
1053 Correct comment for ldc.l for gas testsuite to read.
1054 Remove rogue mul.l from sh1 (duplicate of the one for sh2).
1055 Correct comments for movy.w and movy.l for gas testsuite to read.
1056 Correct comments for fmov.d and fmov.s for gas testsuite to read.
1057
9df48ba9
L		 10582005-01-12 H.J. Lu <hongjiu.lu@intel.com>
1059
1060 * i386-dis.c (OP_E): Don't ignore scale in SIB for 64 bit mode.
1061
2033b4b9
L		 10622005-01-12 H.J. Lu <hongjiu.lu@intel.com>
1063
1064 * i386-dis.c (OP_E): Ignore scale when index == 0x4 in SIB.
1065
0bcb06d2
AS		 10662005-01-10 Andreas Schwab <schwab@suse.de>
1067
1068 * disassemble.c (disassemble_init_for_target) <case
1069 bfd_arch_ia64>: Set skip_zeroes to 16.
1070 <case bfd_arch_tic4x>: Set skip_zeroes to 32.
1071
47add74d
TL		 10722004-12-23 Tomer Levi <Tomer.Levi@nsc.com>
1073
1074 * crx-opc.c: Mark 'bcop' instruction as RELAXABLE.
1075
246f4c05
SS		 10762004-12-14 Svein E. Seldal <Svein.Seldal@solidas.com>
1077
1078 * avr-dis.c: Prettyprint. Added printing of symbol names in all
1079 memory references. Convert avr_operand() to C90 formatting.
1080
0e1200e5
TL		 10812004-12-05 Tomer Levi <Tomer.Levi@nsc.com>
1082
1083 * crx-dis.c (print_arg): Use 'info->print_address_func' for address printing.
1084
89a649f7
TL		 10852004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1086
1087 * crx-opc.c (crx_optab): Mark all rbase_disps* operands as signed.
1088 (no_op_insn): Initialize array with instructions that have no
1089 operands.
1090 * crx-dis.c (make_instruction): Get rid of COP_BRANCH_INS operand swapping.
1091
6255809c
RE		 10922004-11-29 Richard Earnshaw <rearnsha@arm.com>
1093
1094 * arm-dis.c: Correct top-level comment.
1095
2fbad815
RE		 10962004-11-27 Richard Earnshaw <rearnsha@arm.com>
1097
1098 * arm-opc.h (arm_opcode, thumb_opcode): Add extra field for the
1099 architecuture defining the insn.
1100 (arm_opcodes, thumb_opcodes): Delete. Move to ...
6b8725b9
RE		 1101 * arm-dis.c (arm_opcodes, thumb_opcodes): Here. Add architecutre
1102 field.
2fbad815
RE		 1103 Also include opcode/arm.h.
1104 * Makefile.am (arm-dis.lo): Update dependency list.
1105 * Makefile.in: Regenerate.
1106
d81acc42
NC		 11072004-11-22 Ravi Ramaseshan <ravi.ramaseshan@codito.com>
1108
1109 * opcode/arc-opc.c (insert_base): Modify ls_operand[LS_OFFSET] to
1110 reflect the change to the short immediate syntax.
1111
ca4f2377
AM		 11122004-11-19 Alan Modra <amodra@bigpond.net.au>
1113
5da8bf1b
AM		 1114 * or32-opc.c (debug): Warning fix.
1115 * po/POTFILES.in: Regenerate.
1116
ca4f2377
AM		 1117 * maxq-dis.c: Formatting.
1118 (print_insn): Warning fix.
1119
b7693d02
DJ		 11202004-11-17 Daniel Jacobowitz <dan@codesourcery.com>
1121
1122 * arm-dis.c (WORD_ADDRESS): Define.
1123 (print_insn): Use it. Correct big-endian end-of-section handling.
1124
300dac7e
NC		 11252004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1126 Vineet Sharma <vineets@noida.hcltech.com>
1127
1128 * maxq-dis.c: New file.
1129 * disassemble.c (ARCH_maxq): Define.
610ad19b 1130 (disassembler): Add 'print_insn_maxq_little' for handling maxq
300dac7e
NC		 1131 instructions..
1132 * configure.in: Add case for bfd_maxq_arch.
1133 * configure: Regenerate.
1134 * Makefile.am: Add support for maxq-dis.c
1135 * Makefile.in: Regenerate.
1136 * aclocal.m4: Regenerate.
1137
42048ee7
TL		 11382004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1139
1140 * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
1141 mode.
1142 * crx-dis.c: Likewise.
1143
bd21e58e
HPN		 11442004-11-04 Hans-Peter Nilsson <hp@axis.com>
1145
1146 Generally, handle CRISv32.
1147 * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
1148 (struct cris_disasm_data): New type.
1149 (format_reg, format_hex, cris_constraint, print_flags)
1150 (get_opcode_entry): Add struct cris_disasm_data * parameter. All
1151 callers changed.
1152 (format_sup_reg, print_insn_crisv32_with_register_prefix)
1153 (print_insn_crisv32_without_register_prefix)
1154 (print_insn_crisv10_v32_with_register_prefix)
1155 (print_insn_crisv10_v32_without_register_prefix)
1156 (cris_parse_disassembler_options): New functions.
1157 (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
1158 parameter. All callers changed.
1159 (get_opcode_entry): Call malloc, not xmalloc. Return NULL on
1160 failure.
1161 (cris_constraint) <case 'Y', 'U'>: New cases.
1162 (bytes_to_skip): Handle 'Y' and 'N' as 's'. Skip size is 4 bytes
1163 for constraint 'n'.
1164 (print_with_operands) <case 'Y'>: New case.
1165 (print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
1166 <case 'N', 'Y', 'Q'>: New cases.
1167 (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
1168 (print_insn_cris_with_register_prefix)
1169 (print_insn_cris_without_register_prefix): Call
1170 cris_parse_disassembler_options.
1171 * cris-opc.c (cris_spec_regs): Mention that this table isn't used
1172 for CRISv32 and the size of immediate operands. New v32-only
1173 entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
1174 spc. Add v32-only 4-byte entries for p2, p3, p5 and p6. Change
1175 ccr, ibr, irp to be v0..v10. Change bar, dccr to be v8..v10.
1176 Change brp to be v3..v10.
1177 (cris_support_regs): New vector.
1178 (cris_opcodes): Update head comment. New format characters '[',
1179 ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
1180 Add new opcodes for v32 and adjust existing opcodes to accommodate
1181 differences to earlier variants.
1182 (cris_cond15s): New vector.
1183
9306ca4a
JB		 11842004-11-04 Jan Beulich <jbeulich@novell.com>
1185
1186 * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
1187 (indirEb): Remove.
1188 (Mp): Use f_mode rather than none at all.
1189 (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
1190 replaces what previously was x_mode; x_mode now means 128-bit SSE
1191 operands.
1192 (dis386): Make far jumps and calls have an 'l' prefix only in AT&T
1193 mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
1194 pinsrw's second operand is Edqw.
1195 (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
1196 operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
1197 fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
1198 mode when an operand size override is present or always suffixing.
1199 More instructions will need to be added to this group.
1200 (putop): Handle new macro chars 'C' (short/long suffix selector),
1201 'I' (Intel mode override for following macro char), and 'J' (for
1202 adding the 'l' prefix to far branches in AT&T mode). When an
1203 alternative was specified in the template, honor macro character when
1204 specified for Intel mode.
1205 (OP_E): Handle new *_mode values. Correct pointer specifications for
1206 memory operands. Consolidate output of index register.
1207 (OP_G): Handle new *_mode values.
1208 (OP_I): Handle const_1_mode.
1209 (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
1210 respective opcode prefix bits have been consumed.
1211 (OP_EM, OP_EX): Provide some default handling for generating pointer
1212 specifications.
1213
f39c96a9
TL		 12142004-10-28 Tomer Levi <Tomer.Levi@nsc.com>
1215
1216 * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
1217 COP_INST macro.
1218
812337be
TL		 12192004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1220
1221 * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
1222 (getregliststring): Support HI/LO and user registers.
610ad19b 1223 * crx-opc.c (crx_instruction): Update data structure according to the
812337be
TL		 1224 rearrangement done in CRX opcode header file.
1225 (crx_regtab): Likewise.
1226 (crx_optab): Likewise.
610ad19b 1227 (crx_instruction): Reorder load/stor instructions, remove unsupported
812337be
TL		 1228 formats.
1229 support new Co-Processor instruction 'cpi'.
1230
4030fa5a
NC		 12312004-10-27 Nick Clifton <nickc@redhat.com>
1232
1233 * opcodes/iq2000-asm.c: Regenerate.
1234 * opcodes/iq2000-desc.c: Regenerate.
1235 * opcodes/iq2000-desc.h: Regenerate.
1236 * opcodes/iq2000-dis.c: Regenerate.
1237 * opcodes/iq2000-ibld.c: Regenerate.
1238 * opcodes/iq2000-opc.c: Regenerate.
1239 * opcodes/iq2000-opc.h: Regenerate.
1240
fc3d45e8
TL		 12412004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1242
1243 * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
1244 us4, us5 (respectively).
1245 Remove unsupported 'popa' instruction.
1246 Reverse operands order in store co-processor instructions.
1247
3c55da70
AM		 12482004-10-15 Alan Modra <amodra@bigpond.net.au>
1249
1250 * Makefile.am: Run "make dep-am"
1251 * Makefile.in: Regenerate.
1252
7fa3d080
BW		 12532004-10-12 Bob Wilson <bob.wilson@acm.org>
1254
1255 * xtensa-dis.c: Use ISO C90 formatting.
1256
e612bb4d
AM		 12572004-10-09 Alan Modra <amodra@bigpond.net.au>
1258
1259 * ppc-opc.c: Revert 2004-09-09 change.
1260
43cd72b9
BW		 12612004-10-07 Bob Wilson <bob.wilson@acm.org>
1262
1263 * xtensa-dis.c (state_names): Delete.
1264 (fetch_data): Use xtensa_isa_maxlength.
1265 (print_xtensa_operand): Replace operand parameter with opcode/operand
1266 pair. Remove print_sr_name parameter. Use new xtensa-isa.h functions.
1267 (print_insn_xtensa): Use new xtensa-isa.h functions. Handle multislot
1268 instruction bundles. Use xmalloc instead of malloc.
1269
bbac1f2a
NC		 12702004-10-07 David Gibson <david@gibson.dropbear.id.au>
1271
1272 * ppc-opc.c: Replace literal "0"s with NULLs in pointer
1273 initializers.
1274
48c9f030
NC		 12752004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1276
1277 * crx-opc.c (crx_instruction): Support Co-processor insns.
1278 * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
1279 (getregliststring): Change function to use the above enum.
1280 (print_arg): Handle CO-Processor insns.
1281 (crx_cinvs): Add 'b' option to invalidate the branch-target
1282 cache.
1283
12c64a4e
AH		 12842004-10-06 Aldy Hernandez <aldyh@redhat.com>
1285
1286 * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
1287 efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
1288 efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
1289 efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
1290 efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
1291
14127cc4
NC		 12922004-10-01 Bill Farmer <Bill@the-farmers.freeserve.co.uk>
1293
1294 * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
1295 rather than add it.
1296
0dd132b6
NC		 12972004-09-30 Paul Brook <paul@codesourcery.com>
1298
1299 * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
1300 * arm-opc.h: Document %e. Add ARMv6ZK instructions.
1301
3f85e526
L		 13022004-09-17 H.J. Lu <hongjiu.lu@intel.com>
1303
1304 * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
1305 (CONFIG_STATUS_DEPENDENCIES): New.
1306 (Makefile): Removed.
1307 (config.status): Likewise.
1308 * Makefile.in: Regenerated.
1309
8ae85421
AM		 13102004-09-17 Alan Modra <amodra@bigpond.net.au>
1311
1312 * Makefile.am: Run "make dep-am".
1313 * Makefile.in: Regenerate.
1314 * aclocal.m4: Regenerate.
1315 * configure: Regenerate.
1316 * po/POTFILES.in: Regenerate.
1317 * po/opcodes.pot: Regenerate.
1318
24443139
AS		 13192004-09-11 Andreas Schwab <schwab@suse.de>
1320
1321 * configure: Rebuild.
1322
2a309db0
AM		 13232004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1324
1325 * ppc-opc.c (L): Make this field not optional.
1326
42851540
NC		 13272004-09-03 Tomer Levi <Tomer.Levi@nsc.com>
1328
1329 * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
1330 Fix parameter to 'm[t|f]csr' insns.
1331
979273e3
NN		 13322004-08-30 Nathanael Nerode <neroden@gcc.gnu.org>
1333
1334 * configure.in: Autoupdate to autoconf 2.59.
1335 * aclocal.m4: Rebuild with aclocal 1.4p6.
1336 * configure: Rebuild with autoconf 2.59.
1337 * Makefile.in: Rebuild with automake 1.4p6 (picking up
1338 bfd changes for autoconf 2.59 on the way).
1339 * config.in: Rebuild with autoheader 2.59.
1340
ac28a1cb
RS		 13412004-08-27 Richard Sandiford <rsandifo@redhat.com>
1342
1343 * frv-desc.[ch], frv-opc.[ch]: Regenerated.
1344
30d1c836
ML		 13452004-07-30 Michal Ludvig <mludvig@suse.cz>
1346
1347 * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
1348 (GRPPADLCK2): New define.
1349 (twobyte_has_modrm): True for 0xA6.
1350 (grps): GRPPADLCK2 for opcode 0xA6.
1351
0b0ac059
AO		 13522004-07-29 Alexandre Oliva <aoliva@redhat.com>
1353
1354 Introduce SH2a support.
1355 * sh-opc.h (arch_sh2a_base): Renumber.
1356 (arch_sh2a_nofpu_base): Remove.
1357 (arch_sh_base_mask): Adjust.
1358 (arch_opann_mask): New.
1359 (arch_sh2a, arch_sh2a_nofpu): Adjust.
1360 (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
1361 (sh_table): Adjust whitespace.
1362 2004-02-24 Corinna Vinschen <vinschen@redhat.com>
1363 * sh-opc.h (arch_sh2a_nofpu_up): New. Use instead of arch_sh2a_up in
1364 instruction list throughout.
1365 (arch_sh2a_up): Redefine to include fpu instruction set. Use instead
1366 of arch_sh2a in instruction list throughout.
1367 (arch_sh2e_up): Accomodate above changes.
1368 (arch_sh2_up): Ditto.
1369 2004-02-20 Corinna Vinschen <vinschen@redhat.com>
1370 * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
1371 2004-02-18 Corinna Vinschen <vinschen@redhat.com>
1372 * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
1373 * sh-opc.h (arch_sh2a_nofpu): New.
1374 (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
1375 (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
1376 instruction.
1377 2004-01-20 DJ Delorie <dj@redhat.com>
1378 * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
1379 2003-12-29 DJ Delorie <dj@redhat.com>
1380 * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
1381 sh_opcode_info, sh_table): Add sh2a support.
1382 (arch_op32): New, to tag 32-bit opcodes.
1383 * sh-dis.c (print_insn_sh): Support sh2a opcodes.
1384 2003-12-02 Michael Snyder <msnyder@redhat.com>
1385 * sh-opc.h (arch_sh2a): Add.
1386 * sh-dis.c (arch_sh2a): Handle.
1387 * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
1388
670ec21d
NC		 13892004-07-27 Tomer Levi <Tomer.Levi@nsc.com>
1390
1391 * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
1392
ed049af3
NC		 13932004-07-22 Nick Clifton <nickc@redhat.com>
1394
1395 PR/280
1396 * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
1397 insns - this is done by objdump itself.
1398 * h8500-dis.c (print_insn_h8500): Likewise.
1399
20f0a1fc
NC		 14002004-07-21 Jan Beulich <jbeulich@novell.com>
1401
1402 * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
1403 regardless of address size prefix in effect.
1404 (ptr_reg): Size or address registers does not depend on rex64, but
1405 on the presence of an address size override.
1406 (OP_MMX): Use rex.x only for xmm registers.
1407 (OP_EM): Use rex.z only for xmm registers.
1408
6f14957b
MR		 14092004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
1410
1411 * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
1412 move/branch operations to the bottom so that VR5400 multimedia
1413 instructions take precedence in disassembly.
1414
1586d91e
MR		 14152004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
1416
1417 * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
1418 ISA-specific "break" encoding.
1419
982de27a
NC		 14202004-07-13 Elvis Chiang <elvisfb@gmail.com>
1421
1422 * arm-opc.h: Fix typo in comment.
1423
4300ab10
AS		 14242004-07-11 Andreas Schwab <schwab@suse.de>
1425
1426 * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
1427
8577e690
AS		 14282004-07-09 Andreas Schwab <schwab@suse.de>
1429
1430 * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
1431
1fe1f39c
NC		 14322004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1433
1434 * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
1435 (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
1436 (crx-dis.lo): New target.
1437 (crx-opc.lo): Likewise.
1438 * Makefile.in: Regenerate.
1439 * configure.in: Handle bfd_crx_arch.
1440 * configure: Regenerate.
1441 * crx-dis.c: New file.
1442 * crx-opc.c: New file.
1443 * disassemble.c (ARCH_crx): Define.
1444 (disassembler): Handle ARCH_crx.
1445
7a33b495
JW		 14462004-06-29 James E Wilson <wilson@specifixinc.com>
1447
1448 * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
1449 * ia64-asmtab.c: Regnerate.
1450
98e69875
AM		 14512004-06-28 Alan Modra <amodra@bigpond.net.au>
1452
1453 * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
1454 (extract_fxm): Don't test dialect.
1455 (XFXFXM_MASK): Include the power4 bit.
1456 (XFXM): Add p4 param.
1457 (powerpc_opcodes): Add mfocrf and mtocrf. Adjust mtcr.
1458
a53b85e2
AO		 14592004-06-27 Alexandre Oliva <aoliva@redhat.com>
1460
1461 2003-07-21 Richard Sandiford <rsandifo@redhat.com>
1462 * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
1463
d0618d1c
AM		 14642004-06-26 Alan Modra <amodra@bigpond.net.au>
1465
1466 * ppc-opc.c (BH, XLBH_MASK): Define.
1467 (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
1468
1d9f512f
AM		 14692004-06-24 Alan Modra <amodra@bigpond.net.au>
1470
1471 * i386-dis.c (x_mode): Comment.
1472 (two_source_ops): File scope.
1473 (float_mem): Correct fisttpll and fistpll.
1474 (float_mem_mode): New table.
1475 (dofloat): Use it.
1476 (OP_E): Correct intel mode PTR output.
1477 (ptr_reg): Use open_char and close_char.
1478 (PNI_Fixup): Handle possible suffix on sidt. Use op1out etc. for
1479 operands. Set two_source_ops.
1480
52886d70
AM		 14812004-06-15 Alan Modra <amodra@bigpond.net.au>
1482
1483 * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
1484 instead of _raw_size.
1485
bad9ceea
JJ		 14862004-06-08 Jakub Jelinek <jakub@redhat.com>
1487
1488 * ia64-gen.c (in_iclass): Handle more postinc st
1489 and ld variants.
1490 * ia64-asmtab.c: Rebuilt.
1491
0451f5df
MS		 14922004-06-01 Martin Schwidefsky <schwidefsky@de.ibm.com>
1493
1494 * s390-opc.txt: Correct architecture mask for some opcodes.
1495 lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
1496 in the esa mode as well.
1497
f6f9408f
JR		 14982004-05-28 Andrew Stubbs <andrew.stubbs@superh.com>
1499
1500 * sh-dis.c (target_arch): Make unsigned.
1501 (print_insn_sh): Replace (most of) switch with a call to
1502 sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
1503 * sh-opc.h: Redefine architecture flags values.
1504 Add sh3-nommu architecture.
1505 Reorganise <arch>_up macros so they make more visual sense.
1506 (SH_MERGE_ARCH_SET): Define new macro.
1507 (SH_VALID_BASE_ARCH_SET): Likewise.
1508 (SH_VALID_MMU_ARCH_SET): Likewise.
1509 (SH_VALID_CO_ARCH_SET): Likewise.
1510 (SH_VALID_ARCH_SET): Likewise.
1511 (SH_MERGE_ARCH_SET_VALID): Likewise.
1512 (SH_ARCH_SET_HAS_FPU): Likewise.
1513 (SH_ARCH_SET_HAS_DSP): Likewise.
1514 (SH_ARCH_UNKNOWN_ARCH): Likewise.
1515 (sh_get_arch_from_bfd_mach): Add prototype.
1516 (sh_get_arch_up_from_bfd_mach): Likewise.
1517 (sh_get_bfd_mach_from_arch_set): Likewise.
1518 (sh_merge_bfd_arc): Likewise.
1519
be8c092b
NC		 15202004-05-24 Peter Barada <peter@the-baradas.com>
1521
1522 * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
610ad19b
AM		 1523 into new match_insn_m68k function. Loop over canidate
1524 matches and select first that completely matches.
be8c092b
NC		 1525 * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
1526 * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
610ad19b 1527 to verify addressing for MAC/EMAC.
be8c092b
NC		 1528 * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
1529 reigster halves since 'fpu' and 'spl' look misleading.
1530 * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
1531 * m68k-opc.c: Rearragne mac/emac cases to use longest for
1532 first, tighten up match masks.
1533 * m68k-opc.c: Add 'size' field to struct m68k_opcode. Produce
1534 'size' from special case code in print_insn_m68k to
1535 determine decode size of insns.
1536
a30e9cc4
AM		 15372004-05-19 Alan Modra <amodra@bigpond.net.au>
1538
1539 * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
1540 well as when -mpower4.
1541
9598fbe5
NC		 15422004-05-13 Nick Clifton <nickc@redhat.com>
1543
1544 * po/fr.po: Updated French translation.
1545
6b6e92f4
NC		 15462004-05-05 Peter Barada <peter@the-baradas.com>
1547
1548 * m68k-dis.c(print_insn_m68k): Add new chips, use core
1549 variants in arch_mask. Only set m68881/68851 for 68k chips.
1550 * m68k-op.c: Switch from ColdFire chips to core variants.
1551
a404d431
AM		 15522004-05-05 Alan Modra <amodra@bigpond.net.au>
1553
a30e9cc4 1554 PR 147.
a404d431
AM		 1555 * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
1556
f3806e43
BE		 15572004-04-29 Ben Elliston <bje@au.ibm.com>
1558
520ceea4
BE		 1559 * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
1560 (powerpc_opcodes): Add "dbczl" instruction for PPC970.
f3806e43 1561
1f1799d5
KK		 15622004-04-22 Kaz Kojima <kkojima@rr.iij4u.or.jp>
1563
1564 * sh-dis.c (print_insn_sh): Print the value in constant pool
1565 as a symbol if it looks like a symbol.
1566
fd99574b
NC		 15672004-04-22 Peter Barada <peter@the-baradas.com>
1568
1569 * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
1570 appropriate ColdFire architectures.
1571 (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
1572 mask addressing.
1573 Add EMAC instructions, fix MAC instructions. Remove
1574 macmw/macml/msacmw/msacml instructions since mask addressing now
1575 supported.
1576
b4781d44
JJ		 15772004-04-20 Jakub Jelinek <jakub@redhat.com>
1578
1579 * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
1580 (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
1581 suffix. Use fmov*x macros, create all 3 fpsize variants in one
1582 macro. Adjust all users.
1583
91809fda 15842004-04-15 Anil Paranjpe <anilp1@kpitcummins.com>
610ad19b 1585
91809fda
NC		 1586 * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
1587 separately.
1588
f4453dfa
NC		 15892004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
1590
1591 * m32r-asm.c: Regenerate.
1592
9b0de91a
SS		 15932004-03-29 Stan Shebs <shebs@apple.com>
1594
1595 * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
1596 used.
1597
e20c0b3d
AM		 15982004-03-19 Alan Modra <amodra@bigpond.net.au>
1599
1600 * aclocal.m4: Regenerate.
1601 * config.in: Regenerate.
1602 * configure: Regenerate.
1603 * po/POTFILES.in: Regenerate.
1604 * po/opcodes.pot: Regenerate.
1605
fdd12ef3
AM		 16062004-03-16 Alan Modra <amodra@bigpond.net.au>
1607
1608 * ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
1609 PPC_OPERANDS_GPR_0.
1610 * ppc-opc.c (RA0): Define.
1611 (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
1612 (RAOPT): Rename from RAO. Update all uses.
a9c3619e 1613 (powerpc_opcodes): Use RA0 as appropriate.
fdd12ef3 1614
2dc111b3 16152004-03-15 Aldy Hernandez <aldyh@redhat.com>
fdd12ef3
AM		 1616
1617 * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
2dc111b3 1618
7bfeee7b
AM		 16192004-03-15 Alan Modra <amodra@bigpond.net.au>
1620
1621 * sparc-dis.c (print_insn_sparc): Update getword prototype.
1622
7ffdda93
ML		 16232004-03-12 Michal Ludvig <mludvig@suse.cz>
1624
1625 * i386-dis.c (GRPPLOCK): Delete.
7bfeee7b 1626 (grps): Delete GRPPLOCK entry.
7ffdda93 1627
cc0ec051
AM		 16282004-03-12 Alan Modra <amodra@bigpond.net.au>
1629
1630 * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
1631 (M, Mp): Use OP_M.
1632 (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
1633 (GRPPADLCK): Define.
1634 (dis386): Use NOP_Fixup on "nop".
1635 (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
1636 (twobyte_has_modrm): Set for 0xa7.
1637 (padlock_table): Delete. Move to..
1638 (grps): ..here, using OP_0f07. Use OP_Ofae on lfence, mfence
1639 and clflush.
1640 (print_insn): Revert PADLOCK_SPECIAL code.
1641 (OP_E): Delete sfence, lfence, mfence checks.
1642
4fd61dcb
JJ		 16432004-03-12 Jakub Jelinek <jakub@redhat.com>
1644
1645 * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
1646 (INVLPG_Fixup): New function.
1647 (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
1648
0f10071e
ML		 16492004-03-12 Michal Ludvig <mludvig@suse.cz>
1650
1651 * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
1652 (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
1653 (padlock_table): New struct with PadLock instructions.
1654 (print_insn): Handle PADLOCK_SPECIAL.
1655
c02908d2
AM		 16562004-03-12 Alan Modra <amodra@bigpond.net.au>
1657
1658 * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
1659 (OP_E): Twiddle clflush to sfence here.
1660
d5bb7600
NC		 16612004-03-08 Nick Clifton <nickc@redhat.com>
1662
1663 * po/de.po: Updated German translation.
1664
ae51a426
JR		 16652003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>
1666
1667 * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
1668 nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu.
1669 * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
1670 accordingly.
1671
676a64f4
RS		 16722004-03-01 Richard Sandiford <rsandifo@redhat.com>
1673
1674 * frv-asm.c: Regenerate.
1675 * frv-desc.c: Regenerate.
1676 * frv-desc.h: Regenerate.
1677 * frv-dis.c: Regenerate.
1678 * frv-ibld.c: Regenerate.
1679 * frv-opc.c: Regenerate.
1680 * frv-opc.h: Regenerate.
1681
c7a48b9a
RS		 16822004-03-01 Richard Sandiford <rsandifo@redhat.com>
1683
1684 * frv-desc.c, frv-opc.c: Regenerate.
1685
8ae0baa2
RS		 16862004-03-01 Richard Sandiford <rsandifo@redhat.com>
1687
1688 * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
1689
ce11586c
JR		 16902004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
1691
1692 * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
1693 Also correct mistake in the comment.
1694
6a5709a5
JR		 16952004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
1696
1697 * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
1698 ensure that double registers have even numbers.
1699 Add REG_N_B01 for nn01 (binary 01) nibble to ensure
1700 that reserved instruction 0xfffd does not decode the same
1701 as 0xfdfd (ftrv).
1702 * sh-opc.h: Add REG_N_D nibble type and use it whereever
1703 REG_N refers to a double register.
1704 Add REG_N_B01 nibble type and use it instead of REG_NM
1705 in ftrv.
1706 Adjust the bit patterns in a few comments.
1707
e5d2b64f 17082004-02-25 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 1709
1710 * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
e5d2b64f 1711
1f04b05f
AH		 17122004-02-20 Aldy Hernandez <aldyh@redhat.com>
1713
1714 * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
1715
2f3b8700
AH		 17162004-02-20 Aldy Hernandez <aldyh@redhat.com>
1717
1718 * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
1719
f0b26da6 17202004-02-20 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 1721
1722 * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
1723 mtivor32, mtivor33, mtivor34.
f0b26da6 1724
23d59c56 17252004-02-19 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 1726
1727 * ppc-opc.c (powerpc_opcodes): Add mfmcar.
23d59c56 1728
34920d91
NC		 17292004-02-10 Petko Manolov <petkan@nucleusys.com>
1730
1731 * arm-opc.h Maverick accumulator register opcode fixes.
1732
44d86481
BE		 17332004-02-13 Ben Elliston <bje@wasabisystems.com>
1734
1735 * m32r-dis.c: Regenerate.
1736
17707c23
MS		 17372004-01-27 Michael Snyder <msnyder@redhat.com>
1738
1739 * sh-opc.h (sh_table): "fsrra", not "fssra".
1740
fe3a9bc4
NC		 17412004-01-23 Andrew Over <andrew.over@cs.anu.edu.au>
1742
1743 * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
1744 contraints.
1745
ff24f124
JJ		 17462004-01-19 Andrew Over <andrew.over@cs.anu.edu.au>
1747
1748 * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
1749
a02a862a
AM		 17502004-01-19 Alan Modra <amodra@bigpond.net.au>
1751
1752 * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
1753 1. Don't print scale factor on AT&T mode when index missing.
1754
d164ea7f
AO		 17552004-01-16 Alexandre Oliva <aoliva@redhat.com>
1756
1757 * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
1758 when loaded into XR registers.
1759
cb10e79a
RS		 17602004-01-14 Richard Sandiford <rsandifo@redhat.com>
1761
1762 * frv-desc.h: Regenerate.
1763 * frv-desc.c: Regenerate.
1764 * frv-opc.c: Regenerate.
1765
f532f3fa
MS		 17662004-01-13 Michael Snyder <msnyder@redhat.com>
1767
1768 * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
1769
e45d0630
PB		 17702004-01-09 Paul Brook <paul@codesourcery.com>
1771
1772 * arm-opc.h (arm_opcodes): Move generic mcrr after known
1773 specific opcodes.
1774
3ba7a1aa
DJ		 17752004-01-07 Daniel Jacobowitz <drow@mvista.com>
1776
1777 * Makefile.am (libopcodes_la_DEPENDENCIES)
1778 (libopcodes_la_LIBADD): Revert 2003-05-17 change. Add explanatory
1779 comment about the problem.
1780 * Makefile.in: Regenerate.
1781
ba2d3f07
AO		 17822004-01-06 Alexandre Oliva <aoliva@redhat.com>
1783
1784 2003-12-19 Alexandre Oliva <aoliva@redhat.com>
1785 * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
1786 cut&paste errors in shifting/truncating numerical operands.
1787 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
1788 * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
1789 (parse_uslo16): Likewise.
1790 (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
1791 (parse_d12): Parse gotoff12 and gotofffuncdesc12.
1792 (parse_s12): Likewise.
1793 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
1794 * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
1795 (parse_uslo16): Likewise.
1796 (parse_uhi16): Parse gothi and gotfuncdeschi.
1797 (parse_d12): Parse got12 and gotfuncdesc12.
1798 (parse_s12): Likewise.
1799
3ab48931
NC		 18002004-01-02 Albert Bartoszko <albar@nt.kegel.com.pl>
1801
1802 * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
1803 instruction which looks similar to an 'rla' instruction.
a0bd404e 1804
c9e214e5 1805For older changes see ChangeLog-0203
252b5132
RH		 1806\f
1807Local Variables:
2f6d2f85
NC		 1808mode: change-log
1809left-margin: 8
1810fill-column: 74
252b5132
RH		 1811version-control: never
1812End:
GDB Binutils - Deliverables
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