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MIPS/BFD: Fix TLS relocation resolution for regular executables
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
a79eaed6
JB		 12018-07-11 Jan Beulich <jbeulich@suse.com>
2
3 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
4 requiring 32-bit registers as operands 2 and 3. Improve
5 comments.
6 (mwait, mwaitx): Fold templates. Improve comments.
7 OPERAND_TYPE_INOUTPORTREG.
8 * i386-tbl.h: Re-generate.
9
2fb5be8d
JB		 102018-07-11 Jan Beulich <jbeulich@suse.com>
11
12 * i386-gen.c (operand_type_init): Remove
13 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
14 OPERAND_TYPE_INOUTPORTREG.
15 * i386-init.h: Re-generate.
16
7f5cad30
JB		 172018-07-11 Jan Beulich <jbeulich@suse.com>
18
19 * i386-opc.tbl (wrssd, wrussd): Add Dword.
20 (wrssq, wrussq): Add Qword.
21 * i386-tbl.h: Re-generate.
22
f0a85b07
JB		 232018-07-11 Jan Beulich <jbeulich@suse.com>
24
25 * i386-opc.h: Rename OTMax to OTNum.
26 (OTNumOfUints): Adjust calculation.
27 (OTUnused): Directly alias to OTNum.
28
9dcb0ba4
MR		 292018-07-09 Maciej W. Rozycki <macro@mips.com>
30
31 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
32 `reg_xys'.
33 (lea_reg_xys): Likewise.
34 (print_insn_loop_primitive): Rename `reg' local variable to
35 `reg_dxy'.
36
f311ba7e
TC		 372018-07-06 Tamar Christina <tamar.christina@arm.com>
38
39 PR binutils/23242
40 * aarch64-tbl.h (ldarh): Fix disassembly mask.
41
cba05feb
TC		 422018-07-06 Tamar Christina <tamar.christina@arm.com>
43
44 PR binutils/23369
45 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
46 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
47
471b9d15
MR		 482018-07-02 Maciej W. Rozycki <macro@mips.com>
49
50 PR tdep/8282
51 * mips-dis.c (mips_option_arg_t): New enumeration.
52 (mips_options): New variable.
53 (disassembler_options_mips): New function.
54 (print_mips_disassembler_options): Reimplement in terms of
55 `disassembler_options_mips'.
56 * arm-dis.c (disassembler_options_arm): Adapt to using the
57 `disasm_options_and_args_t' structure.
58 * ppc-dis.c (disassembler_options_powerpc): Likewise.
59 * s390-dis.c (disassembler_options_s390): Likewise.
60
c0c468d5
TP		 612018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
62
63 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
64 expected result.
65 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
66 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
67 * testsuite/ld-arm/tls-longplt.d: Likewise.
68
369c9167
TC		 692018-06-29 Tamar Christina <tamar.christina@arm.com>
70
71 PR binutils/23192
72 * aarch64-asm-2.c: Regenerate.
73 * aarch64-dis-2.c: Likewise.
74 * aarch64-opc-2.c: Likewise.
75 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
76 * aarch64-opc.c (operand_general_constraint_met_p,
77 aarch64_print_operand): Likewise.
78 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
79 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
80 fmlal2, fmlsl2.
81 (AARCH64_OPERANDS): Add Em2.
82
30aa1306
NC		 832018-06-26 Nick Clifton <nickc@redhat.com>
84
85 * po/uk.po: Updated Ukranian translation.
86 * po/de.po: Updated German translation.
87 * po/pt_BR.po: Updated Brazilian Portuguese translation.
88
eca4b721
NC		 892018-06-26 Nick Clifton <nickc@redhat.com>
90
91 * nfp-dis.c: Fix spelling mistake.
92
71300e2c
NC		 932018-06-24 Nick Clifton <nickc@redhat.com>
94
95 * configure: Regenerate.
96 * po/opcodes.pot: Regenerate.
97
719d8288
NC		 982018-06-24 Nick Clifton <nickc@redhat.com>
99
100 2.31 branch created.
101
514cd3a0
TC		 1022018-06-19 Tamar Christina <tamar.christina@arm.com>
103
104 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
105 * aarch64-asm-2.c: Regenerate.
106 * aarch64-dis-2.c: Likewise.
107
385e4d0f
MR		 1082018-06-21 Maciej W. Rozycki <macro@mips.com>
109
110 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
111 `-M ginv' option description.
112
160d1b3d
SH		 1132018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
114
115 PR gas/23305
116 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
117 la and lla.
118
d0ac1c44
SM		 1192018-06-19 Simon Marchi <simon.marchi@ericsson.com>
120
121 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
122 * configure.ac: Remove AC_PREREQ.
123 * Makefile.in: Re-generate.
124 * aclocal.m4: Re-generate.
125 * configure: Re-generate.
126
6f20c942
FS		 1272018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
128
129 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
130 mips64r6 descriptors.
131 (parse_mips_ase_option): Handle -Mginv option.
132 (print_mips_disassembler_options): Document -Mginv.
133 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
134 (GINV): New macro.
135 (mips_opcodes): Define ginvi and ginvt.
136
730c3174
SE		 1372018-06-13 Scott Egerton <scott.egerton@imgtec.com>
138 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
139
140 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
141 * mips-opc.c (CRC, CRC64): New macros.
142 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
143 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
144 crc32cd for CRC64.
145
cb366992
EB		 1462018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
147
148 PR 20319
149 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
150 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
151
ce72cd46
AM		 1522018-06-06 Alan Modra <amodra@gmail.com>
153
154 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
155 setjmp. Move init for some other vars later too.
156
4b8e28c7
MF		 1572018-06-04 Max Filippov <jcmvbkbc@gmail.com>
158
159 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
160 (dis_private): Add new fields for property section tracking.
161 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
162 (xtensa_instruction_fits): New functions.
163 (fetch_data): Bump minimal fetch size to 4.
164 (print_insn_xtensa): Make struct dis_private static.
165 Load and prepare property table on section change.
166 Don't disassemble literals. Don't disassemble instructions that
167 cross property table boundaries.
168
55e99962
L		 1692018-06-01 H.J. Lu <hongjiu.lu@intel.com>
170
171 * configure: Regenerated.
172
733bd0ab
JB		 1732018-06-01 Jan Beulich <jbeulich@suse.com>
174
175 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
176 * i386-tbl.h: Re-generate.
177
dfd27d41
JB		 1782018-06-01 Jan Beulich <jbeulich@suse.com>
179
180 * i386-opc.tbl (sldt, str): Add NoRex64.
181 * i386-tbl.h: Re-generate.
182
64795710
JB		 1832018-06-01 Jan Beulich <jbeulich@suse.com>
184
185 * i386-opc.tbl (invpcid): Add Oword.
186 * i386-tbl.h: Re-generate.
187
030157d8
AM		 1882018-06-01 Alan Modra <amodra@gmail.com>
189
190 * sysdep.h (_bfd_error_handler): Don't declare.
191 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
192 * rl78-decode.opc: Likewise.
193 * msp430-decode.c: Regenerate.
194 * rl78-decode.c: Regenerate.
195
a9660a6f
AP		 1962018-05-30 Amit Pawar <Amit.Pawar@amd.com>
197
198 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
199 * i386-init.h : Regenerated.
200
277eb7f6
AM		 2012018-05-25 Alan Modra <amodra@gmail.com>
202
203 * Makefile.in: Regenerate.
204 * po/POTFILES.in: Regenerate.
205
98553ad3
PB		 2062018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
207
208 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
209 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
210 (insert_bab, extract_bab, insert_btab, extract_btab,
211 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
212 (BAT, BBA VBA RBS XB6S): Delete macros.
213 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
214 (BB, BD, RBX, XC6): Update for new macros.
215 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
216 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
217 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
218 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
219
7b4ae824
JD		 2202018-05-18 John Darrington <john@darrington.wattle.id.au>
221
222 * Makefile.am: Add support for s12z architecture.
223 * configure.ac: Likewise.
224 * disassemble.c: Likewise.
225 * disassemble.h: Likewise.
226 * Makefile.in: Regenerate.
227 * configure: Regenerate.
228 * s12z-dis.c: New file.
229 * s12z.h: New file.
230
29e0f0a1
AM		 2312018-05-18 Alan Modra <amodra@gmail.com>
232
233 * nfp-dis.c: Don't #include libbfd.h.
234 (init_nfp3200_priv): Use bfd_get_section_contents.
235 (nit_nfp6000_mecsr_sec): Likewise.
236
809276d2
NC		 2372018-05-17 Nick Clifton <nickc@redhat.com>
238
239 * po/zh_CN.po: Updated simplified Chinese translation.
240
ff329288
TC		 2412018-05-16 Tamar Christina <tamar.christina@arm.com>
242
243 PR binutils/23109
244 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
245 * aarch64-dis-2.c: Regenerate.
246
f9830ec1
TC		 2472018-05-15 Tamar Christina <tamar.christina@arm.com>
248
249 PR binutils/21446
250 * aarch64-asm.c (opintl.h): Include.
251 (aarch64_ins_sysreg): Enforce read/write constraints.
252 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
253 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
254 (F_REG_READ, F_REG_WRITE): New.
255 * aarch64-opc.c (aarch64_print_operand): Generate notes for
256 AARCH64_OPND_SYSREG.
257 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
258 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
259 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
260 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
261 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
262 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
263 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
264 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
265 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
266 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
267 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
268 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
269 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
270 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
271 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
272 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
273 msr (F_SYS_WRITE), mrs (F_SYS_READ).
274
7d02540a
TC		 2752018-05-15 Tamar Christina <tamar.christina@arm.com>
276
277 PR binutils/21446
278 * aarch64-dis.c (no_notes: New.
279 (parse_aarch64_dis_option): Support notes.
280 (aarch64_decode_insn, print_operands): Likewise.
281 (print_aarch64_disassembler_options): Document notes.
282 * aarch64-opc.c (aarch64_print_operand): Support notes.
283
561a72d4
TC		 2842018-05-15 Tamar Christina <tamar.christina@arm.com>
285
286 PR binutils/21446
287 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
288 and take error struct.
289 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
290 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
291 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
292 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
293 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
294 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
295 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
296 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
297 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
298 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
299 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
300 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
301 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
302 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
303 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
304 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
305 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
306 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
307 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
308 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
309 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
310 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
311 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
312 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
313 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
314 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
315 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
316 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
317 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
318 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
319 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
320 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
321 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
322 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
323 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
324 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
325 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
326 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
327 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
328 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
329 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
330 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
331 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
332 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
333 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
334 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
335 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
336 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
337 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
338 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
339 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
340 (determine_disassembling_preference, aarch64_decode_insn,
341 print_insn_aarch64_word, print_insn_data): Take errors struct.
342 (print_insn_aarch64): Use errors.
343 * aarch64-asm-2.c: Regenerate.
344 * aarch64-dis-2.c: Regenerate.
345 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
346 boolean in aarch64_insert_operan.
347 (print_operand_extractor): Likewise.
348 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
349
1678bd35
FT		 3502018-05-15 Francois H. Theron <francois.theron@netronome.com>
351
352 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
353
06cfb1c8
L		 3542018-05-09 H.J. Lu <hongjiu.lu@intel.com>
355
356 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
357
84f9f8c3
AM		 3582018-05-09 Sebastian Rasmussen <sebras@gmail.com>
359
360 * cr16-opc.c (cr16_instruction): Comment typo fix.
361 * hppa-dis.c (print_insn_hppa): Likewise.
362
e6f372ba
JW		 3632018-05-08 Jim Wilson <jimw@sifive.com>
364
365 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
366 (match_c_slli64, match_srxi_as_c_srxi): New.
367 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
368 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
369 <c.slli, c.srli, c.srai>: Use match_s_slli.
370 <c.slli64, c.srli64, c.srai64>: New.
371
f413a913
AM		 3722018-05-08 Alan Modra <amodra@gmail.com>
373
374 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
375 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
376 partition opcode space for index lookup.
377
a87a6478
PB		 3782018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
379
380 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
381 <insn_length>: ...with this. Update usage.
382 Remove duplicate call to *info->memory_error_func.
383
c0a30a9f
L		 3842018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
385 H.J. Lu <hongjiu.lu@intel.com>
386
387 * i386-dis.c (Gva): New.
388 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
389 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
390 (prefix_table): New instructions (see prefix above).
391 (mod_table): New instructions (see prefix above).
392 (OP_G): Handle va_mode.
393 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
394 CPU_MOVDIR64B_FLAGS.
395 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
396 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
397 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
398 * i386-opc.tbl: Add movidir{i,64b}.
399 * i386-init.h: Regenerated.
400 * i386-tbl.h: Likewise.
401
75c0a438
L		 4022018-05-07 H.J. Lu <hongjiu.lu@intel.com>
403
404 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
405 AddrPrefixOpReg.
406 * i386-opc.h (AddrPrefixOp0): Renamed to ...
407 (AddrPrefixOpReg): This.
408 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
409 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
410
2ceb7719
PB		 4112018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
412
413 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
414 (vle_num_opcodes): Likewise.
415 (spe2_num_opcodes): Likewise.
416 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
417 initialization loop.
418 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
419 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
420 only once.
421
b3ac5c6c
TC		 4222018-05-01 Tamar Christina <tamar.christina@arm.com>
423
424 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
425
fe944acf
FT		 4262018-04-30 Francois H. Theron <francois.theron@netronome.com>
427
428 Makefile.am: Added nfp-dis.c.
429 configure.ac: Added bfd_nfp_arch.
430 disassemble.h: Added print_insn_nfp prototype.
431 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
432 nfp-dis.c: New, for NFP support.
433 po/POTFILES.in: Added nfp-dis.c to the list.
434 Makefile.in: Regenerate.
435 configure: Regenerate.
436
e2195274
JB		 4372018-04-26 Jan Beulich <jbeulich@suse.com>
438
439 * i386-opc.tbl: Fold various non-memory operand AVX512VL
440 templates into their base ones.
441 * i386-tlb.h: Re-generate.
442
59ef5df4
JB		 4432018-04-26 Jan Beulich <jbeulich@suse.com>
444
445 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
446 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
447 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
448 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
449 * i386-init.h: Re-generate.
450
6e041cf4
JB		 4512018-04-26 Jan Beulich <jbeulich@suse.com>
452
453 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
454 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
455 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
456 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
457 comment.
458 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
459 and CpuRegMask.
460 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
461 CpuRegMask: Delete.
462 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
463 cpuregzmm, and cpuregmask.
464 * i386-init.h: Re-generate.
465 * i386-tbl.h: Re-generate.
466
0e0eea78
JB		 4672018-04-26 Jan Beulich <jbeulich@suse.com>
468
469 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
470 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
471 * i386-init.h: Re-generate.
472
2f1bada2
JB		 4732018-04-26 Jan Beulich <jbeulich@suse.com>
474
475 * i386-gen.c (VexImmExt): Delete.
476 * i386-opc.h (VexImmExt, veximmext): Delete.
477 * i386-opc.tbl: Drop all VexImmExt uses.
478 * i386-tlb.h: Re-generate.
479
bacd1457
JB		 4802018-04-25 Jan Beulich <jbeulich@suse.com>
481
482 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
483 register-only forms.
484 * i386-tlb.h: Re-generate.
485
10bba94b
TC		 4862018-04-25 Tamar Christina <tamar.christina@arm.com>
487
488 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
489
c48935d7
IT		 4902018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
491
492 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
493 PREFIX_0F1C.
494 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
495 (cpu_flags): Add CpuCLDEMOTE.
496 * i386-init.h: Regenerate.
497 * i386-opc.h (enum): Add CpuCLDEMOTE,
498 (i386_cpu_flags): Add cpucldemote.
499 * i386-opc.tbl: Add cldemote.
500 * i386-tbl.h: Regenerate.
501
211dc24b
AM		 5022018-04-16 Alan Modra <amodra@gmail.com>
503
504 * Makefile.am: Remove sh5 and sh64 support.
505 * configure.ac: Likewise.
506 * disassemble.c: Likewise.
507 * disassemble.h: Likewise.
508 * sh-dis.c: Likewise.
509 * sh64-dis.c: Delete.
510 * sh64-opc.c: Delete.
511 * sh64-opc.h: Delete.
512 * Makefile.in: Regenerate.
513 * configure: Regenerate.
514 * po/POTFILES.in: Regenerate.
515
a9a4b302
AM		 5162018-04-16 Alan Modra <amodra@gmail.com>
517
518 * Makefile.am: Remove w65 support.
519 * configure.ac: Likewise.
520 * disassemble.c: Likewise.
521 * disassemble.h: Likewise.
522 * w65-dis.c: Delete.
523 * w65-opc.h: Delete.
524 * Makefile.in: Regenerate.
525 * configure: Regenerate.
526 * po/POTFILES.in: Regenerate.
527
04cb01fd
AM		 5282018-04-16 Alan Modra <amodra@gmail.com>
529
530 * configure.ac: Remove we32k support.
531 * configure: Regenerate.
532
c2bf1eec
AM		 5332018-04-16 Alan Modra <amodra@gmail.com>
534
535 * Makefile.am: Remove m88k support.
536 * configure.ac: Likewise.
537 * disassemble.c: Likewise.
538 * disassemble.h: Likewise.
539 * m88k-dis.c: Delete.
540 * Makefile.in: Regenerate.
541 * configure: Regenerate.
542 * po/POTFILES.in: Regenerate.
543
6793974d
AM		 5442018-04-16 Alan Modra <amodra@gmail.com>
545
546 * Makefile.am: Remove i370 support.
547 * configure.ac: Likewise.
548 * disassemble.c: Likewise.
549 * disassemble.h: Likewise.
550 * i370-dis.c: Delete.
551 * i370-opc.c: Delete.
552 * Makefile.in: Regenerate.
553 * configure: Regenerate.
554 * po/POTFILES.in: Regenerate.
555
e82aa794
AM		 5562018-04-16 Alan Modra <amodra@gmail.com>
557
558 * Makefile.am: Remove h8500 support.
559 * configure.ac: Likewise.
560 * disassemble.c: Likewise.
561 * disassemble.h: Likewise.
562 * h8500-dis.c: Delete.
563 * h8500-opc.h: Delete.
564 * Makefile.in: Regenerate.
565 * configure: Regenerate.
566 * po/POTFILES.in: Regenerate.
567
fceadf09
AM		 5682018-04-16 Alan Modra <amodra@gmail.com>
569
570 * configure.ac: Remove tahoe support.
571 * configure: Regenerate.
572
ae1d3843
L		 5732018-04-15 H.J. Lu <hongjiu.lu@intel.com>
574
575 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
576 umwait.
577 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
578 64-bit mode.
579 * i386-tbl.h: Regenerated.
580
de89d0a3
IT		 5812018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
582
583 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
584 PREFIX_MOD_1_0FAE_REG_6.
585 (va_mode): New.
586 (OP_E_register): Use va_mode.
587 * i386-dis-evex.h (prefix_table):
588 New instructions (see prefixes above).
589 * i386-gen.c (cpu_flag_init): Add WAITPKG.
590 (cpu_flags): Likewise.
591 * i386-opc.h (enum): Likewise.
592 (i386_cpu_flags): Likewise.
593 * i386-opc.tbl: Add umonitor, umwait, tpause.
594 * i386-init.h: Regenerate.
595 * i386-tbl.h: Likewise.
596
a8eb42a8
AM		 5972018-04-11 Alan Modra <amodra@gmail.com>
598
599 * opcodes/i860-dis.c: Delete.
600 * opcodes/i960-dis.c: Delete.
601 * Makefile.am: Remove i860 and i960 support.
602 * configure.ac: Likewise.
603 * disassemble.c: Likewise.
604 * disassemble.h: Likewise.
605 * Makefile.in: Regenerate.
606 * configure: Regenerate.
607 * po/POTFILES.in: Regenerate.
608
caf0678c
L		 6092018-04-04 H.J. Lu <hongjiu.lu@intel.com>
610
611 PR binutils/23025
612 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
613 to 0.
614 (print_insn): Clear vex instead of vex.evex.
615
4fb0d2b9
NC		 6162018-04-04 Nick Clifton <nickc@redhat.com>
617
618 * po/es.po: Updated Spanish translation.
619
c39e5b26
JB		 6202018-03-28 Jan Beulich <jbeulich@suse.com>
621
622 * i386-gen.c (opcode_modifiers): Delete VecESize.
623 * i386-opc.h (VecESize): Delete.
624 (struct i386_opcode_modifier): Delete vecesize.
625 * i386-opc.tbl: Drop VecESize.
626 * i386-tlb.h: Re-generate.
627
8e6e0792
JB		 6282018-03-28 Jan Beulich <jbeulich@suse.com>
629
630 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
631 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
632 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
633 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
634 * i386-tlb.h: Re-generate.
635
9f123b91
JB		 6362018-03-28 Jan Beulich <jbeulich@suse.com>
637
638 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
639 Fold AVX512 forms
640 * i386-tlb.h: Re-generate.
641
9646c87b
JB		 6422018-03-28 Jan Beulich <jbeulich@suse.com>
643
644 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
645 (vex_len_table): Drop Y for vcvt*2si.
646 (putop): Replace plain 'Y' handling by abort().
647
c8d59609
NC		 6482018-03-28 Nick Clifton <nickc@redhat.com>
649
650 PR 22988
651 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
652 instructions with only a base address register.
653 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
654 handle AARHC64_OPND_SVE_ADDR_R.
655 (aarch64_print_operand): Likewise.
656 * aarch64-asm-2.c: Regenerate.
657 * aarch64_dis-2.c: Regenerate.
658 * aarch64-opc-2.c: Regenerate.
659
b8c169f3
JB		 6602018-03-22 Jan Beulich <jbeulich@suse.com>
661
662 * i386-opc.tbl: Drop VecESize from register only insn forms and
663 memory forms not allowing broadcast.
664 * i386-tlb.h: Re-generate.
665
96bc132a
JB		 6662018-03-22 Jan Beulich <jbeulich@suse.com>
667
668 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
669 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
670 sha256*): Drop Disp<N>.
671
9f79e886
JB		 6722018-03-22 Jan Beulich <jbeulich@suse.com>
673
674 * i386-dis.c (EbndS, bnd_swap_mode): New.
675 (prefix_table): Use EbndS.
676 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
677 * i386-opc.tbl (bndmov): Move misplaced Load.
678 * i386-tlb.h: Re-generate.
679
d6793fa1
JB		 6802018-03-22 Jan Beulich <jbeulich@suse.com>
681
682 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
683 templates allowing memory operands and folded ones for register
684 only flavors.
685 * i386-tlb.h: Re-generate.
686
f7768225
JB		 6872018-03-22 Jan Beulich <jbeulich@suse.com>
688
689 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
690 256-bit templates. Drop redundant leftover Disp<N>.
691 * i386-tlb.h: Re-generate.
692
0e35537d
JW		 6932018-03-14 Kito Cheng <kito.cheng@gmail.com>
694
695 * riscv-opc.c (riscv_insn_types): New.
696
b4a3689a
NC		 6972018-03-13 Nick Clifton <nickc@redhat.com>
698
699 * po/pt_BR.po: Updated Brazilian Portuguese translation.
700
d3d50934
L		 7012018-03-08 H.J. Lu <hongjiu.lu@intel.com>
702
703 * i386-opc.tbl: Add Optimize to clr.
704 * i386-tbl.h: Regenerated.
705
bd5dea88
L		 7062018-03-08 H.J. Lu <hongjiu.lu@intel.com>
707
708 * i386-gen.c (opcode_modifiers): Remove OldGcc.
709 * i386-opc.h (OldGcc): Removed.
710 (i386_opcode_modifier): Remove oldgcc.
711 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
712 instructions for old (<= 2.8.1) versions of gcc.
713 * i386-tbl.h: Regenerated.
714
e771e7c9
JB		 7152018-03-08 Jan Beulich <jbeulich@suse.com>
716
717 * i386-opc.h (EVEXDYN): New.
718 * i386-opc.tbl: Fold various AVX512VL templates.
719 * i386-tlb.h: Re-generate.
720
ed438a93
JB		 7212018-03-08 Jan Beulich <jbeulich@suse.com>
722
723 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
724 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
725 vpexpandd, vpexpandq): Fold AFX512VF templates.
726 * i386-tlb.h: Re-generate.
727
454172a9
JB		 7282018-03-08 Jan Beulich <jbeulich@suse.com>
729
730 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
731 Fold 128- and 256-bit VEX-encoded templates.
732 * i386-tlb.h: Re-generate.
733
36824150
JB		 7342018-03-08 Jan Beulich <jbeulich@suse.com>
735
736 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
737 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
738 vpexpandd, vpexpandq): Fold AVX512F templates.
739 * i386-tlb.h: Re-generate.
740
e7f5c0a9
JB		 7412018-03-08 Jan Beulich <jbeulich@suse.com>
742
743 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
744 64-bit templates. Drop Disp<N>.
745 * i386-tlb.h: Re-generate.
746
25a4277f
JB		 7472018-03-08 Jan Beulich <jbeulich@suse.com>
748
749 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
750 and 256-bit templates.
751 * i386-tlb.h: Re-generate.
752
d2224064
JB		 7532018-03-08 Jan Beulich <jbeulich@suse.com>
754
755 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
756 * i386-tlb.h: Re-generate.
757
1b193f0b
JB		 7582018-03-08 Jan Beulich <jbeulich@suse.com>
759
760 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
761 Drop NoAVX.
762 * i386-tlb.h: Re-generate.
763
f2f6a710
JB		 7642018-03-08 Jan Beulich <jbeulich@suse.com>
765
766 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
767 * i386-tlb.h: Re-generate.
768
38e314eb
JB		 7692018-03-08 Jan Beulich <jbeulich@suse.com>
770
771 * i386-gen.c (opcode_modifiers): Delete FloatD.
772 * i386-opc.h (FloatD): Delete.
773 (struct i386_opcode_modifier): Delete floatd.
774 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
775 FloatD by D.
776 * i386-tlb.h: Re-generate.
777
d53e6b98
JB		 7782018-03-08 Jan Beulich <jbeulich@suse.com>
779
780 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
781
2907c2f5
JB		 7822018-03-08 Jan Beulich <jbeulich@suse.com>
783
784 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
785 * i386-tlb.h: Re-generate.
786
73053c1f
JB		 7872018-03-08 Jan Beulich <jbeulich@suse.com>
788
789 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
790 forms.
791 * i386-tlb.h: Re-generate.
792
52fe4420
AM		 7932018-03-07 Alan Modra <amodra@gmail.com>
794
795 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
796 bfd_arch_rs6000.
797 * disassemble.h (print_insn_rs6000): Delete.
798 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
799 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
800 (print_insn_rs6000): Delete.
801
a6743a54
AM		 8022018-03-03 Alan Modra <amodra@gmail.com>
803
804 * sysdep.h (opcodes_error_handler): Define.
805 (_bfd_error_handler): Declare.
806 * Makefile.am: Remove stray #.
807 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
808 EDIT" comment.
809 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
810 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
811 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
812 opcodes_error_handler to print errors. Standardize error messages.
813 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
814 and include opintl.h.
815 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
816 * i386-gen.c: Standardize error messages.
817 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
818 * Makefile.in: Regenerate.
819 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
820 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
821 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
822 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
823 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
824 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
825 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
826 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
827 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
828 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
829 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
830 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
831 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
832
8305403a
L		 8332018-03-01 H.J. Lu <hongjiu.lu@intel.com>
834
835 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
836 vpsub[bwdq] instructions.
837 * i386-tbl.h: Regenerated.
838
e184813f
AM		 8392018-03-01 Alan Modra <amodra@gmail.com>
840
841 * configure.ac (ALL_LINGUAS): Sort.
842 * configure: Regenerate.
843
5b616bef
TP		 8442018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
845
846 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
847 macro by assignements.
848
b6f8c7c4
L		 8492018-02-27 H.J. Lu <hongjiu.lu@intel.com>
850
851 PR gas/22871
852 * i386-gen.c (opcode_modifiers): Add Optimize.
853 * i386-opc.h (Optimize): New enum.
854 (i386_opcode_modifier): Add optimize.
855 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
856 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
857 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
858 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
859 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
860 vpxord and vpxorq.
861 * i386-tbl.h: Regenerated.
862
e95b887f
AM		 8632018-02-26 Alan Modra <amodra@gmail.com>
864
865 * crx-dis.c (getregliststring): Allocate a large enough buffer
866 to silence false positive gcc8 warning.
867
0bccfb29
JW		 8682018-02-22 Shea Levy <shea@shealevy.com>
869
870 * disassemble.c (ARCH_riscv): Define if ARCH_all.
871
6b6b6807
L		 8722018-02-22 H.J. Lu <hongjiu.lu@intel.com>
873
874 * i386-opc.tbl: Add {rex},
875 * i386-tbl.h: Regenerated.
876
75f31665
MR		 8772018-02-20 Maciej W. Rozycki <macro@mips.com>
878
879 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
880 (mips16_opcodes): Replace `M' with `m' for "restore".
881
e207bc53
TP		 8822018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
883
884 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
885
87993319
MR		 8862018-02-13 Maciej W. Rozycki <macro@mips.com>
887
888 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
889 variable to `function_index'.
890
68d20676
NC		 8912018-02-13 Nick Clifton <nickc@redhat.com>
892
893 PR 22823
894 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
895 about truncation of printing.
896
d2159fdc
HW		 8972018-02-12 Henry Wong <henry@stuffedcow.net>
898
899 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
900
f174ef9f
NC		 9012018-02-05 Nick Clifton <nickc@redhat.com>
902
903 * po/pt_BR.po: Updated Brazilian Portuguese translation.
904
be3a8dca
IT		 9052018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
906
907 * i386-dis.c (enum): Add pconfig.
908 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
909 (cpu_flags): Add CpuPCONFIG.
910 * i386-opc.h (enum): Add CpuPCONFIG.
911 (i386_cpu_flags): Add cpupconfig.
912 * i386-opc.tbl: Add PCONFIG instruction.
913 * i386-init.h: Regenerate.
914 * i386-tbl.h: Likewise.
915
3233d7d0
IT		 9162018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
917
918 * i386-dis.c (enum): Add PREFIX_0F09.
919 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
920 (cpu_flags): Add CpuWBNOINVD.
921 * i386-opc.h (enum): Add CpuWBNOINVD.
922 (i386_cpu_flags): Add cpuwbnoinvd.
923 * i386-opc.tbl: Add WBNOINVD instruction.
924 * i386-init.h: Regenerate.
925 * i386-tbl.h: Likewise.
926
e925c834
JW		 9272018-01-17 Jim Wilson <jimw@sifive.com>
928
929 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
930
d777820b
IT		 9312018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
932
933 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
934 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
935 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
936 (cpu_flags): Add CpuIBT, CpuSHSTK.
937 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
938 (i386_cpu_flags): Add cpuibt, cpushstk.
939 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
940 * i386-init.h: Regenerate.
941 * i386-tbl.h: Likewise.
942
f6efed01
NC		 9432018-01-16 Nick Clifton <nickc@redhat.com>
944
945 * po/pt_BR.po: Updated Brazilian Portugese translation.
946 * po/de.po: Updated German translation.
947
2721d702
JW		 9482018-01-15 Jim Wilson <jimw@sifive.com>
949
950 * riscv-opc.c (match_c_nop): New.
951 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
952
616dcb87
NC		 9532018-01-15 Nick Clifton <nickc@redhat.com>
954
955 * po/uk.po: Updated Ukranian translation.
956
3957a496
NC		 9572018-01-13 Nick Clifton <nickc@redhat.com>
958
959 * po/opcodes.pot: Regenerated.
960
769c7ea5
NC		 9612018-01-13 Nick Clifton <nickc@redhat.com>
962
963 * configure: Regenerate.
964
faf766e3
NC		 9652018-01-13 Nick Clifton <nickc@redhat.com>
966
967 2.30 branch created.
968
888a89da
IT		 9692018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
970
971 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
972 * i386-tbl.h: Regenerate.
973
cbda583a
JB		 9742018-01-10 Jan Beulich <jbeulich@suse.com>
975
976 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
977 * i386-tbl.h: Re-generate.
978
c9e92278
JB		 9792018-01-10 Jan Beulich <jbeulich@suse.com>
980
981 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
982 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
983 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
984 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
985 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
986 Disp8MemShift of AVX512VL forms.
987 * i386-tbl.h: Re-generate.
988
35fd2b2b
JW		 9892018-01-09 Jim Wilson <jimw@sifive.com>
990
991 * riscv-dis.c (maybe_print_address): If base_reg is zero,
992 then the hi_addr value is zero.
993
91d8b670
JG		 9942018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
995
996 * arm-dis.c (arm_opcodes): Add csdb.
997 (thumb32_opcodes): Add csdb.
998
be2e7d95
JG		 9992018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1000
1001 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1002 * aarch64-asm-2.c: Regenerate.
1003 * aarch64-dis-2.c: Regenerate.
1004 * aarch64-opc-2.c: Regenerate.
1005
704a705d
L		 10062018-01-08 H.J. Lu <hongjiu.lu@intel.com>
1007
1008 PR gas/22681
1009 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1010 Remove AVX512 vmovd with 64-bit operands.
1011 * i386-tbl.h: Regenerated.
1012
35eeb78f
JW		 10132018-01-05 Jim Wilson <jimw@sifive.com>
1014
1015 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1016 jalr.
1017
219d1afa
AM		 10182018-01-03 Alan Modra <amodra@gmail.com>
1019
1020 Update year range in copyright notice of all files.
1021
1508bbf5
JB		 10222018-01-02 Jan Beulich <jbeulich@suse.com>
1023
1024 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1025 and OPERAND_TYPE_REGZMM entries.
1026
1e563868 1027For older changes see ChangeLog-2017
3499769a 1028\f
1e563868 1029Copyright (C) 2018 Free Software Foundation, Inc.
3499769a
AM		 1030
1031Copying and distribution of this file, with or without modification,
1032are permitted in any medium without royalty provided the copyright
1033notice and this notice are preserved.
1034
1035Local Variables:
1036mode: change-log
1037left-margin: 8
1038fill-column: 74
1039version-control: never
1040End:
GDB Binutils - Deliverables
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