opcodes,gas: associate SPARC ASIs with an architecture level.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
1e9d41d4
SL
12017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
2
3 Add support for associating SPARC ASIs with an architecture level.
4 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
5 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
6 decoding of SPARC ASIs.
7
53c4d625
JB
82017-02-23 Jan Beulich <jbeulich@suse.com>
9
10 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
11 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
12
11648de5
JB
132017-02-21 Jan Beulich <jbeulich@suse.com>
14
15 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
16 1 (instead of to itself). Correct typo.
17
f98d33be
AW
182017-02-14 Andrew Waterman <andrew@sifive.com>
19
20 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
21 pseudoinstructions.
22
773fb663
RS
232017-02-15 Richard Sandiford <richard.sandiford@arm.com>
24
25 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
26 (aarch64_sys_reg_supported_p): Handle them.
27
cc07cda6
CZ
282017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
29
30 * arc-opc.c (UIMM6_20R): Define.
31 (SIMM12_20): Use above.
32 (SIMM12_20R): Define.
33 (SIMM3_5_S): Use above.
34 (UIMM7_A32_11R_S): Define.
35 (UIMM7_9_S): Use above.
36 (UIMM3_13R_S): Define.
37 (SIMM11_A32_7_S): Use above.
38 (SIMM9_8R): Define.
39 (UIMM10_A32_8_S): Use above.
40 (UIMM8_8R_S): Define.
41 (W6): Use above.
42 (arc_relax_opcodes): Use all above defines.
43
66a5a740
VG
442017-02-15 Vineet Gupta <vgupta@synopsys.com>
45
46 * arc-regs.h: Distinguish some of the registers different on
47 ARC700 and HS38 cpus.
48
7e0de605
AM
492017-02-14 Alan Modra <amodra@gmail.com>
50
51 PR 21118
52 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
53 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
54
54064fdb
AM
552017-02-11 Stafford Horne <shorne@gmail.com>
56 Alan Modra <amodra@gmail.com>
57
58 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
59 Use insn_bytes_value and insn_int_value directly instead. Don't
60 free allocated memory until function exit.
61
dce75bf9
NP
622017-02-10 Nicholas Piggin <npiggin@gmail.com>
63
64 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
65
1b7e3d2f
NC
662017-02-03 Nick Clifton <nickc@redhat.com>
67
68 PR 21096
69 * aarch64-opc.c (print_register_list): Ensure that the register
70 list index will fir into the tb buffer.
71 (print_register_offset_address): Likewise.
72 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
73
8ec5cf65
AD
742017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
75
76 PR 21056
77 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
78 instructions when the previous fetch packet ends with a 32-bit
79 instruction.
80
a1aa5e81
DD
812017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
82
83 * pru-opc.c: Remove vague reference to a future GDB port.
84
add3afb2
NC
852017-01-20 Nick Clifton <nickc@redhat.com>
86
87 * po/ga.po: Updated Irish translation.
88
c13a63b0
SN
892017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
90
91 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
92
9608051a
YQ
932017-01-13 Yao Qi <yao.qi@linaro.org>
94
95 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
96 if FETCH_DATA returns 0.
97 (m68k_scan_mask): Likewise.
98 (print_insn_m68k): Update code to handle -1 return value.
99
f622ea96
YQ
1002017-01-13 Yao Qi <yao.qi@linaro.org>
101
102 * m68k-dis.c (enum print_insn_arg_error): New.
103 (NEXTBYTE): Replace -3 with
104 PRINT_INSN_ARG_MEMORY_ERROR.
105 (NEXTULONG): Likewise.
106 (NEXTSINGLE): Likewise.
107 (NEXTDOUBLE): Likewise.
108 (NEXTDOUBLE): Likewise.
109 (NEXTPACKED): Likewise.
110 (FETCH_ARG): Likewise.
111 (FETCH_DATA): Update comments.
112 (print_insn_arg): Update comments. Replace magic numbers with
113 enum.
114 (match_insn_m68k): Likewise.
115
620214f7
IT
1162017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
117
118 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
119 * i386-dis-evex.h (evex_table): Updated.
120 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
121 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
122 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
123 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
124 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
125 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
126 * i386-init.h: Regenerate.
127 * i386-tbl.h: Ditto.
128
d95014a2
YQ
1292017-01-12 Yao Qi <yao.qi@linaro.org>
130
131 * msp430-dis.c (msp430_singleoperand): Return -1 if
132 msp430dis_opcode_signed returns false.
133 (msp430_doubleoperand): Likewise.
134 (msp430_branchinstr): Return -1 if
135 msp430dis_opcode_unsigned returns false.
136 (msp430x_calla_instr): Likewise.
137 (print_insn_msp430): Likewise.
138
0ae60c3e
NC
1392017-01-05 Nick Clifton <nickc@redhat.com>
140
141 PR 20946
142 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
143 could not be matched.
144 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
145 NULL.
146
d74d4880
SN
1472017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
148
149 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
150 (aarch64_opcode_table): Use RCPC_INSN.
151
cc917fd9
KC
1522017-01-03 Kito Cheng <kito.cheng@gmail.com>
153
154 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
155 extension.
156 * riscv-opcodes/all-opcodes: Likewise.
157
b52d3cfc
DP
1582017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
159
160 * riscv-dis.c (print_insn_args): Add fall through comment.
161
f90c58d5
NC
1622017-01-03 Nick Clifton <nickc@redhat.com>
163
164 * po/sr.po: New Serbian translation.
165 * configure.ac (ALL_LINGUAS): Add sr.
166 * configure: Regenerate.
167
f47b0d4a
AM
1682017-01-02 Alan Modra <amodra@gmail.com>
169
170 * epiphany-desc.h: Regenerate.
171 * epiphany-opc.h: Regenerate.
172 * fr30-desc.h: Regenerate.
173 * fr30-opc.h: Regenerate.
174 * frv-desc.h: Regenerate.
175 * frv-opc.h: Regenerate.
176 * ip2k-desc.h: Regenerate.
177 * ip2k-opc.h: Regenerate.
178 * iq2000-desc.h: Regenerate.
179 * iq2000-opc.h: Regenerate.
180 * lm32-desc.h: Regenerate.
181 * lm32-opc.h: Regenerate.
182 * m32c-desc.h: Regenerate.
183 * m32c-opc.h: Regenerate.
184 * m32r-desc.h: Regenerate.
185 * m32r-opc.h: Regenerate.
186 * mep-desc.h: Regenerate.
187 * mep-opc.h: Regenerate.
188 * mt-desc.h: Regenerate.
189 * mt-opc.h: Regenerate.
190 * or1k-desc.h: Regenerate.
191 * or1k-opc.h: Regenerate.
192 * xc16x-desc.h: Regenerate.
193 * xc16x-opc.h: Regenerate.
194 * xstormy16-desc.h: Regenerate.
195 * xstormy16-opc.h: Regenerate.
196
2571583a
AM
1972017-01-02 Alan Modra <amodra@gmail.com>
198
199 Update year range in copyright notice of all files.
200
5c1ad6b5 201For older changes see ChangeLog-2016
3499769a 202\f
5c1ad6b5 203Copyright (C) 2017 Free Software Foundation, Inc.
3499769a
AM
204
205Copying and distribution of this file, with or without modification,
206are permitted in any medium without royalty provided the copyright
207notice and this notice are preserved.
208
209Local Variables:
210mode: change-log
211left-margin: 8
212fill-column: 74
213version-control: never
214End:
This page took 0.08566 seconds and 4 git commands to generate.